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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=46842bc30=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/25 01:44:23 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Once an interrupt has been claimed, but before it has been compelted we shouldn't receive any more pending interrupts. This patche keeps track of this to ensure that we don't see any more interrupts until it is completed. Signed-off-by: Alistair Francis --- include/hw/intc/ibex_plic.h | 1 + hw/intc/ibex_plic.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h index ddc7909903..d8eb09b258 100644 --- a/include/hw/intc/ibex_plic.h +++ b/include/hw/intc/ibex_plic.h @@ -33,6 +33,7 @@ typedef struct IbexPlicState { MemoryRegion mmio; =20 uint32_t *pending; + uint32_t *claimed; uint32_t *source; uint32_t *priority; uint32_t *enable; diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index 578edd2ce0..669247ef08 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -43,6 +43,14 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s,= int irq, bool level) { int pending_num =3D irq / 32; =20 + if (s->claimed[pending_num] & 1 << (irq % 32)) { + /* + * The interrupt has been claimed, but not compelted. + * The pending bit can't be set. + */ + return; + } + s->pending[pending_num] |=3D level << (irq % 32); } =20 @@ -120,6 +128,10 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr ad= dr, int pending_num =3D s->claim / 32; s->pending[pending_num] &=3D ~(1 << (s->claim % 32)); =20 + /* Set the interrupt as claimed, but not compelted */ + s->claimed[pending_num] |=3D 1 << (s->claim % 32); + + /* Return the current claimed interrupt */ ret =3D s->claim; =20 /* Update the interrupt status after the claim */ @@ -155,6 +167,10 @@ static void ibex_plic_write(void *opaque, hwaddr addr, /* Interrupt was completed */ s->claim =3D 0; } + if (s->claimed[value / 32] & 1 << (value % 32)) { + /* This value was already claimed, clear it. */ + s->claimed[value / 32] &=3D ~(1 << (value % 32)); + } } =20 ibex_plic_update(s); @@ -215,6 +231,7 @@ static void ibex_plic_realize(DeviceState *dev, Error *= *errp) int i; =20 s->pending =3D g_new0(uint32_t, s->pending_num); + s->claimed =3D g_new0(uint32_t, s->pending_num); s->source =3D g_new0(uint32_t, s->source_num); s->priority =3D g_new0(uint32_t, s->priority_num); s->enable =3D g_new0(uint32_t, s->enable_num); --=20 2.27.0