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Sat, 07 Mar 2026 23:20:43 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 22/28] hw/riscv/dm: add system bus access Date: Sun, 8 Mar 2026 15:17:25 +0800 Message-ID: <37a88487caad84ae50b47cc190820ebfac5ecb3e.1772936778.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1341; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954542813154100 Content-Type: text/plain; charset="utf-8" Implement the optional System Bus Access (SBA) register set that allows the debugger to read and write system memory without involving a hart. This adds SBCS, SBADDRESS0-3, and SBDATA0-3 register handlers with sticky error reporting, sbreadonaddr, sbreadondata, and sbautoincrement support. The SBA path supports 8/16/32/64-bit access widths and sets the SBA capability bits during DM reset based on the configured sba-addr-width property. Signed-off-by: Chao Liu --- hw/riscv/dm.c | 249 ++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 242 insertions(+), 7 deletions(-) diff --git a/hw/riscv/dm.c b/hw/riscv/dm.c index 818e48629f..bcaaffd02b 100644 --- a/hw/riscv/dm.c +++ b/hw/riscv/dm.c @@ -19,6 +19,7 @@ #include "exec/cpu-common.h" #include "migration/vmstate.h" #include "exec/translation-block.h" +#include "system/address-spaces.h" #include "system/tcg.h" #include "target/riscv/cpu.h" #include "trace.h" @@ -736,6 +737,95 @@ static bool dm_execute_abstract_cmd(RISCVDMState *s, u= int32_t command) } =20 =20 +static int dm_sba_access_bytes(uint32_t sbaccess) +{ + if (sbaccess <=3D 4) { + return 1 << sbaccess; + } + return 0; +} + +static bool dm_sba_access_supported(RISCVDMState *s, uint32_t sbaccess) +{ + switch (sbaccess) { + case 0: return ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS8); + case 1: return ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS16); + case 2: return ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS32); + case 3: return ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS64); + case 4: return ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS128); + default: return false; + } +} + +static void dm_sba_execute(RISCVDMState *s, bool is_write) +{ + uint32_t sbaccess =3D ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS); + int access_bytes =3D dm_sba_access_bytes(sbaccess); + uint8_t buf[16] =3D { 0 }; + MemTxResult result; + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSYERROR) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBERROR)) { + return; + } + + if (!access_bytes || !dm_sba_access_supported(s, sbaccess)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBERROR, 4); /* other error */ + return; + } + + if (s->regs[R_SBADDRESS2] || s->regs[R_SBADDRESS3]) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBERROR, 2); + return; + } + + hwaddr lo =3D s->regs[R_SBADDRESS0]; + hwaddr hi =3D s->regs[R_SBADDRESS1]; + hwaddr addr =3D (hi << 32) | lo; + + if (addr & (access_bytes - 1)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBERROR, 3); /* alignment */ + return; + } + + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSY, 1); + for (int i =3D 0; i < 4; i++) { + stl_le_p(buf + i * 4, s->regs[R_SBDATA0 + i]); + } + + if (is_write) { + result =3D address_space_rw(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, buf, + access_bytes, true); + } else { + result =3D address_space_rw(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, buf, + access_bytes, false); + if (result =3D=3D MEMTX_OK) { + for (int i =3D 0; i < 4; i++) { + s->regs[R_SBDATA0 + i] =3D ldl_le_p(buf + i * 4); + } + } + } + + if (result !=3D MEMTX_OK) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBERROR, + result =3D=3D MEMTX_DECODE_ERROR ? 2 : 7); + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSY, 0); + return; + } + + trace_riscv_dm_sba_access(addr, s->regs[R_SBDATA0], access_bytes, is_w= rite); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBAUTOINCREMENT)) { + addr +=3D access_bytes; + s->regs[R_SBADDRESS0] =3D (uint32_t)addr; + s->regs[R_SBADDRESS1] =3D addr >> 32; + } + + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSY, 0); +} + =20 static void dm_status_refresh(RISCVDMState *s) { @@ -1108,6 +1198,129 @@ static uint64_t dm_progbuf_post_read(RegisterInfo *= reg, uint64_t val) return val; } =20 +static uint64_t dm_sbcs_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + uint32_t val =3D (uint32_t)val64; + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + qemu_log_mask(LOG_GUEST_ERROR, + "riscv-dm: write to sbcs while busy\n"); + return s->regs[R_SBCS]; + } + + uint32_t cur =3D s->regs[R_SBCS]; + + /* W1C: sberror and sbbusyerror */ + uint32_t sberror_clr =3D FIELD_EX32(val, SBCS, SBERROR); + uint32_t sberror_cur =3D FIELD_EX32(cur, SBCS, SBERROR); + cur =3D FIELD_DP32(cur, SBCS, SBERROR, sberror_cur & ~sberror_clr); + + uint32_t busyerr_clr =3D FIELD_EX32(val, SBCS, SBBUSYERROR); + uint32_t busyerr_cur =3D FIELD_EX32(cur, SBCS, SBBUSYERROR); + cur =3D FIELD_DP32(cur, SBCS, SBBUSYERROR, busyerr_cur & ~busyerr_clr); + + /* Writable fields */ + cur =3D FIELD_DP32(cur, SBCS, SBREADONADDR, + FIELD_EX32(val, SBCS, SBREADONADDR)); + cur =3D FIELD_DP32(cur, SBCS, SBACCESS, + FIELD_EX32(val, SBCS, SBACCESS)); + cur =3D FIELD_DP32(cur, SBCS, SBAUTOINCREMENT, + FIELD_EX32(val, SBCS, SBAUTOINCREMENT)); + cur =3D FIELD_DP32(cur, SBCS, SBREADONDATA, + FIELD_EX32(val, SBCS, SBREADONDATA)); + + return cur; +} + +static void dm_sbaddress0_post_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSYERROR, 1); + return; + } + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBREADONADDR) && + !ARRAY_FIELD_EX32(s->regs, SBCS, SBERROR) && + !ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSYERROR)) { + dm_sba_execute(s, false); + } +} + +static uint64_t dm_sbaddress1_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSYERROR, 1); + return s->regs[R_SBADDRESS1]; + } + return (uint32_t)val64; +} + +static void dm_sbdata0_post_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSYERROR, 1); + return; + } + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSYERROR) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBERROR)) { + return; + } + + dm_sba_execute(s, true); +} + +static uint64_t dm_sbdata0_post_read(RegisterInfo *reg, uint64_t val) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSYERROR, 1); + return val; + } + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSYERROR) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBERROR)) { + return val; + } + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBREADONDATA)) { + dm_sba_execute(s, false); + return val; + } + return val; +} + +static uint64_t dm_sbdata1_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSYERROR, 1); + return s->regs[R_SBDATA1]; + } + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSYERROR) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBERROR)) { + return s->regs[R_SBDATA1]; + } + return (uint32_t)val64; +} + +static uint64_t dm_sbdata_hi_post_read(RegisterInfo *reg, uint64_t val) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, SBCS, SBBUSY)) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBBUSYERROR, 1); + } + return val; +} + static uint64_t dm_haltsum0_post_read(RegisterInfo *reg, uint64_t val) { RISCVDMState *s =3D RISCV_DM(reg->opaque); @@ -1287,20 +1500,31 @@ static RegisterAccessInfo riscv_dm_regs_info[] =3D { .ro =3D R_SBCS_SBACCESS8_MASK | R_SBCS_SBACCESS16_MASK | R_SBCS_SBACCESS32_MASK | R_SBCS_SBACCESS64_MASK | R_SBCS_SBACCESS128_MASK | R_SBCS_SBASIZE_MASK | - R_SBCS_SBBUSY_MASK | R_SBCS_SBVERSION_MASK, }, + R_SBCS_SBBUSY_MASK | R_SBCS_SBVERSION_MASK, + .pre_write =3D dm_sbcs_pre_write, }, =20 - { .name =3D "SBADDRESS0", .addr =3D A_SBADDRESS0, }, + { .name =3D "SBADDRESS0", .addr =3D A_SBADDRESS0, + .post_write =3D dm_sbaddress0_post_write, }, =20 - { .name =3D "SBADDRESS1", .addr =3D A_SBADDRESS1, }, + { .name =3D "SBADDRESS1", .addr =3D A_SBADDRESS1, + .pre_write =3D dm_sbaddress1_pre_write, }, =20 { .name =3D "SBADDRESS2", .addr =3D A_SBADDRESS2, }, =20 - { .name =3D "SBDATA0", .addr =3D A_SBDATA0, }, + { .name =3D "SBDATA0", .addr =3D A_SBDATA0, + .post_write =3D dm_sbdata0_post_write, + .post_read =3D dm_sbdata0_post_read, }, =20 - { .name =3D "SBDATA1", .addr =3D A_SBDATA1, }, + { .name =3D "SBDATA1", .addr =3D A_SBDATA1, + .pre_write =3D dm_sbdata1_pre_write, + .post_read =3D dm_sbdata_hi_post_read, }, =20 - { .name =3D "SBDATA2", .addr =3D A_SBDATA2, }, - { .name =3D "SBDATA3", .addr =3D A_SBDATA3, }, + { .name =3D "SBDATA2", .addr =3D A_SBDATA2, + .pre_write =3D dm_sbdata1_pre_write, + .post_read =3D dm_sbdata_hi_post_read, }, + { .name =3D "SBDATA3", .addr =3D A_SBDATA3, + .pre_write =3D dm_sbdata1_pre_write, + .post_read =3D dm_sbdata_hi_post_read, }, =20 { .name =3D "HALTSUM0", .addr =3D A_HALTSUM0, .ro =3D 0xFFFFFFFF, @@ -1602,6 +1826,17 @@ static void dm_debug_reset(RISCVDMState *s) ARRAY_FIELD_DP32(s->regs, ABSTRACTCS, DATACOUNT, s->num_abstract_data); ARRAY_FIELD_DP32(s->regs, ABSTRACTCS, PROGBUFSIZE, s->progbuf_size); =20 + /* SBA capabilities */ + if (s->sba_addr_width > 0) { + ARRAY_FIELD_DP32(s->regs, SBCS, SBACCESS8, 1); + ARRAY_FIELD_DP32(s->regs, SBCS, SBACCESS16, 1); + ARRAY_FIELD_DP32(s->regs, SBCS, SBACCESS32, 1); + ARRAY_FIELD_DP32(s->regs, SBCS, SBACCESS64, 1); + ARRAY_FIELD_DP32(s->regs, SBCS, SBASIZE, s->sba_addr_width); + ARRAY_FIELD_DP32(s->regs, SBCS, SBACCESS, 2); /* default 32-bit */ + ARRAY_FIELD_DP32(s->regs, SBCS, SBVERSION, 1); + } + /* Reset per-hart state */ if (s->hart_resumeack && s->num_harts > 0) { for (uint32_t i =3D 0; i < s->num_harts; i++) { --=20 2.53.0