From nobody Mon Feb 9 07:06:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492789522821583.3422086433814; Fri, 21 Apr 2017 08:45:22 -0700 (PDT) Received: from localhost ([::1]:60264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d1akL-0000tl-25 for importer@patchew.org; Fri, 21 Apr 2017 11:45:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49976) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d1aWG-0001TH-0T for qemu-devel@nongnu.org; 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[Qemu-devel] [PATCH v7 01/13] sm501: Fixed code style and a few typos in comments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Magnus Damm , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: BALATON Zoltan Reviewed-by: Peter Maydell Tested-by: Aurelien Jarno --- hw/display/sm501.c | 1132 ++++++++++++++++++++++-----------------= ---- hw/display/sm501_template.h | 52 +- 2 files changed, 594 insertions(+), 590 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 040a0b9..4f40dee 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -38,7 +38,7 @@ /* * Status: 2010/05/07 * - Minimum implementation for Linux console : mmio regs and CRT layer. - * - 2D grapihcs acceleration partially supported : only fill rectangle. + * - 2D graphics acceleration partially supported : only fill rectangle. * * TODO: * - Panel support @@ -49,13 +49,13 @@ * - Performance tuning */ =20 -//#define DEBUG_SM501 -//#define DEBUG_BITBLT +/*#define DEBUG_SM501*/ +/*#define DEBUG_BITBLT*/ =20 #ifdef DEBUG_SM501 #define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__) #else -#define SM501_DPRINTF(fmt, ...) do {} while(0) +#define SM501_DPRINTF(fmt, ...) do {} while (0) #endif =20 =20 @@ -65,379 +65,379 @@ =20 /* System Configuration area */ /* System config base */ -#define SM501_SYS_CONFIG (0x000000) +#define SM501_SYS_CONFIG (0x000000) =20 /* config 1 */ -#define SM501_SYSTEM_CONTROL (0x000000) +#define SM501_SYSTEM_CONTROL (0x000000) =20 -#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) -#define SM501_SYSCTRL_MEM_TRISTATE (1<<1) -#define SM501_SYSCTRL_CRT_TRISTATE (1<<2) +#define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0) +#define SM501_SYSCTRL_MEM_TRISTATE (1 << 1) +#define SM501_SYSCTRL_CRT_TRISTATE (1 << 2) =20 -#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) -#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) -#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) -#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) -#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4) =20 -#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) -#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) -#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) -#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) +#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6) +#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7) +#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11) +#define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15) =20 /* miscellaneous control */ =20 -#define SM501_MISC_CONTROL (0x000004) +#define SM501_MISC_CONTROL (0x000004) =20 -#define SM501_MISC_BUS_SH (0x0) -#define SM501_MISC_BUS_PCI (0x1) -#define SM501_MISC_BUS_XSCALE (0x2) -#define SM501_MISC_BUS_NEC (0x6) -#define SM501_MISC_BUS_MASK (0x7) +#define SM501_MISC_BUS_SH (0x0) +#define SM501_MISC_BUS_PCI (0x1) +#define SM501_MISC_BUS_XSCALE (0x2) +#define SM501_MISC_BUS_NEC (0x6) +#define SM501_MISC_BUS_MASK (0x7) =20 -#define SM501_MISC_VR_62MB (1<<3) -#define SM501_MISC_CDR_RESET (1<<7) -#define SM501_MISC_USB_LB (1<<8) -#define SM501_MISC_USB_SLAVE (1<<9) -#define SM501_MISC_BL_1 (1<<10) -#define SM501_MISC_MC (1<<11) -#define SM501_MISC_DAC_POWER (1<<12) -#define SM501_MISC_IRQ_INVERT (1<<16) -#define SM501_MISC_SH (1<<17) +#define SM501_MISC_VR_62MB (1 << 3) +#define SM501_MISC_CDR_RESET (1 << 7) +#define SM501_MISC_USB_LB (1 << 8) +#define SM501_MISC_USB_SLAVE (1 << 9) +#define SM501_MISC_BL_1 (1 << 10) +#define SM501_MISC_MC (1 << 11) +#define SM501_MISC_DAC_POWER (1 << 12) +#define SM501_MISC_IRQ_INVERT (1 << 16) +#define SM501_MISC_SH (1 << 17) =20 -#define SM501_MISC_HOLD_EMPTY (0<<18) -#define SM501_MISC_HOLD_8 (1<<18) -#define SM501_MISC_HOLD_16 (2<<18) -#define SM501_MISC_HOLD_24 (3<<18) -#define SM501_MISC_HOLD_32 (4<<18) -#define SM501_MISC_HOLD_MASK (7<<18) +#define SM501_MISC_HOLD_EMPTY (0 << 18) +#define SM501_MISC_HOLD_8 (1 << 18) +#define SM501_MISC_HOLD_16 (2 << 18) +#define SM501_MISC_HOLD_24 (3 << 18) +#define SM501_MISC_HOLD_32 (4 << 18) +#define SM501_MISC_HOLD_MASK (7 << 18) =20 -#define SM501_MISC_FREQ_12 (1<<24) -#define SM501_MISC_PNL_24BIT (1<<25) -#define SM501_MISC_8051_LE (1<<26) +#define SM501_MISC_FREQ_12 (1 << 24) +#define SM501_MISC_PNL_24BIT (1 << 25) +#define SM501_MISC_8051_LE (1 << 26) =20 =20 =20 -#define SM501_GPIO31_0_CONTROL (0x000008) -#define SM501_GPIO63_32_CONTROL (0x00000C) -#define SM501_DRAM_CONTROL (0x000010) +#define SM501_GPIO31_0_CONTROL (0x000008) +#define SM501_GPIO63_32_CONTROL (0x00000C) +#define SM501_DRAM_CONTROL (0x000010) =20 /* command list */ -#define SM501_ARBTRTN_CONTROL (0x000014) +#define SM501_ARBTRTN_CONTROL (0x000014) =20 /* command list */ -#define SM501_COMMAND_LIST_STATUS (0x000024) +#define SM501_COMMAND_LIST_STATUS (0x000024) =20 /* interrupt debug */ -#define SM501_RAW_IRQ_STATUS (0x000028) -#define SM501_RAW_IRQ_CLEAR (0x000028) -#define SM501_IRQ_STATUS (0x00002C) -#define SM501_IRQ_MASK (0x000030) -#define SM501_DEBUG_CONTROL (0x000034) +#define SM501_RAW_IRQ_STATUS (0x000028) +#define SM501_RAW_IRQ_CLEAR (0x000028) +#define SM501_IRQ_STATUS (0x00002C) +#define SM501_IRQ_MASK (0x000030) +#define SM501_DEBUG_CONTROL (0x000034) =20 /* power management */ -#define SM501_POWERMODE_P2X_SRC (1<<29) -#define SM501_POWERMODE_V2X_SRC (1<<20) -#define SM501_POWERMODE_M_SRC (1<<12) -#define SM501_POWERMODE_M1_SRC (1<<4) - -#define SM501_CURRENT_GATE (0x000038) -#define SM501_CURRENT_CLOCK (0x00003C) -#define SM501_POWER_MODE_0_GATE (0x000040) -#define SM501_POWER_MODE_0_CLOCK (0x000044) -#define SM501_POWER_MODE_1_GATE (0x000048) -#define SM501_POWER_MODE_1_CLOCK (0x00004C) -#define SM501_SLEEP_MODE_GATE (0x000050) -#define SM501_POWER_MODE_CONTROL (0x000054) +#define SM501_POWERMODE_P2X_SRC (1 << 29) +#define SM501_POWERMODE_V2X_SRC (1 << 20) +#define SM501_POWERMODE_M_SRC (1 << 12) +#define SM501_POWERMODE_M1_SRC (1 << 4) + +#define SM501_CURRENT_GATE (0x000038) +#define SM501_CURRENT_CLOCK (0x00003C) +#define SM501_POWER_MODE_0_GATE (0x000040) +#define SM501_POWER_MODE_0_CLOCK (0x000044) +#define SM501_POWER_MODE_1_GATE (0x000048) +#define SM501_POWER_MODE_1_CLOCK (0x00004C) +#define SM501_SLEEP_MODE_GATE (0x000050) +#define SM501_POWER_MODE_CONTROL (0x000054) =20 /* power gates for units within the 501 */ -#define SM501_GATE_HOST (0) -#define SM501_GATE_MEMORY (1) -#define SM501_GATE_DISPLAY (2) -#define SM501_GATE_2D_ENGINE (3) -#define SM501_GATE_CSC (4) -#define SM501_GATE_ZVPORT (5) -#define SM501_GATE_GPIO (6) -#define SM501_GATE_UART0 (7) -#define SM501_GATE_UART1 (8) -#define SM501_GATE_SSP (10) -#define SM501_GATE_USB_HOST (11) -#define SM501_GATE_USB_GADGET (12) -#define SM501_GATE_UCONTROLLER (17) -#define SM501_GATE_AC97 (18) +#define SM501_GATE_HOST (0) +#define SM501_GATE_MEMORY (1) +#define SM501_GATE_DISPLAY (2) +#define SM501_GATE_2D_ENGINE (3) +#define SM501_GATE_CSC (4) +#define SM501_GATE_ZVPORT (5) +#define SM501_GATE_GPIO (6) +#define SM501_GATE_UART0 (7) +#define SM501_GATE_UART1 (8) +#define SM501_GATE_SSP (10) +#define SM501_GATE_USB_HOST (11) +#define SM501_GATE_USB_GADGET (12) +#define SM501_GATE_UCONTROLLER (17) +#define SM501_GATE_AC97 (18) =20 /* panel clock */ -#define SM501_CLOCK_P2XCLK (24) +#define SM501_CLOCK_P2XCLK (24) /* crt clock */ -#define SM501_CLOCK_V2XCLK (16) +#define SM501_CLOCK_V2XCLK (16) /* main clock */ -#define SM501_CLOCK_MCLK (8) +#define SM501_CLOCK_MCLK (8) /* SDRAM controller clock */ -#define SM501_CLOCK_M1XCLK (0) +#define SM501_CLOCK_M1XCLK (0) =20 /* config 2 */ -#define SM501_PCI_MASTER_BASE (0x000058) -#define SM501_ENDIAN_CONTROL (0x00005C) -#define SM501_DEVICEID (0x000060) +#define SM501_PCI_MASTER_BASE (0x000058) +#define SM501_ENDIAN_CONTROL (0x00005C) +#define SM501_DEVICEID (0x000060) /* 0x050100A0 */ =20 -#define SM501_DEVICEID_SM501 (0x05010000) -#define SM501_DEVICEID_IDMASK (0xffff0000) -#define SM501_DEVICEID_REVMASK (0x000000ff) +#define SM501_DEVICEID_SM501 (0x05010000) +#define SM501_DEVICEID_IDMASK (0xffff0000) +#define SM501_DEVICEID_REVMASK (0x000000ff) =20 -#define SM501_PLLCLOCK_COUNT (0x000064) -#define SM501_MISC_TIMING (0x000068) -#define SM501_CURRENT_SDRAM_CLOCK (0x00006C) +#define SM501_PLLCLOCK_COUNT (0x000064) +#define SM501_MISC_TIMING (0x000068) +#define SM501_CURRENT_SDRAM_CLOCK (0x00006C) =20 -#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) +#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) =20 /* GPIO base */ -#define SM501_GPIO (0x010000) -#define SM501_GPIO_DATA_LOW (0x00) -#define SM501_GPIO_DATA_HIGH (0x04) -#define SM501_GPIO_DDR_LOW (0x08) -#define SM501_GPIO_DDR_HIGH (0x0C) -#define SM501_GPIO_IRQ_SETUP (0x10) -#define SM501_GPIO_IRQ_STATUS (0x14) -#define SM501_GPIO_IRQ_RESET (0x14) +#define SM501_GPIO (0x010000) +#define SM501_GPIO_DATA_LOW (0x00) +#define SM501_GPIO_DATA_HIGH (0x04) +#define SM501_GPIO_DDR_LOW (0x08) +#define SM501_GPIO_DDR_HIGH (0x0C) +#define SM501_GPIO_IRQ_SETUP (0x10) +#define SM501_GPIO_IRQ_STATUS (0x14) +#define SM501_GPIO_IRQ_RESET (0x14) =20 /* I2C controller base */ -#define SM501_I2C (0x010040) -#define SM501_I2C_BYTE_COUNT (0x00) -#define SM501_I2C_CONTROL (0x01) -#define SM501_I2C_STATUS (0x02) -#define SM501_I2C_RESET (0x02) -#define SM501_I2C_SLAVE_ADDRESS (0x03) -#define SM501_I2C_DATA (0x04) +#define SM501_I2C (0x010040) +#define SM501_I2C_BYTE_COUNT (0x00) +#define SM501_I2C_CONTROL (0x01) +#define SM501_I2C_STATUS (0x02) +#define SM501_I2C_RESET (0x02) +#define SM501_I2C_SLAVE_ADDRESS (0x03) +#define SM501_I2C_DATA (0x04) =20 /* SSP base */ -#define SM501_SSP (0x020000) +#define SM501_SSP (0x020000) =20 /* Uart 0 base */ -#define SM501_UART0 (0x030000) +#define SM501_UART0 (0x030000) =20 /* Uart 1 base */ -#define SM501_UART1 (0x030020) +#define SM501_UART1 (0x030020) =20 /* USB host port base */ -#define SM501_USB_HOST (0x040000) +#define SM501_USB_HOST (0x040000) =20 /* USB slave/gadget base */ -#define SM501_USB_GADGET (0x060000) +#define SM501_USB_GADGET (0x060000) =20 /* USB slave/gadget data port base */ -#define SM501_USB_GADGET_DATA (0x070000) +#define SM501_USB_GADGET_DATA (0x070000) =20 /* Display controller/video engine base */ -#define SM501_DC (0x080000) +#define SM501_DC (0x080000) =20 /* common defines for the SM501 address registers */ -#define SM501_ADDR_FLIP (1<<31) -#define SM501_ADDR_EXT (1<<27) -#define SM501_ADDR_CS1 (1<<26) -#define SM501_ADDR_MASK (0x3f << 26) +#define SM501_ADDR_FLIP (1 << 31) +#define SM501_ADDR_EXT (1 << 27) +#define SM501_ADDR_CS1 (1 << 26) +#define SM501_ADDR_MASK (0x3f << 26) =20 -#define SM501_FIFO_MASK (0x3 << 16) -#define SM501_FIFO_1 (0x0 << 16) -#define SM501_FIFO_3 (0x1 << 16) -#define SM501_FIFO_7 (0x2 << 16) -#define SM501_FIFO_11 (0x3 << 16) +#define SM501_FIFO_MASK (0x3 << 16) +#define SM501_FIFO_1 (0x0 << 16) +#define SM501_FIFO_3 (0x1 << 16) +#define SM501_FIFO_7 (0x2 << 16) +#define SM501_FIFO_11 (0x3 << 16) =20 /* common registers for panel and the crt */ -#define SM501_OFF_DC_H_TOT (0x000) -#define SM501_OFF_DC_V_TOT (0x008) -#define SM501_OFF_DC_H_SYNC (0x004) -#define SM501_OFF_DC_V_SYNC (0x00C) - -#define SM501_DC_PANEL_CONTROL (0x000) - -#define SM501_DC_PANEL_CONTROL_FPEN (1<<27) -#define SM501_DC_PANEL_CONTROL_BIAS (1<<26) -#define SM501_DC_PANEL_CONTROL_DATA (1<<25) -#define SM501_DC_PANEL_CONTROL_VDD (1<<24) -#define SM501_DC_PANEL_CONTROL_DP (1<<23) - -#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) -#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) -#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) - -#define SM501_DC_PANEL_CONTROL_DE (1<<20) - -#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) -#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) -#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) - -#define SM501_DC_PANEL_CONTROL_CP (1<<14) -#define SM501_DC_PANEL_CONTROL_VSP (1<<13) -#define SM501_DC_PANEL_CONTROL_HSP (1<<12) -#define SM501_DC_PANEL_CONTROL_CK (1<<9) -#define SM501_DC_PANEL_CONTROL_TE (1<<8) -#define SM501_DC_PANEL_CONTROL_VPD (1<<7) -#define SM501_DC_PANEL_CONTROL_VP (1<<6) -#define SM501_DC_PANEL_CONTROL_HPD (1<<5) -#define SM501_DC_PANEL_CONTROL_HP (1<<4) -#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) -#define SM501_DC_PANEL_CONTROL_EN (1<<2) - -#define SM501_DC_PANEL_CONTROL_8BPP (0<<0) -#define SM501_DC_PANEL_CONTROL_16BPP (1<<0) -#define SM501_DC_PANEL_CONTROL_32BPP (2<<0) - - -#define SM501_DC_PANEL_PANNING_CONTROL (0x004) -#define SM501_DC_PANEL_COLOR_KEY (0x008) -#define SM501_DC_PANEL_FB_ADDR (0x00C) -#define SM501_DC_PANEL_FB_OFFSET (0x010) -#define SM501_DC_PANEL_FB_WIDTH (0x014) -#define SM501_DC_PANEL_FB_HEIGHT (0x018) -#define SM501_DC_PANEL_TL_LOC (0x01C) -#define SM501_DC_PANEL_BR_LOC (0x020) -#define SM501_DC_PANEL_H_TOT (0x024) -#define SM501_DC_PANEL_H_SYNC (0x028) -#define SM501_DC_PANEL_V_TOT (0x02C) -#define SM501_DC_PANEL_V_SYNC (0x030) -#define SM501_DC_PANEL_CUR_LINE (0x034) - -#define SM501_DC_VIDEO_CONTROL (0x040) -#define SM501_DC_VIDEO_FB0_ADDR (0x044) -#define SM501_DC_VIDEO_FB_WIDTH (0x048) -#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) -#define SM501_DC_VIDEO_TL_LOC (0x050) -#define SM501_DC_VIDEO_BR_LOC (0x054) -#define SM501_DC_VIDEO_SCALE (0x058) -#define SM501_DC_VIDEO_INIT_SCALE (0x05C) -#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) -#define SM501_DC_VIDEO_FB1_ADDR (0x064) -#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) - -#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) -#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) -#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) -#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) -#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) -#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) -#define SM501_DC_VIDEO_ALPHA_SCALE (0x098) -#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) -#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) -#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) - -#define SM501_DC_PANEL_HWC_BASE (0x0F0) -#define SM501_DC_PANEL_HWC_ADDR (0x0F0) -#define SM501_DC_PANEL_HWC_LOC (0x0F4) -#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) -#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) - -#define SM501_HWC_EN (1<<31) - -#define SM501_OFF_HWC_ADDR (0x00) -#define SM501_OFF_HWC_LOC (0x04) -#define SM501_OFF_HWC_COLOR_1_2 (0x08) -#define SM501_OFF_HWC_COLOR_3 (0x0C) - -#define SM501_DC_ALPHA_CONTROL (0x100) -#define SM501_DC_ALPHA_FB_ADDR (0x104) -#define SM501_DC_ALPHA_FB_OFFSET (0x108) -#define SM501_DC_ALPHA_TL_LOC (0x10C) -#define SM501_DC_ALPHA_BR_LOC (0x110) -#define SM501_DC_ALPHA_CHROMA_KEY (0x114) -#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) - -#define SM501_DC_CRT_CONTROL (0x200) - -#define SM501_DC_CRT_CONTROL_TVP (1<<15) -#define SM501_DC_CRT_CONTROL_CP (1<<14) -#define SM501_DC_CRT_CONTROL_VSP (1<<13) -#define SM501_DC_CRT_CONTROL_HSP (1<<12) -#define SM501_DC_CRT_CONTROL_VS (1<<11) -#define SM501_DC_CRT_CONTROL_BLANK (1<<10) -#define SM501_DC_CRT_CONTROL_SEL (1<<9) -#define SM501_DC_CRT_CONTROL_TE (1<<8) +#define SM501_OFF_DC_H_TOT (0x000) +#define SM501_OFF_DC_V_TOT (0x008) +#define SM501_OFF_DC_H_SYNC (0x004) +#define SM501_OFF_DC_V_SYNC (0x00C) + +#define SM501_DC_PANEL_CONTROL (0x000) + +#define SM501_DC_PANEL_CONTROL_FPEN (1 << 27) +#define SM501_DC_PANEL_CONTROL_BIAS (1 << 26) +#define SM501_DC_PANEL_CONTROL_DATA (1 << 25) +#define SM501_DC_PANEL_CONTROL_VDD (1 << 24) +#define SM501_DC_PANEL_CONTROL_DP (1 << 23) + +#define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21) +#define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21) +#define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21) + +#define SM501_DC_PANEL_CONTROL_DE (1 << 20) + +#define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18) +#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18) +#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18) + +#define SM501_DC_PANEL_CONTROL_CP (1 << 14) +#define SM501_DC_PANEL_CONTROL_VSP (1 << 13) +#define SM501_DC_PANEL_CONTROL_HSP (1 << 12) +#define SM501_DC_PANEL_CONTROL_CK (1 << 9) +#define SM501_DC_PANEL_CONTROL_TE (1 << 8) +#define SM501_DC_PANEL_CONTROL_VPD (1 << 7) +#define SM501_DC_PANEL_CONTROL_VP (1 << 6) +#define SM501_DC_PANEL_CONTROL_HPD (1 << 5) +#define SM501_DC_PANEL_CONTROL_HP (1 << 4) +#define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3) +#define SM501_DC_PANEL_CONTROL_EN (1 << 2) + +#define SM501_DC_PANEL_CONTROL_8BPP (0 << 0) +#define SM501_DC_PANEL_CONTROL_16BPP (1 << 0) +#define SM501_DC_PANEL_CONTROL_32BPP (2 << 0) + + +#define SM501_DC_PANEL_PANNING_CONTROL (0x004) +#define SM501_DC_PANEL_COLOR_KEY (0x008) +#define SM501_DC_PANEL_FB_ADDR (0x00C) +#define SM501_DC_PANEL_FB_OFFSET (0x010) +#define SM501_DC_PANEL_FB_WIDTH (0x014) +#define SM501_DC_PANEL_FB_HEIGHT (0x018) +#define SM501_DC_PANEL_TL_LOC (0x01C) +#define SM501_DC_PANEL_BR_LOC (0x020) +#define SM501_DC_PANEL_H_TOT (0x024) +#define SM501_DC_PANEL_H_SYNC (0x028) +#define SM501_DC_PANEL_V_TOT (0x02C) +#define SM501_DC_PANEL_V_SYNC (0x030) +#define SM501_DC_PANEL_CUR_LINE (0x034) + +#define SM501_DC_VIDEO_CONTROL (0x040) +#define SM501_DC_VIDEO_FB0_ADDR (0x044) +#define SM501_DC_VIDEO_FB_WIDTH (0x048) +#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) +#define SM501_DC_VIDEO_TL_LOC (0x050) +#define SM501_DC_VIDEO_BR_LOC (0x054) +#define SM501_DC_VIDEO_SCALE (0x058) +#define SM501_DC_VIDEO_INIT_SCALE (0x05C) +#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) +#define SM501_DC_VIDEO_FB1_ADDR (0x064) +#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) + +#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) +#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) +#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) +#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) +#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) +#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) +#define SM501_DC_VIDEO_ALPHA_SCALE (0x098) +#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) +#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) +#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) + +#define SM501_DC_PANEL_HWC_BASE (0x0F0) +#define SM501_DC_PANEL_HWC_ADDR (0x0F0) +#define SM501_DC_PANEL_HWC_LOC (0x0F4) +#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) +#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) + +#define SM501_HWC_EN (1 << 31) + +#define SM501_OFF_HWC_ADDR (0x00) +#define SM501_OFF_HWC_LOC (0x04) +#define SM501_OFF_HWC_COLOR_1_2 (0x08) +#define SM501_OFF_HWC_COLOR_3 (0x0C) + +#define SM501_DC_ALPHA_CONTROL (0x100) +#define SM501_DC_ALPHA_FB_ADDR (0x104) +#define SM501_DC_ALPHA_FB_OFFSET (0x108) +#define SM501_DC_ALPHA_TL_LOC (0x10C) +#define SM501_DC_ALPHA_BR_LOC (0x110) +#define SM501_DC_ALPHA_CHROMA_KEY (0x114) +#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) + +#define SM501_DC_CRT_CONTROL (0x200) + +#define SM501_DC_CRT_CONTROL_TVP (1 << 15) +#define SM501_DC_CRT_CONTROL_CP (1 << 14) +#define SM501_DC_CRT_CONTROL_VSP (1 << 13) +#define SM501_DC_CRT_CONTROL_HSP (1 << 12) +#define SM501_DC_CRT_CONTROL_VS (1 << 11) +#define SM501_DC_CRT_CONTROL_BLANK (1 << 10) +#define SM501_DC_CRT_CONTROL_SEL (1 << 9) +#define SM501_DC_CRT_CONTROL_TE (1 << 8) #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) -#define SM501_DC_CRT_CONTROL_GAMMA (1<<3) -#define SM501_DC_CRT_CONTROL_ENABLE (1<<2) +#define SM501_DC_CRT_CONTROL_GAMMA (1 << 3) +#define SM501_DC_CRT_CONTROL_ENABLE (1 << 2) =20 -#define SM501_DC_CRT_CONTROL_8BPP (0<<0) -#define SM501_DC_CRT_CONTROL_16BPP (1<<0) -#define SM501_DC_CRT_CONTROL_32BPP (2<<0) +#define SM501_DC_CRT_CONTROL_8BPP (0 << 0) +#define SM501_DC_CRT_CONTROL_16BPP (1 << 0) +#define SM501_DC_CRT_CONTROL_32BPP (2 << 0) =20 -#define SM501_DC_CRT_FB_ADDR (0x204) -#define SM501_DC_CRT_FB_OFFSET (0x208) -#define SM501_DC_CRT_H_TOT (0x20C) -#define SM501_DC_CRT_H_SYNC (0x210) -#define SM501_DC_CRT_V_TOT (0x214) -#define SM501_DC_CRT_V_SYNC (0x218) -#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) -#define SM501_DC_CRT_CUR_LINE (0x220) -#define SM501_DC_CRT_MONITOR_DETECT (0x224) +#define SM501_DC_CRT_FB_ADDR (0x204) +#define SM501_DC_CRT_FB_OFFSET (0x208) +#define SM501_DC_CRT_H_TOT (0x20C) +#define SM501_DC_CRT_H_SYNC (0x210) +#define SM501_DC_CRT_V_TOT (0x214) +#define SM501_DC_CRT_V_SYNC (0x218) +#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) +#define SM501_DC_CRT_CUR_LINE (0x220) +#define SM501_DC_CRT_MONITOR_DETECT (0x224) =20 -#define SM501_DC_CRT_HWC_BASE (0x230) -#define SM501_DC_CRT_HWC_ADDR (0x230) -#define SM501_DC_CRT_HWC_LOC (0x234) -#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) -#define SM501_DC_CRT_HWC_COLOR_3 (0x23C) +#define SM501_DC_CRT_HWC_BASE (0x230) +#define SM501_DC_CRT_HWC_ADDR (0x230) +#define SM501_DC_CRT_HWC_LOC (0x234) +#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) +#define SM501_DC_CRT_HWC_COLOR_3 (0x23C) =20 -#define SM501_DC_PANEL_PALETTE (0x400) +#define SM501_DC_PANEL_PALETTE (0x400) =20 -#define SM501_DC_VIDEO_PALETTE (0x800) +#define SM501_DC_VIDEO_PALETTE (0x800) =20 -#define SM501_DC_CRT_PALETTE (0xC00) +#define SM501_DC_CRT_PALETTE (0xC00) =20 /* Zoom Video port base */ -#define SM501_ZVPORT (0x090000) +#define SM501_ZVPORT (0x090000) =20 /* AC97/I2S base */ -#define SM501_AC97 (0x0A0000) +#define SM501_AC97 (0x0A0000) =20 /* 8051 micro controller base */ -#define SM501_UCONTROLLER (0x0B0000) +#define SM501_UCONTROLLER (0x0B0000) =20 /* 8051 micro controller SRAM base */ -#define SM501_UCONTROLLER_SRAM (0x0C0000) +#define SM501_UCONTROLLER_SRAM (0x0C0000) =20 /* DMA base */ -#define SM501_DMA (0x0D0000) +#define SM501_DMA (0x0D0000) =20 /* 2d engine base */ -#define SM501_2D_ENGINE (0x100000) -#define SM501_2D_SOURCE (0x00) -#define SM501_2D_DESTINATION (0x04) -#define SM501_2D_DIMENSION (0x08) -#define SM501_2D_CONTROL (0x0C) -#define SM501_2D_PITCH (0x10) -#define SM501_2D_FOREGROUND (0x14) -#define SM501_2D_BACKGROUND (0x18) -#define SM501_2D_STRETCH (0x1C) -#define SM501_2D_COLOR_COMPARE (0x20) -#define SM501_2D_COLOR_COMPARE_MASK (0x24) -#define SM501_2D_MASK (0x28) -#define SM501_2D_CLIP_TL (0x2C) -#define SM501_2D_CLIP_BR (0x30) -#define SM501_2D_MONO_PATTERN_LOW (0x34) -#define SM501_2D_MONO_PATTERN_HIGH (0x38) -#define SM501_2D_WINDOW_WIDTH (0x3C) -#define SM501_2D_SOURCE_BASE (0x40) -#define SM501_2D_DESTINATION_BASE (0x44) -#define SM501_2D_ALPHA (0x48) -#define SM501_2D_WRAP (0x4C) -#define SM501_2D_STATUS (0x50) - -#define SM501_CSC_Y_SOURCE_BASE (0xC8) -#define SM501_CSC_CONSTANTS (0xCC) -#define SM501_CSC_Y_SOURCE_X (0xD0) -#define SM501_CSC_Y_SOURCE_Y (0xD4) -#define SM501_CSC_U_SOURCE_BASE (0xD8) -#define SM501_CSC_V_SOURCE_BASE (0xDC) -#define SM501_CSC_SOURCE_DIMENSION (0xE0) -#define SM501_CSC_SOURCE_PITCH (0xE4) -#define SM501_CSC_DESTINATION (0xE8) -#define SM501_CSC_DESTINATION_DIMENSION (0xEC) -#define SM501_CSC_DESTINATION_PITCH (0xF0) -#define SM501_CSC_SCALE_FACTOR (0xF4) -#define SM501_CSC_DESTINATION_BASE (0xF8) -#define SM501_CSC_CONTROL (0xFC) +#define SM501_2D_ENGINE (0x100000) +#define SM501_2D_SOURCE (0x00) +#define SM501_2D_DESTINATION (0x04) +#define SM501_2D_DIMENSION (0x08) +#define SM501_2D_CONTROL (0x0C) +#define SM501_2D_PITCH (0x10) +#define SM501_2D_FOREGROUND (0x14) +#define SM501_2D_BACKGROUND (0x18) +#define SM501_2D_STRETCH (0x1C) +#define SM501_2D_COLOR_COMPARE (0x20) +#define SM501_2D_COLOR_COMPARE_MASK (0x24) +#define SM501_2D_MASK (0x28) +#define SM501_2D_CLIP_TL (0x2C) +#define SM501_2D_CLIP_BR (0x30) +#define SM501_2D_MONO_PATTERN_LOW (0x34) +#define SM501_2D_MONO_PATTERN_HIGH (0x38) +#define SM501_2D_WINDOW_WIDTH (0x3C) +#define SM501_2D_SOURCE_BASE (0x40) +#define SM501_2D_DESTINATION_BASE (0x44) +#define SM501_2D_ALPHA (0x48) +#define SM501_2D_WRAP (0x4C) +#define SM501_2D_STATUS (0x50) + +#define SM501_CSC_Y_SOURCE_BASE (0xC8) +#define SM501_CSC_CONSTANTS (0xCC) +#define SM501_CSC_Y_SOURCE_X (0xD0) +#define SM501_CSC_Y_SOURCE_Y (0xD4) +#define SM501_CSC_U_SOURCE_BASE (0xD8) +#define SM501_CSC_V_SOURCE_BASE (0xDC) +#define SM501_CSC_SOURCE_DIMENSION (0xE0) +#define SM501_CSC_SOURCE_PITCH (0xE4) +#define SM501_CSC_DESTINATION (0xE8) +#define SM501_CSC_DESTINATION_DIMENSION (0xEC) +#define SM501_CSC_DESTINATION_PITCH (0xF0) +#define SM501_CSC_SCALE_FACTOR (0xF4) +#define SM501_CSC_DESTINATION_BASE (0xF8) +#define SM501_CSC_CONTROL (0xFC) =20 /* 2d engine data port base */ -#define SM501_2D_ENGINE_DATA (0x110000) +#define SM501_2D_ENGINE_DATA (0x110000) =20 /* end of register definitions */ =20 @@ -446,12 +446,12 @@ =20 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */ static const uint32_t sm501_mem_local_size[] =3D { - [0] =3D 4*1024*1024, - [1] =3D 8*1024*1024, - [2] =3D 16*1024*1024, - [3] =3D 32*1024*1024, - [4] =3D 64*1024*1024, - [5] =3D 2*1024*1024, + [0] =3D 4 * 1024 * 1024, + [1] =3D 8 * 1024 * 1024, + [2] =3D 16 * 1024 * 1024, + [3] =3D 32 * 1024 * 1024, + [4] =3D 64 * 1024 * 1024, + [5] =3D 2 * 1024 * 1024, }; #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_ind= ex] =20 @@ -462,7 +462,7 @@ typedef struct SM501State { /* status & internal resources */ hwaddr base; uint32_t local_mem_size_index; - uint8_t * local_mem; + uint8_t *local_mem; MemoryRegion local_mem_region; uint32_t last_width; uint32_t last_height; @@ -536,13 +536,13 @@ static uint32_t get_local_mem_size_index(uint32_t siz= e) int i, index =3D 0; =20 for (i =3D 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) { - uint32_t new_size =3D sm501_mem_local_size[i]; - if (new_size >=3D size) { - if (norm_size =3D=3D 0 || norm_size > new_size) { - norm_size =3D new_size; - index =3D i; - } - } + uint32_t new_size =3D sm501_mem_local_size[i]; + if (new_size >=3D size) { + if (norm_size =3D=3D 0 || norm_size > new_size) { + norm_size =3D new_size; + index =3D i; + } + } } =20 return index; @@ -637,7 +637,7 @@ static int within_hwc_y_range(SM501State *state, int y,= int crt) return (hwc_y <=3D y && y < hwc_y + SM501_HWC_HEIGHT); } =20 -static void sm501_2d_operation(SM501State * s) +static void sm501_2d_operation(SM501State *s) { /* obtain operation parameters */ int operation =3D (s->twoD_control >> 16) & 0x1f; @@ -653,8 +653,8 @@ static void sm501_2d_operation(SM501State * s) int addressing =3D (s->twoD_stretch >> 16) & 0xF; =20 /* get frame buffer info */ - uint8_t * src =3D s->local_mem + (s->twoD_source_base & 0x03FFFFFF); - uint8_t * dst =3D s->local_mem + (s->twoD_destination_base & 0x03FFFFF= F); + uint8_t *src =3D s->local_mem + (s->twoD_source_base & 0x03FFFFFF); + uint8_t *dst =3D s->local_mem + (s->twoD_destination_base & 0x03FFFFFF= ); int src_width =3D (s->dc_crt_h_total & 0x00000FFF) + 1; int dst_width =3D (s->dc_crt_h_total & 0x00000FFF) + 1; =20 @@ -671,20 +671,20 @@ static void sm501_2d_operation(SM501State * s) =20 switch (operation) { case 0x00: /* copy area */ -#define COPY_AREA(_bpp, _pixel_type, rtl) { = \ - int y, x, index_d, index_s; = \ - for (y =3D 0; y < operation_height; y++) { = \ - for (x =3D 0; x < operation_width; x++) { = \ - if (rtl) { = \ - index_s =3D ((src_y - y) * src_width + src_x - x) * _b= pp; \ - index_d =3D ((dst_y - y) * dst_width + dst_x - x) * _b= pp; \ - } else { = \ - index_s =3D ((src_y + y) * src_width + src_x + x) * _b= pp; \ - index_d =3D ((dst_y + y) * dst_width + dst_x + x) * _b= pp; \ - } = \ - *(_pixel_type*)&dst[index_d] =3D *(_pixel_type*)&src[index= _s];\ - } = \ - } = \ +#define COPY_AREA(_bpp, _pixel_type, rtl) { = \ + int y, x, index_d, index_s; = \ + for (y =3D 0; y < operation_height; y++) { = \ + for (x =3D 0; x < operation_width; x++) { = \ + if (rtl) { = \ + index_s =3D ((src_y - y) * src_width + src_x - x) * _b= pp; \ + index_d =3D ((dst_y - y) * dst_width + dst_x - x) * _b= pp; \ + } else { = \ + index_s =3D ((src_y + y) * src_width + src_x + x) * _b= pp; \ + index_d =3D ((dst_y + y) * dst_width + dst_x + x) * _b= pp; \ + } = \ + *(_pixel_type *)&dst[index_d] =3D *(_pixel_type *)&src[ind= ex_s];\ + } = \ + } = \ } switch (format_flags) { case 0: @@ -705,7 +705,7 @@ static void sm501_2d_operation(SM501State * s) for (y =3D 0; y < operation_height; y++) { = \ for (x =3D 0; x < operation_width; x++) { = \ int index =3D ((dst_y + y) * dst_width + dst_x + x) * _bpp= ; \ - *(_pixel_type*)&dst[index] =3D (_pixel_type)color; = \ + *(_pixel_type *)&dst[index] =3D (_pixel_type)color; = \ } = \ } = \ } @@ -733,50 +733,50 @@ static void sm501_2d_operation(SM501State * s) static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, unsigned size) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; uint32_t ret =3D 0; SM501_DPRINTF("sm501 system config regs : read addr=3D%x\n", (int)addr= ); =20 - switch(addr) { + switch (addr) { case SM501_SYSTEM_CONTROL: - ret =3D s->system_control; - break; + ret =3D s->system_control; + break; case SM501_MISC_CONTROL: - ret =3D s->misc_control; - break; + ret =3D s->misc_control; + break; case SM501_GPIO31_0_CONTROL: - ret =3D s->gpio_31_0_control; - break; + ret =3D s->gpio_31_0_control; + break; case SM501_GPIO63_32_CONTROL: - ret =3D s->gpio_63_32_control; - break; + ret =3D s->gpio_63_32_control; + break; case SM501_DEVICEID: - ret =3D 0x050100A0; - break; + ret =3D 0x050100A0; + break; case SM501_DRAM_CONTROL: - ret =3D (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; - break; + ret =3D (s->dram_control & 0x07F107C0) | s->local_mem_size_index <= < 13; + break; case SM501_IRQ_MASK: - ret =3D s->irq_mask; - break; + ret =3D s->irq_mask; + break; case SM501_MISC_TIMING: - /* TODO : simulate gate control */ - ret =3D s->misc_timing; - break; + /* TODO : simulate gate control */ + ret =3D s->misc_timing; + break; case SM501_CURRENT_GATE: - /* TODO : simulate gate control */ - ret =3D 0x00021807; - break; + /* TODO : simulate gate control */ + ret =3D 0x00021807; + break; case SM501_CURRENT_CLOCK: - ret =3D 0x2A1A0A09; - break; + ret =3D 0x2A1A0A09; + break; case SM501_POWER_MODE_CONTROL: - ret =3D s->power_mode_control; - break; + ret =3D s->power_mode_control; + break; =20 default: - printf("sm501 system config : not implemented register read." - " addr=3D%x\n", (int)addr); + printf("sm501 system config : not implemented register read." + " addr=3D%x\n", (int)addr); abort(); } =20 @@ -786,47 +786,47 @@ static uint64_t sm501_system_config_read(void *opaque= , hwaddr addr, static void sm501_system_config_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; SM501_DPRINTF("sm501 system config regs : write addr=3D%x, val=3D%x\n", - (uint32_t)addr, (uint32_t)value); + (uint32_t)addr, (uint32_t)value); =20 - switch(addr) { + switch (addr) { case SM501_SYSTEM_CONTROL: - s->system_control =3D value & 0xE300B8F7; - break; + s->system_control =3D value & 0xE300B8F7; + break; case SM501_MISC_CONTROL: - s->misc_control =3D value & 0xFF7FFF20; - break; + s->misc_control =3D value & 0xFF7FFF20; + break; case SM501_GPIO31_0_CONTROL: - s->gpio_31_0_control =3D value; - break; + s->gpio_31_0_control =3D value; + break; case SM501_GPIO63_32_CONTROL: - s->gpio_63_32_control =3D value; - break; + s->gpio_63_32_control =3D value; + break; case SM501_DRAM_CONTROL: - s->local_mem_size_index =3D (value >> 13) & 0x7; - /* rODO : check validity of size change */ - s->dram_control |=3D value & 0x7FFFFFC3; - break; + s->local_mem_size_index =3D (value >> 13) & 0x7; + /* TODO : check validity of size change */ + s->dram_control |=3D value & 0x7FFFFFC3; + break; case SM501_IRQ_MASK: - s->irq_mask =3D value; - break; + s->irq_mask =3D value; + break; case SM501_MISC_TIMING: - s->misc_timing =3D value & 0xF31F1FFF; - break; + s->misc_timing =3D value & 0xF31F1FFF; + break; case SM501_POWER_MODE_0_GATE: case SM501_POWER_MODE_1_GATE: case SM501_POWER_MODE_0_CLOCK: case SM501_POWER_MODE_1_CLOCK: - /* TODO : simulate gate & clock control */ - break; + /* TODO : simulate gate & clock control */ + break; case SM501_POWER_MODE_CONTROL: - s->power_mode_control =3D value & 0x00000003; - break; + s->power_mode_control =3D value & 0x00000003; + break; =20 default: - printf("sm501 system config : not implemented register write." - " addr=3D%x, val=3D%x\n", (int)addr, (uint32_t)value); + printf("sm501 system config : not implemented register write." + " addr=3D%x, val=3D%x\n", (int)addr, (uint32_t)value); abort(); } } @@ -843,119 +843,119 @@ static const MemoryRegionOps sm501_system_config_op= s =3D { =20 static uint32_t sm501_palette_read(void *opaque, hwaddr addr) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; SM501_DPRINTF("sm501 palette read addr=3D%x\n", (int)addr); =20 /* TODO : consider BYTE/WORD access */ /* TODO : consider endian */ =20 assert(range_covers_byte(0, 0x400 * 3, addr)); - return *(uint32_t*)&s->dc_palette[addr]; + return *(uint32_t *)&s->dc_palette[addr]; } =20 -static void sm501_palette_write(void *opaque, - hwaddr addr, uint32_t value) +static void sm501_palette_write(void *opaque, hwaddr addr, + uint32_t value) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; SM501_DPRINTF("sm501 palette write addr=3D%x, val=3D%x\n", - (int)addr, value); + (int)addr, value); =20 /* TODO : consider BYTE/WORD access */ /* TODO : consider endian */ =20 assert(range_covers_byte(0, 0x400 * 3, addr)); - *(uint32_t*)&s->dc_palette[addr] =3D value; + *(uint32_t *)&s->dc_palette[addr] =3D value; } =20 static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr, unsigned size) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; uint32_t ret =3D 0; SM501_DPRINTF("sm501 disp ctrl regs : read addr=3D%x\n", (int)addr); =20 - switch(addr) { + switch (addr) { =20 case SM501_DC_PANEL_CONTROL: - ret =3D s->dc_panel_control; - break; + ret =3D s->dc_panel_control; + break; case SM501_DC_PANEL_PANNING_CONTROL: - ret =3D s->dc_panel_panning_control; - break; + ret =3D s->dc_panel_panning_control; + break; case SM501_DC_PANEL_FB_ADDR: - ret =3D s->dc_panel_fb_addr; - break; + ret =3D s->dc_panel_fb_addr; + break; case SM501_DC_PANEL_FB_OFFSET: - ret =3D s->dc_panel_fb_offset; - break; + ret =3D s->dc_panel_fb_offset; + break; case SM501_DC_PANEL_FB_WIDTH: - ret =3D s->dc_panel_fb_width; - break; + ret =3D s->dc_panel_fb_width; + break; case SM501_DC_PANEL_FB_HEIGHT: - ret =3D s->dc_panel_fb_height; - break; + ret =3D s->dc_panel_fb_height; + break; case SM501_DC_PANEL_TL_LOC: - ret =3D s->dc_panel_tl_location; - break; + ret =3D s->dc_panel_tl_location; + break; case SM501_DC_PANEL_BR_LOC: - ret =3D s->dc_panel_br_location; - break; + ret =3D s->dc_panel_br_location; + break; =20 case SM501_DC_PANEL_H_TOT: - ret =3D s->dc_panel_h_total; - break; + ret =3D s->dc_panel_h_total; + break; case SM501_DC_PANEL_H_SYNC: - ret =3D s->dc_panel_h_sync; - break; + ret =3D s->dc_panel_h_sync; + break; case SM501_DC_PANEL_V_TOT: - ret =3D s->dc_panel_v_total; - break; + ret =3D s->dc_panel_v_total; + break; case SM501_DC_PANEL_V_SYNC: - ret =3D s->dc_panel_v_sync; - break; + ret =3D s->dc_panel_v_sync; + break; =20 case SM501_DC_CRT_CONTROL: - ret =3D s->dc_crt_control; - break; + ret =3D s->dc_crt_control; + break; case SM501_DC_CRT_FB_ADDR: - ret =3D s->dc_crt_fb_addr; - break; + ret =3D s->dc_crt_fb_addr; + break; case SM501_DC_CRT_FB_OFFSET: - ret =3D s->dc_crt_fb_offset; - break; + ret =3D s->dc_crt_fb_offset; + break; case SM501_DC_CRT_H_TOT: - ret =3D s->dc_crt_h_total; - break; + ret =3D s->dc_crt_h_total; + break; case SM501_DC_CRT_H_SYNC: - ret =3D s->dc_crt_h_sync; - break; + ret =3D s->dc_crt_h_sync; + break; case SM501_DC_CRT_V_TOT: - ret =3D s->dc_crt_v_total; - break; + ret =3D s->dc_crt_v_total; + break; case SM501_DC_CRT_V_SYNC: - ret =3D s->dc_crt_v_sync; - break; + ret =3D s->dc_crt_v_sync; + break; =20 case SM501_DC_CRT_HWC_ADDR: - ret =3D s->dc_crt_hwc_addr; - break; + ret =3D s->dc_crt_hwc_addr; + break; case SM501_DC_CRT_HWC_LOC: - ret =3D s->dc_crt_hwc_location; - break; + ret =3D s->dc_crt_hwc_location; + break; case SM501_DC_CRT_HWC_COLOR_1_2: - ret =3D s->dc_crt_hwc_color_1_2; - break; + ret =3D s->dc_crt_hwc_color_1_2; + break; case SM501_DC_CRT_HWC_COLOR_3: - ret =3D s->dc_crt_hwc_color_3; - break; + ret =3D s->dc_crt_hwc_color_3; + break; =20 - case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: + case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: ret =3D sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE); break; =20 default: - printf("sm501 disp ctrl : not implemented register read." - " addr=3D%x\n", (int)addr); + printf("sm501 disp ctrl : not implemented register read." + " addr=3D%x\n", (int)addr); abort(); } =20 @@ -965,104 +965,104 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, = hwaddr addr, static void sm501_disp_ctrl_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; SM501_DPRINTF("sm501 disp ctrl regs : write addr=3D%x, val=3D%x\n", - (unsigned)addr, (unsigned)value); + (unsigned)addr, (unsigned)value); =20 - switch(addr) { + switch (addr) { case SM501_DC_PANEL_CONTROL: - s->dc_panel_control =3D value & 0x0FFF73FF; - break; + s->dc_panel_control =3D value & 0x0FFF73FF; + break; case SM501_DC_PANEL_PANNING_CONTROL: - s->dc_panel_panning_control =3D value & 0xFF3FFF3F; - break; + s->dc_panel_panning_control =3D value & 0xFF3FFF3F; + break; case SM501_DC_PANEL_FB_ADDR: - s->dc_panel_fb_addr =3D value & 0x8FFFFFF0; - break; + s->dc_panel_fb_addr =3D value & 0x8FFFFFF0; + break; case SM501_DC_PANEL_FB_OFFSET: - s->dc_panel_fb_offset =3D value & 0x3FF03FF0; - break; + s->dc_panel_fb_offset =3D value & 0x3FF03FF0; + break; case SM501_DC_PANEL_FB_WIDTH: - s->dc_panel_fb_width =3D value & 0x0FFF0FFF; - break; + s->dc_panel_fb_width =3D value & 0x0FFF0FFF; + break; case SM501_DC_PANEL_FB_HEIGHT: - s->dc_panel_fb_height =3D value & 0x0FFF0FFF; - break; + s->dc_panel_fb_height =3D value & 0x0FFF0FFF; + break; case SM501_DC_PANEL_TL_LOC: - s->dc_panel_tl_location =3D value & 0x07FF07FF; - break; + s->dc_panel_tl_location =3D value & 0x07FF07FF; + break; case SM501_DC_PANEL_BR_LOC: - s->dc_panel_br_location =3D value & 0x07FF07FF; - break; + s->dc_panel_br_location =3D value & 0x07FF07FF; + break; =20 case SM501_DC_PANEL_H_TOT: - s->dc_panel_h_total =3D value & 0x0FFF0FFF; - break; + s->dc_panel_h_total =3D value & 0x0FFF0FFF; + break; case SM501_DC_PANEL_H_SYNC: - s->dc_panel_h_sync =3D value & 0x00FF0FFF; - break; + s->dc_panel_h_sync =3D value & 0x00FF0FFF; + break; case SM501_DC_PANEL_V_TOT: - s->dc_panel_v_total =3D value & 0x0FFF0FFF; - break; + s->dc_panel_v_total =3D value & 0x0FFF0FFF; + break; case SM501_DC_PANEL_V_SYNC: - s->dc_panel_v_sync =3D value & 0x003F0FFF; - break; + s->dc_panel_v_sync =3D value & 0x003F0FFF; + break; =20 case SM501_DC_PANEL_HWC_ADDR: - s->dc_panel_hwc_addr =3D value & 0x8FFFFFF0; - break; + s->dc_panel_hwc_addr =3D value & 0x8FFFFFF0; + break; case SM501_DC_PANEL_HWC_LOC: - s->dc_panel_hwc_location =3D value & 0x0FFF0FFF; - break; + s->dc_panel_hwc_location =3D value & 0x0FFF0FFF; + break; case SM501_DC_PANEL_HWC_COLOR_1_2: - s->dc_panel_hwc_color_1_2 =3D value; - break; + s->dc_panel_hwc_color_1_2 =3D value; + break; case SM501_DC_PANEL_HWC_COLOR_3: - s->dc_panel_hwc_color_3 =3D value & 0x0000FFFF; - break; + s->dc_panel_hwc_color_3 =3D value & 0x0000FFFF; + break; =20 case SM501_DC_CRT_CONTROL: - s->dc_crt_control =3D value & 0x0003FFFF; - break; + s->dc_crt_control =3D value & 0x0003FFFF; + break; case SM501_DC_CRT_FB_ADDR: - s->dc_crt_fb_addr =3D value & 0x8FFFFFF0; - break; + s->dc_crt_fb_addr =3D value & 0x8FFFFFF0; + break; case SM501_DC_CRT_FB_OFFSET: - s->dc_crt_fb_offset =3D value & 0x3FF03FF0; - break; + s->dc_crt_fb_offset =3D value & 0x3FF03FF0; + break; case SM501_DC_CRT_H_TOT: - s->dc_crt_h_total =3D value & 0x0FFF0FFF; - break; + s->dc_crt_h_total =3D value & 0x0FFF0FFF; + break; case SM501_DC_CRT_H_SYNC: - s->dc_crt_h_sync =3D value & 0x00FF0FFF; - break; + s->dc_crt_h_sync =3D value & 0x00FF0FFF; + break; case SM501_DC_CRT_V_TOT: - s->dc_crt_v_total =3D value & 0x0FFF0FFF; - break; + s->dc_crt_v_total =3D value & 0x0FFF0FFF; + break; case SM501_DC_CRT_V_SYNC: - s->dc_crt_v_sync =3D value & 0x003F0FFF; - break; + s->dc_crt_v_sync =3D value & 0x003F0FFF; + break; =20 case SM501_DC_CRT_HWC_ADDR: - s->dc_crt_hwc_addr =3D value & 0x8FFFFFF0; - break; + s->dc_crt_hwc_addr =3D value & 0x8FFFFFF0; + break; case SM501_DC_CRT_HWC_LOC: - s->dc_crt_hwc_location =3D value & 0x0FFF0FFF; - break; + s->dc_crt_hwc_location =3D value & 0x0FFF0FFF; + break; case SM501_DC_CRT_HWC_COLOR_1_2: - s->dc_crt_hwc_color_1_2 =3D value; - break; + s->dc_crt_hwc_color_1_2 =3D value; + break; case SM501_DC_CRT_HWC_COLOR_3: - s->dc_crt_hwc_color_3 =3D value & 0x0000FFFF; - break; + s->dc_crt_hwc_color_3 =3D value & 0x0000FFFF; + break; =20 - case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4: + case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4: sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value); break; =20 default: - printf("sm501 disp ctrl : not implemented register write." - " addr=3D%x, val=3D%x\n", (int)addr, (unsigned)value); + printf("sm501 disp ctrl : not implemented register write." + " addr=3D%x, val=3D%x\n", (int)addr, (unsigned)value); abort(); } } @@ -1080,11 +1080,11 @@ static const MemoryRegionOps sm501_disp_ctrl_ops = =3D { static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, unsigned size) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; uint32_t ret =3D 0; SM501_DPRINTF("sm501 2d engine regs : read addr=3D%x\n", (int)addr); =20 - switch(addr) { + switch (addr) { case SM501_2D_SOURCE_BASE: ret =3D s->twoD_source_base; break; @@ -1100,11 +1100,11 @@ static uint64_t sm501_2d_engine_read(void *opaque, = hwaddr addr, static void sm501_2d_engine_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; SM501_DPRINTF("sm501 2d engine regs : write addr=3D%x, val=3D%x\n", (unsigned)addr, (unsigned)value); =20 - switch(addr) { + switch (addr) { case SM501_2D_SOURCE: s->twoD_source =3D value; break; @@ -1168,9 +1168,9 @@ static const MemoryRegionOps sm501_2d_engine_ops =3D { /* draw line functions for all console modes */ =20 typedef void draw_line_func(uint8_t *d, const uint8_t *s, - int width, const uint32_t *pal); + int width, const uint32_t *pal); =20 -typedef void draw_hwc_line_func(SM501State * s, int crt, uint8_t * palette, +typedef void draw_hwc_line_func(SM501State *s, int crt, uint8_t *palette, int c_y, uint8_t *d, int width); =20 #define DEPTH 8 @@ -1197,7 +1197,7 @@ typedef void draw_hwc_line_func(SM501State * s, int c= rt, uint8_t * palette, #define DEPTH 32 #include "sm501_template.h" =20 -static draw_line_func * draw_line8_funcs[] =3D { +static draw_line_func *draw_line8_funcs[] =3D { draw_line8_8, draw_line8_15, draw_line8_16, @@ -1207,7 +1207,7 @@ static draw_line_func * draw_line8_funcs[] =3D { draw_line8_16bgr, }; =20 -static draw_line_func * draw_line16_funcs[] =3D { +static draw_line_func *draw_line16_funcs[] =3D { draw_line16_8, draw_line16_15, draw_line16_16, @@ -1217,7 +1217,7 @@ static draw_line_func * draw_line16_funcs[] =3D { draw_line16_16bgr, }; =20 -static draw_line_func * draw_line32_funcs[] =3D { +static draw_line_func *draw_line32_funcs[] =3D { draw_line32_8, draw_line32_15, draw_line32_16, @@ -1227,7 +1227,7 @@ static draw_line_func * draw_line32_funcs[] =3D { draw_line32_16bgr, }; =20 -static draw_hwc_line_func * draw_hwc_line_funcs[] =3D { +static draw_hwc_line_func *draw_hwc_line_funcs[] =3D { draw_hwc_line_8, draw_hwc_line_15, draw_hwc_line_16, @@ -1242,7 +1242,7 @@ static inline int get_depth_index(DisplaySurface *sur= face) switch (surface_bits_per_pixel(surface)) { default: case 8: - return 0; + return 0; case 15: return 1; case 16: @@ -1256,22 +1256,22 @@ static inline int get_depth_index(DisplaySurface *s= urface) } } =20 -static void sm501_draw_crt(SM501State * s) +static void sm501_draw_crt(SM501State *s) { DisplaySurface *surface =3D qemu_console_surface(s->con); int y; int width =3D (s->dc_crt_h_total & 0x00000FFF) + 1; int height =3D (s->dc_crt_v_total & 0x00000FFF) + 1; =20 - uint8_t * src =3D s->local_mem; + uint8_t *src =3D s->local_mem; int src_bpp =3D 0; int dst_bpp =3D surface_bytes_per_pixel(surface); - uint32_t * palette =3D (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE - - SM501_DC_PANEL_PALETTE]; + uint32_t *palette =3D (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE - + SM501_DC_PANEL_PALETTE]; uint8_t hwc_palette[3 * 3]; int ds_depth_index =3D get_depth_index(surface); - draw_line_func * draw_line =3D NULL; - draw_hwc_line_func * draw_hwc_line =3D NULL; + draw_line_func *draw_line =3D NULL; + draw_hwc_line_func *draw_hwc_line =3D NULL; int full_update =3D 0; int y_start =3D -1; ram_addr_t page_min =3D ~0l; @@ -1281,22 +1281,22 @@ static void sm501_draw_crt(SM501State * s) /* choose draw_line function */ switch (s->dc_crt_control & 3) { case SM501_DC_CRT_CONTROL_8BPP: - src_bpp =3D 1; - draw_line =3D draw_line8_funcs[ds_depth_index]; - break; + src_bpp =3D 1; + draw_line =3D draw_line8_funcs[ds_depth_index]; + break; case SM501_DC_CRT_CONTROL_16BPP: - src_bpp =3D 2; - draw_line =3D draw_line16_funcs[ds_depth_index]; - break; + src_bpp =3D 2; + draw_line =3D draw_line16_funcs[ds_depth_index]; + break; case SM501_DC_CRT_CONTROL_32BPP: - src_bpp =3D 4; - draw_line =3D draw_line32_funcs[ds_depth_index]; - break; + src_bpp =3D 4; + draw_line =3D draw_line32_funcs[ds_depth_index]; + break; default: - printf("sm501 draw crt : invalid DC_CRT_CONTROL=3D%x.\n", - s->dc_crt_control); + printf("sm501 draw crt : invalid DC_CRT_CONTROL=3D%x.\n", + s->dc_crt_control); abort(); - break; + break; } =20 /* set up to draw hardware cursor */ @@ -1319,61 +1319,65 @@ static void sm501_draw_crt(SM501State * s) if (s->last_width !=3D width || s->last_height !=3D height) { qemu_console_resize(s->con, width, height); surface =3D qemu_console_surface(s->con); - s->last_width =3D width; - s->last_height =3D height; - full_update =3D 1; + s->last_width =3D width; + s->last_height =3D height; + full_update =3D 1; } =20 /* draw each line according to conditions */ memory_region_sync_dirty_bitmap(&s->local_mem_region); for (y =3D 0; y < height; y++) { - int update_hwc =3D draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0; - int update =3D full_update || update_hwc; + int update_hwc =3D draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0; + int update =3D full_update || update_hwc; ram_addr_t page0 =3D offset; ram_addr_t page1 =3D offset + width * src_bpp - 1; =20 - /* check dirty flags for each line */ + /* check dirty flags for each line */ update =3D memory_region_get_dirty(&s->local_mem_region, page0, page1 - page0, DIRTY_MEMORY_VGA); =20 - /* draw line and change status */ - if (update) { + /* draw line and change status */ + if (update) { uint8_t *d =3D surface_data(surface); d +=3D y * width * dst_bpp; =20 /* draw graphics layer */ draw_line(d, src, width, palette); =20 - /* draw haredware cursor */ + /* draw hardware cursor */ if (update_hwc) { draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, w= idth); } =20 - if (y_start < 0) - y_start =3D y; - if (page0 < page_min) - page_min =3D page0; - if (page1 > page_max) - page_max =3D page1; - } else { - if (y_start >=3D 0) { - /* flush to display */ + if (y_start < 0) { + y_start =3D y; + } + if (page0 < page_min) { + page_min =3D page0; + } + if (page1 > page_max) { + page_max =3D page1; + } + } else { + if (y_start >=3D 0) { + /* flush to display */ dpy_gfx_update(s->con, 0, y_start, width, y - y_start); - y_start =3D -1; - } - } + y_start =3D -1; + } + } =20 - src +=3D width * src_bpp; - offset +=3D width * src_bpp; + src +=3D width * src_bpp; + offset +=3D width * src_bpp; } =20 /* complete flush to display */ - if (y_start >=3D 0) + if (y_start >=3D 0) { dpy_gfx_update(s->con, 0, y_start, width, y - y_start); + } =20 /* clear dirty flags */ if (page_min !=3D ~0l) { - memory_region_reset_dirty(&s->local_mem_region, + memory_region_reset_dirty(&s->local_mem_region, page_min, page_max + TARGET_PAGE_SIZE, DIRTY_MEMORY_VGA); } @@ -1381,10 +1385,11 @@ static void sm501_draw_crt(SM501State * s) =20 static void sm501_update_display(void *opaque) { - SM501State * s =3D (SM501State *)opaque; + SM501State *s =3D (SM501State *)opaque; =20 - if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) - sm501_draw_crt(s); + if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) { + sm501_draw_crt(s); + } } =20 static const GraphicHwOps sm501_ops =3D { @@ -1394,19 +1399,18 @@ static const GraphicHwOps sm501_ops =3D { void sm501_init(MemoryRegion *address_space_mem, uint32_t base, uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr) { - SM501State * s; + SM501State *s; DeviceState *dev; MemoryRegion *sm501_system_config =3D g_new(MemoryRegion, 1); MemoryRegion *sm501_disp_ctrl =3D g_new(MemoryRegion, 1); MemoryRegion *sm501_2d_engine =3D g_new(MemoryRegion, 1); =20 /* allocate management data region */ - s =3D (SM501State *)g_malloc0(sizeof(SM501State)); + s =3D g_new0(SM501State, 1); s->base =3D base; - s->local_mem_size_index - =3D get_local_mem_size_index(local_mem_bytes); + s->local_mem_size_index =3D get_local_mem_size_index(local_mem_bytes); SM501_DPRINTF("local mem size=3D%x. index=3D%d\n", get_local_mem_size(= s), - s->local_mem_size_index); + s->local_mem_size_index); s->system_control =3D 0x00100000; s->misc_control =3D 0x00001000; /* assumes SH, active=3Dlow */ s->dc_panel_control =3D 0x00010000; @@ -1421,8 +1425,8 @@ void sm501_init(MemoryRegion *address_space_mem, uint= 32_t base, memory_region_add_subregion(address_space_mem, base, &s->local_mem_reg= ion); =20 /* map mmio */ - memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_= ops, s, - "sm501-system-config", 0x6c); + memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_= ops, + s, "sm501-system-config", 0x6c); memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET, sm501_system_config); memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s, diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h index f33e499..aeeac5d 100644 --- a/hw/display/sm501_template.h +++ b/hw/display/sm501_template.h @@ -47,40 +47,40 @@ static void glue(draw_line8_, PIXEL_NAME)( { uint8_t v, r, g, b; do { - v =3D ldub_p(s); - r =3D (pal[v] >> 16) & 0xff; - g =3D (pal[v] >> 8) & 0xff; - b =3D (pal[v] >> 0) & 0xff; - ((PIXEL_TYPE *) d)[0] =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); - s ++; - d +=3D BPP; - } while (-- width !=3D 0); + v =3D ldub_p(s); + r =3D (pal[v] >> 16) & 0xff; + g =3D (pal[v] >> 8) & 0xff; + b =3D (pal[v] >> 0) & 0xff; + *(PIXEL_TYPE *)d =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); + s++; + d +=3D BPP; + } while (--width !=3D 0); } =20 static void glue(draw_line16_, PIXEL_NAME)( - uint8_t *d, const uint8_t *s, int width, const uint32_t *pal) + uint8_t *d, const uint8_t *s, int width, const uint32_t *= pal) { uint16_t rgb565; uint8_t r, g, b; =20 do { - rgb565 =3D lduw_p(s); - r =3D ((rgb565 >> 11) & 0x1f) << 3; - g =3D ((rgb565 >> 5) & 0x3f) << 2; - b =3D ((rgb565 >> 0) & 0x1f) << 3; - ((PIXEL_TYPE *) d)[0] =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); - s +=3D 2; - d +=3D BPP; - } while (-- width !=3D 0); + rgb565 =3D lduw_p(s); + r =3D ((rgb565 >> 11) & 0x1f) << 3; + g =3D ((rgb565 >> 5) & 0x3f) << 2; + b =3D ((rgb565 >> 0) & 0x1f) << 3; + *(PIXEL_TYPE *)d =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); + s +=3D 2; + d +=3D BPP; + } while (--width !=3D 0); } =20 static void glue(draw_line32_, PIXEL_NAME)( - uint8_t *d, const uint8_t *s, int width, const uint32_t *pal) + uint8_t *d, const uint8_t *s, int width, const uint32_t *= pal) { uint8_t r, g, b; =20 do { - ldub_p(s); + ldub_p(s); #if defined(TARGET_WORDS_BIGENDIAN) r =3D s[1]; g =3D s[2]; @@ -90,17 +90,17 @@ static void glue(draw_line32_, PIXEL_NAME)( g =3D s[1]; r =3D s[2]; #endif - ((PIXEL_TYPE *) d)[0] =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); - s +=3D 4; - d +=3D BPP; - } while (-- width !=3D 0); + *(PIXEL_TYPE *)d =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); + s +=3D 4; + d +=3D BPP; + } while (--width !=3D 0); } =20 /** * Draw hardware cursor image on the given line. */ -static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt, - uint8_t * palette, int c_y, uint8_t *d, int width) +static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt, + uint8_t *palette, int c_y, uint8_t *d, int width) { int x, i; uint8_t bitset =3D 0; @@ -132,7 +132,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State= * s, int crt, uint8_t r =3D palette[v * 3 + 0]; uint8_t g =3D palette[v * 3 + 1]; uint8_t b =3D palette[v * 3 + 2]; - ((PIXEL_TYPE *) d)[0] =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g,= b); + *(PIXEL_TYPE *)d =3D glue(rgb_to_pixel, PIXEL_NAME)(r, g, b); } d +=3D BPP; } --=20 2.7.4