From nobody Wed Nov 5 17:47:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496748612824852.9128863052746; Tue, 6 Jun 2017 04:30:12 -0700 (PDT) Received: from localhost ([::1]:37643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICga-0001e3-2r for importer@patchew.org; Tue, 06 Jun 2017 07:30:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICeq-0000TC-Ue for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dICeo-0002lR-I7 for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:20 -0400 Received: from [59.151.112.132] (port=9198 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dICen-0002g5-LU for qemu-devel@nongnu.org; Tue, 06 Jun 2017 07:28:18 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 06 Jun 2017 19:27:55 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id E32EC47C7C86; Tue, 6 Jun 2017 19:27:55 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 6 Jun 2017 19:27:55 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19716135" From: Mao Zhongyi To: Date: Tue, 6 Jun 2017 19:26:30 +0800 Message-ID: <3579e47c4bb41476406e26685292aaa9153fcc77.1496746391.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: E32EC47C7C86.A7827 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v3 5/7] pci: Make errp the last parameter of pci_add_capability() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, armbru@redhat.com, marcel@redhat.com, alex.williamson@redhat.com, dmitry@daynix.com, pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Error argument for pci_add_capability() to leverage the errp to pass info on errors. This way is helpful for its callers to make a better error handling when moving to 'realize'. Cc: pbonzini@redhat.com Cc: rth@twiddle.net Cc: ehabkost@redhat.com Cc: mst@redhat.com CC: dmitry@daynix.com Cc: jasowang@redhat.com Cc: marcel@redhat.com Cc: alex.williamson@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi --- hw/i386/amd_iommu.c | 24 +++++++++++++++++------- hw/net/e1000e.c | 7 ++++++- hw/net/eepro100.c | 20 +++++++++++++++----- hw/pci-bridge/i82801b11.c | 1 + hw/pci/pci.c | 10 ++++------ hw/pci/pci_bridge.c | 7 ++++++- hw/pci/pcie.c | 10 ++++++++-- hw/pci/shpc.c | 5 ++++- hw/pci/slotid_cap.c | 7 ++++++- hw/vfio/pci.c | 3 ++- hw/virtio/virtio-pci.c | 19 ++++++++++++++----- include/hw/pci/pci.h | 3 ++- 12 files changed, 85 insertions(+), 31 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 7b6d4ea..d93ffc2 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1158,13 +1158,23 @@ static void amdvi_realize(DeviceState *dev, Error *= *err) x86_iommu->type =3D TYPE_AMD; qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus); object_property_set_bool(OBJECT(&s->pci), true, "realized", err); - s->capab_offset =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC= , 0, - AMDVI_CAPAB_SIZE); - assert(s->capab_offset > 0); - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB= _REG_SIZE); - assert(ret > 0); - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_= REG_SIZE); - assert(ret > 0); + ret =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, + AMDVI_CAPAB_SIZE, err); + if (ret < 0) { + return; + } + s->capab_offset =3D ret; + + ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, + AMDVI_CAPAB_REG_SIZE, err); + if (ret < 0) { + return; + } + ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, + AMDVI_CAPAB_REG_SIZE, err); + if (ret < 0) { + return; + } =20 /* set up MMIO */ memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mm= io", diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 8259d67..41430766 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -47,6 +47,7 @@ #include "e1000e_core.h" =20 #include "trace.h" +#include "qapi/error.h" =20 #define TYPE_E1000E "e1000e" #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E) @@ -372,7 +373,9 @@ e1000e_gen_dsn(uint8_t *mac) static int e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) { - int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZ= EOF); + Error *local_err =3D NULL; + int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, + PCI_PM_SIZEOF, &local_err); =20 if (ret > 0) { pci_set_word(pdev->config + offset + PCI_PM_PMC, @@ -386,6 +389,8 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offse= t, uint16_t pmc) =20 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS); + } else { + error_report_err(local_err); } =20 return ret; diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 62e989c..0625839 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -48,6 +48,7 @@ #include "sysemu/sysemu.h" #include "sysemu/dma.h" #include "qemu/bitops.h" +#include "qapi/error.h" =20 /* QEMU sends frames smaller than 60 bytes to ethernet nics. * Such frames are rejected by real nics and their emulations. @@ -494,7 +495,7 @@ static void eepro100_fcp_interrupt(EEPRO100State *s) } #endif =20 -static void e100_pci_reset(EEPRO100State *s) +static void e100_pci_reset(EEPRO100State *s, Error **errp) { E100PCIDeviceInfo *info =3D eepro100_get_class(s); uint32_t device =3D s->device; @@ -570,9 +571,13 @@ static void e100_pci_reset(EEPRO100State *s) /* Power Management Capabilities */ int cfg_offset =3D 0xdc; int r =3D pci_add_capability(&s->dev, PCI_CAP_ID_PM, - cfg_offset, PCI_PM_SIZEOF); - assert(r > 0); - pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); + cfg_offset, PCI_PM_SIZEOF, + errp); + if (r > 0) { + pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); + } else { + return; + } #if 0 /* TODO: replace dummy code for power management emulation. */ /* TODO: Power Management Control / Status. */ pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000); @@ -1858,12 +1863,17 @@ static void e100_nic_realize(PCIDevice *pci_dev, Er= ror **errp) { EEPRO100State *s =3D DO_UPCAST(EEPRO100State, dev, pci_dev); E100PCIDeviceInfo *info =3D eepro100_get_class(s); + Error *local_err =3D NULL; =20 TRACE(OTHER, logout("\n")); =20 s->device =3D info->device; =20 - e100_pci_reset(s); + e100_pci_reset(s, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } =20 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, * i82559 and later support 64 or 256 word EEPROM. */ diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index 2404e7e..2c065c3 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -44,6 +44,7 @@ #include "qemu/osdep.h" #include "hw/pci/pci.h" #include "hw/i386/ich9.h" +#include "qapi/error.h" =20 =20 /*************************************************************************= ****/ diff --git a/hw/pci/pci.c b/hw/pci/pci.c index b73bfea..2bba37a 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2264,15 +2264,13 @@ static void pci_del_option_rom(PCIDevice *pdev) * in pci config space */ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size) + uint8_t offset, uint8_t size, + Error **errp) { int ret; - Error *local_err =3D NULL; =20 - ret =3D pci_add_capability2(pdev, cap_id, offset, size, &local_err); - if (ret < 0) { - error_report_err(local_err); - } + ret =3D pci_add_capability2(pdev, cap_id, offset, size, errp); + return ret; } =20 diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 5118ef4..bb0f3a3 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -33,6 +33,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "qemu/range.h" +#include "qapi/error.h" =20 /* PCI bridge subsystem vendor ID helper functions */ #define PCI_SSVID_SIZEOF 8 @@ -43,8 +44,12 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, uint16_t svid, uint16_t ssid) { int pos; - pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SI= ZEOF); + Error *local_err =3D NULL; + + pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, + PCI_SSVID_SIZEOF, &local_err); if (pos < 0) { + error_report_err(local_err); return pos; } =20 diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 18e634f..f187512 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -91,11 +91,14 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8= _t type, uint8_t port) /* PCIe cap v2 init */ int pos; uint8_t *exp_cap; + Error *local_err =3D NULL; =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_S= IZEOF); + pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, + PCI_EXP_VER2_SIZEOF, &local_err); if (pos < 0) { + error_report_err(local_err); return pos; } dev->exp.exp_cap =3D pos; @@ -123,11 +126,14 @@ int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, = uint8_t type, { /* PCIe cap v1 init */ int pos; + Error *local_err =3D NULL; =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_S= IZEOF); + pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, + PCI_EXP_VER1_SIZEOF, &local_err); if (pos < 0) { + error_report_err(local_err); return pos; } dev->exp.exp_cap =3D pos; diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index 42fafac..d72d5e4 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -450,9 +450,12 @@ static int shpc_cap_add_config(PCIDevice *d) { uint8_t *config; int config_offset; + Error *local_err =3D NULL; config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, - 0, SHPC_CAP_LENGTH); + 0, SHPC_CAP_LENGTH, + &local_err); if (config_offset < 0) { + error_report_err(local_err); return config_offset; } config =3D d->config + config_offset; diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index aec1e91..bdca205 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -2,6 +2,7 @@ #include "hw/pci/slotid_cap.h" #include "hw/pci/pci.h" #include "qemu/error-report.h" +#include "qapi/error.h" =20 #define SLOTID_CAP_LENGTH 4 #define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS) @@ -11,6 +12,8 @@ int slotid_cap_init(PCIDevice *d, int nslots, unsigned offset) { int cap; + Error *local_err =3D NULL; + if (!chassis) { error_report("Bridge chassis not specified. Each bridge is require= d " "to be assigned a unique chassis id > 0."); @@ -21,8 +24,10 @@ int slotid_cap_init(PCIDevice *d, int nslots, return -EINVAL; } =20 - cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LE= NGTH); + cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, + SLOTID_CAP_LENGTH, &local_err); if (cap < 0) { + error_report_err(local_err); return cap; } /* We make each chassis unique, this way each bridge is First in Chass= is */ diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 5881968..85cfe38 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1743,7 +1743,8 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, i= nt pos, uint8_t size, PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); } =20 - pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); + pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, + errp); if (pos > 0) { vdev->pdev.exp.exp_cap =3D pos; } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index f9b7244..cca5276 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1161,9 +1161,14 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *pr= oxy, { PCIDevice *dev =3D &proxy->pci_dev; int offset; + Error *local_err =3D NULL; =20 - offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len); - assert(offset > 0); + offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, + cap->cap_len, &local_err); + if (offset < 0) { + error_report_err(local_err); + abort(); + } =20 assert(cap->cap_len >=3D sizeof *cap); memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, @@ -1810,9 +1815,13 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) pos =3D pcie_endpoint_cap_init(pci_dev, 0); assert(pos > 0); =20 - pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEO= F); - assert(pos > 0); - pci_dev->exp.pm_cap =3D pos; + pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, + PCI_PM_SIZEOF, errp); + if (pos > 0) { + pci_dev->exp.pm_cap =3D pos; + } else { + return; + } =20 /* * Indicates that this function complies with revision 1.2 of the diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index a37a2d5..fe52aa8 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -356,7 +356,8 @@ void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); =20 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size); + uint8_t offset, uint8_t size, + Error **errp); int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp); --=20 2.9.3