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[124.44.183.209]) by smtp.gmail.com with ESMTPSA id d24sm20905519pfb.97.2017.04.30.16.14.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 30 Apr 2017 16:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=mhrZrYvvGl3Menw0sskgZtSPqZjtewfFHzElGTSobuS4GQGKThCrQgmAGE6ZyUVShp VdXqHFyudFLtZhPR0KNmVZjqLdt3l7881Pz4QTR8XzYmWLjUQlHGPXCoFWd0cWzcetVM bYBmbfjZ8RxqcfBhbOYHxLCbo3mOzgQkY2l6x0FVCMkHu0M6jY+U4zlRphFnds0v6m2Q zg3mX/+pYeIRjdUYnREoCPVJF8jGSzc+NSNdmschwGA/fbkTBDFHSMd9kE5Hir8FdkMd 11i4fJFQ1V3PWzKNe/dDW+U5fBA4+KHFI3EDWnrrD5JNpXghzXwpa+rnTeYrrBZo4Kck VymQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=B22Il4U+lW9qJRmIpKE7jAR5AR4P5G5MCstdmwVkA+0=; b=PQrF5Md8I6xsBBk80XDVgNnZZj4Atmohd60UB5fw2ZK87LKnXh/9/rAjJorW9VDUmi N2q37K/UW4HrwXLjFh1JEOmO6uNkZ1yGU+PVL1ZKyRVqnQVQEY6ORW9jw8ajXfJjz1bw 8CORI9xcheiK9IxzWZBYXTVyuQSTTCSCsxYIh1PMub5WpBQTbYXuSUEvrfeRzP+s/Cmq AeXDOAwwG5983I0DC6XDi+/+0owF9UGlkilHQZqCR9Viv8OGr+aHDqXWsHL3PjJ0+HL2 DMMPcpSytqGox7i6VS21CDaG6y8LsKARKuBDcYAlv+n1INv63UvUWDmXASwZQ7I/mw2c 0Mcg== X-Gm-Message-State: AN3rC/71LtswDW+NNDBlV7gnBPYrSyFtoaltHTJjA+ByYjYrvTVI6LSz I7OD9HGojgP1GQ== X-Received: by 10.99.1.138 with SMTP id 132mr24476702pgb.236.1493594095532; Sun, 30 Apr 2017 16:14:55 -0700 (PDT) From: Stafford Horne To: peter.maydell@linaro.org Date: Mon, 1 May 2017 08:14:16 +0900 Message-Id: <356a2db3c6f84e8e79e5afa3913514184bff5f50.1493593744.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 02/11] target/openrisc: Implement EVBAR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , QEMU Development , Tim 'mithro' Ansell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tim 'mithro' Ansell Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell Signed-off-by: Stafford Horne --- target/openrisc/cpu.c | 2 ++ target/openrisc/cpu.h | 7 +++++++ target/openrisc/interrupt.c | 6 +++++- target/openrisc/sys_helper.c | 7 +++++++ 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a..1524ed9 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj) =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 static void openrisc_any_initfn(Object *obj) @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 set_feature(cpu, OPENRISC_FEATURE_OB32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } =20 typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6..1958b72 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S =3D (1 << 7), CPUCFGR_OF64S =3D (1 << 8), CPUCFGR_OV64S =3D (1 << 9), + /* CPUCFGR_ND =3D (1 << 10), */ + /* CPUCFGR_AVRP =3D (1 << 11), */ + CPUCFGR_EVBARP =3D (1 << 12), + /* CPUCFGR_ISRP =3D (1 << 13), */ + /* CPUCFGR_AECSRP =3D (1 << 14), */ }; =20 /* DMMU configure register */ @@ -200,6 +205,7 @@ enum { OPENRISC_FEATURE_OF32S =3D (1 << 7), OPENRISC_FEATURE_OF64S =3D (1 << 8), OPENRISC_FEATURE_OV64S =3D (1 << 9), + OPENRISC_FEATURE_EVBAR =3D (1 << 12), }; =20 /* Tick Timer Mode Register */ @@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState { uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ uint32_t fpcsr; /* Float register */ float_status fp_status; =20 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6f..78f0ba9 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->lock_addr =3D -1; =20 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc =3D (cs->exception_index << 8); + hwaddr vect_pc =3D cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |=3D env->evbar; + } + env->pc =3D vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 60c3193..6ba8162 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, env->vr =3D rb; break; =20 + case TO_SPR(0, 11): /* EVBAR */ + env->evbar =3D rb; + break; + case TO_SPR(0, 16): /* NPC */ cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state @@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; =20 + case TO_SPR(0, 11): /* EVBAR */ + return env->evbar; + case TO_SPR(0, 16): /* NPC (equals PC) */ cpu_restore_state(cs, GETPC()); return env->pc; --=20 2.9.3