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Sat, 07 Mar 2026 23:20:31 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 20/28] hw/riscv/dm: add register handlers and update state management Date: Sun, 8 Mar 2026 15:17:23 +0800 Message-ID: <339a2c9cfa0a7efb1ef1c630c5b738c55ab05323.1772936778.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1343; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954597749154100 Wire up pre_write/post_write/post_read callbacks for the newly declared registers (DATA, PROGBUF, COMMAND, ABSTRACTAUTO, ABSTRACTCS W1C) and expand the register_info table. Refactor dm_dmcontrol_pre_write for clarity, fix haltsum0/1 to use hartsel-based windowing, expand dm_reg_present for all optional registers, add DATA area remap in ROM read/write, and add realize-time validation for datacount and progbufsize. Signed-off-by: Chao Liu --- hw/riscv/dm.c | 772 +++++++++++++++++++++++++++++++++++++------------- 1 file changed, 571 insertions(+), 201 deletions(-) diff --git a/hw/riscv/dm.c b/hw/riscv/dm.c index 427507e77e..169863c54c 100644 --- a/hw/riscv/dm.c +++ b/hw/riscv/dm.c @@ -228,6 +228,7 @@ REG32(HALTSUM0, 0x100) #define DM_NOP 0x13u #define DM_EBREAK 0x100073u =20 + typedef struct DMHartSelection { int all[RISCV_DM_HAWINDOW_SIZE + 1]; int all_count; @@ -235,19 +236,6 @@ typedef struct DMHartSelection { int valid_count; } DMHartSelection; =20 -static inline uint32_t dm_get_hartsel(RISCVDMState *s) -{ - uint32_t hi =3D ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTSELHI); - uint32_t lo =3D ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTSELLO); - - return (hi << 10) | lo; -} - -static inline bool dm_hart_valid(RISCVDMState *s, uint32_t hartsel) -{ - return hartsel < s->num_harts; -} - static inline uint32_t dm_rom_read32(RISCVDMState *s, uint32_t offset) { return ldl_le_p(s->rom_ptr + offset); @@ -294,54 +282,58 @@ static void dm_flush_cmd_space(RISCVDMState *s) dm_rom_write32(s, RISCV_DM_ROM_WHERETO, DM_JAL(0x1C)); } =20 -static void dm_invalidate_dynamic_code(RISCVDMState *s) +static inline uint32_t dm_get_hartsel(RISCVDMState *s) { - if (tcg_enabled()) { - ram_addr_t base =3D memory_region_get_ram_addr(&s->rom_mr); - - tb_invalidate_phys_range(NULL, base + RISCV_DM_ROM_WHERETO, - base + RISCV_DM_ROM_DATA - 1); - } + uint32_t hi =3D ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTSELHI); + uint32_t lo =3D ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTSELLO); + return (hi << 10) | lo; } =20 -static void dm_update_impebreak(RISCVDMState *s) +static inline bool dm_hart_valid(RISCVDMState *s, uint32_t hartsel) { - hwaddr ebreak_addr =3D RISCV_DM_ROM_PROGBUF + s->progbuf_size * 4; + return hartsel < s->num_harts; +} =20 - if (ebreak_addr + 4 > RISCV_DM_ROM_DATA) { - return; +static void dm_selection_add(RISCVDMState *s, DMHartSelection *sel, int ha= rtsel) +{ + for (int i =3D 0; i < sel->all_count; i++) { + if (sel->all[i] =3D=3D hartsel) { + return; + } + } + sel->all[sel->all_count++] =3D hartsel; + if (dm_hart_valid(s, hartsel)) { + sel->harts[sel->valid_count++] =3D hartsel; } - - dm_rom_write32(s, ebreak_addr, s->impebreak ? DM_EBREAK : DM_NOP); } =20 -static void dm_reset_rom_state(RISCVDMState *s) +static void dm_collect_selected_harts(RISCVDMState *s, DMHartSelection *se= l) { - if (!s->rom_ptr) { - return; - } + uint32_t hartsel =3D dm_get_hartsel(s); =20 - memset(s->rom_ptr + RISCV_DM_ROM_WORK_BASE, 0, RISCV_DM_ROM_WORK_SIZE); + memset(sel, 0, sizeof(*sel)); + dm_selection_add(s, sel, hartsel); =20 - dm_flush_cmd_space(s); + if (!ARRAY_FIELD_EX32(s->regs, DMCONTROL, HASEL)) { + return; + } =20 - for (uint32_t i =3D 0; i < s->num_abstract_data; i++) { - dm_sync_data_to_rom(s, i); + uint32_t wsel =3D ARRAY_FIELD_EX32(s->regs, HAWINDOWSEL, HAWINDOWSEL); + if (wsel >=3D RISCV_DM_MAX_HARTS / RISCV_DM_HAWINDOW_SIZE) { + return; } - for (uint32_t i =3D 0; i < s->progbuf_size; i++) { - dm_sync_progbuf_to_rom(s, i); + uint32_t window =3D s->hawindow[wsel]; + uint32_t base =3D wsel * RISCV_DM_HAWINDOW_SIZE; + for (int i =3D 0; i < RISCV_DM_HAWINDOW_SIZE; i++) { + if ((window >> i) & 1) { + dm_selection_add(s, sel, base + i); + } } - - dm_update_impebreak(s); - dm_invalidate_dynamic_code(s); } =20 -static inline void dm_set_cmderr(RISCVDMState *s, uint32_t err) +static inline bool dm_ndmreset_active(RISCVDMState *s) { - uint32_t cur =3D ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, CMDERR); - if (cur =3D=3D RISCV_DM_CMDERR_NONE) { - ARRAY_FIELD_DP32(s->regs, ABSTRACTCS, CMDERR, err); - } + return ARRAY_FIELD_EX32(s->regs, DMCONTROL, NDMRESET); } =20 static bool dm_abstract_cmd_completed(RISCVDMState *s, uint32_t hartsel) @@ -361,135 +353,137 @@ static bool dm_abstract_cmd_completed(RISCVDMState = *s, uint32_t hartsel) return !(flags & RISCV_DM_FLAG_GOING); } =20 -static void dm_selection_add(RISCVDMState *s, DMHartSelection *sel, int ha= rtsel) +static void dm_invalidate_dynamic_code(RISCVDMState *s) { - for (int i =3D 0; i < sel->all_count; i++) { - if (sel->all[i] =3D=3D hartsel) { - return; - } - } + if (tcg_enabled()) { + ram_addr_t base =3D memory_region_get_ram_addr(&s->rom_mr); =20 - sel->all[sel->all_count++] =3D hartsel; - if (dm_hart_valid(s, hartsel)) { - sel->harts[sel->valid_count++] =3D hartsel; + tb_invalidate_phys_range(NULL, base + RISCV_DM_ROM_WHERETO, + base + RISCV_DM_ROM_DATA - 1); } } =20 -static void dm_collect_selected_harts(RISCVDMState *s, DMHartSelection *se= l) +static bool dm_data_reg_present(RISCVDMState *s, hwaddr addr) { - uint32_t hartsel =3D dm_get_hartsel(s); - uint32_t wsel; - uint32_t window; - uint32_t base; + unsigned int index =3D (addr - A_DATA0) / 4; =20 - memset(sel, 0, sizeof(*sel)); - dm_selection_add(s, sel, hartsel); + return index < s->num_abstract_data; +} =20 - if (!ARRAY_FIELD_EX32(s->regs, DMCONTROL, HASEL)) { - return; - } +static bool dm_progbuf_reg_present(RISCVDMState *s, hwaddr addr) +{ + unsigned int index =3D (addr - A_PROGBUF0) / 4; =20 - wsel =3D ARRAY_FIELD_EX32(s->regs, HAWINDOWSEL, HAWINDOWSEL); - if (wsel >=3D RISCV_DM_MAX_HARTS / RISCV_DM_HAWINDOW_SIZE) { - return; - } + return index < s->progbuf_size; +} =20 - window =3D s->hawindow[wsel]; - base =3D wsel * RISCV_DM_HAWINDOW_SIZE; - for (int i =3D 0; i < RISCV_DM_HAWINDOW_SIZE; i++) { - if ((window >> i) & 1) { - dm_selection_add(s, sel, base + i); - } +static bool dm_sba_addr_reg_present(RISCVDMState *s, hwaddr addr) +{ + switch (addr) { + case A_SBADDRESS0: + return s->sba_addr_width > 0; + case A_SBADDRESS1: + return s->sba_addr_width > 32; + case A_SBADDRESS2: + return s->sba_addr_width > 64; + case A_SBADDRESS3: + return s->sba_addr_width > 96; + default: + return false; } } =20 -static inline bool dm_ndmreset_active(RISCVDMState *s) +static bool dm_sba_data_reg_present(RISCVDMState *s, hwaddr addr) { - return ARRAY_FIELD_EX32(s->regs, DMCONTROL, NDMRESET); + bool sbdata0 =3D ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS8) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS16) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS32) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS64) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS128); + bool sbdata1 =3D ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS64) || + ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS128); + bool sbdata23 =3D ARRAY_FIELD_EX32(s->regs, SBCS, SBACCESS128); + + switch (addr) { + case A_SBDATA0: + return sbdata0; + case A_SBDATA1: + return sbdata1; + case A_SBDATA2: + case A_SBDATA3: + return sbdata23; + default: + return false; + } } =20 static bool dm_reg_present(RISCVDMState *s, hwaddr addr) { + if (addr >=3D A_DATA0 && addr <=3D A_DATA11) { + return dm_data_reg_present(s, addr); + } + + if (addr >=3D A_PROGBUF0 && addr <=3D A_PROGBUF15) { + return dm_progbuf_reg_present(s, addr); + } + switch (addr) { + case A_AUTHDATA: + case A_DMCS2: + return false; case A_HALTSUM1: return s->num_harts >=3D 33; + case A_HALTSUM2: + return s->num_harts >=3D 1025; + case A_HALTSUM3: + return s->num_harts >=3D 32769; + case A_SBADDRESS0: + case A_SBADDRESS1: + case A_SBADDRESS2: + case A_SBADDRESS3: + return dm_sba_addr_reg_present(s, addr); + case A_SBDATA0: + case A_SBDATA1: + case A_SBDATA2: + case A_SBDATA3: + return dm_sba_data_reg_present(s, addr); default: return true; } } =20 -static void dm_status_refresh(RISCVDMState *s) +static void dm_update_impebreak(RISCVDMState *s) { - DMHartSelection sel; - bool anyhalted =3D false; - bool allhalted =3D true; - bool anyrunning =3D false; - bool allrunning =3D true; - bool anyunavail =3D false; - bool allunavail =3D true; - bool anyresumeack =3D false; - bool allresumeack =3D true; - bool anyhavereset =3D false; - bool allhavereset =3D true; - bool anynonexistent; - bool allnonexistent; - bool reset_unavail =3D dm_ndmreset_active(s) || - ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTRESET); + hwaddr ebreak_addr =3D RISCV_DM_ROM_PROGBUF + s->progbuf_size * 4; =20 - dm_collect_selected_harts(s, &sel); + if (ebreak_addr + 4 > RISCV_DM_ROM_DATA) { + return; + } =20 - anynonexistent =3D sel.all_count > sel.valid_count; - allnonexistent =3D sel.valid_count =3D=3D 0 && sel.all_count > 0; + dm_rom_write32(s, ebreak_addr, s->impebreak ? DM_EBREAK : DM_NOP); +} =20 - if (sel.valid_count =3D=3D 0) { - allhalted =3D false; - allrunning =3D false; - allunavail =3D false; - allresumeack =3D false; - allhavereset =3D false; +static void dm_reset_rom_state(RISCVDMState *s) +{ + if (!s->rom_ptr) { + return; } =20 - for (int i =3D 0; i < sel.valid_count; i++) { - int h =3D sel.harts[i]; - bool halted =3D s->hart_halted[h]; - bool resumeack =3D s->hart_resumeack[h]; - bool havereset =3D s->hart_havereset[h]; + memset(s->rom_ptr + RISCV_DM_ROM_WORK_BASE, 0, RISCV_DM_ROM_WORK_SIZE); =20 - if (reset_unavail) { - anyunavail =3D true; - allhalted =3D false; - allrunning =3D false; - } else { - anyhalted |=3D halted; - allhalted &=3D halted; - anyrunning |=3D !halted; - allrunning &=3D !halted; - } + dm_flush_cmd_space(s); =20 - allunavail &=3D reset_unavail; - anyresumeack |=3D resumeack; - allresumeack &=3D resumeack; - anyhavereset |=3D havereset; - allhavereset &=3D havereset; + for (uint32_t i =3D 0; i < s->num_abstract_data; i++) { + dm_sync_data_to_rom(s, i); + } + for (uint32_t i =3D 0; i < s->progbuf_size; i++) { + dm_sync_progbuf_to_rom(s, i); } =20 - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYHALTED, anyhalted); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLHALTED, allhalted); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYRUNNING, anyrunning); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLRUNNING, allrunning); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYUNAVAIL, anyunavail); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLUNAVAIL, allunavail); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYNONEXISTENT, anynonexistent); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLNONEXISTENT, allnonexistent); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYRESUMEACK, anyresumeack); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLRESUMEACK, allresumeack); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYHAVERESET, anyhavereset); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLHAVERESET, allhavereset); - ARRAY_FIELD_DP32(s->regs, DMSTATUS, HASRESETHALTREQ, 1); + dm_update_impebreak(s); + dm_invalidate_dynamic_code(s); } =20 -static void dm_debug_reset(RISCVDMState *s); - static void dm_cpu_reset_on_cpu(CPUState *cpu, run_on_cpu_data data) { bool request_reset_halt =3D data.host_int; @@ -543,20 +537,93 @@ static void dm_reset_all_harts(RISCVDMState *s) } } =20 + +static inline void dm_set_cmderr(RISCVDMState *s, uint32_t err) +{ + uint32_t cur =3D ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, CMDERR); + if (cur =3D=3D RISCV_DM_CMDERR_NONE) { + ARRAY_FIELD_DP32(s->regs, ABSTRACTCS, CMDERR, err); + } +} + +static void dm_status_refresh(RISCVDMState *s) +{ + DMHartSelection sel; + bool anyhalted =3D false, allhalted =3D true; + bool anyrunning =3D false, allrunning =3D true; + bool anyunavail =3D false, allunavail =3D true; + bool anyresumeack =3D false, allresumeack =3D true; + bool anyhavereset =3D false, allhavereset =3D true; + bool anynonexistent =3D false, allnonexistent =3D false; + bool reset_unavail =3D dm_ndmreset_active(s) || + ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTRESET); + + dm_collect_selected_harts(s, &sel); + + anynonexistent =3D (sel.all_count > sel.valid_count); + allnonexistent =3D (sel.valid_count =3D=3D 0 && sel.all_count > 0); + + if (sel.valid_count =3D=3D 0) { + allhalted =3D false; + allrunning =3D false; + allunavail =3D false; + allresumeack =3D false; + allhavereset =3D false; + } + + for (int i =3D 0; i < sel.valid_count; i++) { + int h =3D sel.harts[i]; + bool halted =3D s->hart_halted[h]; + bool resumeack =3D s->hart_resumeack[h]; + bool havereset =3D s->hart_havereset[h]; + + if (reset_unavail) { + anyunavail =3D true; + allhalted =3D false; + allrunning =3D false; + } else { + anyhalted |=3D halted; + allhalted &=3D halted; + anyrunning |=3D !halted; + allrunning &=3D !halted; + } + + allunavail &=3D reset_unavail; + anyresumeack |=3D resumeack; + allresumeack &=3D resumeack; + anyhavereset |=3D havereset; + allhavereset &=3D havereset; + } + + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYHALTED, anyhalted); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLHALTED, allhalted); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYRUNNING, anyrunning); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLRUNNING, allrunning); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYUNAVAIL, anyunavail); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLUNAVAIL, allunavail); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYNONEXISTENT, anynonexistent); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLNONEXISTENT, allnonexistent); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYRESUMEACK, anyresumeack); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLRESUMEACK, allresumeack); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ANYHAVERESET, anyhavereset); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, ALLHAVERESET, allhavereset); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, HASRESETHALTREQ, 1); +} + + +static void dm_debug_reset(RISCVDMState *s); static uint64_t dm_dmcontrol_pre_write(RegisterInfo *reg, uint64_t val64) { RISCVDMState *s =3D RISCV_DM(reg->opaque); - uint32_t val =3D val64; + uint32_t val =3D (uint32_t)val64; uint32_t cur_ctl =3D s->regs[R_DMCONTROL]; bool busy =3D ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, BUSY); bool ndmreset_was =3D FIELD_EX32(cur_ctl, DMCONTROL, NDMRESET); bool hartreset_was =3D FIELD_EX32(cur_ctl, DMCONTROL, HARTRESET); - bool dmactive =3D FIELD_EX32(val, DMCONTROL, DMACTIVE); - DMHartSelection sel; - uint32_t stored =3D 0; =20 trace_riscv_dm_control_write(s->regs[R_DMCONTROL], val, busy); =20 + /* If busy, preserve hart selection and suppress run-control */ if (busy) { val =3D FIELD_DP32(val, DMCONTROL, HARTSELHI, ARRAY_FIELD_EX32(s->regs, DMCONTROL, HARTSELHI)); @@ -569,25 +636,34 @@ static uint64_t dm_dmcontrol_pre_write(RegisterInfo *= reg, uint64_t val64) val =3D FIELD_DP32(val, DMCONTROL, ACKHAVERESET, 0); } =20 + bool dmactive =3D FIELD_EX32(val, DMCONTROL, DMACTIVE); + if (!dmactive) { + /* dmactive=3D0: reset the DM */ dm_debug_reset(s); + /* Return the reset value (only dmactive=3D0) */ return 0; } =20 + /* Store first so helpers see updated fields */ s->regs[R_DMCONTROL] =3D val; + + DMHartSelection sel; dm_collect_selected_harts(s, &sel); =20 - if (FIELD_EX32(val, DMCONTROL, NDMRESET) && !ndmreset_was) { + bool ndmreset =3D FIELD_EX32(val, DMCONTROL, NDMRESET); + bool hartreset =3D FIELD_EX32(val, DMCONTROL, HARTRESET); + + if (ndmreset && !ndmreset_was) { dm_reset_all_harts(s); } - - if (FIELD_EX32(val, DMCONTROL, HARTRESET) && !hartreset_was) { + if (hartreset && !hartreset_was) { dm_reset_selected_harts(s, &sel); } =20 - ARRAY_FIELD_DP32(s->regs, DMSTATUS, NDMRESETPENDING, - FIELD_EX32(val, DMCONTROL, NDMRESET)); + ARRAY_FIELD_DP32(s->regs, DMSTATUS, NDMRESETPENDING, ndmreset); =20 + /* ACKHAVERESET: clear havereset for selected harts */ if (!busy && FIELD_EX32(val, DMCONTROL, ACKHAVERESET)) { for (int i =3D 0; i < sel.valid_count; i++) { s->hart_havereset[sel.harts[i]] =3D false; @@ -606,22 +682,24 @@ static uint64_t dm_dmcontrol_pre_write(RegisterInfo *= reg, uint64_t val64) } } =20 - if (!busy && FIELD_EX32(val, DMCONTROL, RESUMEREQ) && - !FIELD_EX32(val, DMCONTROL, HALTREQ)) { + /* RESUMEREQ */ + bool resumereq =3D FIELD_EX32(val, DMCONTROL, RESUMEREQ); + bool haltreq =3D FIELD_EX32(val, DMCONTROL, HALTREQ); + + if (!busy && resumereq && !haltreq) { for (int i =3D 0; i < sel.valid_count; i++) { int h =3D sel.harts[i]; - s->hart_resumeack[h] =3D false; dm_rom_write8(s, RISCV_DM_ROM_FLAGS + h, RISCV_DM_FLAG_RESUME); trace_riscv_dm_control_resume(h); } } =20 + /* HALTREQ */ if (!busy) { - if (FIELD_EX32(val, DMCONTROL, HALTREQ)) { + if (haltreq) { for (int i =3D 0; i < sel.valid_count; i++) { int h =3D sel.harts[i]; - dm_rom_write8(s, RISCV_DM_ROM_FLAGS + h, RISCV_DM_FLAG_CLE= AR); qemu_set_irq(s->halt_irqs[h], 1); trace_riscv_dm_control_halt(h); @@ -633,6 +711,12 @@ static uint64_t dm_dmcontrol_pre_write(RegisterInfo *r= eg, uint64_t val64) } } =20 + /* + * Build the stored value: only keep fields with readable semantics. + * WARZ fields (haltreq, resumereq, ackhavereset, setresethaltreq, + * clrresethaltreq, setkeepalive, clrkeepalive, ackunavail) read as 0. + */ + uint32_t stored =3D 0; stored =3D FIELD_DP32(stored, DMCONTROL, DMACTIVE, 1); stored =3D FIELD_DP32(stored, DMCONTROL, NDMRESET, FIELD_EX32(val, DMCONTROL, NDMRESET)); @@ -643,17 +727,17 @@ static uint64_t dm_dmcontrol_pre_write(RegisterInfo *= reg, uint64_t val64) stored =3D FIELD_DP32(stored, DMCONTROL, HASEL, FIELD_EX32(val, DMCONTROL, HASEL)); stored =3D FIELD_DP32(stored, DMCONTROL, HARTRESET, - FIELD_EX32(val, DMCONTROL, HARTRESET)); + hartreset); =20 s->dm_active =3D true; dm_status_refresh(s); + return stored; } =20 static uint64_t dm_dmstatus_post_read(RegisterInfo *reg, uint64_t val) { RISCVDMState *s =3D RISCV_DM(reg->opaque); - dm_status_refresh(s); return s->regs[R_DMSTATUS]; } @@ -661,8 +745,7 @@ static uint64_t dm_dmstatus_post_read(RegisterInfo *reg= , uint64_t val) static uint64_t dm_hartinfo_post_read(RegisterInfo *reg, uint64_t val) { RISCVDMState *s =3D RISCV_DM(reg->opaque); - uint32_t v =3D val; - + uint32_t v =3D 0; v =3D FIELD_DP32(v, HARTINFO, DATAADDR, RISCV_DM_ROM_DATA); v =3D FIELD_DP32(v, HARTINFO, DATASIZE, s->num_abstract_data); v =3D FIELD_DP32(v, HARTINFO, DATAACCESS, 1); @@ -673,9 +756,7 @@ static uint64_t dm_hartinfo_post_read(RegisterInfo *reg= , uint64_t val) static uint64_t dm_hawindowsel_pre_write(RegisterInfo *reg, uint64_t val64) { uint32_t max_sel =3D RISCV_DM_MAX_HARTS / RISCV_DM_HAWINDOW_SIZE; - uint32_t val =3D val64 & R_HAWINDOWSEL_HAWINDOWSEL_MASK; - - (void)reg; + uint32_t val =3D (uint32_t)val64 & R_HAWINDOWSEL_HAWINDOWSEL_MASK; if (val >=3D max_sel) { val =3D max_sel - 1; } @@ -686,9 +767,8 @@ static uint64_t dm_hawindow_pre_write(RegisterInfo *reg= , uint64_t val64) { RISCVDMState *s =3D RISCV_DM(reg->opaque); uint32_t wsel =3D ARRAY_FIELD_EX32(s->regs, HAWINDOWSEL, HAWINDOWSEL); - if (wsel < RISCV_DM_MAX_HARTS / RISCV_DM_HAWINDOW_SIZE) { - s->hawindow[wsel] =3D val64; + s->hawindow[wsel] =3D (uint32_t)val64; } return (uint32_t)val64; } @@ -697,69 +777,312 @@ static uint64_t dm_hawindow_post_read(RegisterInfo *= reg, uint64_t val) { RISCVDMState *s =3D RISCV_DM(reg->opaque); uint32_t wsel =3D ARRAY_FIELD_EX32(s->regs, HAWINDOWSEL, HAWINDOWSEL); - - (void)val; if (wsel < RISCV_DM_MAX_HARTS / RISCV_DM_HAWINDOW_SIZE) { return s->hawindow[wsel]; } return 0; } =20 +static uint64_t dm_abstractcs_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, BUSY)) { + dm_set_cmderr(s, RISCV_DM_CMDERR_BUSY); + return s->regs[R_ABSTRACTCS]; + } + + /* W1C on CMDERR */ + uint32_t w1c_bits =3D FIELD_EX32((uint32_t)val64, ABSTRACTCS, CMDERR); + uint32_t cur =3D s->regs[R_ABSTRACTCS]; + uint32_t cmderr =3D FIELD_EX32(cur, ABSTRACTCS, CMDERR); + cmderr &=3D ~w1c_bits; + cur =3D FIELD_DP32(cur, ABSTRACTCS, CMDERR, cmderr); + + return cur; +} + +static uint64_t dm_command_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + /* Stub: abstract command execution added in a follow-on patch. */ + s->last_cmd =3D (uint32_t)val64; + return s->regs[R_COMMAND]; +} + +static uint64_t dm_command_post_read(RegisterInfo *reg, uint64_t val) +{ + return 0; +} + +static uint64_t dm_abstractauto_pre_write(RegisterInfo *reg, uint64_t val6= 4) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, BUSY)) { + dm_set_cmderr(s, RISCV_DM_CMDERR_BUSY); + return s->regs[R_ABSTRACTAUTO]; + } + + /* Stub: autoexec trigger logic added in a follow-on patch. */ + uint32_t data_count =3D MIN(s->num_abstract_data, 12); + uint32_t pbuf_size =3D MIN(s->progbuf_size, 16); + uint32_t data_mask =3D data_count ? ((1u << data_count) - 1u) : 0; + uint32_t pbuf_mask =3D pbuf_size ? ((1u << pbuf_size) - 1u) : 0; + uint32_t mask =3D data_mask | (pbuf_mask << 16); + + return (uint32_t)val64 & mask; +} + +static uint64_t dm_data_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, BUSY)) { + dm_set_cmderr(s, RISCV_DM_CMDERR_BUSY); + return s->regs[reg->access->addr / 4]; + } + return (uint32_t)val64; +} + +static void dm_data_post_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + int index =3D (reg->access->addr - A_DATA0) / 4; + + dm_sync_data_to_rom(s, index); +} + +static uint64_t dm_data_post_read(RegisterInfo *reg, uint64_t val) +{ + return val; +} + +static uint64_t dm_progbuf_pre_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, ABSTRACTCS, BUSY)) { + dm_set_cmderr(s, RISCV_DM_CMDERR_BUSY); + return s->regs[reg->access->addr / 4]; + } + return (uint32_t)val64; +} + +static void dm_progbuf_post_write(RegisterInfo *reg, uint64_t val64) +{ + RISCVDMState *s =3D RISCV_DM(reg->opaque); + int index =3D (reg->access->addr - A_PROGBUF0) / 4; + + dm_sync_progbuf_to_rom(s, index); +} + +static uint64_t dm_progbuf_post_read(RegisterInfo *reg, uint64_t val) +{ + return val; +} + static uint64_t dm_haltsum0_post_read(RegisterInfo *reg, uint64_t val) { RISCVDMState *s =3D RISCV_DM(reg->opaque); - uint32_t sum =3D 0; - uint32_t base =3D 0; - uint32_t limit =3D MIN(s->num_harts, 32u); - - (void)val; - for (uint32_t h =3D base; h < limit; h++) { - if (s->hart_halted[h]) { - sum |=3D 1u << (h - base); + uint32_t result =3D 0; + uint32_t base =3D dm_get_hartsel(s) & ~0x1fu; + + for (uint32_t i =3D 0; i < 32; i++) { + uint32_t h =3D base + i; + if (h < s->num_harts && s->hart_halted[h]) { + result |=3D (1u << i); } } - return sum; + return result; } =20 static uint64_t dm_haltsum1_post_read(RegisterInfo *reg, uint64_t val) { RISCVDMState *s =3D RISCV_DM(reg->opaque); - uint32_t sum =3D 0; - - (void)reg; - (void)val; - for (uint32_t h =3D 0; h < s->num_harts; h++) { - if (s->hart_halted[h]) { - sum |=3D 1u << (h / 32); + uint32_t result =3D 0; + uint32_t base =3D dm_get_hartsel(s) & ~0x3ffu; + + for (uint32_t g =3D 0; g < 32; g++) { + for (uint32_t i =3D 0; i < 32; i++) { + uint32_t h =3D base + g * 32 + i; + if (h < s->num_harts && s->hart_halted[h]) { + result |=3D (1u << g); + break; + } } } - return sum; + return result; } =20 + static RegisterAccessInfo riscv_dm_regs_info[] =3D { + { .name =3D "DATA0", .addr =3D A_DATA0, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA1", .addr =3D A_DATA1, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA2", .addr =3D A_DATA2, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA3", .addr =3D A_DATA3, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA4", .addr =3D A_DATA4, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA5", .addr =3D A_DATA5, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA6", .addr =3D A_DATA6, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA7", .addr =3D A_DATA7, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA8", .addr =3D A_DATA8, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA9", .addr =3D A_DATA9, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA10", .addr =3D A_DATA10, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DATA11", .addr =3D A_DATA11, .pre_write =3D dm_data_pre_w= rite, + .post_write =3D dm_data_post_write, .post_read =3D dm_data_post_read= , }, + { .name =3D "DMCONTROL", .addr =3D A_DMCONTROL, .pre_write =3D dm_dmcontrol_pre_write, }, + { .name =3D "DMSTATUS", .addr =3D A_DMSTATUS, - .ro =3D 0xffffffff, + .ro =3D 0xFFFFFFFF, .post_read =3D dm_dmstatus_post_read, }, + { .name =3D "HARTINFO", .addr =3D A_HARTINFO, - .ro =3D 0xffffffff, + .ro =3D 0xFFFFFFFF, .post_read =3D dm_hartinfo_post_read, }, + { .name =3D "HALTSUM1", .addr =3D A_HALTSUM1, - .ro =3D 0xffffffff, + .ro =3D 0xFFFFFFFF, .post_read =3D dm_haltsum1_post_read, }, + { .name =3D "HAWINDOWSEL", .addr =3D A_HAWINDOWSEL, .pre_write =3D dm_hawindowsel_pre_write, }, + { .name =3D "HAWINDOW", .addr =3D A_HAWINDOW, .pre_write =3D dm_hawindow_pre_write, .post_read =3D dm_hawindow_post_read, }, + { .name =3D "ABSTRACTCS", .addr =3D A_ABSTRACTCS, - .ro =3D 0xffffffff, }, + .ro =3D R_ABSTRACTCS_DATACOUNT_MASK | R_ABSTRACTCS_BUSY_MASK | + R_ABSTRACTCS_PROGBUFSIZE_MASK, + .pre_write =3D dm_abstractcs_pre_write, }, + + { .name =3D "COMMAND", .addr =3D A_COMMAND, + .pre_write =3D dm_command_pre_write, + .post_read =3D dm_command_post_read, }, + + { .name =3D "ABSTRACTAUTO", .addr =3D A_ABSTRACTAUTO, + .pre_write =3D dm_abstractauto_pre_write, }, + + { .name =3D "CONFSTRPTR0", .addr =3D A_CONFSTRPTR0, .ro =3D 0xFFFFFFFF= , }, + { .name =3D "CONFSTRPTR1", .addr =3D A_CONFSTRPTR1, .ro =3D 0xFFFFFFFF= , }, + { .name =3D "CONFSTRPTR2", .addr =3D A_CONFSTRPTR2, .ro =3D 0xFFFFFFFF= , }, + { .name =3D "CONFSTRPTR3", .addr =3D A_CONFSTRPTR3, .ro =3D 0xFFFFFFFF= , }, + + { .name =3D "NEXTDM", .addr =3D A_NEXTDM, .ro =3D 0xFFFFFFFF, }, + + { .name =3D "PROGBUF0", .addr =3D A_PROGBUF0, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF1", .addr =3D A_PROGBUF1, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF2", .addr =3D A_PROGBUF2, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF3", .addr =3D A_PROGBUF3, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF4", .addr =3D A_PROGBUF4, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF5", .addr =3D A_PROGBUF5, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF6", .addr =3D A_PROGBUF6, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF7", .addr =3D A_PROGBUF7, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF8", .addr =3D A_PROGBUF8, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF9", .addr =3D A_PROGBUF9, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF10", .addr =3D A_PROGBUF10, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF11", .addr =3D A_PROGBUF11, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF12", .addr =3D A_PROGBUF12, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF13", .addr =3D A_PROGBUF13, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF14", .addr =3D A_PROGBUF14, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + { .name =3D "PROGBUF15", .addr =3D A_PROGBUF15, + .pre_write =3D dm_progbuf_pre_write, + .post_write =3D dm_progbuf_post_write, + .post_read =3D dm_progbuf_post_read, }, + + { .name =3D "AUTHDATA", .addr =3D A_AUTHDATA, }, + + { .name =3D "DMCS2", .addr =3D A_DMCS2, }, + + { .name =3D "HALTSUM2", .addr =3D A_HALTSUM2, .ro =3D 0xFFFFFFFF, }, + { .name =3D "HALTSUM3", .addr =3D A_HALTSUM3, .ro =3D 0xFFFFFFFF, }, + + { .name =3D "SBADDRESS3", .addr =3D A_SBADDRESS3, }, + + { .name =3D "SBCS", .addr =3D A_SBCS, + .ro =3D R_SBCS_SBACCESS8_MASK | R_SBCS_SBACCESS16_MASK | + R_SBCS_SBACCESS32_MASK | R_SBCS_SBACCESS64_MASK | + R_SBCS_SBACCESS128_MASK | R_SBCS_SBASIZE_MASK | + R_SBCS_SBBUSY_MASK | R_SBCS_SBVERSION_MASK, }, + + { .name =3D "SBADDRESS0", .addr =3D A_SBADDRESS0, }, + + { .name =3D "SBADDRESS1", .addr =3D A_SBADDRESS1, }, + + { .name =3D "SBADDRESS2", .addr =3D A_SBADDRESS2, }, + + { .name =3D "SBDATA0", .addr =3D A_SBDATA0, }, + + { .name =3D "SBDATA1", .addr =3D A_SBDATA1, }, + + { .name =3D "SBDATA2", .addr =3D A_SBDATA2, }, + { .name =3D "SBDATA3", .addr =3D A_SBDATA3, }, + { .name =3D "HALTSUM0", .addr =3D A_HALTSUM0, - .ro =3D 0xffffffff, + .ro =3D 0xFFFFFFFF, .post_read =3D dm_haltsum0_post_read, }, }; =20 + static uint64_t riscv_dm_read(void *opaque, hwaddr addr, unsigned size) { RegisterInfoArray *reg_array =3D opaque; @@ -829,6 +1152,16 @@ static uint64_t dm_rom_read(void *opaque, hwaddr offs= et, unsigned size) uint64_t ret; =20 ret =3D ldn_le_p(s->rom_ptr + offset, size); + + /* DATA area remap: reads from ROM DATA area return register values */ + if (offset >=3D RISCV_DM_ROM_DATA && + offset < RISCV_DM_ROM_DATA + s->num_abstract_data * 4) { + int idx =3D (offset - RISCV_DM_ROM_DATA) / 4; + if (size =3D=3D 4) { + ret =3D s->regs[R_DATA0 + idx]; + } + } + trace_riscv_dm_rom_access(offset, ret, size, false); return ret; } @@ -837,54 +1170,59 @@ static void dm_rom_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { RISCVDMState *s =3D opaque; - uint32_t hartsel; =20 stn_le_p(s->rom_ptr + offset, size, value); =20 trace_riscv_dm_rom_access(offset, value, size, true); =20 + /* CPU wrote to HARTID register =E2=86=92 hart has halted */ if (offset =3D=3D RISCV_DM_ROM_HARTID && size =3D=3D 4) { - hartsel =3D value; + uint32_t hartsel =3D (uint32_t)value; if (dm_hart_valid(s, hartsel)) { riscv_dm_hart_halted(s, hartsel); } - return; } =20 + /* CPU wrote GOING acknowledgment */ if (offset =3D=3D RISCV_DM_ROM_GOING && size =3D=3D 4) { - hartsel =3D dm_rom_read32(s, RISCV_DM_ROM_HARTID); + uint32_t hartsel =3D dm_rom_read32(s, RISCV_DM_ROM_HARTID); if (dm_hart_valid(s, hartsel)) { dm_rom_write8(s, RISCV_DM_ROM_FLAGS + hartsel, RISCV_DM_FLAG_CLEAR); trace_riscv_dm_going(hartsel); } - return; } =20 + /* CPU wrote RESUME acknowledgment */ if (offset =3D=3D RISCV_DM_ROM_RESUME && size =3D=3D 4) { - hartsel =3D value; + uint32_t hartsel =3D (uint32_t)value; if (dm_hart_valid(s, hartsel)) { riscv_dm_hart_resumed(s, hartsel); } - return; } =20 + /* CPU wrote EXCEPTION */ if (offset =3D=3D RISCV_DM_ROM_EXCP && size =3D=3D 4) { - hartsel =3D dm_rom_read32(s, RISCV_DM_ROM_HARTID); + uint32_t hartsel =3D dm_rom_read32(s, RISCV_DM_ROM_HARTID); if (dm_hart_valid(s, hartsel)) { riscv_dm_abstracts_exception(s, hartsel); } } + + /* DATA area remap: writes to ROM DATA area update registers */ + if (offset >=3D RISCV_DM_ROM_DATA && + offset < RISCV_DM_ROM_DATA + s->num_abstract_data * 4 && size =3D= =3D 4) { + int idx =3D (offset - RISCV_DM_ROM_DATA) / 4; + s->regs[R_DATA0 + idx] =3D (uint32_t)value; + } } =20 static const MemoryRegionOps dm_rom_ops =3D { .read =3D dm_rom_read, .write =3D dm_rom_write, .endianness =3D DEVICE_LITTLE_ENDIAN, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 4, - }, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 4, }; =20 static bool dm_rom_realize(RISCVDMState *s, Error **errp) @@ -967,12 +1305,18 @@ static bool dm_rom_realize(RISCVDMState *s, Error **= errp) "riscv-dm.rom-entry", &s->rom_mr, RISCV_DM_ROM_ENTRY, RISCV_DM_ROM_ENTRY_SIZE); =20 + /* + * Expose debug backing store in two non-overlapping physical windows: + * - work area at low addresses (mailbox/data/progbuf/flags) + * - ROM entry vector at VIRT_DM_ROM base + */ sysbus_init_mmio(sbd, &s->rom_work_alias_mr); sysbus_init_mmio(sbd, &s->rom_entry_alias_mr); =20 return true; } =20 + void riscv_dm_hart_halted(RISCVDMState *s, uint32_t hartsel) { if (!dm_hart_valid(s, hartsel)) { @@ -998,6 +1342,7 @@ void riscv_dm_hart_resumed(RISCVDMState *s, uint32_t h= artsel) s->hart_halted[hartsel] =3D false; s->hart_resumeack[hartsel] =3D true; dm_rom_write8(s, RISCV_DM_ROM_FLAGS + hartsel, RISCV_DM_FLAG_CLEAR); + dm_status_refresh(s); trace_riscv_dm_hart_resumed(hartsel); } @@ -1014,6 +1359,7 @@ void riscv_dm_abstracts_exception(RISCVDMState *s, ui= nt32_t hartsel) trace_riscv_dm_abstract_cmd_exception(hartsel); } =20 + static void dm_debug_reset(RISCVDMState *s) { s->dm_active =3D false; @@ -1048,15 +1394,18 @@ static void dm_debug_reset(RISCVDMState *s) dm_status_refresh(s); } =20 + static void riscv_dm_init(Object *obj) { RISCVDMState *s =3D RISCV_DM(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - s->reg_array =3D register_init_block32(DEVICE(obj), riscv_dm_regs_info, - ARRAY_SIZE(riscv_dm_regs_info), - s->regs_info, s->regs, &riscv_dm_= ops, - false, RISCV_DM_REG_SIZE); + s->reg_array =3D + register_init_block32(DEVICE(obj), riscv_dm_regs_info, + ARRAY_SIZE(riscv_dm_regs_info), + s->regs_info, s->regs, + &riscv_dm_ops, false, + RISCV_DM_REG_SIZE); =20 sysbus_init_mmio(sbd, &s->reg_array->mem); } @@ -1071,6 +1420,25 @@ static void riscv_dm_realize(DeviceState *dev, Error= **errp) return; } =20 + if (s->num_abstract_data =3D=3D 0 || s->num_abstract_data > 12) { + error_setg(errp, "riscv-dm: datacount %u must be in range 1..12", + s->num_abstract_data); + return; + } + + if (s->progbuf_size > 16) { + error_setg(errp, "riscv-dm: progbufsize %u exceeds maximum 16", + s->progbuf_size); + return; + } + + if (s->progbuf_size =3D=3D 1 && !s->impebreak) { + error_setg(errp, + "riscv-dm: progbufsize 1 requires impebreak to be enabl= ed"); + return; + } + + /* Allocate per-hart state */ if (s->num_harts > 0) { s->hart_halted =3D g_new0(bool, s->num_harts); s->hart_resumeack =3D g_new0(bool, s->num_harts); @@ -1089,19 +1457,19 @@ static void riscv_dm_realize(DeviceState *dev, Erro= r **errp) return; } =20 + /* Apply initial reset */ dm_debug_reset(s); } =20 static void riscv_dm_reset_hold(Object *obj, ResetType type) { - (void)type; - dm_debug_reset(RISCV_DM(obj)); + RISCVDMState *s =3D RISCV_DM(obj); + dm_debug_reset(s); } =20 static void riscv_dm_unrealize(DeviceState *dev) { RISCVDMState *s =3D RISCV_DM(dev); - g_free(s->hart_halted); g_free(s->hart_resumeack); g_free(s->hart_havereset); @@ -1109,6 +1477,7 @@ static void riscv_dm_unrealize(DeviceState *dev) g_free(s->halt_irqs); } =20 + static const Property riscv_dm_props[] =3D { DEFINE_PROP_UINT32("num-harts", RISCVDMState, num_harts, 1), DEFINE_PROP_UINT32("datacount", RISCVDMState, num_abstract_data, 2), @@ -1183,5 +1552,6 @@ DeviceState *riscv_dm_create(MemoryRegion *sys_mem, h= waddr base, /* MMIO region 2: debug ROM entry vector */ memory_region_add_subregion(sys_mem, base + RISCV_DM_ROM_ENTRY, sysbus_mmio_get_region(sbd, 2)); + return dev; } --=20 2.53.0