From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288286; cv=none; d=zohomail.com; s=zohoarc; b=agHNNubv4GQGODDrTrwt4hSMVxEt0M6/BKU8qg5NssgjGpx9F98SpAhKRrL5O9GYZKXavUCzpSbTGIa5lC5tcw3kE4whTC/cy3NndLcY+JLe9ZQnUqs4lfblvuwKNMJaa/aFAhLXJTuJydwH1vlCvCqmEPAQO4MbsnSHjk5lBYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288286; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zjIezAop/ZrvVCzTKsN+lfe7Jbi6I/6u2XiNmN/FKcI=; b=LeLRlpBehRYVUUEGPRPs8/hq4xQ0QxEovXKv1MnKwooTMZtixcO4MgorwNVsyLksZGOPK0gTHCTHso7zgfMtLgtaQAcqe0dSG9BYCM9aKIsjh3Zp7ShdYt/Pes+iAzOKqQ8f+ccvFKU/lGjy6416vdDFHolVsaufgdbahKgZQRg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608288286182357.41177507898124; Fri, 18 Dec 2020 02:44:46 -0800 (PST) Received: from localhost ([::1]:51998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDFc-0005Vu-Vh for importer@patchew.org; Fri, 18 Dec 2020 05:44:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9B-00064Z-3h; Fri, 18 Dec 2020 05:38:05 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55276 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD97-0003IC-W8; Fri, 18 Dec 2020 05:38:04 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id C2C045FA93; Fri, 18 Dec 2020 11:37:59 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 01/18] target/arm: remove redundant tests Date: Fri, 18 Dec 2020 12:37:42 +0200 Message-Id: <20201218103759.19929-1-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont In this context, the HCR value is the effective value, and thus is zero in secure mode. The tests for HCR.{F,I}MO are sufficient. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.c | 8 ++++---- target/arm/helper.c | 10 ++++------ 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d6188f6566..0f004d8e51 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -450,14 +450,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, break; =20 case EXCP_VFIQ: - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized and non-secure. */ + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized and non-secure. */ + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ return false; } return !(env->daif & PSTATE_I); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b8bcd6903..786950cfba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2083,13 +2083,11 @@ static void csselr_write(CPUARMState *env, const AR= MCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs =3D env_cpu(env); - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool el1 =3D arm_current_el(env) =3D=3D 1; + uint64_t hcr_el2 =3D el1 ? arm_hcr_el2_eff(env) : 0; uint64_t ret =3D 0; - bool allow_virt =3D (arm_current_el(env) =3D=3D 1 && - (!arm_is_secure_below_el3(env) || - (env->cp15.scr_el3 & SCR_EEL2))); =20 - if (allow_virt && (hcr_el2 & HCR_IMO)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |=3D CPSR_I; } @@ -2099,7 +2097,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMC= PRegInfo *ri) } } =20 - if (allow_virt && (hcr_el2 & HCR_FMO)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |=3D CPSR_F; } --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608287998; cv=none; d=zohomail.com; s=zohoarc; b=FxP5IBNtba+rVhRjfiEkKCWmUHsG8i1bLRE7rrgpMqrCZjvhOssOYAE7rrpXM4juyA4Dhwrl7tfHtrKe0ko16afr7DzYnPa6vEgfve3iGl66g2zSy/1jfGMuLPqGeZcvuWYG77WR1xXzBAX6qcYHm04uUA6Ufe1dnHB7RMATdSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608287998; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Dax2cXVBJa3NOoXgxgMq6eSe8H5SzlKbxcONi6s/ZpI=; b=nieLVQ2nPXsqCNsrmt/QboNzVW3W/HHwSLzrPgsbEApMdEsmROSbvbmicjvExPmpZ7xizZCWnZFQZMIG+0i7lrKk7yVkGbDUMYUM3pSEx9YxHjdNhDijLqDFlpEGdmb3Y27LUNyu0HKUqST5nqcuYwD+q7UlromrsQga62x5IdA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608287998472233.53637385713103; Fri, 18 Dec 2020 02:39:58 -0800 (PST) Received: from localhost ([::1]:38614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDAz-0008HZ-4x for importer@patchew.org; Fri, 18 Dec 2020 05:39:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9A-00063c-NV; Fri, 18 Dec 2020 05:38:04 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55278 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD97-0003IH-8V; Fri, 18 Dec 2020 05:38:02 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 18FBC5FD51; Fri, 18 Dec 2020 11:38:00 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 02/18] target/arm: add arm_is_el2_enabled() helper Date: Fri, 18 Dec 2020 12:37:43 +0200 Message-Id: <20201218103759.19929-2-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont This checks if EL2 is enabled (meaning EL2 registers take effects) in the current security context. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..a37ae8eac6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2072,6 +2072,18 @@ static inline bool arm_is_secure(CPUARMState *env) return arm_is_secure_below_el3(env); } =20 +/* + * Return true if the current security state has AArch64 EL2 or AArch32 Hy= p. + * This corresponds to the pseudocode EL2Enabled() + */ +static inline bool arm_is_el2_enabled(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_EL2)) { + return !arm_is_secure_below_el3(env); + } + return false; +} + #else static inline bool arm_is_secure_below_el3(CPUARMState *env) { @@ -2082,6 +2094,11 @@ static inline bool arm_is_secure(CPUARMState *env) { return false; } + +static inline bool arm_is_el2_enabled(CPUARMState *env) +{ + return false; +} #endif =20 /** --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288171; cv=none; d=zohomail.com; s=zohoarc; b=n5ciTAf0xdvQ68qCjtZwqH2f+/9BrCOEHDb7/Sspx23oOZKpoeeMBLp4Esuvr8DI3gn2ail8AENEqOl3qaHEuaADcckRu1hRd6nU4Y/ZO0W5nZ+xWHqn22uZKl/nW+HT3AS47eidpBZI4RY8Tvajov4bNu5QXODR8O8v0Ty2+Zs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288171; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lUUfKH0TVB36D5jCor6CU4U2/QSG6y7bmbfVUTsV0Q8=; b=Pslgs5DDChtvx24BbbxXdlvuamSaooYJVILBfDX1ME1PJiireyO6xvYils4GNdg8HjUEGSXNdQg9LVpEmLDx7ukIeiR6aWeRNcyEa1w8NG3w93RNUnn7+e5xbHz1i7bWqbx6o7+0m44hACutiXTaKNqDDmgnt1NuLmLNrVG4W9o= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160828817121488.74064695475965; Fri, 18 Dec 2020 02:42:51 -0800 (PST) Received: from localhost ([::1]:47810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDDl-0003mK-TX for importer@patchew.org; Fri, 18 Dec 2020 05:42:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9B-000665-NL; Fri, 18 Dec 2020 05:38:05 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55280 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD97-0003Il-KB; Fri, 18 Dec 2020 05:38:05 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 627885FFBB; Fri, 18 Dec 2020 11:38:00 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 03/18] target/arm: use arm_is_el2_enabled() where applicable Date: Fri, 18 Dec 2020 12:37:44 +0200 Message-Id: <20201218103759.19929-3-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Do not assume that EL2 is available in non-secure context. That equivalence is broken by ARMv8.4-SEL2. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/helper-a64.c | 8 +------- target/arm/helper.c | 33 +++++++++++++-------------------- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a37ae8eac6..c4e370df06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2134,7 +2134,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, i= nt el) return aa64; } =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)= ) { + if (arm_is_el2_enabled(env)) { aa64 =3D aa64 && (env->cp15.hcr_el2 & HCR_RW); } =20 @@ -3078,7 +3078,7 @@ static inline int arm_debug_target_el(CPUARMState *en= v) bool secure =3D arm_is_secure(env); bool route_to_el2 =3D false; =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { + if (arm_is_el2_enabled(env)) { route_to_el2 =3D env->cp15.hcr_el2 & HCR_TGE || env->cp15.mdcr_el2 & MDCR_TDE; } diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 30b2ad119f..c426c23d2c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -972,8 +972,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) if (new_el =3D=3D -1) { goto illegal_return; } - if (new_el > cur_el - || (new_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + if (new_el > cur_el || (new_el =3D=3D 2 && !arm_is_el2_enabled(env))) { /* Disallow return to an EL which is unimplemented or higher * than the current one. */ @@ -985,11 +984,6 @@ void HELPER(exception_return)(CPUARMState *env, uint64= _t new_pc) goto illegal_return; } =20 - if (new_el =3D=3D 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - if (new_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 786950cfba..9b82bcf5f9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1048,8 +1048,8 @@ static CPAccessResult cpacr_access(CPUARMState *env, = const ARMCPRegInfo *ri, { if (arm_feature(env, ARM_FEATURE_V8)) { /* Check if CPACR accesses are to be trapped to EL2 */ - if (arm_current_el(env) =3D=3D 1 && - (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { + if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && + (env->cp15.cptr_el[2] & CPTR_TCPAC)) { return CP_ACCESS_TRAP_EL2; /* Check if CPACR accesses are to be trapped to EL3 */ } else if (arm_current_el(env) < 3 && @@ -2519,7 +2519,7 @@ static CPAccessResult gt_counter_access(CPUARMState *= env, int timeridx, bool isread) { unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); + bool has_el2 =3D arm_is_el2_enabled(env); uint64_t hcr =3D arm_hcr_el2_eff(env); =20 switch (cur_el) { @@ -2543,8 +2543,7 @@ static CPAccessResult gt_counter_access(CPUARMState *= env, int timeridx, } } else { /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && + if (has_el2 && timeridx =3D=3D GTIMER_PHYS && !extract32(env->cp15.cnthctl_el2, 1, 1)) { return CP_ACCESS_TRAP_EL2; } @@ -2553,8 +2552,7 @@ static CPAccessResult gt_counter_access(CPUARMState *= env, int timeridx, =20 case 1: /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H= . */ - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && + if (has_el2 && timeridx =3D=3D GTIMER_PHYS && (hcr & HCR_E2H ? !extract32(env->cp15.cnthctl_el2, 10, 1) : !extract32(env->cp15.cnthctl_el2, 0, 1))) { @@ -2569,7 +2567,7 @@ static CPAccessResult gt_timer_access(CPUARMState *en= v, int timeridx, bool isread) { unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); + bool has_el2 =3D arm_is_el2_enabled(env); uint64_t hcr =3D arm_hcr_el2_eff(env); =20 switch (cur_el) { @@ -2590,8 +2588,7 @@ static CPAccessResult gt_timer_access(CPUARMState *en= v, int timeridx, /* fall through */ =20 case 1: - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure) { + if (has_el2 && timeridx =3D=3D GTIMER_PHYS) { if (hcr & HCR_E2H) { /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1= PTEN. */ if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { @@ -4247,11 +4244,9 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D= { =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D env_archcpu(env); unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); =20 - if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el =3D= =3D 1) { + if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { return env->cp15.vpidr_el2; } return raw_read(env, ri); @@ -4278,9 +4273,8 @@ static uint64_t mpidr_read_val(CPUARMState *env) static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el =3D=3D 1) { + if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { return env->cp15.vmpidr_el2; } return mpidr_read_val(env); @@ -5347,7 +5341,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) { uint64_t ret =3D env->cp15.hcr_el2; =20 - if (arm_is_secure_below_el3(env)) { + if (!arm_is_el2_enabled(env)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -6144,7 +6138,7 @@ int sve_exception_el(CPUARMState *env, int el) /* CPTR_EL2. Since TZ and TFP are positive, * they will be zero when EL2 is not present. */ - if (el <=3D 2 && !arm_is_secure_below_el3(env)) { + if (el <=3D 2 && arm_is_el2_enabled(env)) { if (env->cp15.cptr_el[2] & CPTR_TZ) { return 2; } @@ -8723,8 +8717,7 @@ static int bad_mode_switch(CPUARMState *env, int mode= , CPSRWriteType write_type) } return 0; case ARM_CPU_MODE_HYP: - return !arm_feature(env, ARM_FEATURE_EL2) - || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); + return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; case ARM_CPU_MODE_MON: return arm_current_el(env) < 3; default: @@ -12639,7 +12632,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) =20 /* CPTR_EL2 : present in v7VE or v8 */ if (cur_el <=3D 2 && extract32(env->cp15.cptr_el[2], 10, 1) - && !arm_is_secure_below_el3(env)) { + && arm_is_el2_enabled(env)) { /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ return 2; } --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288386; cv=none; d=zohomail.com; s=zohoarc; b=IP46R+/JyvvSsgqEyEtP0kJ1Q8OPtE8ZVT9JZwmniAXJvXwuw4xrBueai41sG5vEXZ2DVMDSoW2IHXizkDEfXhmRJKx0zQpvVjJwbZZKca4kS05+dwdUweJOG/fGzS4/BJ4iCDkUwDBASLJ/AtS52kgEOr2OW3cFeawaKGYhwYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288386; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TSx3JHlA+N7FUGHG5UeM0WdL6YYgaw08GvA5mIdY6bo=; b=cPn8l6Es8ERu41aamZ7yiwHHWa0QRrZqymgCI/dNeiEgx3UIkj/H46gIA5uVnzT9C0X6KfS0bYG8ej4knsP1opMTH1k8I0GzuNrn9p6PQnqifFv/XrP2VHSyZXxMaxxJJOKaL4Sy4FTfMURIolsKTSIPMj7raWCCZUl4tbIa1Ks= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160828838643441.19194950331337; Fri, 18 Dec 2020 02:46:26 -0800 (PST) Received: from localhost ([::1]:56392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDHF-0007HT-Ab for importer@patchew.org; Fri, 18 Dec 2020 05:46:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9C-00068I-Hq; Fri, 18 Dec 2020 05:38:06 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55282 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD99-0003J8-Jn; Fri, 18 Dec 2020 05:38:06 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id ABBBD6001B; Fri, 18 Dec 2020 11:38:00 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 04/18] target/arm: use arm_hcr_el2_eff() where applicable Date: Fri, 18 Dec 2020 12:37:45 +0200 Message-Id: <20201218103759.19929-4-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont This will simplify accessing HCR conditionally in secure state. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b82bcf5f9..c784efac8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4432,16 +4432,16 @@ static CPAccessResult aa64_cacheop_pou_access(CPUAR= MState *env, =20 static int vae1_tlbmask(CPUARMState *env) { - /* Since we exclude secure first, we may read HCR_EL2 directly. */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) - =3D=3D (HCR_E2H | HCR_TGE)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; + } else if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else { return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | @@ -9968,6 +9968,8 @@ static inline uint64_t regime_sctlr(CPUARMState *env,= ARMMMUIdx mmu_idx) static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { + uint64_t hcr_el2; + if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { @@ -9986,19 +9988,21 @@ static inline bool regime_translation_disabled(CPUA= RMState *env, } } =20 + hcr_el2 =3D arm_hcr_el2_eff(env); + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* HCR.DC means HCR.VM behaves as 1 */ - return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; + return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } =20 - if (env->cp15.hcr_el2 & HCR_TGE) { + if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { return true; } } =20 - if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx= )) { + if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -10349,7 +10353,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, fi->s1ptw =3D true; return ~0; } - if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) =3D= =3D 0) { + if ((arm_hcr_el2_eff(env) & HCR_PTW) && + (cacheattrs.attrs & 0xf0) =3D=3D 0) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -10782,7 +10787,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *en= v, uint8_t s2attrs) uint8_t hihint =3D 0, lohint =3D 0; =20 if (hiattr !=3D 0) { /* normal memory */ - if ((env->cp15.hcr_el2 & HCR_CD) !=3D 0) { /* cache disabled */ + if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ hiattr =3D loattr =3D 1; /* non-cacheable */ } else { if (hiattr !=3D 1) { /* Write-through or write-back */ @@ -12104,7 +12109,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, } =20 /* Combine the S1 and S2 cache attributes. */ - if (env->cp15.hcr_el2 & HCR_DC) { + if (arm_hcr_el2_eff(env) & HCR_DC) { /* * HCR.DC forces the first stage attributes to * Normal Non-Shareable, --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 18 Dec 2020 02:47:58 -0800 (PST) Received: from localhost ([::1]:60378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDIb-0000aU-91 for importer@patchew.org; Fri, 18 Dec 2020 05:47:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9B-000652-92; Fri, 18 Dec 2020 05:38:05 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55284 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD98-0003JJ-9g; Fri, 18 Dec 2020 05:38:04 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id E8F0B60088; Fri, 18 Dec 2020 11:38:00 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 05/18] target/arm: factor MDCR_EL2 common handling Date: Fri, 18 Dec 2020 12:37:46 +0200 Message-Id: <20201218103759.19929-5-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont This adds a common helper to compute the effective value of MDCR_EL2. That is the actual value if EL2 is enabled in the current security context, or 0 elsewise. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c784efac8c..b85c1bf9d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -538,6 +538,11 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMStat= e *env, return CP_ACCESS_TRAP_UNCATEGORIZED; } =20 +static uint64_t arm_mdcr_el2_eff(CPUARMState *env) +{ + return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; +} + /* Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA */ @@ -545,11 +550,11 @@ static CPAccessResult access_tdosa(CPUARMState *env, = const ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); - bool mdcr_el2_tdosa =3D (env->cp15.mdcr_el2 & MDCR_TDOSA) || - (env->cp15.mdcr_el2 & MDCR_TDE) || + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tdosa =3D (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TD= E) || (arm_hcr_el2_eff(env) & HCR_TGE); =20 - if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdosa) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { @@ -565,11 +570,11 @@ static CPAccessResult access_tdra(CPUARMState *env, c= onst ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); - bool mdcr_el2_tdra =3D (env->cp15.mdcr_el2 & MDCR_TDRA) || - (env->cp15.mdcr_el2 & MDCR_TDE) || + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tdra =3D (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE)= || (arm_hcr_el2_eff(env) & HCR_TGE); =20 - if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdra) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { @@ -585,11 +590,11 @@ static CPAccessResult access_tda(CPUARMState *env, co= nst ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); - bool mdcr_el2_tda =3D (env->cp15.mdcr_el2 & MDCR_TDA) || - (env->cp15.mdcr_el2 & MDCR_TDE) || + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || (arm_hcr_el2_eff(env) & HCR_TGE); =20 - if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tda) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { @@ -605,9 +610,9 @@ static CPAccessResult access_tpm(CPUARMState *env, cons= t ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { @@ -1347,12 +1352,12 @@ static CPAccessResult pmreg_access(CPUARMState *env= , const ARMCPRegInfo *ri, * trapping to EL2 or EL3 for other accesses. */ int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); =20 if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { return CP_ACCESS_TRAP; } - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { @@ -1431,7 +1436,8 @@ static bool pmu_counter_enabled(CPUARMState *env, uin= t8_t counter) bool enabled, prohibited, filtered; bool secure =3D arm_is_secure(env); int el =3D arm_current_el(env); - uint8_t hpmn =3D env->cp15.mdcr_el2 & MDCR_HPMN; + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + uint8_t hpmn =3D mdcr_el2 & MDCR_HPMN; =20 if (!arm_feature(env, ARM_FEATURE_PMU)) { return false; @@ -1441,13 +1447,13 @@ static bool pmu_counter_enabled(CPUARMState *env, u= int8_t counter) (counter < hpmn || counter =3D=3D 31)) { e =3D env->cp15.c9_pmcr & PMCRE; } else { - e =3D env->cp15.mdcr_el2 & MDCR_HPME; + e =3D mdcr_el2 & MDCR_HPME; } enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); =20 if (!secure) { if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { - prohibited =3D env->cp15.mdcr_el2 & MDCR_HPMD; + prohibited =3D mdcr_el2 & MDCR_HPMD; } else { prohibited =3D false; } --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288262; cv=none; d=zohomail.com; s=zohoarc; b=k/jS/VpwfwQIzPOEGeWd02sNk9i4jxsaucKmG7fvjbFt6lyn1OgXwY4Ro0ur5w5JmDGYqSXnrV7Rca2VRe5LfwMUqkIjexuiW7+6bkfqyP8sQO2kTlIjApbcJ8LXGX7LKJDBjQ7QoRssZaQydNTZc4YYGf2bZdhtobi41B6flqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288262; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u/mHDpUwCLJG0bICvoUeZlyIM5lb2teF0a1hQiaITTE=; b=ez1vz4111/+naWDu8P0s7wHOYIjmOE9cBpzadApUsLwM0SVkeK27hNfjI2Ehwk87hdy9bgisL4GgQywmnQ9hw05AagubJMcJYpRDz6wA4KUNqRz+O/c6YGbhVGAQH0Qw3tG3WwJbkORf3SmgUkGFlyFjfa9yiZHwSK2x/cbUQpM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160828826248740.85836003836482; Fri, 18 Dec 2020 02:44:22 -0800 (PST) Received: from localhost ([::1]:51048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDFE-00057O-4u for importer@patchew.org; Fri, 18 Dec 2020 05:44:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9D-00069k-7g; Fri, 18 Dec 2020 05:38:07 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55286 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9B-0003Jk-Ko; Fri, 18 Dec 2020 05:38:06 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 4251A6009A; Fri, 18 Dec 2020 11:38:01 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 06/18] target/arm: declare new AA64PFR0 bit-fields Date: Fri, 18 Dec 2020 12:37:47 +0200 Message-Id: <20201218103759.19929-6-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c4e370df06..6a5a253eb6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1881,6 +1881,12 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, SEL2, 36, 4) +FIELD(ID_AA64PFR0, MPAM, 40, 4) +FIELD(ID_AA64PFR0, AMU, 44, 4) +FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) =20 FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) @@ -3928,6 +3934,11 @@ static inline bool isar_feature_aa64_sve(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; } =20 +static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288534; cv=none; d=zohomail.com; s=zohoarc; b=Og5AvkivdV4NV1HCGRffJwcix2V6J/X2otVdnmSGjTSnVsqilsmS8WDDfaCVwAHrYl+bzBJh0cDRCEZAAOUs6HiwEx/+gJGy1a3qw1VUL1ySorxZcoej+a08e+lfxIoP3ichmZPqk6L8/Xp83D4vUn6L5Mq4TyZYugGs4WUQ5S8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288534; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uGjcI52vN7OBfrVJYYTgd0OFGlaClFg5kkA90tqPVDA=; b=KR3F3Ymzp6WZoudBMQZQyYugM/Xh8/+dpYQgGwGBzd1hF+Tj7K2ACTl2/U6woCFCCPz5kVKjEJUPCSUpPWEMrz8AkBhKfNww6Rp4/V33ikwgZMtA5IywMkLwMg5OrAbsc2FaDmclqxUm6H9QrnSHJbpwkAmx8XPSG9W35QCGuvI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608288534090968.7260940559349; Fri, 18 Dec 2020 02:48:54 -0800 (PST) Received: from localhost ([::1]:36496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDJd-0002K0-1x for importer@patchew.org; Fri, 18 Dec 2020 05:48:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9D-0006A8-CR; Fri, 18 Dec 2020 05:38:07 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55288 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9B-0003Jl-NL; Fri, 18 Dec 2020 05:38:07 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 7F6C4600E1; Fri, 18 Dec 2020 11:38:01 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table Date: Fri, 18 Dec 2020 12:37:48 +0200 Message-Id: <20201218103759.19929-7-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in secure mode, though it can only be AArch64. This patch adds the target EL for exceptions from 64-bit S-EL2. It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure mode. Those values were never used in practice as the effective value of HCR was always 0 in secure mode. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 10 +++++----- target/arm/op_helper.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b85c1bf9d8..99adac5cc1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9005,13 +9005,13 @@ static const int8_t target_el_table[2][2][2][2][2][= 4] =3D { {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, - {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, - {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, - {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, + {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, + {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, + {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, - {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, - {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, + {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, + {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, }; =20 /* diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ff91fe6121..5e0f123043 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -652,10 +652,10 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, target_el =3D exception_target_el(env); break; case CP_ACCESS_TRAP_EL2: - /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is + /* Requesting a trap to EL2 when we're in EL3 is * a bug in the access function. */ - assert(!arm_is_secure(env) && arm_current_el(env) !=3D 3); + assert(arm_current_el(env) !=3D 3); target_el =3D 2; break; case CP_ACCESS_TRAP_EL3: --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288878; cv=none; d=zohomail.com; s=zohoarc; b=Q6v9R/vWAxDHTvx/xzdJSAYTyIIIW8g/pNy5h8f0jmecntDzhD7gYssC95U9EGzxgXsulBJiHN82ooaFTY0AXamDSOSOBzWahboT2BTx7a/5trWdGSuhpFPwDdjIcNXtPgOfy+Z9eNkt4ZYquiEfOGr3akoXZsSTJoXLVP0DCro= ARC-Message-Signature: i=1; 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Fri, 18 Dec 2020 05:54:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9E-0006EB-OX; Fri, 18 Dec 2020 05:38:08 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55290 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9C-0003Kj-1b; Fri, 18 Dec 2020 05:38:08 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id BEE8660195; Fri, 18 Dec 2020 11:38:01 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 08/18] target/arm: add MMU stage 1 for Secure EL2 Date: Fri, 18 Dec 2020 12:37:49 +0200 Message-Id: <20201218103759.19929-8-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont This adds the MMU indices for EL2 stage 1 in secure state. To keep code contained, which is largelly identical between secure and non-secure modes, the MMU indices are reassigned. The new assignments provide a systematic pattern with a non-secure bit. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 37 +++++++---- target/arm/helper.c | 127 ++++++++++++++++++++++++------------- target/arm/internals.h | 12 ++++ target/arm/translate-a64.c | 4 ++ 5 files changed, 124 insertions(+), 58 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6321385b46..00e7d9e937 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 11 +#define NB_MMU_MODES 15 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a5a253eb6..ec96784bba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2979,6 +2979,9 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ =20 +/* Meanings of the bits for A profile mmu idx values */ +#define ARM_MMU_IDX_A_NS 0x8 + /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 @@ -2992,20 +2995,22 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, - - ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1_PAN =3D 3 | ARM_MMU_IDX_A, - - ARMMMUIdx_E2 =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2_PAN =3D 6 | ARM_MMU_IDX_A, - - ARMMMUIdx_SE10_0 =3D 7 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1_PAN =3D 9 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_SE20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_SE20_2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1_PAN =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE20_2_PAN =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE2 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, + + ARMMMUIdx_E10_0 =3D ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E20_0 =3D ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_1 =3D ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E20_2 =3D ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_1_PAN =3D ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E20_2_PAN =3D ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E2 =3D ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, =20 /* * These are not allocated TLBs and are used only for AT system @@ -3052,8 +3057,12 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(SE10_0), + TO_CORE_BIT(SE20_0), TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE20_2), TO_CORE_BIT(SE10_1_PAN), + TO_CORE_BIT(SE20_2_PAN), + TO_CORE_BIT(SE2), TO_CORE_BIT(SE3), =20 TO_CORE_BIT(MUser), diff --git a/target/arm/helper.c b/target/arm/helper.c index 99adac5cc1..e92408229b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2861,6 +2861,9 @@ static int gt_phys_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2873,6 +2876,9 @@ static int gt_virt_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3576,7 +3582,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_SE3; break; case 2: - g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ /* fall through */ case 1: if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { @@ -3672,7 +3678,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D ARMMMUIdx_E2; + mmu_idx =3D secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; @@ -3987,10 +3993,15 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *en= v, const ARMCPRegInfo *ri, */ if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { - tlb_flush_by_mmuidx(env_cpu(env), - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0); + uint16_t mask =3D ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); } @@ -4441,9 +4452,15 @@ static int vae1_tlbmask(CPUARMState *env) uint64_t hcr =3D arm_hcr_el2_eff(env); =20 if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; + uint16_t mask =3D ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + return mask; } else if (arm_is_secure_below_el3(env)) { return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_1_PAN | @@ -4468,17 +4485,20 @@ static int tlbbits_for_regime(CPUARMState *env, ARM= MMUIdx mmu_idx, =20 static int vae1_tlbbits(CPUARMState *env, uint64_t addr) { + uint64_t hcr =3D arm_hcr_el2_eff(env); ARMMMUIdx mmu_idx; =20 /* Only the regime of the mmu_idx below is significant. */ - if (arm_is_secure_below_el3(env)) { - mmu_idx =3D ARMMMUIdx_SE10_0; - } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) - =3D=3D (HCR_E2H | HCR_TGE)) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { mmu_idx =3D ARMMMUIdx_E20_0; } else { mmu_idx =3D ARMMMUIdx_E10_0; } + + if (arm_is_secure_below_el3(env)) { + mmu_idx &=3D ~ARM_MMU_IDX_A_NS; + } + return tlbbits_for_regime(env, mmu_idx, addr); } =20 @@ -4524,11 +4544,17 @@ static int alle1_tlbmask(CPUARMState *env) =20 static int e2_tlbmask(CPUARMState *env) { - /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_SE20_0 | + ARMMMUIdxBit_SE20_2 | + ARMMMUIdxBit_SE20_2_PAN | + ARMMMUIdxBit_SE2; + } else { + return ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2; + } } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4648,10 +4674,12 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); + bool secure =3D arm_is_secure_below_el3(env); + int mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + int bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx= _SE2, + pageaddr); =20 - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -9957,7 +9985,8 @@ uint64_t arm_sctlr(CPUARMState *env, int el) /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el =3D=3D 0) { ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1); + el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) + ? 2 : 1; } return env->cp15.sctlr_el[el]; } @@ -10086,6 +10115,7 @@ static inline bool regime_is_user(CPUARMState *env,= ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_SE10_0: case ARMMMUIdx_E20_0: + case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -12668,6 +12698,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE20_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -12677,6 +12708,9 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return 2; case ARMMMUIdx_SE3: return 3; @@ -12694,6 +12728,9 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState = *env, bool secstate) =20 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { + ARMMMUIdx idx; + uint64_t hcr; + if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } @@ -12701,40 +12738,43 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) /* See ARM pseudo-function ELIsInHost. */ switch (el) { case 0: - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdx_SE10_0; - } - if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HC= R_TGE) - && arm_el_is_aa64(env, 2)) { - return ARMMMUIdx_E20_0; + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + idx =3D ARMMMUIdx_E20_0; + } else { + idx =3D ARMMMUIdx_E10_0; } - return ARMMMUIdx_E10_0; + break; case 1: - if (arm_is_secure_below_el3(env)) { - if (env->pstate & PSTATE_PAN) { - return ARMMMUIdx_SE10_1_PAN; - } - return ARMMMUIdx_SE10_1; - } if (env->pstate & PSTATE_PAN) { - return ARMMMUIdx_E10_1_PAN; + idx =3D ARMMMUIdx_E10_1_PAN; + } else { + idx =3D ARMMMUIdx_E10_1; } - return ARMMMUIdx_E10_1; + break; case 2: - /* TODO: ARMv8.4-SecEL2 */ /* Note that TGE does not apply at EL2. */ - if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + if (arm_hcr_el2_eff(env) & HCR_E2H) { if (env->pstate & PSTATE_PAN) { - return ARMMMUIdx_E20_2_PAN; + idx =3D ARMMMUIdx_E20_2_PAN; + } else { + idx =3D ARMMMUIdx_E20_2; } - return ARMMMUIdx_E20_2; + } else { + idx =3D ARMMMUIdx_E2; } - return ARMMMUIdx_E2; + break; case 3: return ARMMMUIdx_SE3; default: g_assert_not_reached(); } + + if (arm_is_secure_below_el3(env)) { + idx &=3D ~ARM_MMU_IDX_A_NS; + } + + return idx; } =20 ARMMMUIdx arm_mmu_idx(CPUARMState *env) @@ -12899,7 +12939,8 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env= , int el, int fp_el, break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - /* TODO: ARMv8.4-SecEL2 */ + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: /* * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is * gated by HCR_EL2. =3D=3D '11', and so is LDTR. diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756..e4e6afef19 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -860,6 +860,9 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_id= x) case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -890,6 +893,10 @@ static inline bool regime_is_secure(CPUARMState *env, = ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_SE2: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -907,6 +914,7 @@ static inline bool regime_is_pan(CPUARMState *env, ARMM= MUIdx mmu_idx) case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -917,10 +925,14 @@ static inline bool regime_is_pan(CPUARMState *env, AR= MMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: + case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2e3fdfdf6b..1ff109ca40 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -118,6 +118,10 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_SE10_1_PAN: useridx =3D ARMMMUIdx_SE10_0; break; + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + useridx =3D ARMMMUIdx_SE20_0; + break; default: g_assert_not_reached(); } --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 18 Dec 2020 02:51:24 -0800 (PST) Received: from localhost ([::1]:44892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDM3-0005ka-Rh for importer@patchew.org; Fri, 18 Dec 2020 05:51:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9E-0006C3-1y; Fri, 18 Dec 2020 05:38:08 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55292 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9C-0003Km-1h; Fri, 18 Dec 2020 05:38:07 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 13CCA603C4; Fri, 18 Dec 2020 11:38:02 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 09/18] target/arm: add ARMv8.4-SEL2 system registers Date: Fri, 18 Dec 2020 12:37:50 +0200 Message-Id: <20201218103759.19929-9-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec96784bba..f6b59cb56b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -168,6 +168,11 @@ typedef struct { uint32_t base_mask; } TCR; =20 +#define VTCR_NSW (1u << 29) +#define VTCR_NSA (1u << 30) +#define VSTCR_SW VTCR_NSW +#define VSTCR_SA VTCR_NSA + /* Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. @@ -323,9 +328,11 @@ typedef struct CPUARMState { uint64_t ttbr1_el[4]; }; uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ + uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; TCR vtcr_el2; /* Virtualization Translation Control. */ + TCR vstcr_el2; /* Secure Virtualization Translation Control. */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register diff --git a/target/arm/helper.c b/target/arm/helper.c index e92408229b..32469abf92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5721,6 +5721,27 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3 || arm_is_secure_below_el3(env)) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { + { .name =3D "VSTTBR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D sel2_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.vsttbr_el2) }, + { .name =3D "VSTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, + .access =3D PL2_RW, .accessfn =3D sel2_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, + REGINFO_SENTINEL +}; + static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -7733,6 +7754,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, el2_v8_cp_reginfo); } + if (cpu_isar_feature(aa64_sel2, cpu)) { + define_arm_cp_regs(cpu, el2_sec_cp_reginfo); + } /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3)) { ARMCPRegInfo rvbar =3D { --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288459; cv=none; d=zohomail.com; s=zohoarc; b=Dgl56IS2E6x11JgkYRDWjC/Q++Y8gorENDtwF9+y5ydq4cbLCBtttsv51KbV/nnoKzEynZ6vHEnk4GCxeZnEwKqcqXNIPFTDITO9WQY9nVrD3Ee5a+VPrQ9n5jkBf1JVN4P7CdP6xR/1ksevWcf+oj7dMkx/3mPp1KpiAWWv1Sc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288459; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PWS0+Dc8vmI9jusHAs8UJDwXdFCkUGP5nUQZkkLcT28=; b=Wi58FTW9jKHQ4I4e9fSiQssnAkQ7/8cjllbKh0fSAxzO2eUFo0CJSVHCdfQkmijU36xTjT5F3X2ii5oLBEUN54EVmg1/KBCud40O/cJCWdqKd88DFkadj9GdSnbdrHewGA/r6QQMCNqwzAUV4+2leXpzNSRr/I4Cr3OQvZB0FGM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608288459152418.1815183294898; Fri, 18 Dec 2020 02:47:39 -0800 (PST) Received: from localhost ([::1]:59634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDIP-0000G7-Qg for importer@patchew.org; Fri, 18 Dec 2020 05:47:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9E-0006Bu-23; Fri, 18 Dec 2020 05:38:08 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55294 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9C-0003Kr-6q; Fri, 18 Dec 2020 05:38:07 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 52D60603D7; Fri, 18 Dec 2020 11:38:02 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 10/18] target/arm: handle VMID change in secure state Date: Fri, 18 Dec 2020 12:37:51 +0200 Message-Id: <20201218103759.19929-10-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont The VTTBR write callback so far assumes that the underlying VM lies in non-secure state. This handles the secure state scenario. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 32469abf92..649c9237ce 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4017,10 +4017,15 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, * the combined stage 1&2 tlbs (EL10_1 and EL10_0). */ if (raw_read(env, ri) !=3D value) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); + uint16_t mask =3D ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } } --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288623; cv=none; d=zohomail.com; s=zohoarc; b=Ajiex4Qg2GhOPYDJ1OV2E45i3UynW49Rbi2Z7p7WTy1kFgI/z0+DIvQ4342bCtFyEd9xBsPn/ywm4TorZUleTPF/d0Ti0osTuUTD4KV72Mx58bmsp4doXTulArz4mh3AKTmSVlOcwi1nKfvPs7FtgjdwHH/8W1NJBKeWPNaEGUo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288623; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JHknvnDR0kSzGQtG5Tjash3RMqcN5Illov61Tcq4U9U=; b=Pg9Cbc6wmfLNPoO2gP067s2fHbAV9bVF/GsdQL+Xdknn3U/SqMWsf2bGq6uDVAq4wrDrvX8dYGMKKln7TFy9aRjusEgM62/1wZTCsEL45a/6JqLyLUwemdHz6qCTuQVcTk+ydFz6wVdP3Mr5pPxcVpnqKYDPNS9GQmheTqxvksU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608288623612979.4688243464091; Fri, 18 Dec 2020 02:50:23 -0800 (PST) Received: from localhost ([::1]:42146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDL4-0004ab-A1 for importer@patchew.org; Fri, 18 Dec 2020 05:50:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46854) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9Y-00071I-4A; Fri, 18 Dec 2020 05:38:28 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55296 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9W-0003Ks-HD; Fri, 18 Dec 2020 05:38:27 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 920D25FD51; Fri, 18 Dec 2020 11:38:02 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 11/18] target/arm: do S1_ptw_translate() before address space lookup Date: Fri, 18 Dec 2020 12:37:52 +0200 Message-Id: <20201218103759.19929-11-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW bits can invert the secure flag for pagetable walks. This patchset allows S1_ptw_translate() to change the non-secure bit. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 649c9237ce..4b6ffcd326 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10396,7 +10396,7 @@ static bool get_level1_table_address(CPUARMState *e= nv, ARMMMUIdx mmu_idx, =20 /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, MemTxAttrs txattrs, + hwaddr addr, bool *is_secure, ARMMMUFaultInfo *fi) { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && @@ -10406,6 +10406,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, int s2prot; int ret; ARMCacheAttrs cacheattrs =3D {}; + MemTxAttrs txattrs =3D {}; + + assert(!*is_secure); /* TODO: S-EL2 */ =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Sta= ge2, false, @@ -10446,9 +10449,9 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr ad= dr, bool is_secure, AddressSpace *as; uint32_t data; =20 + addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); attrs.secure =3D is_secure; as =3D arm_addressspace(cs, attrs); - addr =3D S1_ptw_translate(env, mmu_idx, addr, attrs, fi); if (fi->s1ptw) { return 0; } @@ -10475,9 +10478,9 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr ad= dr, bool is_secure, AddressSpace *as; uint64_t data; =20 + addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); attrs.secure =3D is_secure; as =3D arm_addressspace(cs, attrs); - addr =3D S1_ptw_translate(env, mmu_idx, addr, attrs, fi); if (fi->s1ptw) { return 0; } --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288608; cv=none; d=zohomail.com; s=zohoarc; b=hl7yyFcRnYSGcz0sMRqqGik8Wyw+VM8zNQWQ+ZvpQosYip0nthszCVPrvZvJyvCHbeG/ul41djCq2tKw0MA83iV2RZXqbq4CNBen+MJac0xSOyIxng/JqoJl5FjyGiEK6RA5JH0iOjBqTZ2Wu9qUQJe/l70eyWVLu4Jg6tDviLU= ARC-Message-Signature: i=1; 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Fri, 18 Dec 2020 05:50:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9Z-00074V-AL; Fri, 18 Dec 2020 05:38:29 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55298 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9W-0003L7-NM; Fri, 18 Dec 2020 05:38:29 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id DD64D60413; Fri, 18 Dec 2020 11:38:02 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 12/18] target/arm: translate NS bit in page-walks Date: Fri, 18 Dec 2020 12:37:53 +0200 Message-Id: <20201218103759.19929-12-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4b6ffcd326..ff69b46d43 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10433,6 +10433,18 @@ static hwaddr S1_ptw_translate(CPUARMState *env, A= RMMMUIdx mmu_idx, fi->s1ptw =3D true; return ~0; } + + if (arm_is_secure_below_el3(env)) { + /* Check if page table walk is to secure or non-secure PA spac= e. */ + if (*is_secure) { + *is_secure =3D !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + *is_secure =3D !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!*is_secure); + } + addr =3D s2pa; } return addr; --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288598; cv=none; d=zohomail.com; s=zohoarc; b=NIIU4n0+k+KXo0BVikJV2fIc7TnE+PaG1kncX6EOm+geRNnUGCd+URweoS34qr+2HEctKdC5GqvbugtcXndmxi52syzrY11DkDHydYenrWa/wIHS0if8J+d73xRBnZMMj9PmTEUBWyzePTUQasenQKjc5nwXWuBU6saAsLtTOA0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288598; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 18 Dec 2020 05:38:27 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 28670606AE; Fri, 18 Dec 2020 11:38:03 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 13/18] target/arm: generalize 2-stage page-walk condition Date: Fri, 18 Dec 2020 12:37:54 +0200 Message-Id: <20201218103759.19929-13-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont The stage_1_mmu_idx() already effectively keeps track of which translation regimes have two stages. Don't hard-code another test. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ff69b46d43..6d60fa23c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12152,11 +12152,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong= address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || - mmu_idx =3D=3D ARMMMUIdx_E10_1 || - mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { + ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); + + if (mmu_idx !=3D s1_mmu_idx) { /* Call ourselves recursively to do the stage 1 and then stage 2 - * translations. + * translations if mmu_idx is a two-stage regime. */ if (arm_feature(env, ARM_FEATURE_EL2)) { hwaddr ipa; @@ -12164,9 +12164,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, int ret; ARMCacheAttrs cacheattrs2 =3D {}; =20 - ret =3D get_phys_addr(env, address, access_type, - stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fi, cacheattrs); + ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, &= ipa, + attrs, prot, page_size, fi, cacheattrs); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288965; cv=none; d=zohomail.com; s=zohoarc; b=K8GS2q3PHmWger7uN+xB4sGu42tTHrR49y/BtFxkX49F0Ns+dZ4oO4p1Cc6L2N1slxGZqNLlKuFVG6vVhmxU5KF0te9d8uUQ7f+eof/w50f7YKLbmBLzb07t3DQQwKKHg7hqKuMefPA76nJqSVA0nqPi4S7QsbFvUboS7FrivwA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288965; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X0Yj/PlCYdOeextHlKZZx8Xgro+Sl1p6u7o8VaSb8wE=; b=E26uQMtU1n4mUN3XBqDJ6/3N9RhBHRXJNnV3njoKYksCHSt/vCWfoKLfvIHdQTagHB7eEnGaIV7FjPYYUHTCNeXjodG1gmfecsYz1bF+BUpCcmGfjTrZSpTvyMyWD58IvHeTw94nwfrkSZ6OrvNMY4w8ItaBrkHs8ofhSk63qlU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608288965869123.64928197559072; Fri, 18 Dec 2020 02:56:05 -0800 (PST) Received: from localhost ([::1]:58830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDQa-00036Q-JC for importer@patchew.org; Fri, 18 Dec 2020 05:56:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9a-00075z-Am; Fri, 18 Dec 2020 05:38:30 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55302 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9X-0003LW-EW; Fri, 18 Dec 2020 05:38:30 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 67E7960718; Fri, 18 Dec 2020 11:38:03 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 14/18] target/arm: secure stage 2 translation regime Date: Fri, 18 Dec 2020 12:37:55 +0200 Message-Id: <20201218103759.19929-14-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 +++- target/arm/helper.c | 80 +++++++++++++++++++++++++++++------------- target/arm/internals.h | 22 ++++++++++++ 3 files changed, 83 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f6b59cb56b..9de4224f22 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3026,6 +3026,9 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE0 =3D 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE1 =3D 4 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_SE1_PAN =3D 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -3033,7 +3036,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 =3D 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S =3D 7 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. diff --git a/target/arm/helper.c b/target/arm/helper.c index 6d60fa23c9..5147d77861 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3429,7 +3429,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, uint32_t syn, fsr, fsc; bool take_exc =3D false; =20 - if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) + if (fi.s1ptw && current_el =3D=3D 1 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the @@ -3586,10 +3586,10 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* fall through */ case 1: if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN + mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN); } else { - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E= 1; + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; } break; default: @@ -3603,10 +3603,11 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_SE10_0; break; case 2: + g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E= 0; break; default: g_assert_not_reached(); @@ -3671,10 +3672,10 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_SE10_1_PAN + mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN); } else { - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E= 1; + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ @@ -3688,7 +3689,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; @@ -10054,7 +10055,7 @@ static inline bool regime_translation_disabled(CPUA= RMState *env, =20 hcr_el2 =3D arm_hcr_el2_eff(env); =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { /* HCR.DC means HCR.VM behaves as 1 */ return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } @@ -10087,6 +10088,9 @@ static inline uint64_t regime_ttbr(CPUARMState *env= , ARMMMUIdx mmu_idx, if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return env->cp15.vttbr_el2; } + if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { + return env->cp15.vsttbr_el2; + } if (ttbrn =3D=3D 0) { return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; } else { @@ -10102,6 +10106,12 @@ static inline uint64_t regime_ttbr(CPUARMState *en= v, ARMMMUIdx mmu_idx, static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_SE10_0: + return ARMMMUIdx_Stage1_SE0; + case ARMMMUIdx_SE10_1: + return ARMMMUIdx_Stage1_SE1; + case ARMMMUIdx_SE10_1_PAN: + return ARMMMUIdx_Stage1_SE1_PAN; case ARMMMUIdx_E10_0: return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: @@ -10146,6 +10156,7 @@ static inline bool regime_is_user(CPUARMState *env,= ARMMMUIdx mmu_idx) case ARMMMUIdx_E20_0: case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_SE0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -10311,6 +10322,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx m= mu_idx, bool is_aa64, int wxn =3D 0; =20 assert(mmu_idx !=3D ARMMMUIdx_Stage2); + assert(mmu_idx !=3D ARMMMUIdx_Stage2_S); =20 user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); if (is_user) { @@ -10405,13 +10417,12 @@ static hwaddr S1_ptw_translate(CPUARMState *env, = ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; + ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S + : ARMMMUIdx_Stage2; ARMCacheAttrs cacheattrs =3D {}; MemTxAttrs txattrs =3D {}; =20 - assert(!*is_secure); /* TODO: S-EL2 */ - - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Sta= ge2, - false, + ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, &s2pa, &txattrs, &s2prot, &s2size, fi, &cacheattrs); if (ret) { @@ -10887,7 +10898,7 @@ static int aa64_va_parameter_tbi(uint64_t tcr, ARMM= MUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 37, 2); - } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx= _Stage2_S) { return 0; /* VTCR_EL2 */ } else { /* Replicate the single TBI bit so we always have 2 bits. */ @@ -10899,7 +10910,7 @@ static int aa64_va_parameter_tbid(uint64_t tcr, ARM= MMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 51, 2); - } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx= _Stage2_S) { return 0; /* VTCR_EL2 */ } else { /* Replicate the single TBID bit so we always have 2 bits. */ @@ -10929,7 +10940,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { /* VTCR_EL2 */ hpd =3D false; } else { @@ -10987,6 +10998,8 @@ static ARMVAParameters aa32_va_parameters(CPUARMSta= te *env, uint32_t va, int select, tsz; bool epd, hpd; =20 + assert(mmu_idx !=3D ARMMMUIdx_Stage2_S); + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR */ bool sext =3D extract32(tcr, 4, 1); @@ -11152,7 +11165,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, goto do_fault; } =20 - if (mmu_idx !=3D ARMMMUIdx_Stage2) { + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { /* The starting level depends on the virtual address size (which c= an * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to @@ -11256,7 +11269,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, attrs =3D extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { /* Stage 2 table descriptors do not include any attribute fiel= ds */ break; } @@ -11286,8 +11299,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, u= int64_t address, =20 ap =3D extract32(attrs, 4, 2); =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - ns =3D true; + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + ns =3D true; + } xn =3D extract32(attrs, 11, 2); *prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { @@ -11314,7 +11329,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, arm_tlb_bti_gp(txattrs) =3D true; } =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0= , 4)); } else { /* Index into MAIR registers for cache attributes */ @@ -11333,7 +11348,8 @@ do_fault: fi->type =3D fault_type; fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2); + fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || + mmu_idx =3D=3D ARMMMUIdx_Stage2_S); return true; } =20 @@ -12163,6 +12179,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, int s2_prot; int ret; ARMCacheAttrs cacheattrs2 =3D {}; + ARMMMUIdx s2_mmu_idx; + bool is_el0; =20 ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, &= ipa, attrs, prot, page_size, fi, cacheattrs); @@ -12173,9 +12191,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, return ret; } =20 + s2_mmu_idx =3D attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_= Stage2; + is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; + /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_St= age2, - mmu_idx =3D=3D ARMMMUIdx_E10_0, + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, phys_ptr, attrs, &s2_prot, page_size, fi, &cacheattrs2); fi->s2addr =3D ipa; @@ -12202,6 +12222,18 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, cacheattrs->shareability =3D 0; } *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (arm_is_secure_below_el3(env)) { + if (attrs->secure) { + attrs->secure =3D + !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_= SW)); + } else { + attrs->secure =3D + !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_N= SW)) + || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA)); + } + } return 0; } else { /* @@ -12270,7 +12302,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.TranslateAddressS1Off. */ - if (mmu_idx !=3D ARMMMUIdx_Stage2) { + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { int r_el =3D regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); diff --git a/target/arm/internals.h b/target/arm/internals.h index e4e6afef19..3aec10263e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -851,6 +851,9 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_id= x) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -896,7 +899,11 @@ static inline bool regime_is_secure(CPUARMState *env, = ARMMMUIdx mmu_idx) case ARMMMUIdx_SE20_0: case ARMMMUIdx_SE20_2: case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_SE2: + case ARMMMUIdx_Stage2_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -911,6 +918,7 @@ static inline bool regime_is_pan(CPUARMState *env, ARMM= MUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_1_PAN: @@ -932,18 +940,22 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; case ARMMMUIdx_SE3: return 3; case ARMMMUIdx_SE10_0: + case ARMMMUIdx_Stage1_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_SE10_1: case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: @@ -967,6 +979,13 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMU= Idx mmu_idx) if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { return &env->cp15.vtcr_el2; } + if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { + /* + * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but + * those are not currently used by QEMU, so just return VSTCR_EL2. + */ + return &env->cp15.vstcr_el2; + } return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } =20 @@ -1169,6 +1188,9 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUI= dx mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: return true; 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Fri, 18 Dec 2020 11:38:03 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 15/18] target/arm: set HPFAR_EL2.NS on secure stage 2 faults Date: Fri, 18 Dec 2020 12:37:56 +0200 Message-Id: <20201218103759.19929-15-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 6 ++++++ target/arm/internals.h | 2 ++ target/arm/tlb_helper.c | 3 +++ 4 files changed, 13 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9de4224f22..e5c05111e1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1482,6 +1482,8 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 +#define HPFAR_NS (1ULL << 63) + #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5147d77861..f1c6b5b8ba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3444,6 +3444,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, target_el =3D 3; } else { env->cp15.hpfar_el2 =3D extract64(fi.s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi.s1ns) { + env->cp15.hpfar_el2 |=3D HPFAR_NS; + } target_el =3D 2; } take_exc =3D true; @@ -10430,6 +10433,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; + fi->s1ns =3D !*is_secure; return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && @@ -10442,6 +10446,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; + fi->s1ns =3D !*is_secure; return ~0; } =20 @@ -11350,6 +11355,7 @@ do_fault: /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2_S); + fi->s1ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; return true; } =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 3aec10263e..27cc93f15a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -593,6 +593,7 @@ typedef enum ARMFaultType { * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table = walk + * @s1ns: True if we faulted on a non-secure IPA while in secure state * @ea: True if we should set the EA (external abort type) bit in syndrome */ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; @@ -603,6 +604,7 @@ struct ARMMMUFaultInfo { int domain; bool stage2; bool s1ptw; + bool s1ns; bool ea; }; =20 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index b35dc8a011..df85079d9f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -63,6 +63,9 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, = vaddr addr, if (fi->stage2) { target_el =3D 2; env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi->s1ns) { + env->cp15.hpfar_el2 |=3D HPFAR_NS; + } } same_el =3D (arm_current_el(env) =3D=3D target_el); =20 --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608289143; cv=none; d=zohomail.com; s=zohoarc; b=RBmcpR1jegyT+fhZLozz7uhz1qgPIULmoGUP8c0ZaDhzpJdrQTB/234Se/VV8rqNBPeRwkaVIGZy6E0pw0P+qApEMGZ1PzrJx3QmYjtnKkU+sExm90JZc/7GkWs52DB2WJoF2GaMrOLGWOuY/rh/OHklWc4CcE/UKugASE5Jjbs= ARC-Message-Signature: i=1; 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Fri, 18 Dec 2020 05:59:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9b-000769-2W; Fri, 18 Dec 2020 05:38:31 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55286 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9X-0003Jk-VA; Fri, 18 Dec 2020 05:38:30 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id F042E607A0; Fri, 18 Dec 2020 11:38:03 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 16/18] target/arm: add ARMv8.4-SEL2 extension Date: Fri, 18 Dec 2020 12:37:57 +0200 Message-Id: <20201218103759.19929-16-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont This adds handling for the SCR_EL3.EEL2 bit. A translation block flag is added in A32 mode to route exceptions correctly from AArch32 S-EL1 to (AArch64) S-EL2. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.c | 2 +- target/arm/cpu.h | 11 ++++++++--- target/arm/helper.c | 22 +++++++++++++++++++--- target/arm/translate.c | 6 ++++-- target/arm/translate.h | 1 + 5 files changed, 33 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0f004d8e51..bcca324773 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -479,7 +479,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, * masked from Secure state. The HCR and SCR settings * don't affect the masking logic, only the interrupt routing. */ - if (target_el =3D=3D 3 || !secure) { + if (target_el =3D=3D 3 || !secure || (env->cp15.scr_el3 & SCR_= EEL2)) { unmasked =3D true; } } else { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5c05111e1..39abb2a36b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2094,7 +2094,10 @@ static inline bool arm_is_secure(CPUARMState *env) static inline bool arm_is_el2_enabled(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_EL2)) { - return !arm_is_secure_below_el3(env); + if (arm_is_secure_below_el3(env)) { + return (env->cp15.scr_el3 & SCR_EEL2) !=3D 0; + } + return true; } return false; } @@ -2141,7 +2144,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, i= nt el) return aa64; } =20 - if (arm_feature(env, ARM_FEATURE_EL3)) { + if (arm_feature(env, ARM_FEATURE_EL3) && + ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2)))= { aa64 =3D aa64 && (env->cp15.scr_el3 & SCR_RW); } =20 @@ -3297,7 +3301,7 @@ typedef ARMCPU ArchCPU; * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. * - * 31 20 18 14 9 0 + * 31 20 19 14 9 0 * +--------------+-----+-----+----------+--------------+ * | | | TBFLAG_A32 | | * | | +-----+----------+ TBFLAG_AM32 | @@ -3346,6 +3350,7 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 17, 1) +FIELD(TBFLAG_A32, EEL2, 18, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. diff --git a/target/arm/helper.c b/target/arm/helper.c index f1c6b5b8ba..a96daca233 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -532,6 +532,9 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState= *env, return CP_ACCESS_OK; } if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } return CP_ACCESS_TRAP_EL3; } /* This will be EL1 NS and EL2 NS, which just UNDEF */ @@ -2029,6 +2032,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |=3D SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_sel2, cpu)) { + valid_mask |=3D SCR_EEL2; + } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } @@ -3387,13 +3393,16 @@ static CPAccessResult ats_access(CPUARMState *env, = const ARMCPRegInfo *ri, bool isread) { if (ri->opc2 & 4) { - /* The ATS12NSO* operations must trap to EL3 if executed in + /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in * Secure EL1 (which can only happen if EL3 is AArch64). * They are simply UNDEF if executed from NS EL1. * They function normally from EL2 or EL3. */ if (arm_current_el(env) =3D=3D 1) { if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; + } return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; } return CP_ACCESS_TRAP_UNCATEGORIZED; @@ -3656,7 +3665,8 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) { - if (arm_current_el(env) =3D=3D 3 && !(env->cp15.scr_el3 & SCR_NS)) { + if (arm_current_el(env) =3D=3D 3 && + !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -5755,12 +5765,15 @@ static CPAccessResult nsacr_access(CPUARMState *env= , const ARMCPRegInfo *ri, bool isread) { /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. - * At Secure EL1 it traps to EL3. + * At Secure EL1 it traps to EL3 or EL2. */ if (arm_current_el(env) =3D=3D 3) { return CP_ACCESS_OK; } if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } return CP_ACCESS_TRAP_EL3; } /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads= . */ @@ -12895,6 +12908,9 @@ static uint32_t rebuild_hflags_common_32(CPUARMStat= e *env, int fp_el, flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + if (arm_is_secure_below_el3(env) && (env->cp15.scr_el3 & SCR_EEL2)) { + flags =3D FIELD_DP32(flags, TBFLAG_A32, EEL2, 1); + } =20 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } diff --git a/target/arm/translate.c b/target/arm/translate.c index f5acd32e76..31109839f1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2816,9 +2816,10 @@ static bool msr_banked_access_decode(DisasContext *s= , int r, int sysm, int rn, } if (s->current_el =3D=3D 1) { /* If we're in Secure EL1 (which implies that EL3 is AArch64) - * then accesses to Mon registers trap to EL3 + * then accesses to Mon registers trap to Secure EL2 if it exi= sts + * otherwise EL3. */ - exc_target =3D 3; + exc_target =3D s->sel2 ? 2 : 3; goto undef; } break; @@ -8845,6 +8846,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->sctlr_b =3D FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); dc->hstr_active =3D FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE); dc->ns =3D FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->sel2 =3D FIELD_EX32(tb_flags, TBFLAG_A32, EEL2); dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); if (arm_feature(env, ARM_FEATURE_XSCALE)) { dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); diff --git a/target/arm/translate.h b/target/arm/translate.h index 423b0e08df..bf3624791b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -32,6 +32,7 @@ typedef struct DisasContext { uint8_t tbid; /* TBI1|TBI0 for data */ uint8_t tcma; /* TCMA1|TCMA0 for MTE */ bool ns; /* Use non-secure CPREG bank on access */ + bool sel2; /* Secure EL2 enabled (only used in AArch32) */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; 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Fri, 18 Dec 2020 11:38:04 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 17/18] target/arm: enable Secure EL2 in max CPU Date: Fri, 18 Dec 2020 12:37:58 +0200 Message-Id: <20201218103759.19929-17-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cf9fc4bc6..3dc2f5da6c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -641,6 +641,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; --=20 2.29.2 From nobody Sun May 19 02:06:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608288857; cv=none; d=zohomail.com; s=zohoarc; b=Q9OnMzS+pFiRaZSxkwGTb7epVv2Rn/E1OeHIEbJF4jHZU5jd4h5XGb89FqALJ3RAxfEP09liP+JCuy20mYZ1F+LyOpJaKf9/Q/HYsxvghu/QWVQkKjGygAm14tY0O7ConHP5s1G0m6hBQXvMMjYWC0rsJtky6/9/Eos81YG5Bfc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608288857; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rDJK70FQhkMINSf9d9a2Jct+IrMHOAzfSQtQqXG2RT8=; b=BA1bwEg2oWBES1iGuxZ57vFeJbfwD2wuJVh6CDOlTTiPuQ//s+HgG9XYfNxguFWhn4IeEfBBJjVWRCShNHPn6VKCSA7LgF/hbCTOwhO4nZVbBqjzwBAn3O2Iqe7fzgr+odh5ON4jwYzyVqHzhKtEmPJw/l1M5yPyFRB/jTkhHcM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608288857855449.80195493332474; Fri, 18 Dec 2020 02:54:17 -0800 (PST) Received: from localhost ([::1]:52102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqDOp-0000Id-QY for importer@patchew.org; Fri, 18 Dec 2020 05:54:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqD9b-000768-1n; Fri, 18 Dec 2020 05:38:31 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:55288 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD9Y-0003Jl-4J; Fri, 18 Dec 2020 05:38:30 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 7821860804; Fri, 18 Dec 2020 11:38:04 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 18/18] target/arm: refactor vae1_tlbmask() Date: Fri, 18 Dec 2020 12:37:59 +0200 Message-Id: <20201218103759.19929-18-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <3337797.iIbC2pHGDl@basile.remlab.net> References: <3337797.iIbC2pHGDl@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a96daca233..df195c314c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4469,26 +4469,23 @@ static CPAccessResult aa64_cacheop_pou_access(CPUAR= MState *env, static int vae1_tlbmask(CPUARMState *env) { uint64_t hcr =3D arm_hcr_el2_eff(env); + uint16_t mask; =20 if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - uint16_t mask =3D ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - - return mask; - } else if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; + mask =3D ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; } else { - return ARMMMUIdxBit_E10_1 | + mask =3D ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + return mask; } =20 /* Return 56 if TBI is enabled, 64 otherwise. */ --=20 2.29.2