From nobody Mon Feb 9 00:46:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1541618388375581.9438274359287; Wed, 7 Nov 2018 11:19:48 -0800 (PST) Received: from localhost ([::1]:50383 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKTMh-0006Rn-15 for importer@patchew.org; Wed, 07 Nov 2018 14:19:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55939) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKTL8-0005S1-4T for qemu-devel@nongnu.org; Wed, 07 Nov 2018 14:18:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKTL5-0004Ge-9q for qemu-devel@nongnu.org; Wed, 07 Nov 2018 14:18:10 -0500 Received: from pio-pvt-msa1.bahnhof.se ([79.136.2.40]:60501) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gKTL4-0004GO-Tv for qemu-devel@nongnu.org; Wed, 07 Nov 2018 14:18:07 -0500 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTP id F05E13F7CB; Wed, 7 Nov 2018 20:18:05 +0100 (CET) Received: from pio-pvt-msa1.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa1.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ndPs9s_uTbY9; Wed, 7 Nov 2018 20:18:01 +0100 (CET) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id 54CE93F71C; Wed, 7 Nov 2018 20:18:01 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Date: Wed, 7 Nov 2018 20:18:01 +0100 From: Fredrik Noring To: Aleksandar Markovic , Aurelien Jarno , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson Message-ID: <3275cefbe30ccac35da7f5fc99fb038d46149192.1541616663.git.noring@nocrew.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.40 Subject: [Qemu-devel] [PATCH v2 1/6] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?Q?J=C3=BCrgen?= Urban , qemu-devel@nongnu.org, "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of the generic gen_HILO. Signed-off-by: Fredrik Noring Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 51 ++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 60320cbe69..8601333554 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4359,24 +4359,56 @@ static void gen_shift(DisasContext *ctx, uint32_t o= pc, tcg_temp_free(t1); } =20 +/* Copy GPR to and from TX79 HI1/LO1 register. */ +static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) +{ + if (reg =3D=3D 0 && (opc =3D=3D TX79_MMI_MFHI1 || opc =3D=3D TX79_MMI_= MFLO1)) { + /* Treat as NOP. */ + return; + } + + switch (opc) { + case TX79_MMI_MFHI1: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); + break; + case TX79_MMI_MFLO1: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); + break; + case TX79_MMI_MTHI1: + if (reg !=3D 0) { + tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]); + } else { + tcg_gen_movi_tl(cpu_HI[1], 0); + } + break; + case TX79_MMI_MTLO1: + if (reg !=3D 0) { + tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]); + } else { + tcg_gen_movi_tl(cpu_LO[1], 0); + } + break; + default: + MIPS_INVAL("mfthilo1 TX79"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { - if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D TX79_MMI_MFHI1 = || - opc =3D=3D OPC_MFLO || opc =3D=3D TX79_MMI_MFLO1)) { + if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D OPC_MFLO)) { /* Treat as NOP. */ return; } =20 if (acc !=3D 0) { - if (!(ctx->insn_flags & INSN_R5900)) { - check_dsp(ctx); - } + check_dsp(ctx); } =20 switch (opc) { case OPC_MFHI: - case TX79_MMI_MFHI1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); @@ -4387,7 +4419,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MFLO: - case TX79_MMI_MFLO1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); @@ -4398,7 +4429,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTHI: - case TX79_MMI_MTHI1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -4413,7 +4443,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTLO: - case TX79_MMI_MTLO1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -26500,11 +26529,11 @@ static void decode_tx79_mmi(CPUMIPSState *env, Di= sasContext *ctx) break; case TX79_MMI_MTLO1: case TX79_MMI_MTHI1: - gen_HILO(ctx, opc, 1, rs); + gen_HILO1_tx79(ctx, opc, rs); break; case TX79_MMI_MFLO1: case TX79_MMI_MFHI1: - gen_HILO(ctx, opc, 1, rd); + gen_HILO1_tx79(ctx, opc, rd); break; case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */ --=20 2.18.1