From nobody Mon Feb 9 07:55:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu ARC-Seal: i=1; a=rsa-sha256; t=1612138837; cv=none; d=zohomail.com; s=zohoarc; b=hLjQYIqiOvsMzcwsKNcSUz1hRubVAa7cBBc52BqeheJOrx51x79vpnZW4i6xkey8wQEP5sxyuxJHIp8hohxH6ddf8zIXUApqB+SFnjZTE2Xpd2sowq8c68JcVTc52xcfPTX0WCtywpv/vDcoOm2P/k1EPQoV4N9o+1GWCrNvKgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612138837; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iItKNyZL2TA8X+nBosybvf4Fc+r+LBiaz14evcl5WKg=; b=Pb4HVqWYe8gxn6PJeYuAPYfbWOQs4HjIi5ztjgaw+PPLBTp19LrbBzXfhwqC6tAfwcSzX/EpbMejDRBAbzl7YmMqUvjNLQUDeQwKPQoX1iK38Qn7oLbckMW8doNSFmsQBUw3cSSMsf5XjBTtN6lTHm13aA4Ay//2DW399/TuDzU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161213883770548.255500719713154; Sun, 31 Jan 2021 16:20:37 -0800 (PST) Received: from localhost ([::1]:41030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6MxI-00038C-7d for importer@patchew.org; Sun, 31 Jan 2021 19:20:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Mvg-0001ow-9h for qemu-devel@nongnu.org; Sun, 31 Jan 2021 19:18:57 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:22805) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6MvX-00017c-NN for qemu-devel@nongnu.org; Sun, 31 Jan 2021 19:18:56 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id AA4EC746397; Mon, 1 Feb 2021 01:18:44 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 13D87746344; Mon, 1 Feb 2021 01:18:44 +0100 (CET) Message-Id: <2dfe32672ee6ddce4b54c6bcfce579d35abeaf51.1612137712.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 1/6] m68k: improve cpu instantiation comments Date: Mon, 01 Feb 2021 01:01:52 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 9% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Lucien Murray-Pitts Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Lucien Murray-Pitts Improvement in comments for the instantiation functions. This is to highlight what each cpu class, in the 68000 series, contains in terms of instructions/features. Signed-off-by: Lucien Murray-Pitts Signed-off-by: BALATON Zoltan --- target/m68k/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++ target/m68k/cpu.h | 49 ++++++++++++++++++++++++++++------------------- 2 files changed, 73 insertions(+), 20 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b811a0bdde..ccf1c490c0 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -103,6 +103,7 @@ static void m5206_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); } =20 +/* Base feature set, including isns. for m68k family */ static void m68000_cpu_initfn(Object *obj) { M68kCPU *cpu =3D M68K_CPU(obj); @@ -135,6 +136,13 @@ static void m680x0_cpu_common(CPUM68KState *env) m68k_set_feature(env, M68K_FEATURE_MOVEP); } =20 +/* + * Adds BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST, CAS, CAS= 2, + * CHK2, CMP2, DIVSL, DIVUL, EXTB, PACK, TRAPcc, UNPK. + * + * 68020/30 only: + * CALLM, cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc + */ static void m68020_cpu_initfn(Object *obj) { M68kCPU *cpu =3D M68K_CPU(obj); @@ -144,6 +152,14 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_M68020); } =20 +/* + * Adds: PFLUSH (*5) + * 68030 Only: PFLUSHA (*5), PLOAD (*5), PMOVE + * 68030/40 Only: PTEST + * + * NOTES: + * 5. Not valid on MC68EC030 + */ static void m68030_cpu_initfn(Object *obj) { M68kCPU *cpu =3D M68K_CPU(obj); @@ -153,6 +169,23 @@ static void m68030_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_M68030); } =20 +/* + * Adds: CINV, CPUSH + * Adds all with Note *2: FABS, FSABS, FDABS, FADD, FSADD, FDADD, FBcc, FC= MP, + * FDBcc, FDIV, FSDIV, FDDIV, FMOVE, FSMOVE, FDMOVE, + * FMOVEM, FMUL, FSMUL, FDMUL, FNEG, FSNEG, FDNEG, = FNOP, + * FRESTORE, FSAVE, FScc, FSQRT, FSSQRT, FDSQRT, FS= UB, + * FSSUB, FDSUB, FTRAPcc, FTST + * + * Adds with Notes *2, and *3: FACOS, FASIN, FATAN, FATANH, FCOS, FCOSH, F= ETOX, + * FETOXM, FGETEXP, FGETMAN, FINT, FINTRZ, FLO= G10, + * FLOG2, FLOGN, FLOGNP1, FMOD, FMOVECR, FREM, + * FSCALE, FSGLDIV, FSGLMUL, FSIN, FSINCOS, FS= INH, + * FTAN, FTANH, FTENTOX, FTWOTOX + * NOTES: + * 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060. + * 3. These are software-supported instructions on the MC68040 and MC68060. + */ static void m68040_cpu_initfn(Object *obj) { M68kCPU *cpu =3D M68K_CPU(obj); @@ -162,6 +195,17 @@ static void m68040_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_M68040); } =20 +/* + * Adds: PLPA + * Adds all with Note *2: CAS, CAS2, MULS, MULU, CHK2, CMP2, DIVS, DIVU + * All Fxxxx instructions are as per m68040 with exception to; FMOVEM NOTE3 + * + * Does NOT implement MOVEP + * + * NOTES: + * 2. Not applicable to the MC68EC040, MC68LC040, MC68EC060, and MC68LC060. + * 3. These are software-supported instructions on the MC68040 and MC68060. + */ static void m68060_cpu_initfn(Object *obj) { M68kCPU *cpu =3D M68K_CPU(obj); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index de5b9875fe..1d59cbb3f4 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -450,39 +450,48 @@ void m68k_switch_sp(CPUM68KState *env); void do_m68k_semihosting(CPUM68KState *env, int nr); =20 /* + * The 68000 family is defined in six main CPU classes, the 680[012346]0. + * Generally each successive CPU adds enhanced data/stack/instructions. + * However, some features are only common to one, or a few classes. + * The features covers those subsets of instructons. + * + * CPU32/32+ are basically 680010 compatible with some 68020 class instruc= tons, + * and some additional CPU32 instructions. Mostly Supervisor state differe= nces. + * + * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. * There are 4 ColdFire core ISA revisions: A, A+, B and C. * Each feature covers the subset of instructions common to the * ISA revisions mentioned. */ =20 enum m68k_features { - M68K_FEATURE_M68000, + M68K_FEATURE_M68000, /* Base m68k instruction set */ M68K_FEATURE_M68020, M68K_FEATURE_M68030, M68K_FEATURE_M68040, M68K_FEATURE_M68060, - M68K_FEATURE_CF_ISA_A, - M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ - M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).= */ - M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */ + M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ + M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ + M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).= */ + M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B).= */ M68K_FEATURE_CF_FPU, M68K_FEATURE_CF_MAC, M68K_FEATURE_CF_EMAC, - M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ - M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */ - M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ - M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ - M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ - M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */ - M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */ - M68K_FEATURE_BCCL, /* Long conditional branches. */ - M68K_FEATURE_BITFIELD, /* Bit field insns. */ - M68K_FEATURE_FPU, - M68K_FEATURE_CAS, - M68K_FEATURE_BKPT, - M68K_FEATURE_RTD, - M68K_FEATURE_CHK2, - M68K_FEATURE_MOVEP, + M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */ + M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C= ).*/ + M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */ + M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */ + M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */ + M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */ + M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32)= */ + M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */ + M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */ + M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */ + M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ + M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ }; =20 static inline int m68k_feature(CPUM68KState *env, int feature) --=20 2.21.3