From nobody Wed Nov 5 16:58:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1497007700783704.3418348902425; Fri, 9 Jun 2017 04:28:20 -0700 (PDT) Received: from localhost ([::1]:53904 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJI5T-0004rq-7P for importer@patchew.org; Fri, 09 Jun 2017 07:28:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59158) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJI3j-0003dJ-H0 for qemu-devel@nongnu.org; Fri, 09 Jun 2017 07:26:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJI3h-0000Zu-1v for qemu-devel@nongnu.org; Fri, 09 Jun 2017 07:26:31 -0400 Received: from [59.151.112.132] (port=9596 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJI3g-0000ZG-4c for qemu-devel@nongnu.org; Fri, 09 Jun 2017 07:26:28 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 09 Jun 2017 19:26:23 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 1821147C7C85; Fri, 9 Jun 2017 19:26:23 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 9 Jun 2017 19:26:22 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19856500" From: Mao Zhongyi To: Date: Fri, 9 Jun 2017 19:24:40 +0800 Message-ID: <23d76336ccef24473bf20f83628818eb3d97dac4.1496994386.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: 1821147C7C85.A16AF X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v4 5/7] pci: Replace pci_add_capability() with pci_add_capability2() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, armbru@redhat.com, marcel@redhat.com, alex.williamson@redhat.com, dmitry@daynix.com, pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After the patch 'Make errp the last parameter of pci_add_capability()', pci_add_capability() and pci_add_capability2() now do exactly the same. So drop the wrapper pci_add_capability() of pci_add_capability2(), then replace the pci_add_capability() with pci_add_capability2() everywhere. Cc: pbonzini@redhat.com Cc: rth@twiddle.net Cc: ehabkost@redhat.com Cc: mst@redhat.com Cc: dmitry@daynix.com Cc: jasowang@redhat.com Cc: marcel@redhat.com Cc: alex.williamson@redhat.com Cc: armbru@redhat.com Suggested-by: Eduardo Habkost Signed-off-by: Mao Zhongyi --- hw/i386/amd_iommu.c | 6 +++--- hw/net/e1000e.c | 2 +- hw/net/eepro100.c | 2 +- hw/pci/pci.c | 16 ---------------- hw/pci/pci_bridge.c | 2 +- hw/pci/pcie.c | 4 ++-- hw/pci/shpc.c | 2 +- hw/pci/slotid_cap.c | 2 +- hw/vfio/pci.c | 2 +- hw/virtio/virtio-pci.c | 4 ++-- include/hw/pci/pci.h | 3 --- 11 files changed, 13 insertions(+), 32 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index d93ffc2..281fd16 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1158,19 +1158,19 @@ static void amdvi_realize(DeviceState *dev, Error *= *err) x86_iommu->type =3D TYPE_AMD; qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus); object_property_set_bool(OBJECT(&s->pci), true, "realized", err); - ret =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, + ret =3D pci_add_capability2(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, AMDVI_CAPAB_SIZE, err); if (ret < 0) { return; } s->capab_offset =3D ret; =20 - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, + ret =3D pci_add_capability2(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE, err); if (ret < 0) { return; } - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, + ret =3D pci_add_capability2(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE, err); if (ret < 0) { return; diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index d1b1a97..7d77261 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -374,7 +374,7 @@ static int e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) { Error *local_err =3D NULL; - int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, + int ret =3D pci_add_capability2(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF, &local_err); =20 if (local_err) { diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 5a4774a..0bdb725 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -570,7 +570,7 @@ static void e100_pci_reset(EEPRO100State *s, Error **er= rp) if (info->power_management) { /* Power Management Capabilities */ int cfg_offset =3D 0xdc; - int r =3D pci_add_capability(&s->dev, PCI_CAP_ID_PM, + int r =3D pci_add_capability2(&s->dev, PCI_CAP_ID_PM, cfg_offset, PCI_PM_SIZEOF, errp); if (r < 0) { diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2bba37a..e418ad6 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2259,22 +2259,6 @@ static void pci_del_option_rom(PCIDevice *pdev) } =20 /* - * if offset =3D 0, - * Find and reserve space and add capability to the linked list - * in pci config space - */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) -{ - int ret; - - ret =3D pci_add_capability2(pdev, cap_id, offset, size, errp); - - return ret; -} - -/* * On success, pci_add_capability2() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index bb0f3a3..c3f6215 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -46,7 +46,7 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, int pos; Error *local_err =3D NULL; =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, + pos =3D pci_add_capability2(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF, &local_err); if (pos < 0) { error_report_err(local_err); diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index f187512..9232baa 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -95,7 +95,7 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t= type, uint8_t port) =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, + pos =3D pci_add_capability2(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF, &local_err); if (pos < 0) { error_report_err(local_err); @@ -130,7 +130,7 @@ int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, ui= nt8_t type, =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, + pos =3D pci_add_capability2(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF, &local_err); if (pos < 0) { error_report_err(local_err); diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index d72d5e4..8219691 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -451,7 +451,7 @@ static int shpc_cap_add_config(PCIDevice *d) uint8_t *config; int config_offset; Error *local_err =3D NULL; - config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, + config_offset =3D pci_add_capability2(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_LENGTH, &local_err); if (config_offset < 0) { diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index bdca205..682afaa 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -24,7 +24,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, return -EINVAL; } =20 - cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, + cap =3D pci_add_capability2(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH, &local_err); if (cap < 0) { error_report_err(local_err); diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 70bfb59..190e056 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1743,7 +1743,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, i= nt pos, uint8_t size, PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); } =20 - pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, + pos =3D pci_add_capability2(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, errp); if (pos < 0) { return pos; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 1fc5059..9cd35b3 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1162,7 +1162,7 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *pro= xy, PCIDevice *dev =3D &proxy->pci_dev; int offset; =20 - offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, + offset =3D pci_add_capability2(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len, &error_abort); =20 assert(cap->cap_len >=3D sizeof *cap); @@ -1810,7 +1810,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Er= ror **errp) pos =3D pcie_endpoint_cap_init(pci_dev, 0); assert(pos > 0); =20 - pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, + pos =3D pci_add_capability2(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); if (pos < 0) { return; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index fe52aa8..836dfc7 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -355,9 +355,6 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion = *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); =20 -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp); --=20 2.9.3