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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1785833967; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type; bh=PUCRwA+bUw62h+ogH/Fji4Fq9p/iOalBFNMvNXXrtVI=; b=PvpnmqiypRUGq0+U48NtZyJ3/VT+S3eH4mFTNoSG9Oyd39kNlVvsD9Yt4DH+NC35S6D9n5 iEOQmyw1ByhmxWiLWBGgIN/MKsJlkADu32YQVcJ5ImN6ookiyVqyBeGEFF/l67Ep67BVYb lNLvlR9SApHMO6qskYHXxHOHLLSThBk= X-MC-Unique: C_OZw7iWOny_-oFo7DVODw-1 X-Mimecast-MFC-AGG-ID: C_OZw7iWOny_-oFo7DVODw_1785833965 Date: Tue, 4 Aug 2026 10:59:18 +0200 (CEST) From: Mikulas Patocka To: Yoshinori Sato , Richard Henderson cc: qemu-devel@nongnu.org Subject: [PATCH] linux-user/sh4: Initialize the FPSCR register on signal Message-ID: <22c7eceb-286c-090c-a128-f8a35565e560@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mpatocka@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.811, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1785834014518158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the SH4 architecture, the instructions that perform single precision and double precision floating point operations are encoded in the same way. The bit PR in the FPSCR register determines if the CPU performs single or double operation. According to the ABI, the PR bit must be set at function entry and function exit. GCC generates code that flips this bit as needed during function execution. If we get a signal, we must set the PR bit, so that the signal handler finds the bit in the expected state. Qemu lacked this logic, so that if the signal interrupts single-precision floating point calculation, the PR bit would be incorrectly clear at signal handler entry. If the signal handler performed some floating-point calculation, it would get incorrect result. This patch fixes the bug, by initializing the FPSCR register at signal entry. Note that we initialize the whole register, because the Linux kernel initializes the whole register too. Cc: qemu-stable@nongnu.org Signed-off-by: Mikulas Patocka Reviewed-by: Yoshinori Sato --- linux-user/sh4/signal.c | 4 ++++ 1 file changed, 4 insertions(+) Index: qemu/linux-user/sh4/signal.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu.orig/linux-user/sh4/signal.c 2026-08-02 18:03:09.000000000 +0200 +++ qemu/linux-user/sh4/signal.c 2026-08-04 09:40:21.000000000 +0200 @@ -206,6 +206,8 @@ void setup_frame(int sig, struct target_ __put_user(set->sig[i + 1], &frame->extramask[i]); } =20 + regs->fpscr =3D FPSCR_PR; + /* Set up to return from userspace. If provided, use a stub already in userspace. */ if (ka->sa_flags & TARGET_SA_RESTORER) { @@ -258,6 +260,8 @@ void setup_rt_frame(int sig, struct targ __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); } =20 + regs->fpscr =3D FPSCR_PR; + /* Set up to return from userspace. If provided, use a stub already in userspace. */ if (ka->sa_flags & TARGET_SA_RESTORER) {