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Mon, 6 Oct 2025 11:57:40 +0200 (CEST) Received: (qmail 18762 invoked by uid 990); 6 Oct 2025 09:57:40 -0000 Received: from unknown (HELO unkown) (::1) by skiff.uberspace.de (Haraka/3.0.1) with ESMTPSA; Mon, 06 Oct 2025 11:57:40 +0200 Authentication-Results: skiff.uberspace.de; auth=pass (plain) From: Julian Ganz To: qemu-devel@nongnu.org Cc: Julian Ganz , Richard Henderson , Song Gao Subject: [PATCH v7 10/25] target/loongarch: call plugin trap callbacks Date: Mon, 6 Oct 2025 11:57:05 +0200 Message-ID: <21a5bf2e810e2c1a3d278ba3ed98f4d4491763cb.1759744337.git.neither@nut.email> X-Mailer: git-send-email 2.49.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Bar: ----- X-Rspamd-Report: REPLY(-4) BAYES_HAM(-2.996214) MID_CONTAINS_FROM(1) MIME_GOOD(-0.1) R_MISSING_CHARSET(0.5) X-Rspamd-Score: -5.596214 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nut.email; s=uberspace; h=from:to:cc:subject:date; bh=T8phxctkNXHnTgk9Nb6JHfuj2CnAEADFPzUwA2KJPGI=; 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charset="utf-8" We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for loongarch targets. This architecture has one special "exception" for interrupts and no host calls. Reviewed-by: Richard Henderson Signed-off-by: Julian Ganz --- target/loongarch/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 993602fb8c..a8299dfee6 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -32,6 +32,7 @@ #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" +#include "qemu/plugin.h" #endif #include "tcg/tcg_loongarch.h" =20 @@ -172,6 +173,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) int cause =3D -1; bool tlbfill =3D FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); uint32_t vec_size =3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); + uint64_t last_pc =3D env->pc; =20 if (cs->exception_index !=3D EXCCODE_INT) { qemu_log_mask(CPU_LOG_INT, @@ -282,6 +284,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) __func__, env->pc, env->CSR_ERA, cause, env->CSR_BADV, env->CSR_DERA, vector, env->CSR_ECFG, env->CSR_ESTAT); + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); } else { if (tlbfill) { set_pc(env, env->CSR_TLBRENTRY); @@ -300,6 +303,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, env->CSR_BADI, env->gpr[11], cs->cpu_index, env->CSR_ASID); + qemu_plugin_vcpu_exception_cb(cs, last_pc); } cs->exception_index =3D -1; } --=20 2.49.1