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X-Received-From: 72.21.196.25 X-Mailman-Approved-At: Fri, 24 Aug 2018 16:47:11 -0400 Subject: [Qemu-devel] [PATCH 4/7] target/mips: Add MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MUL instruction. Signed-off-by: Craig Janeczek --- target/mips/translate.c | 55 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4ccccd5849..64fc6089bb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -365,6 +365,7 @@ enum { OPC_DCLZ =3D 0x24 | OPC_SPECIAL2, OPC_DCLO =3D 0x25 | OPC_SPECIAL2, /* MXU */ + OPC_MXU_D16MUL =3D 0x08 | OPC_SPECIAL2, OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, @@ -3794,15 +3795,28 @@ typedef union { uint32_t rb:5; uint32_t special2:6; } S8LDD; + + struct { + uint32_t op:6; + uint32_t xra:4; + uint32_t xrb:4; + uint32_t xrc:4; + uint32_t xrd:4; + uint32_t optn2:2; + uint32_t sel:2; + uint32_t special2:6; + } D16MUL; } MXU_OPCODE; =20 /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { #ifndef TARGET_MIPS64 /* Only works in 32 bit mode */ - TCGv t0, t1; + TCGv t0, t1, t2, t3; t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); MXU_OPCODE *opcode =3D (MXU_OPCODE *)&ctx->opcode; =20 switch (opc) { @@ -3882,10 +3896,48 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) } gen_store_mxu_gpr(t0, opcode->S8LDD.xra); break; + + case OPC_MXU_D16MUL: + if (opcode->D16MUL.sel =3D=3D 1) { + /* D16MULE is not supported */ + generate_exception_end(ctx, EXCP_RI); + } + gen_load_mxu_gpr(t1, opcode->D16MUL.xrb); + tcg_gen_ext16s_tl(t0, t1); + tcg_gen_shri_tl(t1, t1, 16); + tcg_gen_ext16s_tl(t1, t1); + gen_load_mxu_gpr(t3, opcode->D16MUL.xrc); + tcg_gen_ext16s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 16); + tcg_gen_ext16s_tl(t3, t3); + + switch (opcode->D16MUL.optn2) { + case 0: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, opcode->D16MUL.xra); + gen_store_mxu_gpr(t2, opcode->D16MUL.xrd); + break; } =20 tcg_temp_free(t0); tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); #else generate_exception_end(ctx, EXCP_RI); #endif @@ -17975,6 +18027,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MXU_S32I2M: case OPC_MXU_S32M2I: case OPC_MXU_S8LDD: + case OPC_MXU_D16MUL: gen_mxu(ctx, op1); break; =20 --=20 2.18.0