From nobody Fri Apr 4 06:07:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F08BB22B8AC for ; Thu, 27 Feb 2025 11:03:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654239; cv=none; b=ievuDfM2rbbcJznbYR8HfbkVonsSOn1HeL7XZqynYNEAG8Bb1SiyXA/wmB/5VGng+qtMQXGsYNhtdof/C9CcED0NbLDeuWev62JNGbXGFk0yJoiDzlAMpsqBrTEMo/nlzIxvnRYARBVOiLH3wASppRIsQO2GFx5zZluKU8wEUuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654239; c=relaxed/simple; bh=eHspDGfSHDBjvGed5owJw/mr3NFNxLc1K/KjIKK4C1M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XZv2LiZGNVkESOy8Vaz29cA3bfkdBDySng8M6lJnqfpEifdFZoUnADolnO7Uelkgu1VGcsacnj8C7CXA3vKEVoA1whjbvEMkpRxChSSbl0oXzozcaJAPpMN4+JAUdM1KYWwZZ1iOwlZwBaCWrCfjfWSejWzt9PSI99P2fp1zJ5k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Suhz0bRS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Suhz0bRS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5031CC113D0; Thu, 27 Feb 2025 11:03:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740654238; bh=eHspDGfSHDBjvGed5owJw/mr3NFNxLc1K/KjIKK4C1M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Suhz0bRSJUGn8iilEsSyF8S/LOTdn2uZzefkx23HdbGdQfVpLEFJMFBSBNhc0nWDC WREI5iVZvz8i3eQJvlipVwoHn+3nUv1PC/HN3Z0nm/Y7BkoxaA+8EZJR7SW/YjmiTb gF4kyk3Es7MptGe8LS/3IheP+ILrK+ZXrq2COvLEPYdKwZX+2vj+QjbCxNHDyLg5Wc 9b78JG0GI8irKHghv/bH3Y8il0AuUqkHmtkU6Wzcsnt1CbO4cvviVEzycss0wWpCYz ScC3v4dg7q4A0QyBIO0OYnuNt3Se9AqtkhvIjuhYwsGQJulqsZneJKiTTahsM6HUgd UgQ8iFpoCF4BA== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1tnbgK-00000001mRm-28au; Thu, 27 Feb 2025 12:03:56 +0100 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , Dongjiu Geng , linux-kernel@vger.kernel.org Subject: [PATCH v5 19/21] docs: hest: add new "etc/acpi_table_hest_addr" and update workflow Date: Thu, 27 Feb 2025 12:03:49 +0100 Message-ID: <205abbc22ce816d88aa6c1c7058607fe35aae1ea.1740653898.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" While the HEST layout didn't change, there are some internal changes related to how offsets are calculated and how memory error events are triggered. Update specs to reflect such changes. Signed-off-by: Mauro Carvalho Chehab --- docs/specs/acpi_hest_ghes.rst | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/docs/specs/acpi_hest_ghes.rst b/docs/specs/acpi_hest_ghes.rst index c3e9f8d9a702..f3cb3074b082 100644 --- a/docs/specs/acpi_hest_ghes.rst +++ b/docs/specs/acpi_hest_ghes.rst @@ -89,12 +89,21 @@ Design Details addresses in the "error_block_address" fields with a pointer to the respective "Error Status Data Block" in the "etc/hardware_errors" blob. =20 -(8) QEMU defines a third and write-only fw_cfg blob which is called - "etc/hardware_errors_addr". Through that blob, the firmware can send b= ack - the guest-side allocation addresses to QEMU. The "etc/hardware_errors_= addr" - blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER co= mmand - for the firmware. The firmware will write back the start address of - "etc/hardware_errors" blob to the fw_cfg file "etc/hardware_errors_add= r". +(8) QEMU defines a third and write-only fw_cfg blob to store the location + where the error block offsets, read ack registers and CPER records are + stored. + + Up to QEMU 9.2, the location was at "etc/hardware_errors_addr", and + contains an offset for the beginning of "etc/hardware_errors". + + Newer versions place the location at "etc/acpi_table_hest_addr", + pointing to the beginning of the HEST table. + + Through that such offsets, the firmware can send back the guest-side + allocation addresses to QEMU. They contain a 8-byte entry. QEMU genera= tes + a single WRITE_POINTER command for the firmware. The firmware will wri= te + back the start address of either "etc/hardware_errors" or HEST table at + the correspoinding address firmware. =20 (9) When QEMU gets a SIGBUS from the kernel, QEMU writes CPER into corresp= onding "Error Status Data Block", guest memory, and then injects platform spe= cific @@ -105,8 +114,5 @@ Design Details kernel, on receiving notification, guest APEI driver could read the C= PER error and take appropriate action. =20 -(11) kvm_arch_on_sigbus_vcpu() uses source_id as index in "etc/hardware_er= rors" to - find out "Error Status Data Block" entry corresponding to error sourc= e. So supported - source_id values should be assigned here and not be changed afterward= s to make sure - that guest will write error into expected "Error Status Data Block" e= ven if guest was - migrated to a newer QEMU. +(11) kvm_arch_on_sigbus_vcpu() report RAS errors via a SEA notifications, + when a SIGBUS event is triggered. --=20 2.48.1