From nobody Fri Oct 23 21:42:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=zte.com.cn Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792636044052642.8420778401012; Wed, 21 Oct 2026 19:27:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJiW9-0001Fg-JN; Wed, 21 Oct 2026 22:26:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJiW5-0001D2-R2; Wed, 21 Oct 2026 22:26:53 -0400 Received: from mxhk.zte.com.cn ([160.30.148.34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJiW3-0003S6-8s; Wed, 21 Oct 2026 22:26:53 -0400 Received: from mse-fl2.zte.com.cn (unknown [10.5.228.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mxhk.zte.com.cn (FangMail) with ESMTPS id 4j995K5BPBz5B0qN; Thu, 22 Oct 2026 10:26:45 +0800 (CST) Received: from szxlzmapp03.zte.com.cn ([10.5.231.207]) by mse-fl2.zte.com.cn with SMTP id 69M2QeLW024344; Thu, 22 Oct 2026 10:26:40 +0800 (+08) (envelope-from wang.yechao255@zte.com.cn) Received: from localhost.localdomain (unknown [10.234.74.162]) by smtp (Zmail) with SMTP; Thu, 22 Oct 2026 10:26:42 +0800 X-Zmail-TransId: 3e816ad97461026-1c1d0 X-Zmail-LocalSMTP: 1 X-ZMAIL-USEORIGINALEMLTOOUTBOUND: 1 X-Zmail-RealSender: wang.yechao255@zte.com.cn From: Wang Yechao To: Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Wang Yechao Subject: [PATCH v2 1/3] target/riscv/kvm: Detect SBI STA extension support Date: Thu, 22 Oct 2026 10:25:24 +0800 Message-ID: <20261022022535.437892-2-wang.yechao255@zte.com.cn> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20261022022535.437892-1-wang.yechao255@zte.com.cn> References: <20261022022535.437892-1-wang.yechao255@zte.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MAIL: mse-fl2.zte.com.cn 69M2QeLW024344 X-TLS: YES X-ENVELOPE-SENDER: wang.yechao255@zte.com.cn X-SOURCE-IP: 10.5.228.133 unknown Thu, 22 Oct 2026 10:26:45 +0800 X-CLEAN: YES X-Fangmail-Anti-Spam-Filtered: true X-Fangmail-MID-QID: 6AD97465.001/4j995K5BPBz5B0qN Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=160.30.148.34; envelope-from=wang.yechao255@zte.com.cn; helo=mxhk.zte.com.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792636046883158500 Content-Type: text/plain; charset="utf-8" Probe for the SBI STA extension by searching for a one-reg id built from KVM_REG_RISCV_SBI_EXT and KVM_RISCV_SBI_EXT_STA in the register list returned by KVM, following the existing SBI DBCN pattern, and record the result in kvm_sbi_sta.supported. This patch only adds capability detection; nothing consumes kvm_sbi_sta.supported yet. The register synchronization that uses it is added by a subsequent patch. Signed-off-by: Wang Yechao Reviewed-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c085b22b23..8ab43432dd 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -473,6 +473,12 @@ static KVMCPUConfig kvm_sbi_dbcn =3D { KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN }; =20 +static KVMCPUConfig kvm_sbi_sta =3D { + .name =3D "sbi_sta", + .kvm_reg_id =3D KVM_REG_RISCV | KVM_REG_SIZE_U64 | + KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_STA +}; + static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { uint64_t id, reg; @@ -1233,6 +1239,19 @@ static void kvm_riscv_check_sbi_dbcn_support(RISCVCP= U *cpu, } } =20 +static void kvm_riscv_check_sbi_sta_support(RISCVCPU *cpu, + struct kvm_reg_list *reglist) +{ + struct kvm_reg_list *reg_search; + + reg_search =3D bsearch(&kvm_sbi_sta.kvm_reg_id, reglist->reg, reglist-= >n, + sizeof(uint64_t), uint64_cmp); + + if (reg_search) { + kvm_sbi_sta.supported =3D true; + } +} + static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, struct kvm_reg_list *reglist) { @@ -1365,6 +1384,7 @@ static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScra= tchCPU *kvmcpu) } =20 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); + kvm_riscv_check_sbi_sta_support(cpu, reglist); kvm_riscv_read_csr_cfg(reglist); } =20 --=20 2.27.0 From nobody Fri Oct 23 21:42:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=zte.com.cn Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792636069966245.53310874801525; Wed, 21 Oct 2026 19:27:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJiWG-0001LI-6O; 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Thu, 22 Oct 2026 10:26:44 +0800 X-Zmail-TransId: 3e816ad97463026-1c1dc X-Zmail-LocalSMTP: 1 X-ZMAIL-USEORIGINALEMLTOOUTBOUND: 1 X-Zmail-RealSender: wang.yechao255@zte.com.cn From: Wang Yechao To: Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Wang Yechao Subject: [PATCH v2 2/3] target/riscv/kvm: Sync SBI STA shmem registers with KVM Date: Thu, 22 Oct 2026 10:25:25 +0800 Message-ID: <20261022022535.437892-3-wang.yechao255@zte.com.cn> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20261022022535.437892-1-wang.yechao255@zte.com.cn> References: <20261022022535.437892-1-wang.yechao255@zte.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MAIL: mse-fl1.zte.com.cn 69M2QhHA019007 X-TLS: YES X-ENVELOPE-SENDER: wang.yechao255@zte.com.cn X-SOURCE-IP: 10.5.228.132 unknown Thu, 22 Oct 2026 10:26:54 +0800 X-CLEAN: YES X-Fangmail-Anti-Spam-Filtered: true X-Fangmail-MID-QID: 6AD9746E.002/4j995V4Jkkz8XrrZ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=160.30.148.35; envelope-from=wang.yechao255@zte.com.cn; helo=mxhk.zte.com.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792636071346158500 Content-Type: text/plain; charset="utf-8" Now that SBI STA support is detected, synchronize the shared memory address (shmem_lo and shmem_hi) between KVM and QEMU using the KVM_REG_RISCV_SBI_STA one-reg interface. The shmem address is configured by the guest, so QEMU does not need to perform put reg operations during reset. Signed-off-by: Wang Yechao Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 6 +++ target/riscv/kvm/kvm-cpu.c | 97 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b65d631994..4da7963d3d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,6 +34,9 @@ #include "cpu_cfg.h" #include "qapi/qapi-types-common.h" #include "cpu-qom.h" +#ifdef CONFIG_KVM +#include +#endif =20 typedef struct CPUArchState CPURISCVState; =20 @@ -550,6 +553,9 @@ struct CPUArchState { /* KVM multiprocessor state */ uint32_t kvm_mp_state; bool kvm_mp_state_loaded; + + /* kvm sbi state */ + struct kvm_riscv_sbi_sta kvm_sbi_sta; #endif /* CONFIG_KVM */ }; =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 8ab43432dd..ba5ba63854 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -123,6 +123,11 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) =20 +#define RISCV_SBI_STA_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_SBI_STATE, \ + KVM_REG_RISCV_SBI_STA | \ + KVM_REG_RISCV_SBI_STA_REG(name)) + #define KVM_RISCV_GET_TIMER(cs, name, reg) \ do { \ int ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ @@ -1010,6 +1015,88 @@ static int kvm_riscv_put_regs_vector(CPUState *cs) return ret; } =20 +static int kvm_riscv_get_regs_sbi_sta(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong reg; + int ret =3D 0; + + if (!kvm_sbi_sta.supported) { + return 0; + } + + ret =3D kvm_get_one_reg(cs, RISCV_SBI_STA_REG(shmem_lo), ®); + if (ret) { + return ret; + } + env->kvm_sbi_sta.shmem_lo =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_SBI_STA_REG(shmem_hi), ®); + if (ret) { + return ret; + } + env->kvm_sbi_sta.shmem_hi =3D reg; + + return ret; +} + +static int kvm_riscv_get_regs_sbi_state(CPUState *cs) +{ + int ret =3D 0; + + ret =3D kvm_riscv_get_regs_sbi_sta(cs); + if (ret) { + return ret; + } + + return 0; +} + +static int kvm_riscv_put_regs_sbi_sta(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong reg; + int ret =3D 0; + + if (!kvm_sbi_sta.supported) { + return 0; + } + + reg =3D env->kvm_sbi_sta.shmem_lo; + ret =3D kvm_set_one_reg(cs, RISCV_SBI_STA_REG(shmem_lo), ®); + if (ret) { + return ret; + } + + reg =3D env->kvm_sbi_sta.shmem_hi; + ret =3D kvm_set_one_reg(cs, RISCV_SBI_STA_REG(shmem_hi), ®); + if (ret) { + return ret; + } + + return ret; +} + +static int kvm_riscv_put_regs_sbi_state(CPUState *cs, KvmPutState level) +{ + int ret =3D 0; + + /* + * The shmem address of SBI STA is configured by the guest. During res= et, + * QEMU does not need to perform put reg operations. + */ + if (level !=3D KVM_PUT_RESET_STATE) { + ret =3D kvm_riscv_put_regs_sbi_sta(cs); + if (ret) { + return ret; + } + } + + return ret; +} + typedef struct KVMScratchCPU { int kvmfd; int vmfd; @@ -1433,6 +1520,11 @@ int kvm_arch_get_registers(CPUState *cs, Error **err= p) return ret; } =20 + ret =3D kvm_riscv_get_regs_sbi_state(cs); + if (ret) { + return ret; + } + if (cap_has_mp_state) { struct kvm_mp_state mp_state; =20 @@ -1520,6 +1612,11 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState= level, Error **errp) return ret; } =20 + ret =3D kvm_riscv_put_regs_sbi_state(cs, level); + if (ret) { + return ret; + } + if (KVM_PUT_RESET_STATE =3D=3D level) { CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 --=20 2.27.0 From nobody Fri Oct 23 21:42:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=zte.com.cn Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792636079284214.7203595618323; Wed, 21 Oct 2026 19:27:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJiWD-0001Ih-GJ; Wed, 21 Oct 2026 22:27:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJiWA-0001Gp-C8; Wed, 21 Oct 2026 22:26:58 -0400 Received: from mxhk.zte.com.cn ([160.30.148.35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJiW8-0003T9-G2; Wed, 21 Oct 2026 22:26:57 -0400 Received: from mse-fl2.zte.com.cn (unknown [10.5.228.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mxhk.zte.com.cn (FangMail) with ESMTPS id 4j995T565Vz8XrrX; Thu, 22 Oct 2026 10:26:53 +0800 (CST) Received: from szxl2zmapp07.zte.com.cn ([10.1.32.52]) by mse-fl2.zte.com.cn with SMTP id 69M2QjLj024411; Thu, 22 Oct 2026 10:26:45 +0800 (+08) (envelope-from wang.yechao255@zte.com.cn) Received: from localhost.localdomain (unknown [10.234.74.162]) by smtp (Zmail) with SMTP; Thu, 22 Oct 2026 10:26:46 +0800 X-Zmail-TransId: 3e816ad97466026-1c1ea X-Zmail-LocalSMTP: 1 X-ZMAIL-USEORIGINALEMLTOOUTBOUND: 1 X-Zmail-RealSender: wang.yechao255@zte.com.cn From: Wang Yechao To: Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Wang Yechao Subject: [PATCH v2 3/3] target/riscv: Add SBI STA state to vmstate Date: Thu, 22 Oct 2026 10:25:26 +0800 Message-ID: <20261022022535.437892-4-wang.yechao255@zte.com.cn> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20261022022535.437892-1-wang.yechao255@zte.com.cn> References: <20261022022535.437892-1-wang.yechao255@zte.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MAIL: mse-fl2.zte.com.cn 69M2QjLj024411 X-TLS: YES X-ENVELOPE-SENDER: wang.yechao255@zte.com.cn X-SOURCE-IP: 10.5.228.133 unknown Thu, 22 Oct 2026 10:26:53 +0800 X-CLEAN: YES X-Fangmail-Anti-Spam-Filtered: true X-Fangmail-MID-QID: 6AD9746D.001/4j995T565Vz8XrrX Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=160.30.148.35; envelope-from=wang.yechao255@zte.com.cn; helo=mxhk.zte.com.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792636081685158500 Content-Type: text/plain; charset="utf-8" Save and restore the KVM SBI state as a vmstate subsection, so that a guest using SBI STA keeps working after live migration. Only the STA shmem address (shmem_lo and shmem_hi) is saved for now; other SBI state can be appended to kvm_sbi_state as it is added. Signed-off-by: Wang Yechao Reviewed-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 5 +++++ target/riscv/kvm/kvm_riscv.h | 1 + target/riscv/machine.c | 18 ++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index ba5ba63854..0586e290dd 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1015,6 +1015,11 @@ static int kvm_riscv_put_regs_vector(CPUState *cs) return ret; } =20 +bool kvm_riscv_has_sbi_sta_state(void) +{ + return kvm_sbi_sta.supported; +} + static int kvm_riscv_get_regs_sbi_sta(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index aef681f0a2..5e17bacad1 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -35,6 +35,7 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); bool kvm_riscv_has_mp_state(void); +bool kvm_riscv_has_sbi_sta_state(void); int kvm_riscv_check_timer_frequency(RISCVCPU *cpu); void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 0de06e9588..9fc699a482 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -318,6 +318,23 @@ static const VMStateDescription vmstate_kvm_mp_state = =3D { VMSTATE_END_OF_LIST() } }; + +static bool kvm_sbi_state_needed(void *opaque) +{ + return kvm_enabled() && kvm_riscv_has_sbi_sta_state(); +} + +static const VMStateDescription vmstate_kvm_sbi_state =3D { + .name =3D "cpu/kvm-sbi-state", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D kvm_sbi_state_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(env.kvm_sbi_sta.shmem_lo, RISCVCPU), + VMSTATE_UINT64(env.kvm_sbi_sta.shmem_hi, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; #endif =20 static bool debug_needed(void *opaque) @@ -645,6 +662,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_kvm_timer_frequency, &vmstate_kvmtimer, &vmstate_kvm_mp_state, + &vmstate_kvm_sbi_state, #endif &vmstate_envcfg, &vmstate_debug, --=20 2.27.0