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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1792666617; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mf6SO3/uI+ctOuFbT5rPNsyur+/OAm8KwsordM51mew=; b=ROCrhhJ49ObL7Kk3gx+n8m2xLTri++D/qqo8Rlx6FMCkLnSl1k9nMZ7ONlOffAcXk/CDpU K/HS7TxmEDRw7FywlI3+Ls9gzz31eJkotJwum3NKKOdh0gxZZzujyhj7vQZOyKWiVkgqjS goeONbAmSoL7joaakrf6bOPQaBszUyk= X-MC-Unique: vL3EZTvtOr-LlfXecE1Cqg-1 X-Mimecast-MFC-AGG-ID: vL3EZTvtOr-LlfXecE1Cqg_1792666609 From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Date: Thu, 22 Oct 2026 14:56:28 +0400 Subject: [PATCH v3 01/18] hmp: don't crash on invalid register MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261022-query-reg-v3-1-7ad902b9a7cf@redhat.com> References: <20261022-query-reg-v3-0-7ad902b9a7cf@redhat.com> In-Reply-To: <20261022-query-reg-v3-0-7ad902b9a7cf@redhat.com> To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Developer-Signature: v=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792667064525158500 When printing an invalid/denied register, QEMU crashes with: ERROR:include/qemu/bswap.h:488:ldn_le_p: code should not be reached (ex: "p $sireg" when siselect=3D0 on riscv) Return false instead. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Marc-Andr=C3=A9 Lureau --- monitor/hmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/monitor/hmp.c b/monitor/hmp.c index 7b80d8480055..e97e0a9ff0d7 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -424,7 +424,7 @@ static bool gdb_get_register(MonitorHMP *hmp, int64_t *= pval, const char *name) =20 buf =3D g_byte_array_new(); reg_size =3D gdb_read_register(cs, buf, reg->gdb_reg); - if (reg_size > sizeof(*pval)) { + if (reg_size =3D=3D 0 || reg_size > sizeof(*pval)) { return false; } =20 --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792666685; cv=none; d=zohomail.com; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666688135158500 Commit b3e88abb200c ("gdbstub: Consider GDBFeature::base_reg in gdb_register_coprocessor()") identified that register numbers may have gaps. We also need to adjust the next base_reg correctly to avoid overlapping registers. Rename the field to be more explicit about its usage. Acked-by: Alex Benn=C3=A9e Signed-off-by: Marc-Andr=C3=A9 Lureau --- gdbstub/gdbstub.c | 13 ++++++------- include/hw/core/cpu.h | 5 +++-- target/arm/gdbstub.c | 8 +++++--- target/arm/gdbstub64.c | 10 ++++++---- target/ppc/gdbstub.c | 2 +- target/riscv/gdbstub.c | 9 ++++++--- target/xtensa/cpu.c | 2 +- 7 files changed, 28 insertions(+), 21 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 0a328b0dd488..0ce871d74929 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -605,13 +605,13 @@ void gdb_init_cpu(CPUState *cpu) gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, feature); - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D feature->num_regs; + cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D feature->num_re= gs; } else { - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_reg= s; + cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D cc->gdb_num_cor= e_regs; } =20 trace_gdbxml_init_cpu(object_get_typename(OBJECT(cpu)), cpu->cpu_index, - cpu->gdb_num_regs, cpu->gdb_num_g_regs, + cpu->gdb_next_base_reg, cpu->gdb_num_g_regs, cc->gdb_num_core_regs); } =20 @@ -621,7 +621,7 @@ void gdb_register_coprocessor(CPUState *cpu, { GDBRegisterState *s; guint i; - int base_reg =3D cpu->gdb_num_regs; + int base_reg =3D cpu->gdb_next_base_reg; =20 for (i =3D 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ @@ -639,7 +639,7 @@ void gdb_register_coprocessor(CPUState *cpu, gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); =20 /* Add to end of list. */ - cpu->gdb_num_regs +=3D feature->num_regs; + cpu->gdb_next_base_reg =3D base_reg + feature->num_regs; } =20 void gdb_unregister_coprocessor_all(CPUState *cpu) @@ -651,7 +651,7 @@ void gdb_unregister_coprocessor_all(CPUState *cpu) g_array_free(cpu->gdb_regs, true); =20 cpu->gdb_regs =3D NULL; - cpu->gdb_num_regs =3D 0; + cpu->gdb_next_base_reg =3D 0; cpu->gdb_num_g_regs =3D 0; } =20 @@ -2522,4 +2522,3 @@ void gdb_create_default_process(GDBState *s) process->attached =3D false; process->target_xml =3D NULL; } - diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 456154df6f69..04e0088ed5b6 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -455,7 +455,8 @@ struct qemu_work_item; * @as: Pointer to the first AddressSpace, for the convenience of targets = which * only have a single AddressSpace * @gdb_regs: Additional GDB registers. - * @gdb_num_regs: Number of total registers accessible to GDB. + * @gdb_next_base_reg: Next register number after registered GDB features, + * including numbering gaps and internal registers. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. * @node: QTAILQ of CPUs sharing TB cache. * @opaque: User data. @@ -529,7 +530,7 @@ struct CPUState { struct CPUJumpCache *tb_jmp_cache; =20 GArray *gdb_regs; - int gdb_num_regs; + int gdb_next_base_reg; int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index d6e29c4cf467..e5cbe4d951ef 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -555,19 +555,21 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, gdb_find_static_feature("arm-m-profile-mv= e.xml")); } + GDBFeature *feature =3D + arm_gen_dynamic_sysreg_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_feature(cs, cs->gdb_nu= m_regs)); + feature); =20 #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)); + arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_next_base_reg)= ); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)); + arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_next_base_= reg)); } #endif } diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 0c3e5b30bd6a..cf5b95b54641 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -885,7 +885,8 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU = *cpu) CPUState *cs =3D CPU(cpu); if (isar_feature_aa64_sve(&cpu->isar) || isar_feature_aa64_sme(&cpu->isar)) { - GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs->gdb= _num_regs); + GDBFeature *feature =3D + arm_gen_dynamic_svereg_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature); } else { @@ -896,7 +897,7 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU = *cpu) =20 if (isar_feature_aa64_sme(&cpu->isar)) { GDBFeature *sme_feature =3D - arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs); + arm_gen_dynamic_smereg_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, aarch64_gdb_set_sme_reg, sme_feature); if (isar_feature_aa64_sme2(&cpu->isar)) { @@ -927,7 +928,8 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU = *cpu) #endif =20 /* All AArch64 CPUs have at least TPIDR */ + GDBFeature *tls_feature =3D + arm_gen_dynamic_tls_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg, - aarch64_gdb_set_tls_reg, - arm_gen_dynamic_tls_feature(cs, cs->gdb_num_r= egs)); + aarch64_gdb_set_tls_reg, tls_feature); } diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 4d622c5cad59..ec25c541c685 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -206,7 +206,7 @@ static void gdb_gen_spr_feature(CPUState *cs) =20 gdb_feature_builder_init(&builder, &pcc->gdb_spr, "org.qemu.power.spr", "power-spr.xml", - cs->gdb_num_regs); + cs->gdb_next_base_reg); =20 for (i =3D 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr =3D &env->spr_cb[i]; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9abbf5bcdf0e..f279f4ab2461 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -348,9 +348,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) gdb_find_static_feature("riscv-32bit-fpu.= xml")); } if (cpu->cfg.ext_zve32x) { + GDBFeature *feature =3D + ricsv_gen_dynamic_vector_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, riscv_gdb_get_vector, - riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs)); + riscv_gdb_set_vector, feature); } =20 #ifdef CONFIG_TCG @@ -373,8 +374,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) } =20 if (cpu->cfg.ext_zicsr) { + GDBFeature *feature =3D + riscv_gen_dynamic_csr_feature(cs, cs->gdb_next_base_reg); gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs)); + feature); } #endif } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7c25b9ab707a..48863a1859d4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -263,7 +263,7 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 - cs->gdb_num_regs =3D xcc->config->gdb_regmap.num_regs; + cs->gdb_next_base_reg =3D xcc->config->gdb_regmap.num_regs; =20 qemu_init_vcpu(cs); =20 --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.6 on 10.30.177.95 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666688063158500 gdb_feature_builder_end() never propagated builder->base_reg into feature->base_reg, leaving it at 0 for all dynamically-built features. This made the trace log at gdb_get_register_list() report an incorrect base_reg for dynamic features. GDBRegisterState::base_reg was correctly set, so this doesn't fix an actual issue. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Marc-Andr=C3=A9 Lureau --- gdbstub/gdbstub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 0ce871d74929..912e31b66744 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -476,6 +476,7 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *b= uilder) =20 g_ptr_array_free(builder->xml, TRUE); =20 + builder->feature->base_reg =3D builder->base_reg; builder->feature->num_regs =3D builder->regs->len; builder->feature->regs =3D (void *)g_ptr_array_free(builder->regs, FAL= SE); trace_gdbxml_feature_builder_header(builder->feature->name, --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792667015910158500 Add support for registering coprocessor features that are only visible to QEMU's internal APIs (HMP monitor $register expressions, plugins) but hidden from GDB's target description XML. When a feature is registered as internal: - It is excluded from the target.xml sent to GDB - Its XML is not served via qXfer:features:read - 'p'/'P' packets for internal register numbers return E14 This is useful for exposing system registers to the HMP monitor without affecting GDB's register namespace. Exposing aliases or synthetic registers through GDB's target description can cause problems: name collisions with GDB's pseudo-registers, independent register caching, and missing DWARF unwind rules. Internal features must be registered after all GDB-visible features to keep remote register numbering consistent. This ordering is enforced with an assertion. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Pierrick Bouvier --- gdbstub/gdbstub.c | 71 ++++++++++++++++++++++++++++++++++++++++++++--= ---- include/exec/gdbstub.h | 21 +++++++++++++++ 2 files changed, 84 insertions(+), 8 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 912e31b66744..1675f4d6cd4a 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -54,6 +54,7 @@ typedef struct GDBRegisterState { gdb_get_reg_cb get_reg; gdb_set_reg_cb set_reg; const GDBFeature *feature; + bool internal; /* hidden from GDB, accessible via API/monitor */ } GDBRegisterState; =20 GDBState gdbserver_state; @@ -385,6 +386,11 @@ static const char *get_feature_xml(const char *p, cons= t char **newp, } for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + /* The core target.xml feature must never be internal. */ + g_assert(i > 0 || !r->internal); + if (r->internal) { + continue; + } g_ptr_array_add( xml, g_markup_printf_escaped("", @@ -400,6 +406,9 @@ static const char *get_feature_xml(const char *p, const= char **newp, /* Is it one of the features? */ for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (r->internal) { + continue; + } if (strncmp(p, r->feature->xmlname, len) =3D=3D 0) { return r->feature->xml; } @@ -563,13 +572,14 @@ int gdb_write_register(CPUState *cpu, uint8_t *mem_bu= f, int reg) =20 static void gdb_register_feature(CPUState *cpu, int base_reg, gdb_get_reg_cb get_reg, gdb_set_reg_cb se= t_reg, - const GDBFeature *feature) + const GDBFeature *feature, bool internal) { GDBRegisterState s =3D { .base_reg =3D base_reg, .get_reg =3D get_reg, .set_reg =3D set_reg, - .feature =3D feature + .feature =3D feature, + .internal =3D internal }; =20 trace_gdbxml_register_feature(feature->name, feature->xmlname, @@ -605,7 +615,7 @@ void gdb_init_cpu(CPUState *cpu) assert(feature->base_reg =3D=3D 0); gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, - feature); + feature, false); cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D feature->num_re= gs; } else { cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D cc->gdb_num_cor= e_regs; @@ -616,20 +626,26 @@ void gdb_init_cpu(CPUState *cpu) cc->gdb_num_core_regs); } =20 -void gdb_register_coprocessor(CPUState *cpu, - gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, - const GDBFeature *feature) +static void do_gdb_register_coprocessor(CPUState *cpu, + gdb_get_reg_cb get_reg, + gdb_set_reg_cb set_reg, + const GDBFeature *feature, + bool internal) { GDBRegisterState *s; guint i; int base_reg =3D cpu->gdb_next_base_reg; =20 for (i =3D 0; i < cpu->gdb_regs->len; i++) { - /* Check for duplicates. */ s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + /* Check for duplicates. */ if (s->feature =3D=3D feature) { return; } + /* GDB-visible features must not follow internal ones. */ + if (!internal) { + g_assert(!s->internal); + } } =20 if (base_reg < feature->base_reg) { @@ -637,12 +653,27 @@ void gdb_register_coprocessor(CPUState *cpu, feature->base_reg); base_reg =3D feature->base_reg; } - gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); + gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature, interna= l); =20 /* Add to end of list. */ cpu->gdb_next_base_reg =3D base_reg + feature->num_regs; } =20 +void gdb_register_coprocessor(CPUState *cpu, + gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, + const GDBFeature *feature) +{ + do_gdb_register_coprocessor(cpu, get_reg, set_reg, feature, false); +} + +void gdb_register_internal_coprocessor(CPUState *cpu, + gdb_get_reg_cb get_reg, + gdb_set_reg_cb set_reg, + const GDBFeature *feature) +{ + do_gdb_register_coprocessor(cpu, get_reg, set_reg, feature, true); +} + void gdb_unregister_coprocessor_all(CPUState *cpu) { /* @@ -1223,6 +1254,18 @@ static void handle_remove_bp(GArray *params, void *u= ser_ctx) * the remote gdb to fallback to older methods. */ =20 +static bool gdb_register_is_internal(CPUState *cpu, int reg) +{ + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { + GDBRegisterState *r =3D &g_array_index(cpu->gdb_regs, GDBRegisterS= tate, i); + + if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->num_re= gs) { + return r->internal; + } + } + return false; +} + static void handle_set_reg(GArray *params, void *user_ctx) { int reg_size; @@ -1232,6 +1275,12 @@ static void handle_set_reg(GArray *params, void *use= r_ctx) return; } =20 + if (gdb_register_is_internal(gdbserver_state.g_cpu, + gdb_get_cmd_param(params, 0)->val_ull)) { + gdb_put_packet("E14"); + return; + } + reg_size =3D strlen(gdb_get_cmd_param(params, 1)->data) / 2; gdb_hextomem(gdbserver_state.mem_buf, gdb_get_cmd_param(params, 1)->da= ta, reg_size); gdb_write_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf->dat= a, @@ -1248,6 +1297,12 @@ static void handle_get_reg(GArray *params, void *use= r_ctx) return; } =20 + if (gdb_register_is_internal(gdbserver_state.g_cpu, + gdb_get_cmd_param(params, 0)->val_ull)) { + gdb_put_packet("E14"); + return; + } + reg_size =3D gdb_read_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf, gdb_get_cmd_param(params, 0)->val_ull); diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 75eb4d9c365e..1bc778324758 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -40,6 +40,27 @@ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, const GDBFeature *feature); =20 +/** + * gdb_register_internal_coprocessor() - register internal registers + * + * Like gdb_register_coprocessor(), but the feature is NOT exposed to + * GDB via the target description XML. The registers are only + * accessible through QEMU's internal APIs (HMP monitor ``$register`` + * expressions via gdb_get_register_list()). + * + * Internal features must be registered after all GDB-visible features + * to avoid register numbering mismatches with GDB. + * + * @cpu - the CPU associated with registers + * @get_reg - get function + * @set_reg - set function + * @feature - the GDBFeature describing the registers + */ +void gdb_register_internal_coprocessor(CPUState *cpu, + gdb_get_reg_cb get_reg, + gdb_set_reg_cb set_reg, + const GDBFeature *feature); + /** * gdb_unregister_coprocessor_all() - unregisters supplemental set of regi= sters * @cpu - the CPU associated with registers --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792667048248158500 Add an i386-system.xml GDB "internal" feature that exposes the six segment limit registers (cs, ds, es, ss, fs, gs) as read-only system registers through the GDB coprocessor interface. This makes them accessible to HMP without relying on the legacy MonitorDef table, which will be removed in a subsequent commit. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/i386-softmmu.mak | 2 +- configs/targets/x86_64-softmmu.mak | 2 +- gdbstub/gdb-xml/i386-system.xml | 14 ++++++++++++++ target/i386/cpu.c | 9 --------- target/i386/gdbstub.c | 25 +++++++++++++++++++++++++ 5 files changed, 41 insertions(+), 11 deletions(-) diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 38a8f85201f9..1424ab6f6834 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-32bit.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-system.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index c7f8746b4f58..51e882b1c747 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-apx.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-apx.xml i386-system.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/gdbstub/gdb-xml/i386-system.xml b/gdbstub/gdb-xml/i386-system.= xml new file mode 100644 index 000000000000..9868b887eab8 --- /dev/null +++ b/gdbstub/gdb-xml/i386-system.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5da80ade70eb..37732b65e408 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10893,17 +10893,8 @@ static int64_t monitor_get_pc(MonitorHMP *hmp, con= st struct MonitorDef *md, } =20 static const MonitorDef x86_monitor_defs[] =3D { -#define SEG(name, seg) \ - { name ".limit", offsetof(CPUX86State, segs[seg].limit) }, - SEG("cs", R_CS) - SEG("ds", R_DS) - SEG("es", R_ES) - SEG("ss", R_SS) - SEG("fs", R_FS) - SEG("gs", R_GS) { "pc", 0, monitor_get_pc, }, { NULL }, -#undef SEG }; #endif =20 diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index e636ca0f4ae7..c0cde26d978c 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -496,6 +496,25 @@ static int i386_cpu_gdb_set_egprs(CPUState *cs, uint8_= t *mem_buf, int n) } #endif =20 +#ifndef CONFIG_USER_ONLY +static int x86_gdb_read_system(CPUState *cs, GByteArray *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + static const int segments[] =3D { R_CS, R_DS, R_ES, R_SS, R_FS, R_GS }; + + if (n < 0 || n >=3D ARRAY_SIZE(segments)) { + return 0; + } + return gdb_get_reg32(buf, env->segs[segments[n]].limit); +} + +static int x86_gdb_write_system(CPUState *cs, uint8_t *buf, int n) +{ + /* Segment caches are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void x86_cpu_gdb_init(CPUState *cs) { #ifdef TARGET_X86_64 @@ -517,4 +536,10 @@ void x86_cpu_gdb_init(CPUState *cs) gdb_find_static_feature("i386-32bit-linux.xml= ")); #endif #endif +#ifndef CONFIG_USER_ONLY + gdb_register_internal_coprocessor( + cs, x86_gdb_read_system, + x86_gdb_write_system, + gdb_find_static_feature("i386-system.xml")); +#endif } --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792666993; cv=none; d=zohomail.com; s=zohoarc; b=MyeGOfZqP+NRxzzpAsz9CksWk+BEeV7WNkIfKxUPFQoUXumTLhsQCW3RYCgtrZJEvlS8Csoq2wltMDJebwDkg2jiRGVLXDPee0fqNcOwynXAIwwB2QrMxW7/4L2favXIzENuRttuzM0TUUiWqQ9/3xUBdmALaXF9cR2Ygfxvcwc= ARC-Message-Signature: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666995896158500 The GDB stub was returning a hardcoded 0 for the x87 FPU tag word register (ftag). Factor out cpu_compute_fptag() helper. Simplify a little bit the code by dropping unnecessary CPU_LDoubleU reinterpretation, building the value 0..7, avoiding signed-shifting. Signed-off-by: Marc-Andr=C3=A9 Lureau --- target/i386/cpu.c | 28 ++++++++++++++++++++++++++++ target/i386/cpu.h | 9 +++++++++ target/i386/gdbstub.c | 2 +- target/i386/tcg/fpu_helper.c | 24 ++---------------------- 4 files changed, 40 insertions(+), 23 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37732b65e408..2f5ea4e51715 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9372,6 +9372,34 @@ static bool cpuid_has_xsave_feature(CPUX86State *env= , const ExtSaveArea *esa) return false; } =20 +uint16_t cpu_compute_fptag(CPUX86State *env) +{ + uint16_t fptag =3D 0; + + for (int i =3D 0; i < 8; i++) { + unsigned tag; + + if (env->fptags[i]) { + tag =3D 3; /* empty */ + } else { + floatx80 f =3D env->fpregs[i].d; + uint16_t exponent =3D f.high & 0x7fff; + uint64_t mantissa =3D f.low; + + if (exponent =3D=3D 0 && mantissa =3D=3D 0) { + tag =3D 1; /* zero */ + } else if (exponent =3D=3D 0 || exponent =3D=3D 0x7fff || + !(mantissa & (1ULL << 63))) { + tag =3D 2; /* NaNs, infinity, denormal */ + } else { + tag =3D 0; /* valid */ + } + } + fptag |=3D tag << (2 * i); + } + return fptag; +} + static void x86_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e7a88074c071..116e28a59701 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2989,6 +2989,15 @@ static inline void cpu_set_mxcsr(CPUX86State *env, u= int32_t mxcsr) } } =20 +/** + * cpu_compute_fptag - Compute the full 16-bit x87 FPU tag word. + * + * Reconstructs the 16-bit tag word from the fpregs and fptags arrays. + * Each of the 8 physical registers gets a 2-bit tag in bits [2*i+1 : 2*i]: + * 0 =3D valid, 1 =3D zero, 2 =3D special (NaN/Inf/denormal), 3 =3D empt= y. + */ +uint16_t cpu_compute_fptag(CPUX86State *env); + static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) { env->fpuc =3D fpuc; diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index c0cde26d978c..420ce845eeae 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -186,7 +186,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11); case IDX_FP_REGS + 10: - return gdb_get_reg32(mem_buf, 0); /* ftag */ + return gdb_get_reg32(mem_buf, cpu_compute_fptag(env)); case IDX_FP_REGS + 11: return gdb_get_reg32(mem_buf, 0); /* fiseg */ case IDX_FP_REGS + 12: diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4bbac996326e..81ae3d8f3d0f 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2459,30 +2459,10 @@ void helper_fxam_ST0(CPUX86State *env) static void do_fstenv(X86Access *ac, target_ulong ptr, int data32) { CPUX86State *env =3D ac->env; - int fpus, fptag, exp, i; - uint64_t mant; - CPU_LDoubleU tmp; + int fpus, fptag; =20 fpus =3D (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; - fptag =3D 0; - for (i =3D 7; i >=3D 0; i--) { - fptag <<=3D 2; - if (env->fptags[i]) { - fptag |=3D 3; - } else { - tmp.d =3D env->fpregs[i].d; - exp =3D EXPD(tmp); - mant =3D MANTD(tmp); - if (exp =3D=3D 0 && mant =3D=3D 0) { - /* zero */ - fptag |=3D 1; - } else if (exp =3D=3D 0 || exp =3D=3D MAXEXPD - || (mant & (1LL << 63)) =3D=3D 0) { - /* NaNs, infinity, denormal */ - fptag |=3D 2; - } - } - } + fptag =3D cpu_compute_fptag(env); if (data32) { /* 32 bit */ access_stl(ac, ptr, env->fpuc); --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792666980; cv=none; d=zohomail.com; s=zohoarc; b=NF/Tuayw7RJMF2+0sCZVVj9A2XKqL8+g3hYroRDFSdoticIxfQGfdGRHG0XhUKaT/F3BwL0VuR3Ux0sdqH2lFHJscHIl+NbLDfDcMyLQkBmMVtMKdL4FW622gJbY9zZooUq7B0pfs4Dz45zqJwj67ppOrIRY+bn3BdQZJghSnh4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792666980; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666983437158500 Move XMM registers and mxcsr out of org.gnu.gdb.i386.core into a separate org.gnu.gdb.i386.sse feature, matching GDB's expected target description layout (gdb/features/i386/{32,64}bit-sse.xml). Previously, SSE registers were embedded in the core feature with a commented-out feature boundary. GDB requires org.gnu.gdb.i386.sse as a prerequisite for the AVX feature (org.gnu.gdb.i386.avx). Without this split, adding AVX support causes GDB to reject the target description entirely. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/i386-bsd-user.mak | 2 +- configs/targets/i386-linux-user.mak | 2 +- configs/targets/i386-softmmu.mak | 2 +- configs/targets/x86_64-bsd-user.mak | 2 +- configs/targets/x86_64-linux-user.mak | 2 +- configs/targets/x86_64-softmmu.mak | 2 +- gdbstub/gdb-xml/i386-32bit-sse.xml | 54 +++++++++++++++++++++++++ gdbstub/gdb-xml/i386-32bit.xml | 46 +-------------------- gdbstub/gdb-xml/i386-64bit-sse.xml | 62 ++++++++++++++++++++++++++++ gdbstub/gdb-xml/i386-64bit.xml | 50 ----------------------- target/i386/gdbstub.c | 76 ++++++++++++++++++++++---------= ---- 11 files changed, 172 insertions(+), 128 deletions(-) diff --git a/configs/targets/i386-bsd-user.mak b/configs/targets/i386-bsd-u= ser.mak index 485f571cb6cd..b2a8b0a42ad9 100644 --- a/configs/targets/i386-bsd-user.mak +++ b/configs/targets/i386-bsd-user.mak @@ -1,3 +1,3 @@ TARGET_ARCH=3Di386 -TARGET_XML_FILES=3D i386-32bit.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml TARGET_LONG_BITS=3D32 diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-lin= ux-user.mak index a3ea4c39c520..234e600860a3 100644 --- a/configs/targets/i386-linux-user.mak +++ b/configs/targets/i386-linux-user.mak @@ -1,5 +1,5 @@ TARGET_ARCH=3Di386 TARGET_SYSTBL_ABI=3Di386 TARGET_SYSTBL=3Dsyscall_32.tbl -TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-linux.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-32bit-linux.xml TARGET_LONG_BITS=3D32 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 1424ab6f6834..a53ee07255b4 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-32bit.xml i386-system.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-system.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/configs/targets/x86_64-bsd-user.mak b/configs/targets/x86_64-b= sd-user.mak index 26b7cfad4e23..f36a9ccbd60a 100644 --- a/configs/targets/x86_64-bsd-user.mak +++ b/configs/targets/x86_64-bsd-user.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-apx.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64= -linux-user.mak index cad68746bdb2..77a035b7eb4c 100644 --- a/configs/targets/x86_64-linux-user.mak +++ b/configs/targets/x86_64-linux-user.mak @@ -2,5 +2,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_SYSTBL_ABI=3Dcommon,64 TARGET_SYSTBL=3Dsyscall_64.tbl -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-linux.xml i386-64bit-apx.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-linux.xml= i386-64bit-apx.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 51e882b1c747..c04fdf2d3fe8 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-apx.xml i386-system.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml i= 386-system.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/gdbstub/gdb-xml/i386-32bit-sse.xml b/gdbstub/gdb-xml/i386-32bi= t-sse.xml new file mode 100644 index 000000000000..3f8a8d2bc8c1 --- /dev/null +++ b/gdbstub/gdb-xml/i386-32bit-sse.xml @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/i386-32bit.xml b/gdbstub/gdb-xml/i386-32bit.xml index 1dec40e1d2c1..dd6b6e7b8481 100644 --- a/gdbstub/gdb-xml/i386-32bit.xml +++ b/gdbstub/gdb-xml/i386-32bit.xml @@ -5,7 +5,7 @@ are permitted in any medium without royalty provided the copyright notice and this notice are preserved. --> =20 - + =20 @@ -152,48 +152,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/gdbstub/gdb-xml/i386-64bit-sse.xml b/gdbstub/gdb-xml/i386-64bi= t-sse.xml new file mode 100644 index 000000000000..06a5f857d92c --- /dev/null +++ b/gdbstub/gdb-xml/i386-64bit-sse.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/i386-64bit.xml b/gdbstub/gdb-xml/i386-64bit.xml index 9ac9164e6a99..a31c38aa8bd7 100644 --- a/gdbstub/gdb-xml/i386-64bit.xml +++ b/gdbstub/gdb-xml/i386-64bit.xml @@ -170,54 +170,4 @@ =20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 420ce845eeae..2b4c28aac162 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -57,9 +57,8 @@ static const int gpr_map32[8] =3D { 0, 1, 2, 3, 4, 5, 6, = 7 }; /* * fpu regs ----------> 8 or 16 */ -#define IDX_NB_MXCSR 1 /* - * total ----> 8+1+1+9+6+16+8+1=3D50 or 16+1+1+9+6+16+16+1=3D66 + * total ----> 8+1+1+9+6+16=3D41 or 16+1+1+9+6+16=3D49 */ =20 #define IDX_IP_REG CPU_NB_REGS @@ -67,8 +66,6 @@ static const int gpr_map32[8] =3D { 0, 1, 2, 3, 4, 5, 6, = 7 }; #define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS) #define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG) #define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL) -#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP) -#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) =20 #define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0) #define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1) @@ -139,13 +136,6 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray= *mem_buf, int n) int len =3D gdb_get_reg64(mem_buf, cpu_to_le64(fp->low)); len +=3D gdb_get_reg16(mem_buf, cpu_to_le16(fp->high)); return len; - } else if (n >=3D IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { - n -=3D IDX_XMM_REGS; - if (n < CPU_NB_REGS32 || TARGET_LONG_BITS =3D=3D 64) { - return gdb_get_reg128(mem_buf, - env->xmm_regs[n].ZMM_Q(1), - env->xmm_regs[n].ZMM_Q(0)); - } } else { switch (n) { case IDX_IP_REG: @@ -198,10 +188,6 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray= *mem_buf, int n) case IDX_FP_REGS + 15: return gdb_get_reg32(mem_buf, 0); /* fop */ =20 - case IDX_MXCSR_REG: - update_mxcsr_from_sse_status(env); - return gdb_get_reg32(mem_buf, env->mxcsr); - case IDX_CTL_CR0_REG: return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]); case IDX_CTL_CR2_REG: @@ -300,13 +286,6 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) fp->low =3D le64_to_cpu(* (uint64_t *) mem_buf); fp->high =3D le16_to_cpu(* (uint16_t *) (mem_buf + 8)); return 10; - } else if (n >=3D IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { - n -=3D IDX_XMM_REGS; - if (n < CPU_NB_REGS32 || TARGET_LONG_BITS =3D=3D 64) { - env->xmm_regs[n].ZMM_Q(0) =3D ldq_p(mem_buf); - env->xmm_regs[n].ZMM_Q(1) =3D ldq_p(mem_buf + 8); - return 16; - } } else { switch (n) { case IDX_IP_REG: @@ -358,10 +337,6 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) case IDX_FP_REGS + 15: /* fop */ return 4; =20 - case IDX_MXCSR_REG: - cpu_set_mxcsr(env, ldl_p(mem_buf)); - return 4; - case IDX_CTL_CR0_REG: len =3D gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); #ifndef CONFIG_USER_ONLY @@ -409,6 +384,44 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) return 0; } =20 +/* + * SSE feature (org.gnu.gdb.i386.sse) =E2=80=94 XMM registers + mxcsr. + * + * Register layout: xmm0..xmm(N-1), mxcsr. + * N =3D CPU_NB_REGS (8 for 32-bit, 16 for 64-bit). + */ +static int x86_gdb_read_sse(CPUState *cs, GByteArray *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + + if (n < CPU_NB_REGS) { + return gdb_get_reg128(buf, + env->xmm_regs[n].ZMM_Q(1), + env->xmm_regs[n].ZMM_Q(0)); + } + if (n =3D=3D CPU_NB_REGS) { + update_mxcsr_from_sse_status(env); + return gdb_get_reg32(buf, env->mxcsr); + } + return 0; +} + +static int x86_gdb_write_sse(CPUState *cs, uint8_t *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + + if (n < CPU_NB_REGS) { + env->xmm_regs[n].ZMM_Q(0) =3D ldq_p(buf); + env->xmm_regs[n].ZMM_Q(1) =3D ldq_p(buf + 8); + return 16; + } + if (n =3D=3D CPU_NB_REGS) { + cpu_set_mxcsr(env, ldl_p(buf)); + return 4; + } + return 0; +} + #ifdef CONFIG_LINUX_USER =20 #define IDX_ORIG_AX 0 @@ -519,11 +532,20 @@ void x86_cpu_gdb_init(CPUState *cs) { #ifdef TARGET_X86_64 CPUX86State *env =3D &X86_CPU(cs)->env; + const char *sse_xml =3D "i386-64bit-sse.xml"; +#else + const char *sse_xml =3D "i386-32bit-sse.xml"; +#endif =20 + gdb_register_coprocessor(cs, x86_gdb_read_sse, x86_gdb_write_sse, + gdb_find_static_feature(sse_xml)); + +#ifdef TARGET_X86_64 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) { gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs, i386_cpu_gdb_set_egprs, - gdb_find_static_feature("i386-64bit-apx.x= ml")); + gdb_find_static_feature( + "i386-64bit-apx.xml")); } #endif =20 --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792666872; cv=none; d=zohomail.com; s=zohoarc; b=N0+y8TnAHw2olMZMMhRM0ZjiBp7ktem1hzYQORXyvZg6tC6xkaaJRi2Q+9DCbc38rTbRd3SZSWSK+rkWcBAnn5gjxppDSEmhBfidzGKk7tefjvzjwKA/UC5eumjCntVOEZKUbujAvdCKzKWzdcoaWQy+avRJ6zXF2h44YnfoAEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792666872; 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GTgxeY8r+QyHkyvupq7KtbJEdiZep5fgjP15fZZxj5uo3ag1DFfpgjSbSV+NzmTemjfglZ 47whJGAURV4Y5gUI8KsK1AeJCZRiQds= X-MC-Unique: mCKMON0xPX2sfCVO0ma3Gg-1 X-Mimecast-MFC-AGG-ID: mCKMON0xPX2sfCVO0ma3Gg_1792666639 From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Date: Thu, 22 Oct 2026 14:56:36 +0400 Subject: [PATCH v3 09/18] target/i386: expose system registers to monitors via gdbstub MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261022-query-reg-v3-9-7ad902b9a7cf@redhat.com> References: <20261022-query-reg-v3-0-7ad902b9a7cf@redhat.com> In-Reply-To: <20261022-query-reg-v3-0-7ad902b9a7cf@redhat.com> To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Developer-Signature: v=1; a=openpgp-sha256; l=12853; i=marcandre.lureau@redhat.com; h=from:subject:message-id; bh=opSL/jxl640/Jj4R9cF7p5dXz4aeRzN7eFn39UEbQ8w=; b=owEBbQKS/ZANAwAKAdro4Ql1lpzlAcsmYgBq2evmlmV6HratXT4gr6GDlf6vEpYwvs+ychS2d FrykLueGKOJAjMEAAEKAB0WIQSHqb2TP4fGBtJ29i3a6OEJdZac5QUCatnr5gAKCRDa6OEJdZac 5Sw4EACq+h5GUlHqg+CJ8xUwmYRpKDf2K1amzD8pH90WeLMpsxZb+cJd+sZri5QVbCp4a01jYIN ZPm0EiEzf1SF6zFkyleX+qTkF6CE8y8XcivE8gv2s35nWndUC/0ltB7770Eg3mQ9Cb3fGmPFPyf jtciydLjfmQCE1Cvg4TLNxiWSuPoPMGZLwSMoz8cmHYjZggl0usOEPfdNf069XlAfQcfIb4H+ws PBRNMwsgTCoN6TCRxNOMqt1GRZb5L+0tsDeERKwOgVSq0Z9APZbOWLaWMTNecJNHiG0MOYz8Bfp wBis2doKtuklM/k5qnLmVOW0wJ5asCXkoK2HDsjT3RB8qDU+H7NjJYTpHG538ycdkLgZBb9qs1D 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DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666873460158500 Expand the org.qemu.gdb.i386.system feature to expose additional read-only registers to HMP/monitor: - segment cache bases and flags (cs/ds/es/ss/fs/gs) - GDT/IDT base and limit - LDT/TR selector, base, limit, and flags - debug registers (dr0-dr3, dr6, dr7) - CPU status fields: CPL, interrupt-inhibit, A20, SMM, HLT - xcr0 - abridged x87 tag word (ftw) This will allow to implement an HMP "info registers" (cpu dump) equivalent based on QMP register query some day. Signed-off-by: Marc-Andr=C3=A9 Lureau --- gdbstub/gdb-xml/i386-system.xml | 41 ++++++++++++- target/i386/cpu-dump.c | 5 +- target/i386/cpu.h | 16 +++++ target/i386/gdbstub.c | 132 ++++++++++++++++++++++++++++++++++++= +--- 4 files changed, 181 insertions(+), 13 deletions(-) diff --git a/gdbstub/gdb-xml/i386-system.xml b/gdbstub/gdb-xml/i386-system.= xml index 9868b887eab8..7e7a5fb2e21f 100644 --- a/gdbstub/gdb-xml/i386-system.xml +++ b/gdbstub/gdb-xml/i386-system.xml @@ -3,7 +3,7 @@ SPDX-License-Identifier: GPL-2.0-or-later --> - + @@ -11,4 +11,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index 9e290c0b9b42..d8d7ebaf0e03 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -511,10 +511,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) XSTATE_Hi16_ZMM_MASK | \ XSTATE_YMM_MASK | XSTATE_SSE_MASK, avx_mask =3D XSTATE_YMM_MASK | XSTATE_SSE_MASK; - fptag =3D 0; - for(i =3D 0; i < 8; i++) { - fptag |=3D ((!env->fptags[i]) << i); - } + fptag =3D x86_fptags_to_abridged(env); update_mxcsr_from_sse_status(env); qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", env->fpuc, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 116e28a59701..cc06f1fb7b68 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2998,6 +2998,22 @@ static inline void cpu_set_mxcsr(CPUX86State *env, u= int32_t mxcsr) */ uint16_t cpu_compute_fptag(CPUX86State *env); =20 +/** + * x86_fptags_to_abridged - Pack fptags[] into the 8-bit abridged tag word. + * + * Returns the FXSAVE/XSAVE-style tag byte: bit i is 1 when ST(i) is + * nonempty (fptags[i] =3D=3D 0) and 0 when empty (fptags[i] =3D=3D 1). + */ +static inline uint8_t x86_fptags_to_abridged(const CPUX86State *env) +{ + uint8_t ftw =3D 0; + + for (int i =3D 0; i < 8; i++) { + ftw |=3D (!env->fptags[i]) << i; + } + return ftw; +} + static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) { env->fpuc =3D fpuc; diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 2b4c28aac162..9a46c46ecff9 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -510,21 +510,135 @@ static int i386_cpu_gdb_set_egprs(CPUState *cs, uint= 8_t *mem_buf, int n) #endif =20 #ifndef CONFIG_USER_ONLY +enum { + /* Segment limits: cs, ds, es, ss, fs, gs (6 =C3=97 32-bit) */ + X86_GDB_SEG_LIMIT_FIRST, + X86_GDB_SEG_LIMIT_LAST =3D X86_GDB_SEG_LIMIT_FIRST + 5, + /* Segment bases: cs, ds, es, ss (4 =C3=97 64-bit; fs/gs in core regs)= */ + X86_GDB_SEG_BASE_FIRST, + X86_GDB_SEG_BASE_LAST =3D X86_GDB_SEG_BASE_FIRST + 3, + /* Segment flags: cs, ds, es, ss, fs, gs (6 =C3=97 32-bit) */ + X86_GDB_SEG_FLAGS_FIRST, + X86_GDB_SEG_FLAGS_LAST =3D X86_GDB_SEG_FLAGS_FIRST + 5, + /* Descriptor tables */ + X86_GDB_GDT_BASE, + X86_GDB_GDT_LIMIT, + X86_GDB_IDT_BASE, + X86_GDB_IDT_LIMIT, + X86_GDB_LDT_SELECTOR, + X86_GDB_LDT_BASE, + X86_GDB_LDT_LIMIT, + X86_GDB_LDT_FLAGS, + X86_GDB_TR_SELECTOR, + X86_GDB_TR_BASE, + X86_GDB_TR_LIMIT, + X86_GDB_TR_FLAGS, + /* Debug registers: dr0-dr3, dr6, dr7 (6 =C3=97 64-bit) */ + X86_GDB_DR0, + X86_GDB_DR1, + X86_GDB_DR2, + X86_GDB_DR3, + X86_GDB_DR6, + X86_GDB_DR7, + /* CPU status */ + X86_GDB_CPL, + X86_GDB_II, + X86_GDB_A20, + X86_GDB_SMM, + X86_GDB_HLT, + X86_GDB_XCR0, + X86_GDB_FTW, + X86_GDB_SYSTEM_COUNT, +}; + static int x86_gdb_read_system(CPUState *cs, GByteArray *buf, int n) { CPUX86State *env =3D cpu_env(cs); static const int segments[] =3D { R_CS, R_DS, R_ES, R_SS, R_FS, R_GS }; =20 - if (n < 0 || n >=3D ARRAY_SIZE(segments)) { + switch (n) { + case X86_GDB_SEG_LIMIT_FIRST ... X86_GDB_SEG_LIMIT_LAST: + return gdb_get_reg32(buf, + env->segs[segments[n - X86_GDB_SEG_LIMIT_FIRS= T]].limit); + case X86_GDB_SEG_BASE_FIRST ... X86_GDB_SEG_BASE_LAST: + return gdb_get_reg64(buf, + env->segs[segments[n - X86_GDB_SEG_BASE_FIRST= ]].base); + case X86_GDB_SEG_FLAGS_FIRST ... X86_GDB_SEG_FLAGS_LAST: + return gdb_get_reg32(buf, + env->segs[segments[n - X86_GDB_SEG_FLAGS_FIRS= T]].flags); + case X86_GDB_GDT_BASE: + return gdb_get_reg64(buf, env->gdt.base); + case X86_GDB_GDT_LIMIT: + return gdb_get_reg32(buf, env->gdt.limit); + case X86_GDB_IDT_BASE: + return gdb_get_reg64(buf, env->idt.base); + case X86_GDB_IDT_LIMIT: + return gdb_get_reg32(buf, env->idt.limit); + case X86_GDB_LDT_SELECTOR: + return gdb_get_reg32(buf, env->ldt.selector); + case X86_GDB_LDT_BASE: + return gdb_get_reg64(buf, env->ldt.base); + case X86_GDB_LDT_LIMIT: + return gdb_get_reg32(buf, env->ldt.limit); + case X86_GDB_LDT_FLAGS: + return gdb_get_reg32(buf, env->ldt.flags); + case X86_GDB_TR_SELECTOR: + return gdb_get_reg32(buf, env->tr.selector); + case X86_GDB_TR_BASE: + return gdb_get_reg64(buf, env->tr.base); + case X86_GDB_TR_LIMIT: + return gdb_get_reg32(buf, env->tr.limit); + case X86_GDB_TR_FLAGS: + return gdb_get_reg32(buf, env->tr.flags); + case X86_GDB_DR0 ... X86_GDB_DR3: + return gdb_get_reg64(buf, env->dr[n - X86_GDB_DR0]); + case X86_GDB_DR6: + return gdb_get_reg64(buf, env->dr[6]); + case X86_GDB_DR7: + return gdb_get_reg64(buf, env->dr[7]); + case X86_GDB_CPL: + return gdb_get_reg32(buf, env->hflags & HF_CPL_MASK); + case X86_GDB_II: + return gdb_get_reg32(buf, !!(env->hflags & HF_INHIBIT_IRQ_MASK)); + case X86_GDB_A20: + return gdb_get_reg32(buf, (env->a20_mask >> 20) & 1); + case X86_GDB_SMM: + return gdb_get_reg32(buf, !!(env->hflags & HF_SMM_MASK)); + case X86_GDB_HLT: + return gdb_get_reg32(buf, cs->halted); + case X86_GDB_XCR0: + return gdb_get_reg64(buf, env->xcr0); + case X86_GDB_FTW: + return gdb_get_reg8(buf, x86_fptags_to_abridged(env)); + default: return 0; } - return gdb_get_reg32(buf, env->segs[segments[n]].limit); } =20 static int x86_gdb_write_system(CPUState *cs, uint8_t *buf, int n) { - /* Segment caches are exposed for inspection only. Ignore writes. */ - return 4; + /* System registers are exposed for inspection only. Ignore writes. */ + static const uint8_t sizes[X86_GDB_SYSTEM_COUNT] =3D { + [X86_GDB_SEG_LIMIT_FIRST ... X86_GDB_SEG_LIMIT_LAST] =3D 4, + [X86_GDB_SEG_BASE_FIRST ... X86_GDB_SEG_BASE_LAST] =3D 8, + [X86_GDB_SEG_FLAGS_FIRST ... X86_GDB_SEG_FLAGS_LAST] =3D 4, + [X86_GDB_GDT_BASE] =3D 8, [X86_GDB_GDT_LIMIT] =3D 4, + [X86_GDB_IDT_BASE] =3D 8, [X86_GDB_IDT_LIMIT] =3D 4, + [X86_GDB_LDT_SELECTOR] =3D 4, [X86_GDB_LDT_BASE] =3D 8, + [X86_GDB_LDT_LIMIT] =3D 4, [X86_GDB_LDT_FLAGS] =3D 4, + [X86_GDB_TR_SELECTOR] =3D 4, [X86_GDB_TR_BASE] =3D 8, + [X86_GDB_TR_LIMIT] =3D 4, [X86_GDB_TR_FLAGS] =3D 4, + [X86_GDB_DR0 ... X86_GDB_DR7] =3D 8, + [X86_GDB_CPL] =3D 4, [X86_GDB_II] =3D 4, + [X86_GDB_A20] =3D 4, [X86_GDB_SMM] =3D 4, + [X86_GDB_HLT] =3D 4, [X86_GDB_XCR0] =3D 8, + [X86_GDB_FTW] =3D 1, + }; + + if (n < 0 || n >=3D X86_GDB_SYSTEM_COUNT) { + return 0; + } + return sizes[n]; } #endif =20 @@ -559,9 +673,11 @@ void x86_cpu_gdb_init(CPUState *cs) #endif #endif #ifndef CONFIG_USER_ONLY - gdb_register_internal_coprocessor( - cs, x86_gdb_read_system, - x86_gdb_write_system, - gdb_find_static_feature("i386-system.xml")); + { + const GDBFeature *sysregs =3D gdb_find_static_feature("i386-system= .xml"); + g_assert(sysregs->num_regs =3D=3D X86_GDB_SYSTEM_COUNT); + gdb_register_internal_coprocessor(cs, x86_gdb_read_system, + x86_gdb_write_system, sysregs); + } #endif } --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666940781158500 Register the standard GDB target description features for AVX and AVX-512, so that GDB clients can inspect and modify vector state: - org.gnu.gdb.i386.avx (requires CPUID_EXT_AVX): YMM upper halves (ymm0h..ymm7h for 32-bit, ymm0h..ymm15h for 64-bit). GDB synthesizes full ymm0..ymm15 pseudo-registers by concatenating xmm + ymmh. - org.gnu.gdb.i386.avx512 (requires CPUID_7_0_EBX_AVX512F): 32-bit: k0..k7 opmask + zmm0h..zmm7h upper halves. 64-bit: xmm16..xmm31, ymm16h..ymm31h, k0..k7 opmask, zmm0h..zmm31h upper halves. GDB synthesizes full zmm0..zmm31 pseudo-registers from the xmm + ymmh + zmmh components. The XML descriptions and register layouts match the GDB feature definitions from binutils-gdb (gdb/features/i386/). Features are conditionally registered based on the CPU model's CPUID. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/i386-bsd-user.mak | 2 +- configs/targets/i386-linux-user.mak | 2 +- configs/targets/i386-softmmu.mak | 2 +- configs/targets/x86_64-bsd-user.mak | 2 +- configs/targets/x86_64-linux-user.mak | 2 +- configs/targets/x86_64-softmmu.mak | 2 +- gdbstub/gdb-xml/i386-32bit-avx.xml | 20 +++++ gdbstub/gdb-xml/i386-32bit-avx512.xml | 31 +++++++ gdbstub/gdb-xml/i386-64bit-avx.xml | 28 +++++++ gdbstub/gdb-xml/i386-64bit-avx512.xml | 108 ++++++++++++++++++++++++ target/i386/gdbstub.c | 154 ++++++++++++++++++++++++++++++= +++- 11 files changed, 346 insertions(+), 7 deletions(-) diff --git a/configs/targets/i386-bsd-user.mak b/configs/targets/i386-bsd-u= ser.mak index b2a8b0a42ad9..18e618258cc6 100644 --- a/configs/targets/i386-bsd-user.mak +++ b/configs/targets/i386-bsd-user.mak @@ -1,3 +1,3 @@ TARGET_ARCH=3Di386 -TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-32bit-avx.xml i= 386-32bit-avx512.xml TARGET_LONG_BITS=3D32 diff --git a/configs/targets/i386-linux-user.mak b/configs/targets/i386-lin= ux-user.mak index 234e600860a3..6b9869a6d253 100644 --- a/configs/targets/i386-linux-user.mak +++ b/configs/targets/i386-linux-user.mak @@ -1,5 +1,5 @@ TARGET_ARCH=3Di386 TARGET_SYSTBL_ABI=3Di386 TARGET_SYSTBL=3Dsyscall_32.tbl -TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-32bit-linux.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-32bit-avx.xml i= 386-32bit-avx512.xml i386-32bit-linux.xml TARGET_LONG_BITS=3D32 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index a53ee07255b4..05cc0bf29716 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-system.xml +TARGET_XML_FILES=3D i386-32bit.xml i386-32bit-sse.xml i386-32bit-avx.xml i= 386-32bit-avx512.xml i386-system.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/configs/targets/x86_64-bsd-user.mak b/configs/targets/x86_64-b= sd-user.mak index f36a9ccbd60a..e157dd9935bd 100644 --- a/configs/targets/x86_64-bsd-user.mak +++ b/configs/targets/x86_64-bsd-user.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-avx.xml i= 386-64bit-avx512.xml i386-64bit-apx.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-linux-user.mak b/configs/targets/x86_64= -linux-user.mak index 77a035b7eb4c..cc65f1333c3e 100644 --- a/configs/targets/x86_64-linux-user.mak +++ b/configs/targets/x86_64-linux-user.mak @@ -2,5 +2,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_SYSTBL_ABI=3Dcommon,64 TARGET_SYSTBL=3Dsyscall_64.tbl -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-linux.xml= i386-64bit-apx.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-avx.xml i= 386-64bit-avx512.xml i386-64bit-linux.xml i386-64bit-apx.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index c04fdf2d3fe8..725db9e4cdb4 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -2,6 +2,6 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy -TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-apx.xml i= 386-system.xml +TARGET_XML_FILES=3D i386-64bit.xml i386-64bit-sse.xml i386-64bit-avx.xml i= 386-64bit-avx512.xml i386-64bit-apx.xml i386-system.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy diff --git a/gdbstub/gdb-xml/i386-32bit-avx.xml b/gdbstub/gdb-xml/i386-32bi= t-avx.xml new file mode 100644 index 000000000000..bc6bc28ff19c --- /dev/null +++ b/gdbstub/gdb-xml/i386-32bit-avx.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/i386-32bit-avx512.xml b/gdbstub/gdb-xml/i386-3= 2bit-avx512.xml new file mode 100644 index 000000000000..764f74f86d6c --- /dev/null +++ b/gdbstub/gdb-xml/i386-32bit-avx512.xml @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/i386-64bit-avx.xml b/gdbstub/gdb-xml/i386-64bi= t-avx.xml new file mode 100644 index 000000000000..d470ee08af30 --- /dev/null +++ b/gdbstub/gdb-xml/i386-64bit-avx.xml @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/i386-64bit-avx512.xml b/gdbstub/gdb-xml/i386-6= 4bit-avx512.xml new file mode 100644 index 000000000000..79156c561db8 --- /dev/null +++ b/gdbstub/gdb-xml/i386-64bit-avx512.xml @@ -0,0 +1,108 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 9a46c46ecff9..8b89f2260a4c 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -422,6 +422,141 @@ static int x86_gdb_write_sse(CPUState *cs, uint8_t *b= uf, int n) return 0; } =20 +/* + * AVX feature (org.gnu.gdb.i386.avx) =E2=80=94 YMM upper halves. + * + * Register layout: ymm0h..ymm(N-1)h, each 128-bit. + * N =3D CPU_NB_REGS (8 for 32-bit, 16 for 64-bit). + */ +static int x86_gdb_read_avx(CPUState *cs, GByteArray *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + + if (n < 0 || n >=3D CPU_NB_REGS) { + return 0; + } + return gdb_get_reg128(buf, + env->xmm_regs[n].ZMM_Q(3), + env->xmm_regs[n].ZMM_Q(2)); +} + +static int x86_gdb_write_avx(CPUState *cs, uint8_t *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + + if (n < 0 || n >=3D CPU_NB_REGS) { + return 0; + } + env->xmm_regs[n].ZMM_Q(2) =3D ldq_p(buf); + env->xmm_regs[n].ZMM_Q(3) =3D ldq_p(buf + 8); + return 16; +} + +/* + * AVX-512 feature (org.gnu.gdb.i386.avx512). + * + * 32-bit layout (CPU_NB_REGS =3D=3D 8): + * n =3D 0..7 k0..k7 (64-bit opmask) + * n =3D 8..15 zmm0h..zmm7h (256-bit ZMM upper halves) + * + * 64-bit layout (CPU_NB_REGS =3D=3D 16): + * n =3D 0..15 xmm16..xmm31 (128-bit) + * n =3D 16..31 ymm16h..ymm31h (128-bit) + * n =3D 32..39 k0..k7 (64-bit opmask) + * n =3D 40..71 zmm0h..zmm31h (256-bit ZMM upper halves) + */ +#ifdef TARGET_X86_64 +enum { + X86_GDB_AVX512_XMM16_FIRST =3D 0, + X86_GDB_AVX512_YMM16H_FIRST =3D 16, + X86_GDB_AVX512_OPMASK_FIRST =3D 32, + X86_GDB_AVX512_ZMM_FIRST =3D 40, + X86_GDB_AVX512_COUNT =3D 72, +}; +#else +enum { + X86_GDB_AVX512_OPMASK_FIRST =3D 0, + X86_GDB_AVX512_ZMM_FIRST =3D NB_OPMASK_REGS, + X86_GDB_AVX512_COUNT =3D NB_OPMASK_REGS + CPU_NB_REGS, +}; +#endif + +static int x86_gdb_read_avx512(CPUState *cs, GByteArray *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + int reg; + + if (n < 0 || n >=3D X86_GDB_AVX512_COUNT) { + return 0; + } + +#ifdef TARGET_X86_64 + if (n < X86_GDB_AVX512_YMM16H_FIRST) { + /* xmm16..xmm31: lower 128 bits */ + reg =3D 16 + n; + return gdb_get_reg128(buf, + env->xmm_regs[reg].ZMM_Q(1), + env->xmm_regs[reg].ZMM_Q(0)); + } + if (n < X86_GDB_AVX512_OPMASK_FIRST) { + /* ymm16h..ymm31h: upper 128 bits of YMM */ + reg =3D 16 + (n - X86_GDB_AVX512_YMM16H_FIRST); + return gdb_get_reg128(buf, + env->xmm_regs[reg].ZMM_Q(3), + env->xmm_regs[reg].ZMM_Q(2)); + } +#endif + if (n < X86_GDB_AVX512_ZMM_FIRST) { + /* k0..k7: opmask registers */ + return gdb_get_reg64(buf, + env->opmask_regs[n - X86_GDB_AVX512_OPMASK_FI= RST]); + } + /* zmm0h..zmm(N-1)h: upper 256 bits of ZMM */ + reg =3D n - X86_GDB_AVX512_ZMM_FIRST; + for (int i =3D 4; i < 8; i++) { + gdb_get_reg64(buf, env->xmm_regs[reg].ZMM_Q(i)); + } + return 32; +} + +static int x86_gdb_write_avx512(CPUState *cs, uint8_t *buf, int n) +{ + CPUX86State *env =3D cpu_env(cs); + int reg; + + if (n < 0 || n >=3D X86_GDB_AVX512_COUNT) { + return 0; + } + +#ifdef TARGET_X86_64 + if (n < X86_GDB_AVX512_YMM16H_FIRST) { + /* xmm16..xmm31 */ + reg =3D 16 + n; + env->xmm_regs[reg].ZMM_Q(0) =3D ldq_p(buf); + env->xmm_regs[reg].ZMM_Q(1) =3D ldq_p(buf + 8); + return 16; + } + if (n < X86_GDB_AVX512_OPMASK_FIRST) { + /* ymm16h..ymm31h */ + reg =3D 16 + (n - X86_GDB_AVX512_YMM16H_FIRST); + env->xmm_regs[reg].ZMM_Q(2) =3D ldq_p(buf); + env->xmm_regs[reg].ZMM_Q(3) =3D ldq_p(buf + 8); + return 16; + } +#endif + if (n < X86_GDB_AVX512_ZMM_FIRST) { + /* k0..k7 */ + env->opmask_regs[n - X86_GDB_AVX512_OPMASK_FIRST] =3D ldq_p(buf); + return 8; + } + /* zmm0h..zmm(N-1)h */ + reg =3D n - X86_GDB_AVX512_ZMM_FIRST; + for (int i =3D 0; i < 4; i++) { + env->xmm_regs[reg].ZMM_Q(4 + i) =3D ldq_p(buf + i * 8); + } + return 32; +} + #ifdef CONFIG_LINUX_USER =20 #define IDX_ORIG_AX 0 @@ -644,16 +779,33 @@ static int x86_gdb_write_system(CPUState *cs, uint8_t= *buf, int n) =20 void x86_cpu_gdb_init(CPUState *cs) { + CPUX86State *env =3D cpu_env(cs); #ifdef TARGET_X86_64 - CPUX86State *env =3D &X86_CPU(cs)->env; const char *sse_xml =3D "i386-64bit-sse.xml"; + const char *avx_xml =3D "i386-64bit-avx.xml"; + const char *avx512_xml =3D "i386-64bit-avx512.xml"; #else const char *sse_xml =3D "i386-32bit-sse.xml"; + const char *avx_xml =3D "i386-32bit-avx.xml"; + const char *avx512_xml =3D "i386-32bit-avx512.xml"; #endif =20 gdb_register_coprocessor(cs, x86_gdb_read_sse, x86_gdb_write_sse, gdb_find_static_feature(sse_xml)); =20 + if (env->features[FEAT_1_ECX] & CPUID_EXT_AVX) { + const GDBFeature *avx =3D gdb_find_static_feature(avx_xml); + g_assert(avx->num_regs =3D=3D CPU_NB_REGS); + gdb_register_coprocessor(cs, x86_gdb_read_avx, + x86_gdb_write_avx, avx); + } + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_AVX512F) { + const GDBFeature *avx512 =3D gdb_find_static_feature(avx512_xml); + g_assert(avx512->num_regs =3D=3D X86_GDB_AVX512_COUNT); + gdb_register_coprocessor(cs, x86_gdb_read_avx512, + x86_gdb_write_avx512, avx512); + } + #ifdef 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DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666810647158500 The to be deprecated MonitorDef provided a synthetic $pc alias on x86 (which begin as an $eip alias). Preserving it requires x86-specific semantics (CPUClass::get_pc() omits the historical truncation). Use $eip or $rip instead, adding $cs.base as required. It was never a documented feature, HMP is not a stable API, x86-only, and the replacement ($rip/$eip + $cs.base) is arguably more correct. Nobody asked for a deprecation window on ML either. Signed-off-by: Marc-Andr=C3=A9 Lureau --- docs/about/removed-features.rst | 8 ++++++++ target/i386/cpu.c | 23 ----------------------- tests/qtest/test-hmp.c | 1 - 3 files changed, 8 insertions(+), 24 deletions(-) diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 6a9944a0c794..444169b5b718 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -908,6 +908,14 @@ Use ``multifd-channels`` instead. =20 Use ``multifd-compression`` instead. =20 +``$pc`` register alias on x86 (removed in 11.2) +''''''''''''''''''''''''''''''''''''''''''''''' + +The ``$pc`` alias (the linear instruction pointer) is no longer +recognized in HMP expressions. Use ``$rip`` or ``$eip`` (depending +on the target) instead, adding ``$cs.base`` when the linear address +is needed. + Host Architectures ------------------ =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2f5ea4e51715..a28c3033ba6d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -42,7 +42,6 @@ #include "exec/watchpoint.h" #ifndef CONFIG_USER_ONLY #include "confidential-guest.h" -#include "monitor/hmp.h" #include "system/reset.h" #include "qapi/qapi-commands-machine.h" #include "system/qmp-cpu.h" @@ -10907,25 +10906,6 @@ static const Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY =20 -#ifdef CONFIG_HMP -static int64_t monitor_get_pc(MonitorHMP *hmp, const struct MonitorDef *md, - int offset) -{ - CPUArchState *env =3D monitor_hmp_get_cpu_env(hmp); - int64_t ret =3D env->eip + env->segs[R_CS].base; - - if (!(env->hflags & HF_CS64_MASK)) { - ret =3D (int32_t)ret; - } - return ret; -} - -static const MonitorDef x86_monitor_defs[] =3D { - { "pc", 0, monitor_get_pc, }, - { NULL }, -}; -#endif - #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps i386_sysemu_ops =3D { @@ -10939,9 +10919,6 @@ static const struct SysemuCPUOps i386_sysemu_ops = =3D { .write_elf64_note =3D x86_cpu_write_elf64_note, .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, -#ifdef CONFIG_HMP - .monitor_defs =3D x86_monitor_defs, -#endif .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c index a523dbb446ce..b3f8fd58612d 100644 --- a/tests/qtest/test-hmp.c +++ b/tests/qtest/test-hmp.c @@ -58,7 +58,6 @@ static const char *hmp_cmds[] =3D { "object_del mem1", "one-insn-per-tb on", "pmemsave 0 4096 \"/dev/null\"", - "p $pc + 8", "qom-list /", "qom-set /machine initrd test", "qom-get /machine initrd", --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666885711158500 Replace the HMP-specific MonitorDef with a GDB feature that exposes supervisor stack pointers (ssp, usp, isp), function code registers (sfc, dfc), MMU registers (urp, srp, dttr0/1, ittr0/1, mmusr) as read-only system registers through the internal GDB coprocessor interface. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/m68k-softmmu.mak | 2 +- gdbstub/gdb-xml/m68k-system.xml | 32 ++++++++++++++++++++++++++ target/m68k/cpu.c | 22 ------------------ target/m68k/helper.c | 49 ++++++++++++++++++++++++++++++++++++= +++- 4 files changed, 81 insertions(+), 24 deletions(-) diff --git a/configs/targets/m68k-softmmu.mak b/configs/targets/m68k-softmm= u.mak index 0bc889f326e3..f3ac9b74c862 100644 --- a/configs/targets/m68k-softmmu.mak +++ b/configs/targets/m68k-softmmu.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Dm68k TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3D cf-core.xml cf-fp.xml m68k-core.xml m68k-fp.xml +TARGET_XML_FILES=3D cf-core.xml cf-fp.xml m68k-core.xml m68k-fp.xml m68k-s= ystem.xml TARGET_LONG_BITS=3D32 diff --git a/gdbstub/gdb-xml/m68k-system.xml b/gdbstub/gdb-xml/m68k-system.= xml new file mode 100644 index 000000000000..0a91be0edc00 --- /dev/null +++ b/gdbstub/gdb-xml/m68k-system.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 9b52ad5fc234..ad7303305848 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -25,7 +25,6 @@ #include "disas/capstone.h" #ifndef CONFIG_USER_ONLY #include "migration/vmstate.h" -#include "monitor/hmp.h" #endif =20 #include "cpu.h" @@ -666,32 +665,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }, }; =20 -#ifdef CONFIG_HMP -static const MonitorDef m68k_monitor_defs[] =3D { - { "ssp", offsetof(CPUM68KState, sp[0]) }, - { "usp", offsetof(CPUM68KState, sp[1]) }, - { "isp", offsetof(CPUM68KState, sp[2]) }, - { "sfc", offsetof(CPUM68KState, sfc) }, - { "dfc", offsetof(CPUM68KState, dfc) }, - { "urp", offsetof(CPUM68KState, mmu.urp) }, - { "srp", offsetof(CPUM68KState, mmu.srp) }, - { "dttr0", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR0]) }, - { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, - { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, - { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, - { "mmusr", offsetof(CPUM68KState, mmu.mmusr) }, - { NULL }, -}; -#endif - #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps m68k_sysemu_ops =3D { .has_work =3D m68k_cpu_has_work, .get_phys_addr_debug =3D m68k_cpu_get_phys_addr_debug, -#ifdef CONFIG_HMP - .monitor_defs =3D m68k_monitor_defs, -#endif }; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 5f91d206f596..1a29eaaf37f6 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -123,6 +123,48 @@ static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t = *mem_buf, int n) return 0; } =20 +#ifndef CONFIG_USER_ONLY +static int m68k_gdb_read_system_register(CPUState *cs, GByteArray *buf, in= t n) +{ + CPUM68KState *env =3D cpu_env(cs); + static const int stacks[] =3D { M68K_SSP, M68K_USP, M68K_ISP }; + + if (n >=3D 0 && n < ARRAY_SIZE(stacks)) { + int sp =3D stacks[n]; + + return gdb_get_reg32(buf, env->sp[sp]); + } + switch (n) { + case 3: + return gdb_get_reg32(buf, env->sfc); + case 4: + return gdb_get_reg32(buf, env->dfc); + case 5: + return gdb_get_reg32(buf, env->mmu.urp); + case 6: + return gdb_get_reg32(buf, env->mmu.srp); + case 7: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_DTTR0]); + case 8: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_DTTR1]); + case 9: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_ITTR0]); + case 10: + return gdb_get_reg32(buf, env->mmu.ttr[M68K_ITTR1]); + case 11: + return gdb_get_reg32(buf, env->mmu.mmusr); + default: + return 0; + } +} + +static int m68k_gdb_write_system_register(CPUState *cs, uint8_t *buf, int = n) +{ + /* These registers are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void m68k_cpu_init_gdb(M68kCPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -135,7 +177,12 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_se= t_reg, gdb_find_static_feature("m68k-fp.xml")); } - /* TODO: Add [E]MAC registers. */ + /* TODO: Add [E]MAC registers. */ +#ifndef CONFIG_USER_ONLY + gdb_register_internal_coprocessor(cs, m68k_gdb_read_system_register, + m68k_gdb_write_system_register, + gdb_find_static_feature("m68k-system= .xml")); +#endif } =20 void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.6 on 10.30.177.95 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666734881158500 Replace the HMP-specific MonitorDef with a GDB feature that exposes asi, pstate, cansave, canrestore, otherwin, wstate, and cleanwin as read-only system registers through the internal GDB coprocessor interface. Signed-off-by: Marc-Andr=C3=A9 Lureau --- configs/targets/sparc64-softmmu.mak | 2 +- gdbstub/gdb-xml/sparc64-system.xml | 22 +++++++++++++++++++++ target/sparc/cpu.c | 19 ------------------- target/sparc/gdbstub.c | 38 +++++++++++++++++++++++++++++++++= ++++ 4 files changed, 61 insertions(+), 20 deletions(-) diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index 4e621fb8e39e..7f2789136653 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3Dsparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml +TARGET_XML_FILES=3Dsparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml sparc64= -system.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/gdbstub/gdb-xml/sparc64-system.xml b/gdbstub/gdb-xml/sparc64-s= ystem.xml new file mode 100644 index 000000000000..e00baedb467e --- /dev/null +++ b/gdbstub/gdb-xml/sparc64-system.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ae9bdca9df82..89dfb091ca87 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -995,31 +995,12 @@ static const Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY =20 -#ifdef TARGET_SPARC64 -#include "monitor/hmp.h" -#ifdef CONFIG_HMP -static const MonitorDef sparc64_monitor_defs[] =3D { - { "asi", offsetof(CPUSPARCState, asi) }, - { "pstate", offsetof(CPUSPARCState, pstate) }, - { "cansave", offsetof(CPUSPARCState, cansave) }, - { "canrestore", offsetof(CPUSPARCState, canrestore) }, - { "otherwin", offsetof(CPUSPARCState, otherwin) }, - { "wstate", offsetof(CPUSPARCState, wstate) }, - { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, - { NULL }, -}; -#endif -#endif - #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps sparc_sysemu_ops =3D { .has_work =3D sparc_cpu_has_work, .get_phys_addr_debug =3D sparc_cpu_get_phys_addr_debug, .legacy_vmsd =3D &vmstate_sparc_cpu, -#if defined(TARGET_SPARC64) && defined(CONFIG_HMP) - .monitor_defs =3D sparc64_monitor_defs, -#endif }; #endif =20 diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 2874ce1b3501..c8aa74a4a8b7 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -266,6 +266,39 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, = uint8_t *mem_buf, int n) #endif } =20 +#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) +static int sparc64_gdb_read_system_register(CPUState *cs, GByteArray *buf, + int n) +{ + CPUSPARCState *env =3D cpu_env(cs); + + switch (n) { + case 0: + return gdb_get_reg32(buf, env->asi); + case 1: + return gdb_get_reg32(buf, env->pstate); + case 2: + return gdb_get_reg32(buf, env->cansave); + case 3: + return gdb_get_reg32(buf, env->canrestore); + case 4: + return gdb_get_reg32(buf, env->otherwin); + case 5: + return gdb_get_reg32(buf, env->wstate); + case 6: + return gdb_get_reg32(buf, env->cleanwin); + default: + return 0; + } +} + +static int sparc64_gdb_write_system_register(CPUState *cs, uint8_t *buf, i= nt n) +{ + /* These registers are exposed for inspection only. Ignore writes. */ + return 4; +} +#endif + void sparc_cpu_register_gdb_regs(CPUState *cs) { #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) @@ -282,5 +315,10 @@ void sparc_cpu_register_gdb_regs(CPUState *cs) gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register, sparc_cp0_gdb_write_register, gdb_find_static_feature("sparc64-cp0.xml")); +#ifndef CONFIG_USER_ONLY + gdb_register_internal_coprocessor(cs, sparc64_gdb_read_system_register, + sparc64_gdb_write_system_register, + gdb_find_static_feature("sparc64-sys= tem.xml")); +#endif #endif } --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792667017; cv=none; d=zohomail.com; s=zohoarc; b=YZw5xCecFtJ3pK5dMTuqzSigKYfYX6WbUhk9CsbScrusEdFDENtjrFEcmgZGS98al2m5crZs9WynebT7mwL5nNrT6/VNGqN4Hy5SoegwMxI+CVLgVIm7JKlgPjizS9yCTqlkYJlr7sEuPdeaFo5+LJLjGzknIEbmVZ0PGi1hfWo= ARC-Message-Signature: i=1; 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Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Marc-Andr=C3=A9 Lureau --- target/riscv/tcg/csr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 063590f56a79..aff5b54d37b1 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -53,7 +53,8 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int i= ndex, uint64_t bit) { bool virt =3D env->virt_enabled; =20 - if (env->priv =3D=3D PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { + if (env->debugger || env->priv =3D=3D PRV_M || + !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; } =20 --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index de3cb9dcaf25..010539dd3588 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -372,6 +372,7 @@ F: configs/targets/riscv* F: docs/system/target-riscv.rst F: docs/specs/riscv-iommu.rst F: target/riscv/ +F: gdbstub/gdb-xml/riscv*.xml F: hw/char/riscv_htif.c F: hw/riscv/ F: hw/intc/riscv* --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792666714; cv=none; d=zohomail.com; s=zohoarc; b=aV5ewK2hE5wWlXyde9MHie5MHyHYr+r6G8s1NHORE4pg07dlP7pTQDN7IQgQzBWCD8k3V9srik9/2hfvQDPJVenQo7jHEQpVaAKcUSRRIyZA5BVhlAu6bN3YbeJ/eRBBxoRfKYDD3F8fmCrXycvLfSKj3JnZb9LhT/248N4+zss= ARC-Message-Signature: i=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666714531158500 The core GDB XML uses ABI names (zero, ra, sp, fp, ft0, fs0, etc.) but users also refer to registers by their numeric names (x0-x31, f0-f31) and the s0 alias for fp. The legacy MonitorDef mechanism supported both via split "x0/zero" name matching. Register a feature that maps: - x0-x31 and s0 to the corresponding core integer registers - x0h-x31h and their ABI aliases (zeroh, rah, ...) to env->gprh[] - f0-f31 to the corresponding FPU registers (when FPU is present) CSR-by-name lookups ($mstatus, $sstatus, ...) keep working, through the existing GDB CSR feature rather than the removed csr_ops loop. Lookup is now case-sensitive (consistent with all other targets), including for the CSR names. Vector registers report "unknown register" instead of the target-specific "Unable to print the value of vector vreg" message. RV32 numeric and high-half aliases now zero-extend into HMP=E2=80=99s 64-bit expression value (for example, $x1 containing 0xffffffff evaluates to 4294967295, whereas the legacy fallback returned -1). This makes aliases consistent with the existing GDB-backed names. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Daniel Henrique Barboza --- configs/targets/riscv32-linux-user.mak | 2 +- configs/targets/riscv32-softmmu.mak | 2 +- configs/targets/riscv64-bsd-user.mak | 2 +- configs/targets/riscv64-linux-user.mak | 2 +- configs/targets/riscv64-softmmu.mak | 2 +- gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 ++++++++++++++++++++++ gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 +++++++++ gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 ++++++++++++++++++++++ gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++++++++ target/riscv/cpu.c | 1 - target/riscv/gdbstub.c | 48 ++++++++++ target/riscv/internals.h | 3 - target/riscv/monitor.c | 140 --------------------------= ---- 13 files changed, 349 insertions(+), 149 deletions(-) diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv= 32-linux-user.mak index d88fdf5e1b2f..8ee14fa14383 100644 --- a/configs/targets/riscv32-linux-user.mak +++ b/configs/targets/riscv32-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv -TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml +TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy TARGET_SYSTBL_ABI=3D32 diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-= softmmu.mak index 5d5016d00832..c717940344f0 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv -TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml +TARGET_XML_FILES=3D riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64= -bsd-user.mak index 5b4e138099fc..1d37e018c871 100644 --- a/configs/targets/riscv64-bsd-user.mak +++ b/configs/targets/riscv64-bsd-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv -TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml +TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv= 64-linux-user.mak index 35621520c560..564d15aaca8c 100644 --- a/configs/targets/riscv64-linux-user.mak +++ b/configs/targets/riscv64-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv -TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml +TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.x= ml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy TARGET_SYSTBL_ABI=3D64 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index a10dc03c04c8..28bfcdc575fb 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES=3D riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fp= u.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml r= iscv-32bit-alias.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-= 64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_LONG_BITS=3D64 diff --git a/gdbstub/gdb-xml/riscv-32bit-alias.xml b/gdbstub/gdb-xml/riscv-= 32bit-alias.xml new file mode 100644 index 000000000000..a00a86ebdf95 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-alias.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml b/gdbstub/gdb-xml/ri= scv-32bit-fpu-alias.xml new file mode 100644 index 000000000000..3935f72ea289 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-64bit-alias.xml b/gdbstub/gdb-xml/riscv-= 64bit-alias.xml new file mode 100644 index 000000000000..28781b230226 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-alias.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml b/gdbstub/gdb-xml/ri= scv-64bit-fpu-alias.xml new file mode 100644 index 000000000000..13e6b341a0f8 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08a4d14ea1f6..7b052da6d8b4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3107,7 +3107,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { .legacy_vmsd =3D &vmstate_riscv_cpu, #ifdef CONFIG_TCG .translate_for_debug =3D riscv_cpu_translate_for_debug, - .monitor_get_register =3D riscv_monitor_get_register_legacy, #endif }; #endif diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f279f4ab2461..0d89caf8ba36 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -336,10 +336,42 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(C= PUState *cs, int base_reg) return &cpu->dyn_vreg_feature; } =20 +/* x0-x31, s0, then pairs of numeric and ABI high-half aliases. */ +static int riscv_gdb_get_alias(CPUState *cs, GByteArray *buf, int n) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint64_t val; + + if (n < 33) { + return riscv_cpu_gdb_read_register(cs, buf, n =3D=3D 32 ? 8 : n); + } + + val =3D cpu->env.gprh[(n - 33) / 2]; + if (riscv_cpu_is_32bit(cpu)) { + return gdb_get_reg32(buf, val); + } + return gdb_get_reg64(buf, val); +} + +static int riscv_gdb_set_alias(CPUState *cs, uint8_t *buf, int n) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + const unsigned regsz =3D riscv_cpu_is_32bit(cpu) ? 4 : 8; + + if (n < 33) { + return riscv_cpu_gdb_write_register(cs, buf, n =3D=3D 32 ? 8 : n); + } + + env->gprh[(n - 33) / 2] =3D ldn(env, buf, regsz); + return regsz; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_find_static_feature("riscv-64bit-fpu.= xml")); @@ -380,4 +412,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) feature); } #endif + + gdb_register_internal_coprocessor( + cs, riscv_gdb_get_alias, riscv_gdb_set_alias, + gdb_find_static_feature(riscv_cpu_is_32bit(cpu) ? + "riscv-32bit-alias.xml" : + "riscv-64bit-alias.xml")); + + if (env->misa_ext & RVD) { + gdb_register_internal_coprocessor( + cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-64bit-fpu-alias.xml")); + } else if (env->misa_ext & RVF) { + gdb_register_internal_coprocessor( + cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-32bit-fpu-alias.xml")); + } } diff --git a/target/riscv/internals.h b/target/riscv/internals.h index f17d011d22fb..f4af4636c6ca 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -265,7 +265,4 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) =3D=3D 3 ? 4 : 2; } =20 -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, - int64_t *pval); - #endif diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 7e61ae2a4717..20f3ba57ae57 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -19,10 +19,7 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/ctype.h" -#include "qemu/qemu-print.h" #include "cpu.h" -#include "target/riscv/tcg/csr.h" #include "cpu_bits.h" #include "monitor/monitor.h" #include "monitor/hmp.h" @@ -247,140 +244,3 @@ void hmp_info_mem(MonitorHMP *hmp, const QDict *qdict) mem_info_svxx(hmp, env); } #endif /* CONFIG_HMP */ - -#ifdef CONFIG_TCG -static bool reg_is_ulong_integer(CPURISCVState *env, const char *name, - target_ulong *val, bool is_gprh) -{ - const char * const *reg_names; - uint64_t *vals; - - if (is_gprh) { - reg_names =3D riscv_int_regnamesh; - vals =3D env->gprh; - } else { - reg_names =3D riscv_int_regnames; - vals =3D env->gpr; - } - - for (int i =3D 0; i < 32; i++) { - g_auto(GStrv) reg_name =3D g_strsplit(reg_names[i], "/", 2); - - g_assert(reg_name[0]); - g_assert(reg_name[1]); - - if (g_ascii_strcasecmp(reg_name[0], name) =3D=3D 0 || - g_ascii_strcasecmp(reg_name[1], name) =3D=3D 0) { - *val =3D vals[i]; - return true; - } - } - - return false; -} - -static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t = *val) -{ - if (qemu_tolower(name[0]) !=3D 'f') { - return false; - } - - for (int i =3D 0; i < 32; i++) { - g_auto(GStrv) reg_name =3D g_strsplit(riscv_fpr_regnames[i], "/", = 2); - - g_assert(reg_name[0]); - g_assert(reg_name[1]); - - if (g_ascii_strcasecmp(reg_name[0], name) =3D=3D 0 || - g_ascii_strcasecmp(reg_name[1], name) =3D=3D 0) { - *val =3D env->fpr[i]; - return true; - } - } - - return false; -} - -static bool reg_is_vreg(const char *name) -{ - if (qemu_tolower(name[0]) !=3D 'v' || strlen(name) > 3) { - return false; - } - - for (int i =3D 0; i < 32; i++) { - if (g_ascii_strcasecmp(name, riscv_rvv_regnames[i]) =3D=3D 0) { - return true; - } - } - - return false; -} - -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, - int64_t *pval) -{ - RISCVCPU *hart =3D RISCV_CPU(cs); - CPURISCVState *env =3D cpu_env(cs); - target_ulong val =3D 0; - uint64_t val64 =3D 0; - int i; - - if (reg_is_ulong_integer(env, name, &val, false) || - reg_is_ulong_integer(env, name, &val, true)) { - *pval =3D riscv_cpu_is_32bit(hart) ? (int32_t)val : val; - return 0; - } - - if (reg_is_u64_fpu(env, name, &val64)) { - *pval =3D val64; - return 0; - } - - if (reg_is_vreg(name)) { - if (!riscv_cpu_cfg(env)->ext_zve32x) { - return -EINVAL; - } - - qemu_printf("Unable to print the value of vector " - "vreg '%s' from this API\n", name); - - /* - * We're returning 0 because returning -EINVAL triggers - * an 'unknown register' message in exp_unary() later, - * which feels ankward after our own error message. - */ - *pval =3D 0; - return 0; - } - - for (i =3D 0; i < ARRAY_SIZE(csr_ops); i++) { - RISCVException res; - int csrno =3D i; - - /* - * Early skip when possible since we're going - * through a lot of NULL entries. - */ - if (csr_ops[csrno].predicate =3D=3D NULL) { - continue; - } - - if (g_ascii_strcasecmp(csr_ops[csrno].name, name) !=3D 0) { - continue; - } - - res =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); - - /* - * Rely on the smode, hmode, etc, predicates within csr.c - * to do the filtering of the registers that are present. - */ - if (res =3D=3D RISCV_EXCP_NONE) { - *pval =3D riscv_cpu_is_32bit(hart) ? (int32_t)val : val; - return 0; - } - } - - return -EINVAL; -} -#endif --=20 2.56.0.116.g6de20f6092dc From nobody Fri Oct 23 20:51:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1792666831; cv=none; d=zohomail.com; s=zohoarc; b=ZF4eKniKAX5LsSQD661Cyoc0nR6E1EA1+dMyhcZbThI1FzVOuclPg64ozUHqwkTPNCotu3b2KrPPG0pq5bARuO9YKwUJYwZK5GWR1DGFQzgYgqi6EIwFeXObvGyAro1j+UeELEidR+swjjORY+6AygIaE14LMB/JrCQpmE3fIhU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792666831; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 22 Oct 2026 10:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1792666678; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1gah91+wf8CPlKNBkPoB+vdQS+y3ma/UGPxFNHcQ3XE=; b=Fs3ENMU3DwZCgfeeCmz1++aMGjm/ymXwX3YDNY4lWj8d82MkdPzMgFLpy6bTlTXYM0TWGi x5mgRHRfTzmtmT6D5gXUqDoV4IvnYkwiwGUhxk2+sHMgSEUxUVB43XFBIygHIvffNwCDwG M8bAlr+SmiLRH2qj9oJzQpe6POYKXB0= X-MC-Unique: T_Ja87l5NyKhVqslGNi62A-1 X-Mimecast-MFC-AGG-ID: T_Ja87l5NyKhVqslGNi62A_1792666671 From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Date: Thu, 22 Oct 2026 14:56:45 +0400 Subject: [PATCH v3 18/18] monitor/hmp: remove legacy MonitorDef infrastructure MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261022-query-reg-v3-18-7ad902b9a7cf@redhat.com> References: <20261022-query-reg-v3-0-7ad902b9a7cf@redhat.com> In-Reply-To: <20261022-query-reg-v3-0-7ad902b9a7cf@redhat.com> To: qemu-devel@nongnu.org Cc: "Dr. David Alan Gilbert" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Developer-Signature: v=1; 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a=openpgp; fpr=87A9BD933F87C606D276F62DDAE8E10975969CE5 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1792666834721158501 Now that all targets expose their system registers via internal GDB register descriptions (i386 segment limits, m68k, sparc64, RISC-V aliases), the legacy MonitorDef table and SysemuCPUOps::monitor_get_register callback are no longer needed. HMP $register expressions now use gdb_get_register_list() exclusively. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Pierrick Bouvier --- include/hw/core/sysemu-cpu-ops.h | 16 --------------- include/monitor/hmp.h | 6 ------ include/qemu/typedefs.h | 1 - monitor/hmp.c | 43 +-----------------------------------= ---- 4 files changed, 1 insertion(+), 65 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index d125540262d2..daac2a3b13b1 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -103,22 +103,6 @@ typedef struct SysemuCPUOps { */ bool (*internal_is_big_endian)(CPUState *cpu); =20 - /** - * @monitor_get_register: Callback to fill @pval with register @name v= alue. - * This field is legacy, use @gdb_core_xml_file - * to dump registers instead. - * Returns: 0 on success or negative errno on failure. - */ - int (*monitor_get_register)(CPUState *cs, const char *name, int64_t *p= val); - -#ifdef CONFIG_HMP - /** - * @monitor_defs: Array of MonitorDef entries. This field is legacy, - * use @gdb_core_xml_file to dump registers instead. - */ - const MonitorDef *monitor_defs; -#endif - /** * @legacy_vmsd: Legacy state for migration. * Do not use in new targets, use #DeviceClass::vmsd ins= tead. diff --git a/include/monitor/hmp.h b/include/monitor/hmp.h index ef53e87f7608..950dd931d452 100644 --- a/include/monitor/hmp.h +++ b/include/monitor/hmp.h @@ -31,12 +31,6 @@ MonitorHMP *monitor_cur_hmp(void); g_assert_not_reached(); \ } =20 -struct MonitorDef { - const char *name; - int offset; - int64_t (*get_value)(MonitorHMP *hmp, const MonitorDef *md, int offset= ); -}; - void monitor_new_hmp(const char *id, const char *chardev_id, bool use_readline, Error **errp); =20 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 2344c92182ea..5580e1fc4aba 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -72,7 +72,6 @@ typedef struct MemoryRegionSection MemoryRegionSection; typedef struct MigrationIncomingState MigrationIncomingState; typedef struct MigrationState MigrationState; typedef struct Monitor Monitor; -typedef struct MonitorDef MonitorDef; typedef struct MSIMessage MSIMessage; typedef struct NetClientState NetClientState; typedef struct NetFilterState NetFilterState; diff --git a/monitor/hmp.c b/monitor/hmp.c index e97e0a9ff0d7..feb604da27f2 100644 --- a/monitor/hmp.c +++ b/monitor/hmp.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include #include "hw/core/qdev.h" -#include "hw/core/sysemu-cpu-ops.h" #include "monitor-internal.h" #include "monitor-hmp-internal.h" #include "monitor/hmp.h" @@ -443,8 +442,6 @@ static bool gdb_get_register(MonitorHMP *hmp, int64_t *= pval, const char *name) static const char *pch; static sigjmp_buf expr_env; =20 -static int get_monitor_def(MonitorHMP *mon, int64_t *pval, const char *nam= e); - static G_NORETURN G_GNUC_PRINTF(2, 3) void expr_error(MonitorHMP *mon, const char *fmt, ...) { @@ -526,8 +523,7 @@ static int64_t expr_unary(MonitorHMP *mon) pch++; } *q =3D 0; - if (!gdb_get_register(mon, ®, buf) - && get_monitor_def(mon, ®, buf) < 0) { + if (!gdb_get_register(mon, ®, buf)) { expr_error(mon, "unknown register"); } n =3D reg; @@ -1720,43 +1716,6 @@ void monitor_register_hmp_info_hrt(const char *name, g_assert_not_reached(); } =20 -/* - * Set @pval to the value in the register identified by @name. - * return 0 if OK, -1 if not found - */ -static int get_monitor_def(MonitorHMP *hmp, int64_t *pval, const char *nam= e) -{ - CPUState *cs =3D monitor_hmp_get_cpu(hmp); - const MonitorDef *md =3D NULL; - void *ptr; - - if (cs =3D=3D NULL) { - return -1; - } - md =3D cs->cc->sysemu_ops->monitor_defs; - if (md =3D=3D NULL) { - return -1; - } - - for (; md->name !=3D NULL; md++) { - if (hmp_compare_cmd(name, md->name)) { - if (md->get_value) { - *pval =3D md->get_value(hmp, md, md->offset); - } else { - CPUArchState *env =3D monitor_hmp_get_cpu_env(hmp); - ptr =3D (uint8_t *)env + md->offset; - *pval =3D *(int32_t *)ptr; - } - return 0; - } - } - - if (!cs->cc->sysemu_ops->monitor_get_register) { - return -1; - } - return cs->cc->sysemu_ops->monitor_get_register(cs, name, pval); -} - int monitor_hmp_vprintf(MonitorHMP *hmp, const char *fmt, va_list ap) { g_autofree char *buf =3D g_strdup_vprintf(fmt, ap); --=20 2.56.0.116.g6de20f6092dc