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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622797540158500 The V79 QFloat entries were placed after the V81 entries. Move them before the V81 block, and group V6_vconv_bf_qf32 with the other V81 entries. No functional change. Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/tag_rev_info.c.inc | 32 +++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index 41ce3cb572f..b380a6b44ae 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -643,21 +643,6 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { [Y2_dcfetchbo_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, [Y2_dczeroa_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VE= R_NONE }, =20 - [Y2_tlbpp] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, - - [V6_valign4] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_N= ONE }, - [V6_veqhf] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, - [V6_veqhf_and] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, - [V6_veqhf_or] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_= NONE }, - [V6_veqhf_xor] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, - [V6_veqsf] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, - [V6_veqsf_and] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, - [V6_veqsf_or] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_= NONE }, - [V6_veqsf_xor] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, - [V6_vconv_h_hf_rnd] =3D { - .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NONE - }, - [V6_get_qfext] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER= _NONE }, [V6_get_qfext_oracc] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE @@ -671,7 +656,6 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_O= PCODE] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE }, [V6_vabs_qf32_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, - [V6_vconv_bf_qf32] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX= _VER_NONE }, [V6_vconv_qf16_hf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, [V6_vconv_qf16_qf16] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE @@ -698,6 +682,22 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { [V6_vneg_qf32_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, [V6_vsub_hf_mix] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_V= ER_NONE }, [V6_vsub_sf_mix] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_V= ER_NONE }, + + [Y2_tlbpp] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, + + [V6_valign4] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_N= ONE }, + [V6_veqhf] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, + [V6_veqhf_and] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_veqhf_or] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_= NONE }, + [V6_veqhf_xor] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_veqsf] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, + [V6_veqsf_and] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_veqsf_or] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_= NONE }, + [V6_veqsf_xor] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_vconv_h_hf_rnd] =3D { + .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NONE + }, + [V6_vconv_bf_qf32] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX= _VER_NONE }, }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622793422158500 Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- docs/system/hexagon/emulation.rst | 2 +- target/hexagon/cpu-qom.h | 4 ++++ linux-user/hexagon/elfload.c | 4 ++++ target/hexagon/cpu.c | 2 ++ 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/docs/system/hexagon/emulation.rst b/docs/system/hexagon/emulat= ion.rst index 12385311aa4..fb57c77ae90 100644 --- a/docs/system/hexagon/emulation.rst +++ b/docs/system/hexagon/emulation.rst @@ -6,7 +6,7 @@ Hexagon CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 QEMU's TCG emulation includes support for v65, v66, v67, v68, v69, v71, v7= 3, -v75, v77, v79, v81. +v75, v77, v79, v81, v83, v85. It also has support for the following architecture extensions: =20 - HVX (Hexagon Vector eXtensions) diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h index 2bfa4d5d0fc..d4c8413ded3 100644 --- a/target/hexagon/cpu-qom.h +++ b/target/hexagon/cpu-qom.h @@ -28,6 +28,8 @@ typedef enum { HEX_VER_V75 =3D 0x75, HEX_VER_V79 =3D 0x79, HEX_VER_V81 =3D 0x81, + HEX_VER_V83 =3D 0x83, + HEX_VER_V85 =3D 0x85, HEX_VER_ANY =3D 0xff, } HexagonVersion; =20 @@ -55,6 +57,8 @@ typedef struct { #define TYPE_HEXAGON_CPU_V75 HEXAGON_CPU_TYPE_NAME("v75") #define TYPE_HEXAGON_CPU_V79 HEXAGON_CPU_TYPE_NAME("v79") #define TYPE_HEXAGON_CPU_V81 HEXAGON_CPU_TYPE_NAME("v81") +#define TYPE_HEXAGON_CPU_V83 HEXAGON_CPU_TYPE_NAME("v83") +#define TYPE_HEXAGON_CPU_V85 HEXAGON_CPU_TYPE_NAME("v85") =20 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) =20 diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c index 3a6ba4e1304..9f98ad8fb86 100644 --- a/linux-user/hexagon/elfload.c +++ b/linux-user/hexagon/elfload.c @@ -113,6 +113,10 @@ const char *get_elf_cpu_model(uint32_t eflags) return "v79"; case 0x81: return "v81"; + case 0x83: + return "v83"; + case 0x85: + return "v85"; } =20 err =3D snprintf(buf, sizeof(buf), "unknown (0x%x)", eflags); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f20d6de6f63..1e3df5d0d03 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -934,6 +934,8 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_HEXAGON_CPU_V75, HEX_VER_V75), DEFINE_CPU(TYPE_HEXAGON_CPU_V79, HEX_VER_V79), DEFINE_CPU(TYPE_HEXAGON_CPU_V81, HEX_VER_V81), + DEFINE_CPU(TYPE_HEXAGON_CPU_V83, HEX_VER_V83), + DEFINE_CPU(TYPE_HEXAGON_CPU_V85, HEX_VER_V85), }; =20 DEFINE_TYPES(hexagon_cpu_type_infos) --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792622778; cv=none; d=zohomail.com; s=zohoarc; b=mx5874vap94aJlSu3UcdEFaRpPk5sFd5R5/0qvkB3V6y5Qq++KNLpuCoi1lGcLD66bQ7oome4joE2+PSq09iAJMkxIZkoB3ifxvfhR0S+fLKwGeBuxSL8odx7fYa6snzIxwdM6gFA1QY8gpsiXUILqUv9l1N2LKTxwbXFt80Kjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792622778; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Kg00cOBQnh7N6nKBceDjWzJVE82xWv+PwcMNpH29WyA=; b=A2niTNAqBXzckUlpeZ2ur+EAnHlYh1Olm9yKpk+1rqjp1UOMe69P091Q65lWFyRLJ++8o85RhS+B2ZqNpBO7D9gDxFySFRkNe/cLQrM3mCAjjSpLE3LH5pj1l2WC5tfCjXj950s1nBQGoOfw0kURI6GQmJ9Zhzw3/WY5W+qAOBs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792622778343464.0643960325; Wed, 21 Oct 2026 15:46:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJf37-00010t-5d; Wed, 21 Oct 2026 18:44:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJf2x-0000z2-FA for qemu-devel@nongnu.org; Wed, 21 Oct 2026 18:44:36 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJf2v-0002YA-6p for qemu-devel@nongnu.org; Wed, 21 Oct 2026 18:44:35 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKeLRh1502223 for ; Wed, 21 Oct 2026 22:44:30 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hf0k2hdpg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 22:44:30 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-30c0d568830so2815378eec.1 for ; Wed, 21 Oct 2026 15:44:30 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622781321158500 Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 6 ++-- hw/hexagon/machine_cfg_v85na_1.h.inc | 50 +++++++++++++++++++++++++++ hw/hexagon/machine_cfg_v85qa_1.h.inc | 51 ++++++++++++++++++++++++++++ hw/hexagon/hexagon_dsp.c | 48 +++++++++++++++++++++++++- 4 files changed, 152 insertions(+), 3 deletions(-) create mode 100644 hw/hexagon/machine_cfg_v85na_1.h.inc create mode 100644 hw/hexagon/machine_cfg_v85qa_1.h.inc diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 9b5d33ffc3b..ffd9967330f 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -29,9 +29,11 @@ typedef enum { v73m_rev =3D 0xcc73, v81_rev =3D 0x8781, v81dgb_1_rev =3D 0xcc81, + v85qa_1_rev =3D 0x8185, + v85na_1_rev =3D 0x8085, } Rev_t; -#define HEXAGON_LATEST_REV v73 -#define HEXAGON_LATEST_REV_UPPER V73 +#define HEXAGON_LATEST_REV v85 +#define HEXAGON_LATEST_REV_UPPER V85 =20 /* * Config table address bases represent bits [35:16]. diff --git a/hw/hexagon/machine_cfg_v85na_1.h.inc b/hw/hexagon/machine_cfg_= v85na_1.h.inc new file mode 100644 index 00000000000..f0ea1be1039 --- /dev/null +++ b/hw/hexagon/machine_cfg_v85na_1.h.inc @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v85na_1 =3D { + .cfgbase =3D 0xd8180000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .subsystem_base =3D 0x00002000, + .etm_base =3D 0x0000d819, + .l2cfg_base =3D 0x0000d81a, + .reserved1 =3D 0x0000d81b, + .l1s0_base =3D 0x0000d900, + .fastl2vic_base =3D 0x0000d81e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x0000001d, + .ext_contexts =3D 0x00000008, + .vtcm_base =3D 0x0000d900, + .vtcm_size_kb =3D 0x00003000, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x00000fff, + .l2line_size =3D 0x00000080, + .l2itcm_base =3D 0x0000d800, + .dma_version =3D 0x0000000c, + .hvx_vec_log_length =3D 0x00000007, + .coproc2_reg0 =3D 0x00000010, + .coproc2_reg1 =3D 0x00000008, + .coproc2_reg2 =3D 0x00000003, + .acd_preset =3D 0x00000001, + .mnd_preset =3D 0x00000001, + .l1d_size_kb =3D 0x00000040, + .l1i_size_kb =3D 0x00000040, + .l1d_write_policy =3D 0x00000002, + .vtcm_bank_width =3D 0x00000080, + .consistency_domain =3D 0x000000e0, + .capacity_domain =3D 0x00000080, + .axi3_lowaddr =3D 0x00004000, + .corecfg_present =3D 0x0000000d, + .coproc2_fp16_acc_exp =3D 0x00000003, + .AXIM_data_width =3D 0x00000100, + .l1d_ways =3D 0x00000008, + .l1i_ways =3D 0x00000004, + .l2way_num =3D 0x00000008, + .dma_jtlb_entries =3D 0x00000040, + }, +}; diff --git a/hw/hexagon/machine_cfg_v85qa_1.h.inc b/hw/hexagon/machine_cfg_= v85qa_1.h.inc new file mode 100644 index 00000000000..916a91ee291 --- /dev/null +++ b/hw/hexagon/machine_cfg_v85qa_1.h.inc @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v85qa_1 =3D { + .cfgbase =3D 0xd8180000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .subsystem_base =3D 0x0000fc90, + .etm_base =3D 0x0000d819, + .l2cfg_base =3D 0x0000d81a, + .reserved1 =3D 0x0000d81b, + .l1s0_base =3D 0x0000d900, + .fastl2vic_base =3D 0x0000d81e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x0000001d, + .ext_contexts =3D 0x00000008, + .vtcm_base =3D 0x0000d900, + .vtcm_size_kb =3D 0x00004000, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x00000fff, + .eccreg_base =3D 0x0000d81f, + .l2line_size =3D 0x00000080, + .l2itcm_base =3D 0x0000d800, + .dma_version =3D 0x0000000c, + .hvx_vec_log_length =3D 0x00000007, + .coproc2_reg0 =3D 0x00000010, + .coproc2_reg1 =3D 0x00000008, + .coproc2_reg2 =3D 0x00000003, + .acd_preset =3D 0x00000001, + .mnd_preset =3D 0x00000001, + .l1d_size_kb =3D 0x00000040, + .l1i_size_kb =3D 0x00000040, + .l1d_write_policy =3D 0x00000002, + .vtcm_bank_width =3D 0x00000080, + .consistency_domain =3D 0x000000e0, + .capacity_domain =3D 0x00000080, + .axi3_lowaddr =3D 0x00004000, + .corecfg_present =3D 0x0000000d, + .coproc2_fp16_acc_exp =3D 0x00000003, + .AXIM_data_width =3D 0x00000100, + .l1d_ways =3D 0x00000008, + .l1i_ways =3D 0x00000004, + .l2way_num =3D 0x00000008, + .dma_jtlb_entries =3D 0x00000040, + }, +}; diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index 8824fe10a59..28b5cf39917 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -32,6 +32,8 @@ #include "machine_cfg_v68n_1024.h.inc" #include "machine_cfg_v81dgb_1.h.inc" #include "machine_cfg_v81qa_1.h.inc" +#include "machine_cfg_v85na_1.h.inc" +#include "machine_cfg_v85qa_1.h.inc" =20 #define TYPE_HEXAGON_DSP_MACHINE "hexagon-dsp-machine" OBJECT_DECLARE_SIMPLE_TYPE(HexagonDspMachineState, HEXAGON_DSP_MACHINE) @@ -227,7 +229,6 @@ static void v81qa_1_init(ObjectClass *oc, const void *d= ata) MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Hexagon V81QA_1"; - mc->alias =3D "sim"; mc->init =3D v81qa_1_config_init; init_mc(mc); mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V81; @@ -235,6 +236,41 @@ static void v81qa_1_init(ObjectClass *oc, const void *= data) mc->default_cpus =3D 12; } =20 +static void v85qa_1_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v85qa_1_rev, &v85qa_1); +} + +static void v85qa_1_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V85QA_1"; + mc->init =3D v85qa_1_config_init; + init_mc(mc); + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V85; + mc->max_cpus =3D 12; + mc->default_cpus =3D 12; +} + +static void v85na_1_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v85na_1_rev, &v85na_1); +} + +static void v85na_1_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V85NA_1"; + mc->alias =3D "sim"; + mc->init =3D v85na_1_config_init; + init_mc(mc); + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V85; + mc->max_cpus =3D 12; + mc->default_cpus =3D 12; +} + static const TypeInfo hexagon_machine_types[] =3D { { .name =3D TYPE_HEXAGON_COMMON_MACHINE, @@ -268,6 +304,16 @@ static const TypeInfo hexagon_machine_types[] =3D { .parent =3D TYPE_HEXAGON_DSP_MACHINE, .class_init =3D v81qa_1_init, }, + { + .name =3D MACHINE_TYPE_NAME("V85QA_1"), + .parent =3D TYPE_HEXAGON_DSP_MACHINE, + .class_init =3D v85qa_1_init, + }, + { + .name =3D MACHINE_TYPE_NAME("V85NA_1"), + .parent =3D TYPE_HEXAGON_DSP_MACHINE, + .class_init =3D v85na_1_init, + }, }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622781216158500 Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- linux-user/hexagon/target_elf.h | 2 ++ linux-user/hexagon/elfload.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/linux-user/hexagon/target_elf.h b/linux-user/hexagon/target_el= f.h index 90e5032d5aa..b1eb5ea5037 100644 --- a/linux-user/hexagon/target_elf.h +++ b/linux-user/hexagon/target_elf.h @@ -43,6 +43,8 @@ enum { HWCAP_HEXAGON_ISA_V77 =3D 16, HWCAP_HEXAGON_ISA_V79 =3D 17, HWCAP_HEXAGON_ISA_V81 =3D 18, + HWCAP_HEXAGON_ISA_V83 =3D 19, + HWCAP_HEXAGON_ISA_V85 =3D 20, HWCAP_HEXAGON_HVX =3D 1 << 7, HWCAP_HEXAGON_CABAC =3D 1 << 8, HWCAP_HEXAGON_HVX_LENGTH_128B =3D 1 << 9, diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c index 9f98ad8fb86..db0bf299cc0 100644 --- a/linux-user/hexagon/elfload.c +++ b/linux-user/hexagon/elfload.c @@ -62,6 +62,12 @@ abi_ulong get_elf_hwcap(CPUState *cs) case HEX_VER_V81: hwcaps =3D HWCAP_HEXAGON_ISA_V81; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622805599158500 The scalar atomic instructions are able to perform a word or double-word read-modify-write atomically. Also add the v85 dcfetch_multi instruction, which prefetches multiple data cache lines. It is modelled as a no-op, as other dcfetch instructions are. Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 27 +++++++++++++++++++++ target/hexagon/genptr.h | 11 +++++++++ target/hexagon/attribs_def.h.inc | 1 + target/hexagon/genptr.c | 32 +++++++++++++++++++++++++ target/hexagon/tag_rev_info.c.inc | 15 ++++++++++++ target/hexagon/gen_idef_parser_funcs.py | 2 ++ target/hexagon/imported/encode_pp.def | 15 +++++++++++- target/hexagon/imported/ldst.idef | 14 ++++++++++- target/hexagon/imported/macros.def | 10 ++++++++ target/hexagon/imported/system.idef | 1 + 10 files changed, 126 insertions(+), 2 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index ed05f97efed..e972bb4e5b8 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -100,6 +100,28 @@ #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ fGEN_TCG_LOAD_AP(RddV, 8, u) =20 +#define fGEN_TCG_ATOMIC4(OP) \ + do { \ + fEA_REG(RsV); \ + gen_atomic4(ctx, RdV, EA, RtV, OP); \ + } while (0) +#define fGEN_TCG_AM_addw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_ADD) +#define fGEN_TCG_AM_addw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_ADD) +#define fGEN_TCG_AM_andw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_AND) +#define fGEN_TCG_AM_andw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_AND) +#define fGEN_TCG_AM_orw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_OR) +#define fGEN_TCG_AM_orw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_OR) +#define fGEN_TCG_AM_xorw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_XOR) +#define fGEN_TCG_AM_xorw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_XOR) +#define fGEN_TCG_AM_swapw_aq(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_SWAP) +#define fGEN_TCG_AM_swapw_rl(SHORTCODE) fGEN_TCG_ATOMIC4(HEX_ATOMIC_SWAP) +#define fGEN_TCG_AM_swapd_aq(SHORTCODE) \ + do { \ + fEA_REG(RsV); \ + gen_atomic8(ctx, RddV, EA, RttV); \ + } while (0) +#define fGEN_TCG_AM_swapd_rl(SHORTCODE) fGEN_TCG_AM_swapd_aq(SHORTCODE) + #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE @@ -1377,6 +1399,11 @@ RsV =3D RsV; \ uiV =3D uiV; \ } while (0) +#define fGEN_TCG_Y4_dcfetch_multi(SHORTCODE) \ + do { \ + RsV =3D RsV; \ + RtV =3D RtV; \ + } while (0) =20 #define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE #define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 238ee089cba..7c0e90e93aa 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -58,6 +58,17 @@ TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, = bool sign); TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign); void gen_set_half(int N, TCGv result, TCGv src); void gen_set_half_i64(int N, TCGv_i64 result, TCGv src); +typedef enum { + HEX_ATOMIC_ADD, + HEX_ATOMIC_AND, + HEX_ATOMIC_OR, + HEX_ATOMIC_XOR, + HEX_ATOMIC_SWAP, +} HexAtomicOp; + +void gen_atomic4(DisasContext *ctx, TCGv dest, TCGv vaddr, TCGv src, + HexAtomicOp operation); +void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 sr= c); void probe_noshuf_load(TCGv va, int s, int mi); void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 5a98ea33139..8deef8e4cfb 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -60,6 +60,7 @@ DEF_ATTRIB(COPBYADDRESS, "Cache operation by address", ""= , "") DEF_ATTRIB(COPBYIDX, "Cache operation by index", "", "") DEF_ATTRIB(RELEASE, "Releases a lock", "", "") DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "") +DEF_ATTRIB(ATOMIC, "Atomic memory instruction", "", "") =20 DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "") DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "") diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1a68d8c1b8d..58c31b05d57 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -698,6 +698,38 @@ static inline void gen_store_conditional8(DisasContext= *ctx, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 +void gen_atomic4(DisasContext *ctx, TCGv dest, TCGv vaddr, TCGv src, + HexAtomicOp operation) +{ + MemOp memop =3D MO_LE | MO_32 | MO_ALIGN; + + switch (operation) { + case HEX_ATOMIC_ADD: + tcg_gen_atomic_fetch_add_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_AND: + tcg_gen_atomic_fetch_and_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_OR: + tcg_gen_atomic_fetch_or_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_XOR: + tcg_gen_atomic_fetch_xor_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + case HEX_ATOMIC_SWAP: + tcg_gen_atomic_xchg_tl(dest, vaddr, src, ctx->mem_idx, memop); + break; + default: + g_assert_not_reached(); + } +} + +void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 sr= c) +{ + tcg_gen_atomic_xchg_i64(dest, vaddr, src, ctx->mem_idx, + MO_LE | MO_64 | MO_ALIGN); +} + #ifndef CONFIG_HEXAGON_IDEF_PARSER static TCGv gen_slotval(DisasContext *ctx) { diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index b380a6b44ae..a1b7b50cbf2 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -698,6 +698,21 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NONE }, [V6_vconv_bf_qf32] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX= _VER_NONE }, + + [Y4_dcfetch_multi] =3D { .introduced =3D HEX_VER_V85, + .removed =3D HEX_VER_NONE }, + [AM_addw_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, + [AM_addw_rl] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, + [AM_andw_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, + [AM_andw_rl] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, + [AM_orw_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_NO= NE }, + [AM_orw_rl] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_NO= NE }, + [AM_swapd_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_= NONE }, + [AM_swapd_rl] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_= NONE }, + [AM_swapw_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_= NONE }, + [AM_swapw_rl] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_= NONE }, + [AM_xorw_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, + [AM_xorw_rl] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, }; =20 #endif /* HEXAGON_TAG_ARCH_TABLE_H */ diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_i= def_parser_funcs.py index 32bce9b0028..7151a4f6713 100644 --- a/target/hexagon/gen_idef_parser_funcs.py +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -68,6 +68,8 @@ def main(): ## Skip the guest instructions if "A_GUEST" in hex_common.attribdict[tag]: continue + if "A_ATOMIC" in hex_common.attribdict[tag]: + continue ## Skip instructions that saturate in a ternary expression if tag in {"S2_asr_r_r_sat", "S2_asl_r_r_sat"}: continue diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index 4b307b97b30..c590ed4f959 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -406,7 +406,8 @@ DEF_ENC32(R6_release_at_vi, ICLASS_ST" 000 01 11ssss= s PP0ttttt --0011dd") DEF_ENC32(R6_release_st_vi, ICLASS_ST" 000 01 11sssss PP0ttttt --1011dd") =20 DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii PP0iiiii 001iiiii") -DEF_ENC32(Y2_dcfetchbo, ICLASS_LD" 010 0 000 sssss PP0--iii iiiiiiii") +DEF_ENC32(Y2_dcfetchbo, "10010100000sssssPP000iiiiiiiiiii") +DEF_ENC32(Y4_dcfetch_multi,"10010100000sssssPP001ttttt------") DEF_ENC32(Y2_dcfetchbo_nt,"10010100000sssssPP10-iiiiiiiiiii") =20 =20 @@ -1895,6 +1896,18 @@ SH_RRR_ENC(S2_cabacdecbin, "0001","11-","-","11= -","ddddd") /* implicit P0 w =20 =20 DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rd= d=3D(Rss,Rtt,Pu)") +DEF_ENC32(AM_addw_aq, "10010000000sssssPP1ttttt001ddddd") +DEF_ENC32(AM_addw_rl, "10010000000sssssPP1ttttt010ddddd") +DEF_ENC32(AM_andw_aq, "10010000000sssssPP1ttttt101ddddd") +DEF_ENC32(AM_andw_rl, "10010000000sssssPP1ttttt110ddddd") +DEF_ENC32(AM_orw_aq, "10010000110sssssPP0ttttt001ddddd") +DEF_ENC32(AM_orw_rl, "10010000110sssssPP0ttttt010ddddd") +DEF_ENC32(AM_xorw_aq, "10010000110sssssPP0ttttt101ddddd") +DEF_ENC32(AM_xorw_rl, "10010000110sssssPP0ttttt110ddddd") +DEF_ENC32(AM_swapw_aq, "10010000110sssssPP1ttttt001ddddd") +DEF_ENC32(AM_swapw_rl, "10010000110sssssPP1ttttt010ddddd") +DEF_ENC32(AM_swapd_aq, "10010000110sssssPP1ttttt101ddddd") +DEF_ENC32(AM_swapd_rl, "10010000110sssssPP1ttttt110ddddd") SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd") SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd") SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd") diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 7106a0c572c..48cda64e0b0 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -135,7 +135,6 @@ STD_ST_AMODES(storerhnew, "Nt8.new", "memh","Store Half= integer",ATTRIBS(A_REGWR =20 Q6INSN(S2_allocframe,"allocframe(Rx32,#u11:3):raw", ATTRIBS(A_REGWRSIZE_8B= ,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY), "Allocate stack frame", { fEA_RI(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << = 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA); RxV = =3D EA-uiV; }) - #define A_RETURN A_RESTRICT_COF_MAX1,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOSLO= T1_STORE,A_RET_TYPE,A_DEALLOCRET =20 /**** Load Acquire Store Release Instructions****/ @@ -156,6 +155,19 @@ Q6INSN(S4_stored_rl_at_vi,"memd_rl(Rs32):at=3DRtt32",A= TTRIBS(A_REGWRSIZE_8B,A_RELE Q6INSN(S2_storew_rl_st_vi,"memw_rl(Rs32):st=3DRt32",ATTRIBS(A_REGWRSIZE_4B= ,A_RELEASE,A_VTCM_ALLBANK_ACCESS,A_RLS_INNER,A_RLS_SAME_THREAD,A_RESTRICT_N= OPACKET,A_MEMSIZE_4B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Word", { = fEA_REG(RsV); fSTORE(1,4,EA,RtV); }) Q6INSN(S4_stored_rl_st_vi,"memd_rl(Rs32):st=3DRtt32",ATTRIBS(A_REGWRSIZE_8= B,A_RELEASE,A_VTCM_ALLBANK_ACCESS,A_RLS_INNER,A_RLS_SAME_THREAD,A_RESTRICT_= NOPACKET,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY),"Store Release Double i= nteger", { fEA_REG(RsV); fSTORE(1,8,EA,RttV); }) =20 +Q6INSN(AM_addw_aq,"Rd32=3Datomw_add(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AX= OK),"Atomic add word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,0,*= EA+RtV); }) +Q6INSN(AM_addw_rl,"Rd32=3Datomw_add(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AX= OK),"Atomic add word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,0,*= EA+RtV); }) +Q6INSN(AM_andw_aq,"Rd32=3Datomw_and(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AX= OK),"Atomic and word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,1,*= EA&RtV); }) +Q6INSN(AM_andw_rl,"Rd32=3Datomw_and(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AX= OK),"Atomic and word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,1,*= EA&RtV); }) +Q6INSN(AM_orw_aq,"Rd32=3Datomw_or(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,A_= MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK= ),"Atomic or word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,2,*EA|= RtV); }) +Q6INSN(AM_orw_rl,"Rd32=3Datomw_or(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,A_= MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK= ),"Atomic or word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,2,*EA|= RtV); }) +Q6INSN(AM_xorw_aq,"Rd32=3Datomw_xor(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AX= OK),"Atomic xor word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,3,*= EA^RtV); }) +Q6INSN(AM_xorw_rl,"Rd32=3Datomw_xor(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4B,= A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AX= OK),"Atomic xor word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,3,*= EA^RtV); }) +Q6INSN(AM_swapw_aq,"Rd32=3Datomw_swap(Rs32,Rt32):aq",ATTRIBS(A_REGWRSIZE_4= B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_= AXOK),"Atomic swap word acquire",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,= 4,RtV); }) +Q6INSN(AM_swapw_rl,"Rd32=3Datomw_swap(Rs32,Rt32):rl",ATTRIBS(A_REGWRSIZE_4= B,A_MEMSIZE_4B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_= AXOK),"Atomic swap word release",{ fEA_REG(RsV); fATOMIC_LDST(4,RdV,EA,RtV,= 4,RtV); }) +Q6INSN(AM_swapd_aq,"Rdd32=3Datomd_swap(Rs32,Rtt32):aq",ATTRIBS(A_REGWRSIZE= _8B,A_MEMSIZE_8B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOT= E_AXOK),"Atomic swap double word acquire",{ fEA_REG(RsV); fATOMIC_LDST(8,Rd= dV,EA,RttV,4,RttV); }) +Q6INSN(AM_swapd_rl,"Rdd32=3Datomd_swap(Rs32,Rtt32):rl",ATTRIBS(A_REGWRSIZE= _8B,A_MEMSIZE_8B,A_ATOMIC,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOT= E_AXOK),"Atomic swap double word release",{ fEA_REG(RsV); fATOMIC_LDST(8,Rd= dV,EA,RttV,4,RttV); }) + Q6INSN(L2_deallocframe,"Rdd32=3Ddeallocframe(Rs32):raw", ATTRIBS(A_REGWRSI= ZE_8B,A_MEMSIZE_8B,A_LOAD,A_DEALLOCFRAME), "Deallocate stack frame", { fHIDE(size8u_t tmp;) fEA_REG(RsV); fLOAD(1,8,u,EA,tmp); diff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/m= acros.def index 13eb13c71f7..ef9955a0212 100644 --- a/target/hexagon/imported/macros.def +++ b/target/hexagon/imported/macros.def @@ -1404,6 +1404,11 @@ DEF_MACRO(fLOAD_LOCKED, (A_LOAD,A_MEMLIKE) ) =20 +DEF_MACRO(fATOMIC_LDST, + { }, + (A_LOAD,A_STORE,A_MEMLIKE) +) + DEF_MACRO(fSTORE, { MEM_STORE##SIZE(thread,EA,SRC,insn); }, (A_STORE,A_MEMLIKE) @@ -1958,6 +1963,11 @@ DEF_MACRO(fDCFETCH, (A_MEMLIKE) ) =20 +DEF_MACRO(fDCFETCH_MULTI, + { }, + (A_MEMLIKE) +) + DEF_MACRO(fICINVA, /* */, (A_ICINVA) diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/= system.idef index a58da8f8269..9c4897a2eee 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -241,6 +241,7 @@ Q6INSN(Y6_dmresume,"dmresume(Rs32)",ATTRIBS(A_NOTE_NOPA= CKET,A_RESTRICT_NOPACKET, =20 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,= A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV);= fDCFETCH(EA);}) Q6INSN(Y2_dcfetchbo_nt,"dcfetch(Rs32+#u11:3):nt",ATTRIBS(A_NA_NT,A_RESTRIC= T_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fE= A_RI(RsV,uiV); fDCFETCH(EA);}) +Q6INSN(Y4_dcfetch_multi,"dcfetch_multi(Rs32,Rt32)",ATTRIBS(A_RESTRICT_PREF= ERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_REG(= RsV); fDCFETCH_MULTI(EA,fEXTRACTU_BITS(RtV,10,0));}) Q6INSN(Y2_dckill,"dckill",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RES= TRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),"Data Cache Inva= lidate",{fDCKILL();}) =20 =20 --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792622770; cv=none; d=zohomail.com; s=zohoarc; b=Y/AKM1yx5Cb8YfvzVr6yZBr6C0SVXPNHZJW8Sw9Saw7X9mYGFnXugySE1Fy2/aSU1nvLjK7ZpWo5V0ymRP3efc9tJFykpRCsMs8uwU6U2oT5H/XJzZS8NiwDLvP27Sa6C5yoK6tv1GpeshSxBM/KvguVT1L98CPAd99Jwh4efeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792622770; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622773164158500 Add decode and translation for trap2 and the vallocframe and vdeallocframe instruction forms introduced with v83. Model vector stack overflow as a precise exception and report it to linux-user as SIGSEGV. Teach the IDEF parser about VSP and vector frame checks. Describe the vallocframe and vdeallocframe instruction semantics in system.idef, and move the vector stack overflow check into a shared TCG generator helper. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu_bits.h | 2 + target/hexagon/gen_tcg.h | 51 +++++++++++++++++++++ target/hexagon/genptr.h | 1 + target/hexagon/hex_regs.h | 2 + target/hexagon/idef-parser/parser-helpers.h | 1 + target/hexagon/translate.h | 1 + linux-user/hexagon/cpu_loop.c | 5 ++ target/hexagon/cpu.c | 2 +- target/hexagon/decode.c | 1 + target/hexagon/genptr.c | 21 +++++++++ target/hexagon/hexswi.c | 25 +++++++++- target/hexagon/iclass.c | 1 + target/hexagon/idef-parser/parser-helpers.c | 14 ++++++ target/hexagon/translate.c | 2 +- target/hexagon/tag_rev_info.c.inc | 10 ++++ target/hexagon/gen_idef_parser_funcs.py | 2 +- target/hexagon/idef-parser/idef-parser.lex | 8 ++++ target/hexagon/idef-parser/idef-parser.y | 9 +++- target/hexagon/imported/encode_pp.def | 5 ++ target/hexagon/imported/system.idef | 8 ++++ 20 files changed, 166 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index a8fba4aa188..6a800525348 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -41,6 +41,7 @@ enum hex_event { HEX_EVENT_TLB_MISS_RW =3D 0x6, HEX_EVENT_TRAP0 =3D 0x8, HEX_EVENT_TRAP1 =3D 0x9, + HEX_EVENT_TRAP2 =3D 0xa, HEX_EVENT_FPTRAP =3D 0xb, HEX_EVENT_DEBUG =3D 0xc, HEX_EVENT_INT0 =3D 0x10, @@ -77,6 +78,7 @@ enum hex_cause { HEX_CAUSE_NO_COPROC2_ENABLE =3D 0x018, HEX_CAUSE_PRIV_USER_NO_GINSN =3D 0x01a, HEX_CAUSE_PRIV_USER_NO_SINSN =3D 0x01b, + HEX_CAUSE_VECTOR_STACK_OVERFLOW =3D 0x01c, HEX_CAUSE_REG_WRITE_CONFLICT =3D 0x01d, HEX_CAUSE_PC_NOT_ALIGNED =3D 0x01e, HEX_CAUSE_MISALIGNED_LOAD =3D 0x020, diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index e972bb4e5b8..690bf20e6b2 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -531,6 +531,57 @@ do { RsV =3D RsV; } while (0) #endif =20 +#ifdef CONFIG_USER_ONLY +#define fGEN_TCG_V2_CHECK_AND_WRITE_VSP(VSP) \ + do { \ + TCGLabel *write_vsp =3D gen_new_label(); \ + tcg_gen_brcond_tl(TCG_COND_GEU, VSP, \ + hex_gpr[HEX_REG_VFRAMELIMIT], write_vsp); \ + gen_precise_exception(HEX_CAUSE_VECTOR_STACK_OVERFLOW, ctx->pkt.pc= ); \ + gen_set_label(write_vsp); \ + tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], VSP); \ + } while (0) +#else +#define fGEN_TCG_V2_CHECK_AND_WRITE_VSP(VSP) \ + do { \ + TCGLabel *write_vsp =3D gen_new_label(); \ + TCGv mode =3D tcg_temp_new(); \ + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], \ + 1 << reg_field_info[SSR_EX].offset); \ + tcg_gen_brcondi_tl(TCG_COND_NE, mode, 0, write_vsp); \ + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], \ + 1 << reg_field_info[SSR_UM].offset); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, mode, 0, write_vsp); \ + tcg_gen_brcond_tl(TCG_COND_GEU, VSP, \ + hex_gpr[HEX_REG_VFRAMELIMIT], write_vsp); \ + gen_precise_exception(HEX_CAUSE_VECTOR_STACK_OVERFLOW, ctx->pkt.pc= ); \ + gen_set_label(write_vsp); \ + tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], VSP); \ + } while (0) +#endif +#define fGEN_TCG_V2_vallocframe_imm(SHORTCODE) \ + do { \ + TCGv vsp =3D tcg_temp_new(); \ + tcg_gen_subi_tl(vsp, hex_gpr[HEX_REG_VSP], uiV << 11); \ + fGEN_TCG_V2_CHECK_AND_WRITE_VSP(vsp); \ + } while (0) +#define fGEN_TCG_V2_vallocframe_reg(SHORTCODE) \ + do { \ + TCGv size =3D tcg_temp_new(); \ + TCGv vsp =3D tcg_temp_new(); \ + tcg_gen_shli_tl(size, RsV, 11); \ + tcg_gen_sub_tl(vsp, hex_gpr[HEX_REG_VSP], size); \ + fGEN_TCG_V2_CHECK_AND_WRITE_VSP(vsp); \ + } while (0) +#define fGEN_TCG_V2_vdeallocframe_imm(SHORTCODE) \ + tcg_gen_addi_tl(hex_gpr[HEX_REG_VSP], hex_gpr[HEX_REG_VSP], uiV << 11) +#define fGEN_TCG_V2_vdeallocframe_reg(SHORTCODE) \ + do { \ + TCGv size =3D tcg_temp_new(); \ + tcg_gen_shli_tl(size, RsV, 11); \ + tcg_gen_add_tl(hex_gpr[HEX_REG_VSP], hex_gpr[HEX_REG_VSP], size); \ + } while (0) + /* * allocframe(#uiV) * RxV =3D=3D r29 diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 7c0e90e93aa..270375251f8 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -69,6 +69,7 @@ typedef enum { void gen_atomic4(DisasContext *ctx, TCGv dest, TCGv vaddr, TCGv src, HexAtomicOp operation); void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCGv vaddr, TCGv_i64 sr= c); +void gen_vframecheck(DisasContext *ctx, TCGv vsp); void probe_noshuf_load(TCGv va, int s, int mi); void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h index 1f6bf9f88a0..03feca477b6 100644 --- a/target/hexagon/hex_regs.h +++ b/target/hexagon/hex_regs.h @@ -77,6 +77,8 @@ enum { HEX_REG_QEMU_PKT_CNT =3D 52, HEX_REG_QEMU_INSN_CNT =3D 53, HEX_REG_QEMU_HVX_CNT =3D 54, + HEX_REG_VFRAMELIMIT =3D 60, + HEX_REG_VSP =3D 61, HEX_REG_UTIMERLO =3D 62, HEX_REG_UTIMERHI =3D 63, }; diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/i= def-parser/parser-helpers.h index d3dfcec5690..0c9ddc0727e 100644 --- a/target/hexagon/idef-parser/parser-helpers.h +++ b/target/hexagon/idef-parser/parser-helpers.h @@ -296,6 +296,7 @@ void gen_cancel(Context *c, YYLTYPE *locp); void gen_load_cancel(Context *c, YYLTYPE *locp); =20 void gen_framecheck(Context *c, YYLTYPE *locp, HexValue *addr, HexValue *e= a); +void gen_vframecheck(Context *c, YYLTYPE *locp, HexValue *addr); =20 void gen_load(Context *c, YYLTYPE *locp, HexValue *size, HexSignedness signedness, HexValue *ea, HexValue *dst); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index dc0c6b18bf1..47ca5e8ae01 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -364,6 +364,7 @@ extern TCGv_i64 hex_llsc_val_i64; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; +void gen_precise_exception(int cause, uint32_t pc); #ifdef CONFIG_USER_ONLY #define hex_hvx_ptr tcg_env #define HEX_HVX_OFFSET(member) offsetof(CPUHexagonState, hvx_ctx.member) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index e6bb3b62a9f..22570a12648 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -48,6 +48,7 @@ void cpu_loop(CPUHexagonState *env) /* just indicate that signals should be handled asap */ break; case HEX_EVENT_TRAP0: + case HEX_EVENT_TRAP2: syscallnum =3D env->gpr[6]; env->gpr[HEX_REG_PC] +=3D 4; ret =3D do_syscall(env, @@ -73,6 +74,10 @@ void cpu_loop(CPUHexagonState *env) force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->gpr[HEX_REG_PC]); break; + case HEX_CAUSE_VECTOR_STACK_OVERFLOW: + force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_BNDERR, + env->gpr[HEX_REG_PC]); + break; case HEX_CAUSE_PRIV_USER_NO_GINSN: case HEX_CAUSE_PRIV_USER_NO_SINSN: case HEX_CAUSE_INVALID_PACKET: diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1e3df5d0d03..f4f733cc251 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -87,7 +87,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS= ] =3D { "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", - "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", + "c24", "c25", "c26", "c27", "vframelimit", "vsp", "c30", "c31", }; =20 #ifndef CONFIG_USER_ONLY diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 89e961331ff..a28bf9ce9fe 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -186,6 +186,7 @@ static bool decode_opcode_can_jump(int opcode) (GET_ATTRIB(opcode, A_CALL)) || (opcode =3D=3D J2_trap0) || (opcode =3D=3D J2_trap1) || + (opcode =3D=3D J2_trap2) || (opcode =3D=3D J2_rte) || (opcode =3D=3D J2_pause)) { /* Exception to A_JUMP attribute */ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 58c31b05d57..d234f994f46 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -730,6 +730,27 @@ void gen_atomic8(DisasContext *ctx, TCGv_i64 dest, TCG= v vaddr, TCGv_i64 src) MO_LE | MO_64 | MO_ALIGN); } =20 +void gen_vframecheck(DisasContext *ctx, TCGv vsp) +{ + TCGLabel *write_vsp =3D gen_new_label(); + +#ifndef CONFIG_USER_ONLY + TCGv mode =3D tcg_temp_new(); + + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], + 1 << reg_field_info[SSR_EX].offset); + tcg_gen_brcondi_tl(TCG_COND_NE, mode, 0, write_vsp); + tcg_gen_andi_tl(mode, hex_t_sreg[HEX_SREG_SSR], + 1 << reg_field_info[SSR_UM].offset); + tcg_gen_brcondi_tl(TCG_COND_EQ, mode, 0, write_vsp); +#endif + tcg_gen_brcond_tl(TCG_COND_GEU, vsp, + hex_gpr[HEX_REG_VFRAMELIMIT], write_vsp); + gen_precise_exception(HEX_CAUSE_VECTOR_STACK_OVERFLOW, ctx->pkt.pc); + gen_set_label(write_vsp); + tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], vsp); +} + #ifndef CONFIG_HEXAGON_IDEF_PARSER static TCGv gen_slotval(DisasContext *ctx) { diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index e7362b56650..5783781195e 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -366,6 +366,10 @@ static void coredump(CPUHexagonState *env) fprintf(f, "0x%x, Stack limit check error", HEX_CAUSE_STACK_LIMIT); break; + case HEX_CAUSE_VECTOR_STACK_OVERFLOW: + fprintf(f, "0x%x, Vector stack overflow", + HEX_CAUSE_VECTOR_STACK_OVERFLOW); + break; case HEX_CAUSE_FPTRAP_CAUSE_BADFLOAT: fprintf(f, "0x%x, Floating-Point: Execution of Floating-Point " "instruction resulted in exception", @@ -743,6 +747,7 @@ static const char *event_name[] =3D { [HEX_EVENT_TLB_MISS_RW] =3D "HEX_EVENT_TLB_MISS_RW", [HEX_EVENT_TRAP0] =3D "HEX_EVENT_TRAP0", [HEX_EVENT_TRAP1] =3D "HEX_EVENT_TRAP1", + [HEX_EVENT_TRAP2] =3D "HEX_EVENT_TRAP2", [HEX_EVENT_FPTRAP] =3D "HEX_EVENT_FPTRAP", [HEX_EVENT_DEBUG] =3D "HEX_EVENT_DEBUG", [HEX_EVENT_INT0] =3D "HEX_EVENT_INT0", @@ -805,6 +810,11 @@ void hexagon_cpu_do_interrupt(CPUState *cs) set_addresses(env, 4, cs->exception_index); break; =20 + case HEX_EVENT_TRAP2: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 4, cs->exception_index); + break; + case HEX_EVENT_TLB_MISS_X: switch (env->cause_code) { case HEX_CAUSE_TLBMISSX_CAUSE_NORMAL: @@ -911,6 +921,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs) case HEX_CAUSE_NO_COPROC_ENABLE: case HEX_CAUSE_NO_COPROC2_ENABLE: case HEX_CAUSE_UNSUPPORTED_HVX_64B: + case HEX_CAUSE_VECTOR_STACK_OVERFLOW: case HEX_CAUSE_REG_WRITE_CONFLICT: case HEX_CAUSE_VWCTRL_WINDOW_MISS: hexagon_ssr_set_cause(env, env->cause_code); @@ -991,7 +1002,19 @@ void register_trap_exception(CPUHexagonState *env, in= t traptype, int imm, { CPUState *cs =3D env_cpu(env); =20 - cs->exception_index =3D (traptype =3D=3D 0) ? HEX_EVENT_TRAP0 : HEX_EV= ENT_TRAP1; + switch (traptype) { + case 0: + cs->exception_index =3D HEX_EVENT_TRAP0; + break; + case 1: + cs->exception_index =3D HEX_EVENT_TRAP1; + break; + case 2: + cs->exception_index =3D HEX_EVENT_TRAP2; + break; + default: + g_assert_not_reached(); + } ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index); =20 env->cause_code =3D imm; diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c index c3f8523b27d..00b8108a8fb 100644 --- a/target/hexagon/iclass.c +++ b/target/hexagon/iclass.c @@ -50,6 +50,7 @@ SlotMask find_iclass_slots(Opcode opcode, int itype) } else if (GET_ATTRIB(opcode, A_RESTRICT_NOSLOT1)) { return SLOTS_0; } else if ((opcode =3D=3D J2_trap0) || + (opcode =3D=3D J2_trap2) || (opcode =3D=3D Y2_isync) || (opcode =3D=3D J2_pause)) { return SLOTS_2; diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 49cc11fddd8..104f935a21e 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -25,6 +25,7 @@ #include #include =20 +#include "hex_regs.h" #include "idef-parser.h" #include "parser-helpers.h" #include "idef-parser.tab.h" @@ -1313,6 +1314,11 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexVal= ue *reg, HexValue *value) yyassert(c, locp, reg->type =3D=3D REGISTER, "reg must be a register!"= ); value_m =3D gen_rvalue_truncate(c, locp, &value_m); value_m =3D rvalue_materialize(c, locp, &value_m); + if (reg->reg.id =3D=3D HEX_REG_VSP) { + OUT(c, locp, "tcg_gen_mov_tl(hex_gpr[HEX_REG_VSP], ", &value_m, + ");\n"); + return; + } OUT(c, locp, "tcg_gen_mov_tl(get_result_gpr(ctx, ", ®->reg.id, "), ", @@ -1740,6 +1746,14 @@ void gen_framecheck(Context *c, YYLTYPE *locp, HexVa= lue *addr, HexValue *ea) OUT(c, locp, "gen_framecheck(ctx, ", &addr_m, ", ", &ea_m, ");\n"); } =20 +void gen_vframecheck(Context *c, YYLTYPE *locp, HexValue *addr) +{ + HexValue addr_m =3D rvalue_materialize(c, locp, addr); + + addr_m =3D gen_rvalue_truncate(c, locp, &addr_m); + OUT(c, locp, "gen_vframecheck(ctx, ", &addr_m, ");\n"); +} + void gen_load(Context *c, YYLTYPE *locp, HexValue *width, HexSignedness signedness, HexValue *ea, HexValue *dst) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2c18f5eebff..6e7c2f32f41 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -136,7 +136,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, return offset; } =20 -static void gen_precise_exception(int cause, uint32_t PC) +void gen_precise_exception(int cause, uint32_t PC) { tcg_gen_movi_i32(hex_cause_code, cause); gen_helper_hexagon_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT= _PRECISE), diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index a1b7b50cbf2..c2d4886a846 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -699,6 +699,16 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { }, [V6_vconv_bf_qf32] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX= _VER_NONE }, =20 + [V2_vallocframe_imm] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [V2_vallocframe_reg] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [V2_vdeallocframe_imm] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [V2_vdeallocframe_reg] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [J2_trap2] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NON= E }, + [Y4_dcfetch_multi] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_NONE }, [AM_addw_aq] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_N= ONE }, diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_i= def_parser_funcs.py index 7151a4f6713..9293be4c398 100644 --- a/target/hexagon/gen_idef_parser_funcs.py +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -77,7 +77,7 @@ def main(): if tag in {"S4_vrcrotate_acc", "S4_vrcrotate"}: continue ## Skip trap instructions - if tag in {"J2_trap0", "J2_trap1"}: + if tag in {"J2_trap0", "J2_trap1", "J2_trap2"}: continue ## Skip 128-bit instructions if tag in {"A7_croundd_ri", "A7_croundd_rr"}: diff --git a/target/hexagon/idef-parser/idef-parser.lex b/target/hexagon/id= ef-parser/idef-parser.lex index cd5958ec904..c2fc10dccce 100644 --- a/target/hexagon/idef-parser/idef-parser.lex +++ b/target/hexagon/idef-parser/idef-parser.lex @@ -161,6 +161,7 @@ STRING_LIT \"(\\.|[^"\\])*\" "fFRAME_SCRAMBLE" | "fFRAME_UNSCRAMBLE" { return FSCR; } "fFRAMECHECK" { return FCHK; } +"fVFRAMECHECK" { return VFCHK; } "Constant_extended" { return CONSTEXT; } "fCL1_"{DIGIT} { return LOCNT; } "fbrev" { return BREV; } @@ -329,6 +330,13 @@ STRING_LIT \"(\\.|[^"\\])*\" yylval->rvalue.bit_width =3D 32; yylval->rvalue.signedness =3D UNSIGNED; return REG; } +"VSP" { yylval->rvalue.type =3D REGISTER; + yylval->rvalue.reg.type =3D GENERAL_PURPOSE; + yylval->rvalue.reg.id =3D HEX_REG_VSP; + yylval->rvalue.reg.bit_width =3D 32; + yylval->rvalue.bit_width =3D 32; + yylval->rvalue.signedness =3D UNSIGNED; + return REG; } "fREAD_FP()" | "FP" { yylval->rvalue.type =3D REGISTER; yylval->rvalue.reg.type =3D GENERAL_PURPOSE; diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef= -parser/idef-parser.y index 3cffafa5b76..b846cf24d01 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -51,7 +51,7 @@ =20 %token IN INAME VAR %token ABS CROUND ROUND CIRCADD COUNTONES INC DEC ANDA ORA XORA PLUSPLUS A= SL -%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK SXT +%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK VFCH= K SXT %token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC LPCFG %token LOAD_CANCEL STORE_CANCEL CANCEL IDENTITY ROTL INSBITS SETBITS EXTRA= NGE %token CAST4_8U FAIL CARRY_FROM_ADD ADDSAT64 LSBNEW @@ -398,6 +398,7 @@ assign_statement : lvalue '=3D' rvalue ; =20 control_statement : frame_check + | vframe_check | cancel_statement | if_statement | for_statement @@ -409,6 +410,12 @@ frame_check : FCHK '(' rvalue ',' rvalue ')' ';' } ; =20 +vframe_check : VFCHK '(' rvalue ',' rvalue ')' ';' + { + gen_vframecheck(c, &@1, &$3); + } + ; + cancel_statement : LOAD_CANCEL { gen_load_cancel(c, &@1); diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index c590ed4f959..ed1de09a40c 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -409,6 +409,11 @@ DEF_EXT_SPACE(EXTRACTW, ICLASS_LD" 001 0 000 iiiii P= P0iiiii 001iiiii") DEF_ENC32(Y2_dcfetchbo, "10010100000sssssPP000iiiiiiiiiii") DEF_ENC32(Y4_dcfetch_multi,"10010100000sssssPP001ttttt------") DEF_ENC32(Y2_dcfetchbo_nt,"10010100000sssssPP10-iiiiiiiiiii") +DEF_ENC32(V2_vallocframe_imm,"01100000100-----PP001----iiiiiii") +DEF_ENC32(V2_vallocframe_reg,"01100000100sssssPP010-----------") +DEF_ENC32(V2_vdeallocframe_imm,"01101010100-----PP001----iiiiiii") +DEF_ENC32(V2_vdeallocframe_reg,"01101001010sssssPP010-----------") +DEF_ENC32(J2_trap2,"0101010011------PP-iiiii---iii--") =20 =20 =20 diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/= system.idef index 9c4897a2eee..80fa0cd5618 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -48,6 +48,9 @@ Q6INSN(J2_trap1,"trap1(Rx32,#u8)",ATTRIBS(A_COF,A_NOTE_NO= PACKET,A_RESTRICT_NOPAC fVIRTINSN_SPSWAP(uiV,RxV); }) =20 +Q6INSN(J2_trap2,"trap2(#u8)",ATTRIBS(A_COF,A_RESTRICT_NOPACKET), + "Trap to Operating System", { fTRAP(2,uiV); }) + Q6INSN(J2_pause,"pause(#u8)",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPA= CKET), "Enter low-power state for #u8 cycles",{fPAUSE(uiV);}) =20 @@ -241,6 +244,11 @@ Q6INSN(Y6_dmresume,"dmresume(Rs32)",ATTRIBS(A_NOTE_NOP= ACKET,A_RESTRICT_NOPACKET, =20 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,= A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_RI(RsV,uiV);= fDCFETCH(EA);}) Q6INSN(Y2_dcfetchbo_nt,"dcfetch(Rs32+#u11:3):nt",ATTRIBS(A_NA_NT,A_RESTRIC= T_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fE= A_RI(RsV,uiV); fDCFETCH(EA);}) + +Q6INSN(V2_vallocframe_imm,"vallocframe(#u7:0)",ATTRIBS(A_RESTRICT_NOPACKET= ),"Allocate vector stack frame",{ fVFRAMECHECK(VSP - (uiV << 11), VSP); }) +Q6INSN(V2_vallocframe_reg,"vallocframe(Rs32)",ATTRIBS(A_RESTRICT_NOPACKET)= ,"Allocate vector stack frame",{ fVFRAMECHECK(VSP - (RsV << 11), VSP); }) +Q6INSN(V2_vdeallocframe_imm,"vdeallocframe(#u7:0)",ATTRIBS(A_RESTRICT_NOPA= CKET),"Deallocate vector stack frame",{ VSP =3D VSP + (uiV << 11); }) +Q6INSN(V2_vdeallocframe_reg,"vdeallocframe(Rs32)",ATTRIBS(A_RESTRICT_NOPAC= KET),"Deallocate vector stack frame",{ VSP =3D VSP + (RsV << 11); }) Q6INSN(Y4_dcfetch_multi,"dcfetch_multi(Rs32,Rt32)",ATTRIBS(A_RESTRICT_PREF= ERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),"Data Cache Prefetch",{fEA_REG(= RsV); fDCFETCH_MULTI(EA,fEXTRACTU_BITS(RtV,10,0));}) Q6INSN(Y2_dckill,"dckill",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RES= TRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),"Data Cache Inva= lidate",{fDCKILL();}) =20 --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622769275158500 Bit 7 of L4_loadw_phys is valid through v81 but reserved starting with v83. Decode it as a legacy don't-care bit, then reject it for v83 and later. Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/decode.h | 2 ++ target/hexagon/decode.c | 19 +++++++++++++++++++ target/hexagon/printinsn.c | 3 ++- 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h index d4b049961ed..1e1e339b08a 100644 --- a/target/hexagon/decode.h +++ b/target/hexagon/decode.h @@ -31,5 +31,7 @@ int decode_packet(DisasContext *ctx, int max_words, const= uint32_t *words, Packet *pkt, bool disas_only); =20 bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def); +bool encoding_supported(uint16_t opcode, uint32_t encoding, + const HexagonCPUDef *hex_def); =20 #endif diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index a28bf9ce9fe..35d741ce864 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -692,6 +692,22 @@ bool opcode_supported(uint16_t opcode, const HexagonCP= UDef *hex_def) return true; } =20 +/* + * Some encodings of an otherwise supported opcode are reserved on newer + * versions. HEX_VER_ANY (used when only disassembling) accepts everythin= g. + */ +bool encoding_supported(uint16_t opcode, uint32_t encoding, + const HexagonCPUDef *hex_def) +{ + /* Bit 7 of L4_loadw_phys became reserved in v83. */ + if (hex_def->hex_version !=3D HEX_VER_ANY && + hex_def->hex_version >=3D HEX_VER_V83 && + opcode =3D=3D L4_loadw_phys && (encoding & 0x80)) { + return false; + } + return true; +} + /* * decode_packet * Decodes packet with given words @@ -722,6 +738,9 @@ int decode_packet(DisasContext *ctx, int max_words, con= st uint32_t *words, /* Invalid instruction encoding */ return 0; } + if (!encoding_supported(insn->opcode, encoding32, ctx->hex_def)) { + return 0; + } /* * If we saw an extender, mark next word extended so immediate * decode works diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c index 023ea12dba5..cdb9dcd7de9 100644 --- a/target/hexagon/printinsn.c +++ b/target/hexagon/printinsn.c @@ -171,7 +171,8 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uin= t32_t *words, } =20 g_string_append(buf, "\t"); - if (opcode_supported(pkt->insn[i].opcode, cfg->hex_def)) { + if (opcode_supported(pkt->insn[i].opcode, cfg->hex_def) && + encoding_supported(pkt->insn[i].opcode, words[i], cfg->hex_def= )) { snprintinsn(buf, &(pkt->insn[i])); } else { g_string_append(buf, ""); --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792622807; cv=none; d=zohomail.com; s=zohoarc; b=JomTA7EWvJMlKjV+xLN9rGkXcuhK9qZ7CaCW87qeF+FOVNdKrBeuFKKlYd6dZiBhOqkiVMlVQsDm160R4Ka28po1MdeN054tzMZk1nVRt5qdSjkpSxyA9/YwuE4zmF8YmKiAOIRJsMN4Y0TehnziP5aTD68Cu2CMNJZGA95+1VI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792622807; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EXMlL0CQEUWxaU5cW50xDxNN5MRk9w89xRLd3/Rde3M=; b=V0YdyfQ3We/tmcQJFHPHYppFAS5AkG22Qg05wt4YWVEDOgylgdb2C60/gGxD9OsyFBZq2cyAbfqfrApl91Mb5lhEI0lxnV5dzq7bfEntIoIjwLO91Tt4ua1+Ydka95HJnKZ4Ji2U4dhZ+U+sRZnK1tJOFiTmlYet/N7bvmVUS84= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792622807507673.2078189658985; Wed, 21 Oct 2026 15:46:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJf3I-00014L-Eb; Wed, 21 Oct 2026 18:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJf34-00010J-Uy for qemu-devel@nongnu.org; Wed, 21 Oct 2026 18:44:43 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJf32-0002ZP-KO for qemu-devel@nongnu.org; Wed, 21 Oct 2026 18:44:41 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKeNlw1154640 for ; Wed, 21 Oct 2026 22:44:39 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hf0cv1g16-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 22:44:39 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-35cbea41088so2207073eec.1 for ; Wed, 21 Oct 2026 15:44:39 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622807622158500 gen_callr wrote the link register before consuming the target, so "callr r31" jumped to the new return address instead of the old LR value. Copy the target to a temporary first. Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/genptr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index d234f994f46..f1d0529d0c8 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1059,6 +1059,8 @@ static void gen_call(DisasContext *ctx, int pc_off) static void gen_callr(DisasContext *ctx, TCGv new_pc) { TCGv lr =3D get_result_gpr(ctx, HEX_REG_LR); + + new_pc =3D gen_unalias_gpr_src(new_pc, lr); tcg_gen_movi_tl(lr, ctx->next_PC); gen_write_new_pc_addr(ctx, new_pc, TCG_COND_ALWAYS, NULL); } --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792622755; cv=none; d=zohomail.com; s=zohoarc; b=nPL3KyvNFwPSThCzM3EZEHIbNqcNQwBRaFccoIAFit8djqpNL8YnKY/2TXTMdJlbyeuHTjTGtD03YJxxvuz+X04kT9OX46sXOmih5xob3STW0zKaDnVbSrwTG3F/qnVzarhWM4ZfUz+zLP9K9+QqoKQz7NJXHhBBMTRa5bXiAuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792622755; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9zkb9QAoIgmf4cMeJN8onn7XBZA35tLSIJPkOEx/HbU=; b=ZEqwLthnYN1PAFAk+4EGVHM4N5ON2bOeSLod1B++CMRN7V2B8HKiNLe31T87k0FnphHBI+dRR51FFF1c8cOskJea9PnfevWNBPEq+r1vB6lfobQYGaAkY0ctwiWz83DKsFsls1Jxbpz5Re8ZH8yzUMKsRzCbx5l+tw3v4GsTDdc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179262275529825.502864443918384; Wed, 21 Oct 2026 15:45:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJf3R-0001JS-5x; Wed, 21 Oct 2026 18:45:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJf3A-00011B-Cc for qemu-devel@nongnu.org; Wed, 21 Oct 2026 18:44:48 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJf36-0002Zn-IL for qemu-devel@nongnu.org; Wed, 21 Oct 2026 18:44:48 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKeMOv1723127 for ; Wed, 21 Oct 2026 22:44:43 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hetj4b2xx-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 22:44:43 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-33c35f5ca6cso2259853eec.1 for ; Wed, 21 Oct 2026 15:44:43 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622756986158500 Implement v83 restricted indirect-control-flow instructions and validate their targets. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- target/hexagon/cpu.h | 3 ++ target/hexagon/cpu_bits.h | 1 + target/hexagon/gen_tcg.h | 62 +++++++++++++++++++++- target/hexagon/gen_tcg_sys.h | 6 +++ target/hexagon/macros.h | 12 +++++ target/hexagon/translate.h | 3 ++ target/hexagon/attribs_def.h.inc | 1 + target/hexagon/reg_fields_def.h.inc | 1 + linux-user/hexagon/cpu_loop.c | 9 ++++ linux-user/hexagon/signal.c | 8 +++ target/hexagon/cpu.c | 6 +++ target/hexagon/genptr.c | 36 +++++++++++++ target/hexagon/hex_interrupts.c | 3 ++ target/hexagon/hexswi.c | 11 ++++ target/hexagon/machine.c | 3 +- target/hexagon/translate.c | 59 ++++++++++++++++++++ target/hexagon/tag_rev_info.c.inc | 20 +++++++ target/hexagon/imported/alu.idef | 3 ++ target/hexagon/imported/branch.idef | 38 +++++++++++++ target/hexagon/imported/encode_pp.def | 18 ++++++- target/hexagon/imported/encode_subinsn.def | 1 + target/hexagon/imported/ldst.idef | 2 + target/hexagon/imported/subinsns.idef | 2 + target/hexagon/imported/system.idef | 2 +- 24 files changed, 306 insertions(+), 4 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c1a944920e8..b1a092eb42b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -132,6 +132,9 @@ typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; uint32_t cause_code; + uint32_t cfi_active; + uint32_t cfi_active_log; + uint32_t cfi_updated; =20 /* For comparing with LLDB on target - see adjust_stack_ptrs function = */ target_ulong last_pc_dumped; diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 6a800525348..3104b497be7 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -72,6 +72,7 @@ enum hex_cause { HEX_CAUSE_TRAP1 =3D 0x009, HEX_CAUSE_FETCH_NO_XPAGE =3D 0x011, HEX_CAUSE_FETCH_NO_UPAGE =3D 0x012, + HEX_CAUSE_CFI_VIOLATION =3D 0x014, HEX_CAUSE_INVALID_PACKET =3D 0x015, HEX_CAUSE_INVALID_OPCODE =3D 0x015, /* alias: same cause as INVALID_PA= CKET */ HEX_CAUSE_NO_COPROC_ENABLE =3D 0x016, diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 690bf20e6b2..f040288e81f 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -589,6 +589,9 @@ #define fGEN_TCG_S2_allocframe(SHORTCODE) \ gen_allocframe(ctx, RxV, uiV) =20 +#define fGEN_TCG_S2_allocframe_rb(SHORTCODE) \ + fGEN_TCG_S2_allocframe(SHORTCODE) + /* sub-instruction version (no RxV, so handle it manually) */ #define fGEN_TCG_SS2_allocframe(SHORTCODE) \ do { \ @@ -597,6 +600,9 @@ gen_allocframe(ctx, r29, uiV); \ } while (0) =20 +#define fGEN_TCG_SS2_allocframe_rb(SHORTCODE) \ + fGEN_TCG_SS2_allocframe(SHORTCODE) + /* * Rdd32 =3D deallocframe(Rs32):raw * RddV =3D=3D r31:30 @@ -777,6 +783,16 @@ gen_callr(ctx, RsV) #define fGEN_TCG_J2_callrh(SHORTCODE) \ gen_callr(ctx, RsV) +#define fGEN_TCG_J2_callr_rb(SHORTCODE) \ + do { \ + gen_callr(ctx, RsV); \ + gen_set_cfi(ctx); \ + } while (0) +#define fGEN_TCG_J2_callrh_rb(SHORTCODE) \ + do { \ + gen_callr(ctx, RsV); \ + gen_set_cfi(ctx); \ + } while (0) =20 #define fGEN_TCG_J2_callt(SHORTCODE) \ gen_cond_call(ctx, PuV, TCG_COND_TSTEQ, riV) @@ -786,6 +802,16 @@ gen_cond_callr(ctx, TCG_COND_TSTEQ, PuV, RsV) #define fGEN_TCG_J2_callrf(SHORTCODE) \ gen_cond_callr(ctx, TCG_COND_TSTNE, PuV, RsV) +#define fGEN_TCG_J2_callrt_rb(SHORTCODE) \ + do { \ + gen_cond_callr(ctx, TCG_COND_TSTEQ, PuV, RsV); \ + gen_cond_set_cfi(ctx, true, PuV, -1); \ + } while (0) +#define fGEN_TCG_J2_callrf_rb(SHORTCODE) \ + do { \ + gen_cond_callr(ctx, TCG_COND_TSTNE, PuV, RsV); \ + gen_cond_set_cfi(ctx, false, PuV, -1); \ + } while (0) =20 #define fGEN_TCG_J2_loop0r(SHORTCODE) \ gen_loop0r(ctx, RsV, riV) @@ -1006,6 +1032,39 @@ gen_jumpr(ctx, RsV) #define fGEN_TCG_J2_jumprh(SHORTCODE) \ gen_jumpr(ctx, RsV) +#define fGEN_TCG_J2_jumpr_rb(SHORTCODE) \ + do { \ + gen_jumpr(ctx, RsV); \ + gen_set_cfi_for_target(ctx, RsN); \ + } while (0) +#define fGEN_TCG_J2_jumprh_rb(SHORTCODE) \ + fGEN_TCG_J2_jumpr_rb(SHORTCODE) +#define fGEN_TCG_J2_jumprt_rb(SHORTCODE) \ + do { \ + gen_cond_jumpr(ctx, RsV, TCG_COND_TSTEQ, PuV); \ + gen_cond_set_cfi(ctx, true, PuV, RsN); \ + } while (0) +#define fGEN_TCG_J2_jumprf_rb(SHORTCODE) \ + do { \ + gen_cond_jumpr(ctx, RsV, TCG_COND_TSTNE, PuV); \ + gen_cond_set_cfi(ctx, false, PuV, RsN); \ + } while (0) +#define fGEN_TCG_J2_jumprtpt_rb(SHORTCODE) fGEN_TCG_J2_jumprt_rb(SHORTCODE) +#define fGEN_TCG_J2_jumprfpt_rb(SHORTCODE) fGEN_TCG_J2_jumprf_rb(SHORTCODE) +#define fGEN_TCG_J2_jumprtnew_rb(SHORTCODE) \ + do { \ + gen_cond_jumpr(ctx, RsV, TCG_COND_TSTEQ, PuN); \ + gen_cond_set_cfi(ctx, true, PuN, RsN); \ + } while (0) +#define fGEN_TCG_J2_jumprfnew_rb(SHORTCODE) \ + do { \ + gen_cond_jumpr(ctx, RsV, TCG_COND_TSTNE, PuN); \ + gen_cond_set_cfi(ctx, false, PuN, RsN); \ + } while (0) +#define fGEN_TCG_J2_jumprtnewpt_rb(SHORTCODE) \ + fGEN_TCG_J2_jumprtnew_rb(SHORTCODE) +#define fGEN_TCG_J2_jumprfnewpt_rb(SHORTCODE) \ + fGEN_TCG_J2_jumprfnew_rb(SHORTCODE) #define fGEN_TCG_J4_jumpseti(SHORTCODE) \ do { \ tcg_gen_movi_tl(RdV, UiV); \ @@ -1195,7 +1254,7 @@ RdV, tcg_constant_tl(0)); \ } while (0) =20 -#define fGEN_TCG_Y2_break(SHORTCODE) +#define fGEN_TCG_Y2_break(SHORTCODE) gen_reset_cfi(ctx) #define fGEN_TCG_J2_unpause(SHORTCODE) =20 #ifdef CONFIG_USER_ONLY @@ -1477,4 +1536,5 @@ #endif =20 #define fGEN_TCG_A2_nop(SHORTCODE) do { } while (0) +#define fGEN_TCG_A2_nop_rb(SHORTCODE) gen_reset_cfi(ctx) #define fGEN_TCG_SA1_setin1(SHORTCODE) tcg_gen_movi_tl(RdV, -1) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 3760b671adf..a76ac8ad391 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/target/hexagon/gen_tcg_sys.h @@ -131,11 +131,17 @@ */ #define fGEN_TCG_J2_rte(SHORTCODE) \ do { \ + TCGv_i32 cfi =3D tcg_temp_new_i32(); \ TCGv_i32 new_ssr =3D tcg_temp_new_i32(); \ + tcg_gen_extract_i32(cfi, hex_t_sreg[HEX_SREG_SSR], \ + reg_field_info[SSR_CFI].offset, 1); \ + fSET_CFI(cfi); \ tcg_gen_deposit_tl(new_ssr, hex_t_sreg[HEX_SREG_SSR], \ tcg_constant_tl(0), \ reg_field_info[SSR_EX].offset, \ reg_field_info[SSR_EX].width); \ + tcg_gen_deposit_tl(new_ssr, new_ssr, tcg_constant_tl(0), \ + reg_field_info[SSR_CFI].offset, 1); \ gen_log_sreg_write(ctx, HEX_SREG_SSR, new_ssr); \ gen_jumpr(ctx, hex_t_sreg[HEX_SREG_ELR]); \ } while (0) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index a5b9c24c6bb..195bd6a0c9c 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -423,6 +423,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) #define fCAST8S_16S(A) (int128_exts64(A)) #define fCAST16S_8S(A) (int128_getlo(A)) =20 +#define fSET_CFI(CFI_VALUE) \ + do { \ + TCGLabel *skip_cfi_reset =3D gen_new_label(); \ + tcg_gen_movcond_i32(TCG_COND_NE, hex_cfi_active_log, hex_cfi_updat= ed, \ + tcg_constant_i32(1), tcg_constant_i32(0), \ + hex_cfi_active_log); \ + tcg_gen_movi_i32(hex_cfi_updated, 1); \ + tcg_gen_brcondi_i32(TCG_COND_EQ, CFI_VALUE, 0, skip_cfi_reset); \ + tcg_gen_movi_i32(hex_cfi_active_log, 1); \ + gen_set_label(skip_cfi_reset); \ + } while (0) + #ifdef QEMU_GENERATE #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) #define fEA_RRs(REG, REG2, SCALE) \ diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 47ca5e8ae01..dc23d122ab0 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -364,6 +364,9 @@ extern TCGv_i64 hex_llsc_val_i64; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; +extern TCGv_i32 hex_cfi_active; +extern TCGv_i32 hex_cfi_active_log; +extern TCGv_i32 hex_cfi_updated; void gen_precise_exception(int cause, uint32_t pc); #ifdef CONFIG_USER_ONLY #define hex_hvx_ptr tcg_env diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 8deef8e4cfb..96ad1fd2f8e 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -200,6 +200,7 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift res= ource.", "", "") /* Restrictions to make note of */ DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", ""= , "") DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", = "") +DEF_ATTRIB(RESTRICT_TARGET, "Restricted branch target instruction", "", "") =20 /* HVX IEEE FP extension attributes */ DEF_ATTRIB(HVX_IEEE_FP, "HVX IEEE FP extension instruction", "", "") diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_field= s_def.h.inc index 553f6ffffbc..21babbbb982 100644 --- a/target/hexagon/reg_fields_def.h.inc +++ b/target/hexagon/reg_fields_def.h.inc @@ -95,6 +95,7 @@ DEF_REG_FIELD(SYSCFG_L2GCA, 31, 1) /* SSR fields */ DEF_REG_FIELD(SSR_CAUSE, 0, 8) DEF_REG_FIELD(SSR_ASID, 8, 7) +DEF_REG_FIELD(SSR_CFI, 15, 1) DEF_REG_FIELD(SSR_UM, 16, 1) DEF_REG_FIELD(SSR_EX, 17, 1) DEF_REG_FIELD(SSR_IE, 18, 1) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 22570a12648..32249f27b93 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -49,6 +49,9 @@ void cpu_loop(CPUHexagonState *env) break; case HEX_EVENT_TRAP0: case HEX_EVENT_TRAP2: + /* Exception entry ends any pending restricted-branch check. */ + env->cfi_active =3D 0; + env->cfi_updated =3D 0; syscallnum =3D env->gpr[6]; env->gpr[HEX_REG_PC] +=3D 4; ret =3D do_syscall(env, @@ -78,6 +81,12 @@ void cpu_loop(CPUHexagonState *env) force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_BNDERR, env->gpr[HEX_REG_PC]); break; + case HEX_CAUSE_CFI_VIOLATION: + env->cfi_active =3D 0; + env->cfi_updated =3D 0; + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, + env->gpr[HEX_REG_PC]); + break; case HEX_CAUSE_PRIV_USER_NO_GINSN: case HEX_CAUSE_PRIV_USER_NO_SINSN: case HEX_CAUSE_INVALID_PACKET: diff --git a/linux-user/hexagon/signal.c b/linux-user/hexagon/signal.c index 183ecfaa19a..f8ba4a6b478 100644 --- a/linux-user/hexagon/signal.c +++ b/linux-user/hexagon/signal.c @@ -106,6 +106,10 @@ static void setup_sigcontext(struct target_sigcontext = *sc, CPUHexagonState *env) =20 __put_user(env->gpr[HEX_REG_CS0], &sc->sc_regs.cs0); __put_user(env->gpr[HEX_REG_CS1], &sc->sc_regs.cs1); + /* Preserve a pending restricted-branch landing pad across the signal.= */ + __put_user(env->cfi_active, &sc->sc_regs.pad1); + env->cfi_active =3D 0; + env->cfi_updated =3D 0; } =20 static void setup_ucontext(struct target_ucontext *uc, @@ -176,6 +180,7 @@ static void restore_sigcontext(CPUHexagonState *env, struct target_sigcontext *sc) { abi_ulong preds; + abi_ulong cfi; =20 for (int i =3D 0; i < 32; i++) { __get_user(env->gpr[HEX_REG_R00 + i], &sc->sc_regs.gpr[i]); @@ -199,6 +204,9 @@ static void restore_sigcontext(CPUHexagonState *env, =20 __get_user(env->gpr[HEX_REG_CS0], &sc->sc_regs.cs0); __get_user(env->gpr[HEX_REG_CS1], &sc->sc_regs.cs1); + __get_user(cfi, &sc->sc_regs.pad1); + env->cfi_active =3D cfi & 1; + env->cfi_updated =3D 0; } =20 static void restore_ucontext(CPUHexagonState *env, struct target_ucontext = *uc) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f4f733cc251..5a941899883 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -414,6 +414,9 @@ void hexagon_cpu_soft_reset(CPUHexagonState *env) =20 BQL_LOCK_GUARD(); env->llsc_addr =3D ~0; + env->cfi_active =3D 0; + env->cfi_active_log =3D 0; + env->cfi_updated =3D 0; env->t_sreg[HEX_SREG_SSR] =3D 0; hexagon_ssr_set_cause(env, HEX_CAUSE_RESET); =20 @@ -451,6 +454,9 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status); =20 env->llsc_addr =3D ~0; + env->cfi_active =3D 0; + env->cfi_active_log =3D 0; + env->cfi_updated =3D 0; #ifndef CONFIG_USER_ONLY memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS); memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS); diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index f1d0529d0c8..7ef36e336fa 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1085,6 +1085,42 @@ static void gen_cond_callr(DisasContext *ctx, gen_set_label(skip); } =20 +static void gen_set_cfi(DisasContext *ctx) +{ + fSET_CFI(tcg_constant_i32(1)); +} + +static void gen_reset_cfi(DisasContext *ctx) +{ + fSET_CFI(tcg_constant_i32(0)); +} + +/* Indirect transfers through LR are returns, which do not set the CFI sta= te */ +static void gen_set_cfi_for_target(DisasContext *ctx, int rs_num) +{ + if (rs_num =3D=3D HEX_REG_LR) { + gen_reset_cfi(ctx); + } else { + gen_set_cfi(ctx); + } +} + +/* + * Update the CFI state if the predicate (true if @sense, else false) hold= s. + * @rs_num is the jump target register, or -1 for calls. + */ +static void gen_cond_set_cfi(DisasContext *ctx, bool sense, TCGv pred, + int rs_num) +{ + TCGv lsb =3D tcg_temp_new(); + TCGLabel *skip =3D gen_new_label(); + + tcg_gen_andi_tl(lsb, pred, 1); + tcg_gen_brcondi_tl(sense ? TCG_COND_EQ : TCG_COND_NE, lsb, 0, skip); + gen_set_cfi_for_target(ctx, rs_num); + gen_set_label(skip); +} + #ifndef CONFIG_HEXAGON_IDEF_PARSER /* frame =3D ((LR << 32) | FP) ^ (FRAMEKEY << 32)) */ static TCGv_i64 gen_frame_scramble(void) diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupt= s.c index 03e1f28da9b..81e7d016c3d 100644 --- a/target/hexagon/hex_interrupts.c +++ b/target/hexagon/hex_interrupts.c @@ -48,6 +48,7 @@ static void set_ssr_ex_cause(CPUHexagonState *env, int ex= , uint32_t cause) old =3D env->t_sreg[HEX_SREG_SSR]; SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, ex); SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause); + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CFI, env->cfi_active); new =3D env->t_sreg[HEX_SREG_SSR]; hexagon_modify_ssr(env, new, old); } @@ -373,6 +374,8 @@ static void hex_accept_int(CPUHexagonState *env, int in= t_num) env->threadId); =20 set_ssr_ex_cause(env, 1, HEX_CAUSE_INT0 | int_num); + env->cfi_active =3D 0; + env->cfi_updated =3D 0; set_elr(env, elr); env->gpr[HEX_REG_PC] =3D evb | (cs->exception_index << 2); } diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index 5783781195e..11472a9f1dd 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -786,7 +786,17 @@ void hexagon_cpu_do_interrupt(CPUState *cs) env->llsc_addr =3D ~0; =20 ssr =3D env->t_sreg[HEX_SREG_SSR]; + if (GET_SSR_FIELD(SSR_EX, ssr) =3D=3D 0) { + SET_SSR_FIELD(env, SSR_CFI, env->cfi_active); + } + env->cfi_active =3D 0; + env->cfi_updated =3D 0; + if (GET_SSR_FIELD(SSR_EX, ssr) =3D=3D 1) { + /* + * Double exception: keep the SSR.CFI value saved by the first + * exception, which a later rte would need to restore. + */ if (cpu->globalregs) { hexagon_globalreg_write(cpu->globalregs, HEX_SREG_DIAG, env->cause_code, env->threadId); @@ -891,6 +901,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs) switch (env->cause_code) { case HEX_CAUSE_FETCH_NO_XPAGE: case HEX_CAUSE_FETCH_NO_UPAGE: + case HEX_CAUSE_CFI_VIOLATION: case HEX_CAUSE_PRIV_NO_READ: case HEX_CAUSE_PRIV_NO_UREAD: case HEX_CAUSE_PRIV_NO_WRITE: diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index 36fee33d333..6a41551d8fa 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -21,7 +21,7 @@ static int hexagon_cpu_post_load(void *opaque, int versio= n_id) =20 const VMStateDescription vmstate_hexagon_cpu =3D { .name =3D "cpu", - .version_id =3D 2, + .version_id =3D 3, .minimum_version_id =3D 2, .post_load =3D hexagon_cpu_post_load, .fields =3D (const VMStateField[]) { @@ -37,6 +37,7 @@ const VMStateDescription vmstate_hexagon_cpu =3D { VMSTATE_UINT32(env.cause_code, HexagonCPU), VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_UINT32(env.imprecise_exception, HexagonCPU), + VMSTATE_UINT32_V(env.cfi_active, HexagonCPU, 3), =20 VMSTATE_END_OF_LIST() }, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 6e7c2f32f41..a0806bc4394 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -68,6 +68,9 @@ TCGv hex_imprecise_exception; TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; +TCGv_i32 hex_cfi_active; +TCGv_i32 hex_cfi_active_log; +TCGv_i32 hex_cfi_updated; #ifndef CONFIG_USER_ONLY TCGv_ptr hex_hvx_ptr; #endif @@ -442,6 +445,45 @@ static void mark_implicit_reg_write(DisasContext *ctx,= int attrib, int rnum) } } =20 +static bool pkt_legal_cfi_target(const Packet *pkt) +{ + int i; + + for (i =3D 0; i < pkt->num_insns; i++) { + if (GET_ATTRIB(pkt->insn[i].opcode, A_RESTRICT_TARGET) || + pkt->insn[i].opcode =3D=3D Y2_break || + (pkt->insn[i].opcode =3D=3D J2_trap0 && + pkt->insn[i].immed[0] =3D=3D 0xdb)) { + return true; + } + } + return false; +} + +static void gen_cfi_check(DisasContext *ctx) +{ + TCGLabel *skip; + + if (ctx->hex_def->hex_version < HEX_VER_V83 || + pkt_legal_cfi_target(&ctx->pkt)) { + return; + } + + skip =3D gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_EQ, hex_cfi_active, 0, skip); + gen_precise_exception(HEX_CAUSE_CFI_VIOLATION, ctx->pkt.pc); + gen_set_label(skip); +} + +static void gen_cfi_target_update(DisasContext *ctx) +{ + if (ctx->hex_def->hex_version >=3D HEX_VER_V83 && + pkt_legal_cfi_target(&ctx->pkt)) { + tcg_gen_movi_i32(hex_cfi_active_log, 0); + tcg_gen_movi_i32(hex_cfi_updated, 1); + } +} + static void mark_implicit_usr_write(DisasContext *ctx, int attrib) { uint16_t opcode =3D ctx->insn->opcode; @@ -710,6 +752,9 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); } =20 + gen_cfi_target_update(ctx); + gen_cfi_check(ctx); + /* Preload the predicated registers into get_result_gpr(ctx, i) */ if (ctx->need_commit && !bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { @@ -1231,6 +1276,14 @@ static void gen_commit_packet(DisasContext *ctx) gen_helper_probe_pkt_scalar_store_s0(tcg_env, args_tcgv); } =20 + if (ctx->hex_def->hex_version >=3D HEX_VER_V83) { + /* A restricted branch commits before a faulting store in its pack= et. */ + tcg_gen_movcond_i32(TCG_COND_NE, hex_cfi_active, hex_cfi_updated, + tcg_constant_i32(0), hex_cfi_active_log, + hex_cfi_active); + tcg_gen_movi_i32(hex_cfi_updated, 0); + } + process_store_log(ctx); =20 gen_reg_writes(ctx); @@ -1468,6 +1521,12 @@ void hexagon_translate_init(void) } hex_new_value_usr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); + hex_cfi_active =3D tcg_global_mem_new_i32(tcg_env, + offsetof(CPUHexagonState, cfi_active), "cfi_active"); + hex_cfi_active_log =3D tcg_global_mem_new_i32(tcg_env, + offsetof(CPUHexagonState, cfi_active_log), "cfi_active_log"); + hex_cfi_updated =3D tcg_global_mem_new_i32(tcg_env, + offsetof(CPUHexagonState, cfi_updated), "cfi_updated"); =20 for (i =3D 0; i < NUM_PREGS; i++) { hex_pred[i] =3D tcg_global_mem_new(tcg_env, diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index c2d4886a846..88958b334d8 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -707,6 +707,26 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { .removed =3D HEX_VER_NONE }, [V2_vdeallocframe_reg] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NONE }, + [J2_callr_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_= NONE }, + [J2_callrh_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER= _NONE }, + [J2_callrt_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER= _NONE }, + [J2_callrf_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER= _NONE }, + [J2_jumpr_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_= NONE }, + [J2_jumprh_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER= _NONE }, + [J2_jumprt_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER= _NONE }, + [J2_jumprf_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER= _NONE }, + [J2_jumprtpt_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_V= ER_NONE }, + [J2_jumprfpt_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_V= ER_NONE }, + [J2_jumprtnew_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_= VER_NONE }, + [J2_jumprfnew_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_= VER_NONE }, + [J2_jumprtnewpt_rb] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [J2_jumprfnewpt_rb] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [S2_allocframe_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX= _VER_NONE }, + [SS2_allocframe_rb] =3D { .introduced =3D HEX_VER_V83, + .removed =3D HEX_VER_NONE }, + [A2_nop_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, [J2_trap2] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NON= E }, =20 [Y4_dcfetch_multi] =3D { .introduced =3D HEX_VER_V85, diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu= .idef index b8556769891..7c039ab018a 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -241,6 +241,9 @@ Q6INSN(A2_minup,"Rdd32=3Dminu(Rtt32,Rss32)",ATTRIBS(A_A= RCHV3), Q6INSN(A2_nop,"nop",ATTRIBS(A_IT_NOP), "Nop (32-bit encoding)", fHIDE( { } )) +Q6INSN(A2_nop_rb,"nop_rb",ATTRIBS(A_IT_NOP,A_RESTRICT_TARGET), +"Restricted branch nop target", + fHIDE( { } )) =20 =20 Q6INSN(A4_ext,"immext(#u26:6)",ATTRIBS(A_IT_EXTENDER), diff --git a/target/hexagon/imported/branch.idef b/target/hexagon/imported/= branch.idef index 93e2e375a5c..b943a41a3fc 100644 --- a/target/hexagon/imported/branch.idef +++ b/target/hexagon/imported/branch.idef @@ -37,6 +37,19 @@ Q6INSN(J2_jumpr,"jumpr Rs32",ATTRIBS(A_JINDIR), "indirec= t unconditional jump", Q6INSN(J2_jumprh,"jumprh Rs32",ATTRIBS(A_JINDIR, A_HINTED_COF), "indirect = unconditional jump", {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);}) =20 +Q6INSN(J2_jumpr_rb,"jumpr_rb Rs32",ATTRIBS(A_JINDIR), + "restricted indirect unconditional jump", + {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);}) +Q6INSN(J2_jumprh_rb,"jumprh_rb Rs32",ATTRIBS(A_JINDIR, A_HINTED_COF), + "restricted hinted indirect unconditional jump", + {fJUMPR(RsN,RsV,COF_TYPE_JUMPR);}) + +#define OLDCOND_JUMP_RB(TAG,OPER,OPER2,ATTRIB,DESCR,SEMANTICS) \ +Q6INSN(TAG##t_rb,"if (Pu4) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_SPECULAT= E_STALL(fLSBOLD(PuV),,SPECULATE_NOT_TAKEN,12,0); if (fLSBOLD(PuV)) { SEMANT= ICS; }}) \ +Q6INSN(TAG##f_rb,"if (!Pu4) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_SPECULA= TE_STALL(fLSBOLDNOT(PuV),,SPECULATE_NOT_TAKEN,12,0); if (fLSBOLDNOT(PuV)) {= SEMANTICS; }}) \ +Q6INSN(TAG##tpt_rb,"if (Pu4) "OPER":t "OPER2,ATTRIB,DESCR,{fBRANCH_SPECULA= TE_STALL(fLSBOLD(PuV),,SPECULATE_TAKEN,12,0); if (fLSBOLD(PuV)) { SEMANTICS= ; }}) \ +Q6INSN(TAG##fpt_rb,"if (!Pu4) "OPER":t "OPER2,ATTRIB,DESCR,{fBRANCH_SPECUL= ATE_STALL(fLSBOLDNOT(PuV),,SPECULATE_TAKEN,12,0); if (fLSBOLDNOT(PuV)) { SE= MANTICS; }}) + #define OLDCOND_JUMP(TAG,OPER,OPER2,ATTRIB,DESCR,SEMANTICS) \ Q6INSN(TAG##t,"if (Pu4) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_SPECULATE_S= TALL(fLSBOLD(PuV),,SPECULATE_NOT_TAKEN,12,0); if (fLSBOLD(PuV)) { SEMANTICS= ; }}) \ Q6INSN(TAG##f,"if (!Pu4) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_SPECULATE_= STALL(fLSBOLDNOT(PuV),,SPECULATE_NOT_TAKEN,12,0); if (fLSBOLDNOT(PuV)) { SE= MANTICS; }}) \ @@ -48,6 +61,9 @@ fIMMEXT(riV);fPCALIGN(riV); fBRANCH(fREAD_PC()+riV,COF_TY= PE_JUMP);) =20 OLDCOND_JUMP(J2_jumpr,"jumpr","Rs32",ATTRIBS(A_JINDIROLD),"indirect condit= ional jump", fJUMPR(RsN,RsV,COF_TYPE_JUMPR);) +OLDCOND_JUMP_RB(J2_jumpr,"jumpr_rb","Rs32",ATTRIBS(A_JINDIROLD), + "restricted indirect conditional jump", + fJUMPR(RsN,RsV,COF_TYPE_JUMPR);) =20 #define NEWCOND_JUMP(TAG,OPER,OPER2,ATTRIB,DESCR,SEMANTICS)\ Q6INSN(TAG##tnew,"if (Pu4.new) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_SPEC= ULATE_STALL(fLSBNEW(PuN),, SPECULATE_NOT_TAKEN , 12,0)} {if(fLSBNEW(PuN)){S= EMANTICS;}})\ @@ -61,6 +77,17 @@ fIMMEXT(riV); fPCALIGN(riV); fBRANCH(fREAD_PC()+riV,COF_= TYPE_JUMPNEW);) NEWCOND_JUMP(J2_jumpr,"jumpr","Rs32",ATTRIBS(A_JINDIRNEW,A_ARCHV3),"indire= ct conditional jump", fJUMPR(RsN,RsV,COF_TYPE_JUMPR);) =20 +#define NEWCOND_JUMP_RB(TAG,OPER,OPER2,ATTRIB,DESCR,SEMANTICS) \ +Q6INSN(TAG##tnew_rb,"if (Pu4.new) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_S= PECULATE_STALL(fLSBNEW(PuN),, SPECULATE_NOT_TAKEN , 12,0)} {if(fLSBNEW(PuN)= ){SEMANTICS;}}) \ +Q6INSN(TAG##fnew_rb,"if (!Pu4.new) "OPER":nt "OPER2,ATTRIB,DESCR,{fBRANCH_= SPECULATE_STALL(fLSBNEWNOT(PuN),, SPECULATE_NOT_TAKEN , 12,0)} {if(fLSBNEWN= OT(PuN)){SEMANTICS;}}) \ +Q6INSN(TAG##tnewpt_rb,"if (Pu4.new) "OPER":t "OPER2,ATTRIB,DESCR,{fBRANCH_= SPECULATE_STALL(fLSBNEW(PuN),, SPECULATE_TAKEN , 12,0)} {if(fLSBNEW(PuN)){S= EMANTICS;}}) \ +Q6INSN(TAG##fnewpt_rb,"if (!Pu4.new) "OPER":t "OPER2,ATTRIB,DESCR,{fBRANCH= _SPECULATE_STALL(fLSBNEWNOT(PuN),, SPECULATE_TAKEN , 12,0)} {if(fLSBNEWNOT(= PuN)){SEMANTICS;}}) + +NEWCOND_JUMP_RB(J2_jumpr,"jumpr_rb","Rs32", + ATTRIBS(A_JINDIRNEW,A_ARCHV3), + "restricted indirect conditional jump", + fJUMPR(RsN,RsV,COF_TYPE_JUMPR);) + =20 =20 Q6INSN(J4_hintjumpr,"hintjr(Rs32)",ATTRIBS(A_JINDIR),"hint indirect condit= ional jump", @@ -202,6 +229,17 @@ Q6INSN(J2_callrf,"if (!Pu4) callr Rs32",ATTRIBS(CINDIR= _STD),"indirect conditiona Q6INSN(J2_callrh,"callrh Rs32",ATTRIBS(CINDIR_STD, A_HINTED_COF), "hinted = indirect unconditional call", { fCALLR(RsV); }) =20 +Q6INSN(J2_callr_rb,"callr_rb Rs32",ATTRIBS(CINDIR_STD), + "restricted indirect unconditional call", { fCALLR(RsV); }) +Q6INSN(J2_callrh_rb,"callrh_rb Rs32",ATTRIBS(CINDIR_STD, A_HINTED_COF), + "restricted hinted indirect unconditional call", { fCALLR(RsV); }) +Q6INSN(J2_callrt_rb,"if (Pu4) callr_rb Rs32",ATTRIBS(CINDIR_STD), + "restricted indirect conditional call if true", + {if (fLSBOLD(PuV)) { fCALLR(RsV); }}) +Q6INSN(J2_callrf_rb,"if (!Pu4) callr_rb Rs32",ATTRIBS(CINDIR_STD), + "restricted indirect conditional call if false", + {if (fLSBOLDNOT(PuV)) { fCALLR(RsV); }}) + =20 =20 /*********************************************/ diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index ed1de09a40c..97af0fcb394 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -413,6 +413,20 @@ DEF_ENC32(V2_vallocframe_imm,"01100000100-----PP001---= -iiiiiii") DEF_ENC32(V2_vallocframe_reg,"01100000100sssssPP010-----------") DEF_ENC32(V2_vdeallocframe_imm,"01101010100-----PP001----iiiiiii") DEF_ENC32(V2_vdeallocframe_reg,"01101001010sssssPP010-----------") +DEF_ENC32(J2_callr_rb,"01010000001sssssPP--------------") +DEF_ENC32(J2_callrh_rb,"01010000010sssssPP--------------") +DEF_ENC32(J2_callrt_rb,"01010001100sssssPP----uu--------") +DEF_ENC32(J2_callrf_rb,"01010001101sssssPP----uu--------") +DEF_ENC32(J2_jumpr_rb,"01010010000sssssPP--------------") +DEF_ENC32(J2_jumprh_rb,"01010010010sssssPP--------------") +DEF_ENC32(J2_jumprt_rb,"01010011110sssssPP-00-uu--------") +DEF_ENC32(J2_jumprf_rb,"01010011111sssssPP-00-uu--------") +DEF_ENC32(J2_jumprtpt_rb,"01010011110sssssPP-10-uu--------") +DEF_ENC32(J2_jumprfpt_rb,"01010011111sssssPP-10-uu--------") +DEF_ENC32(J2_jumprtnew_rb,"01010011110sssssPP-01-uu--------") +DEF_ENC32(J2_jumprfnew_rb,"01010011111sssssPP-01-uu--------") +DEF_ENC32(J2_jumprtnewpt_rb,"01010011110sssssPP-11-uu--------") +DEF_ENC32(J2_jumprfnewpt_rb,"01010011111sssssPP-11-uu--------") DEF_ENC32(J2_trap2,"0101010011------PP-iiiii---iii--") =20 =20 @@ -514,6 +528,7 @@ DEF_ENC32(S2_pstorerdf_pi_nt,"10101010110xxxxxPP1ttttt0= iiii1vv") /* x bus/cache */ /* x store/cache */ DEF_ENC32(S2_allocframe, ICLASS_ST" 000 01 00xxxxx PP000iii iiiiiiii") +DEF_ENC32(S2_allocframe_rb,ICLASS_ST" 000 01 00xxxxx PP100iii iiiiiiii") DEF_ENC32(Y5_l2locka, ICLASS_ST" 000 01 11sssss PP1----- ------dd") DEF_ENC32(Y2_dczeroa, ICLASS_ST" 000 01 10sssss PP0----- --------") DEF_ENC32(Y2_dczeroa_nt,"10100000110sssssPP1-------------") @@ -1407,7 +1422,8 @@ DEF_ENC32(C2_cmoveif, ICLASS_ALU2op" 1110 1uu0iiii = PP0iiiii iiiddddd") =20 =20 DEF_FIELDROW_DESC32( ICLASS_ALU2op" 1111 -------- PP------ --------","[= #15] nop") -DEF_ENC32(A2_nop, ICLASS_ALU2op" 1111 -------- PP------ --------") +DEF_ENC32(A2_nop, ICLASS_ALU2op" 1111 0------- PP------ --------") +DEF_ENC32(A2_nop_rb, ICLASS_ALU2op" 1111 1------- PP------ --------") =20 =20 =20 diff --git a/target/hexagon/imported/encode_subinsn.def b/target/hexagon/im= ported/encode_subinsn.def index 742fb50efb6..4ff3e95a253 100644 --- a/target/hexagon/imported/encode_subinsn.def +++ b/target/hexagon/imported/encode_subinsn.def @@ -71,6 +71,7 @@ DEF_ENC_SUBINSN(SS2_storebi0, SUBINSN_S2, "100 10ssssi= iii") DEF_ENC_SUBINSN(SS2_storebi1, SUBINSN_S2, "100 11ssssiiii") =20 DEF_ENC_SUBINSN(SS2_allocframe, SUBINSN_S2, "111 0iiiii----") +DEF_ENC_SUBINSN(SS2_allocframe_rb,SUBINSN_S2, "111 1iiiii----") =20 =20 =20 diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 48cda64e0b0..1e176ccc464 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -135,6 +135,8 @@ STD_ST_AMODES(storerhnew, "Nt8.new", "memh","Store Half= integer",ATTRIBS(A_REGWR =20 Q6INSN(S2_allocframe,"allocframe(Rx32,#u11:3):raw", ATTRIBS(A_REGWRSIZE_8B= ,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY), "Allocate stack frame", { fEA_RI(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << = 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA); RxV = =3D EA-uiV; }) +Q6INSN(S2_allocframe_rb,"allocframe_rb(Rx32,#u11:3):raw", ATTRIBS(A_REGWRS= IZE_8B,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY,A_RESTRICT_TARGET), "Alloc= ate stack frame", +{ fEA_RI(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << = 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA); RxV = =3D EA-uiV; }) #define A_RETURN A_RESTRICT_COF_MAX1,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOSLO= T1_STORE,A_RET_TYPE,A_DEALLOCRET =20 /**** Load Acquire Store Release Instructions****/ diff --git a/target/hexagon/imported/subinsns.idef b/target/hexagon/importe= d/subinsns.idef index be0ae8779da..a4be385f588 100644 --- a/target/hexagon/imported/subinsns.idef +++ b/target/hexagon/imported/subinsns.idef @@ -147,3 +147,5 @@ Q6INSN(SS2_storebi1, "memb(Rs16+#u4:0)=3D#1", ATTRIBS= (A_MEMSIZE_1B,A_STORE,A_SUB =20 Q6INSN(SS2_allocframe,"allocframe(#u5:3)", ATTRIBS(A_REGWRSIZE_8B,A_SUBINS= N,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY), "Allocate stack frame", { fEA_RI(fREAD_SP(),-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_L= R()) << 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA= ); fWRITE_SP(EA-uiV); }) +Q6INSN(SS2_allocframe_rb,"allocframe_rb(#u5:3)", ATTRIBS(A_REGWRSIZE_8B,A_= SUBINSN,A_MEMSIZE_8B,A_STORE,A_RESTRICT_SLOT0ONLY,A_RESTRICT_TARGET), "Allo= cate stack frame", +{ fEA_RI(fREAD_SP(),-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_L= R()) << 32) | fCAST4_4u(fREAD_FP()))); fWRITE_FP(EA); fFRAMECHECK(EA-uiV,EA= ); fWRITE_SP(EA-uiV); }) diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/= system.idef index 80fa0cd5618..f279c52b7d6 100644 --- a/target/hexagon/imported/system.idef +++ b/target/hexagon/imported/system.idef @@ -48,7 +48,7 @@ Q6INSN(J2_trap1,"trap1(Rx32,#u8)",ATTRIBS(A_COF,A_NOTE_NO= PACKET,A_RESTRICT_NOPAC fVIRTINSN_SPSWAP(uiV,RxV); }) =20 -Q6INSN(J2_trap2,"trap2(#u8)",ATTRIBS(A_COF,A_RESTRICT_NOPACKET), +Q6INSN(J2_trap2,"trap2(#u8)",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPA= CKET), "Trap to Operating System", { fTRAP(2,uiV); }) =20 Q6INSN(J2_pause,"pause(#u8)",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPA= CKET), --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792622788; cv=none; d=zohomail.com; s=zohoarc; b=V9KZgRGv+VFSLipo6wWu8Aq12x2oQ21yB1C/GkmlQqfyQhY5vFKKIp3dpCZb8vnE3YJHyfx8qHGrMy8rAqvGPNDBsoRRDmSn8Lg+j1B9L5YDjdBUPqIzfflF3s3DPMzc0bmgUSScmnTbYjmeAozat/oQFqCBVnlIUHm1fSDRbFA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792622788; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622789308158500 Implement the v83 two-lane scalar floating-point arithmetic instructions. Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 10 ++++ target/hexagon/helper.h | 5 ++ target/hexagon/op_helper.c | 73 +++++++++++++++++++++++++++ target/hexagon/tag_rev_info.c.inc | 5 ++ target/hexagon/imported/encode_pp.def | 5 ++ target/hexagon/imported/float.idef | 49 ++++++++++++++++++ 6 files changed, 147 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index f040288e81f..e6105622c87 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1393,6 +1393,16 @@ gen_helper_sfadd(RdV, tcg_env, RsV, RtV, pkt_need_commit) #define fGEN_TCG_F2_sfsub(SHORTCODE) \ gen_helper_sfsub(RdV, tcg_env, RsV, RtV, pkt_need_commit) +#define fGEN_TCG_F7_vsfadd(SHORTCODE) \ + gen_helper_vsfadd(RddV, tcg_env, RssV, RttV, pkt_need_commit) +#define fGEN_TCG_F7_vsfsub(SHORTCODE) \ + gen_helper_vsfsub(RddV, tcg_env, RssV, RttV, pkt_need_commit) +#define fGEN_TCG_F7_vsfmpy(SHORTCODE) \ + gen_helper_vsfmpy(RddV, tcg_env, RssV, RttV, pkt_need_commit) +#define fGEN_TCG_F7_vsffma(SHORTCODE) \ + gen_helper_vsffma(RxxV, tcg_env, RxxV, RssV, RttV, pkt_need_commit) +#define fGEN_TCG_F7_vsffms(SHORTCODE) \ + gen_helper_vsffms(RxxV, tcg_env, RxxV, RssV, RttV, pkt_need_commit) #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV, pkt_need_commit) #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 28591417040..00b37f36309 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -60,6 +60,11 @@ DEF_HELPER_3(conv_df2ud_chop, i64, env, f64, i32) DEF_HELPER_3(conv_df2d_chop, s64, env, f64, i32) DEF_HELPER_4(sfadd, f32, env, f32, f32, i32) DEF_HELPER_4(sfsub, f32, env, f32, f32, i32) +DEF_HELPER_4(vsfadd, i64, env, i64, i64, i32) +DEF_HELPER_4(vsfsub, i64, env, i64, i64, i32) +DEF_HELPER_4(vsfmpy, i64, env, i64, i64, i32) +DEF_HELPER_5(vsffma, i64, env, i64, i64, i64, i32) +DEF_HELPER_5(vsffms, i64, env, i64, i64, i64, i32) DEF_HELPER_4(sfcmpeq, s32, env, f32, f32, i32) DEF_HELPER_4(sfcmpgt, s32, env, f32, f32, i32) DEF_HELPER_4(sfcmpge, s32, env, f32, f32, i32) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 9850dc07289..769f56e2422 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -926,6 +926,79 @@ float32 HELPER(sfsub)(CPUHexagonState *env, float32 Rs= V, float32 RtV, return RdV; } =20 +uint64_t HELPER(vsfadd)(CPUHexagonState *env, uint64_t RssV, uint64_t RttV, + uint32_t pkt_need_commit) +{ + uint64_t RddV; + float32 lo, hi; + + arch_fpop_start(env); + lo =3D float32_add(RssV, RttV, &env->fp_status); + hi =3D float32_add(RssV >> 32, RttV >> 32, &env->fp_status); + arch_fpop_end(env, pkt_need_commit); + RddV =3D lo | ((uint64_t)hi << 32); + return RddV; +} + +uint64_t HELPER(vsfsub)(CPUHexagonState *env, uint64_t RssV, uint64_t RttV, + uint32_t pkt_need_commit) +{ + uint64_t RddV; + float32 lo, hi; + + arch_fpop_start(env); + lo =3D float32_sub(RssV, RttV, &env->fp_status); + hi =3D float32_sub(RssV >> 32, RttV >> 32, &env->fp_status); + arch_fpop_end(env, pkt_need_commit); + RddV =3D lo | ((uint64_t)hi << 32); + return RddV; +} + +uint64_t HELPER(vsfmpy)(CPUHexagonState *env, uint64_t RssV, uint64_t RttV, + uint32_t pkt_need_commit) +{ + uint64_t RddV; + float32 lo, hi; + + arch_fpop_start(env); + lo =3D float32_mul(RssV, RttV, &env->fp_status); + hi =3D float32_mul(RssV >> 32, RttV >> 32, &env->fp_status); + arch_fpop_end(env, pkt_need_commit); + RddV =3D lo | ((uint64_t)hi << 32); + return RddV; +} + +uint64_t HELPER(vsffma)(CPUHexagonState *env, uint64_t RxxV, uint64_t RssV, + uint64_t RttV, uint32_t pkt_need_commit) +{ + uint64_t RddV; + float32 lo, hi; + + arch_fpop_start(env); + lo =3D float32_muladd(RssV, RttV, RxxV, 0, &env->fp_status); + hi =3D float32_muladd(RssV >> 32, RttV >> 32, RxxV >> 32, 0, + &env->fp_status); + arch_fpop_end(env, pkt_need_commit); + RddV =3D lo | ((uint64_t)hi << 32); + return RddV; +} + +uint64_t HELPER(vsffms)(CPUHexagonState *env, uint64_t RxxV, uint64_t RssV, + uint64_t RttV, uint32_t pkt_need_commit) +{ + uint64_t RddV; + float32 lo, hi; + + arch_fpop_start(env); + lo =3D float32_muladd(RssV, RttV, RxxV, float_muladd_negate_product, + &env->fp_status); + hi =3D float32_muladd(RssV >> 32, RttV >> 32, RxxV >> 32, + float_muladd_negate_product, &env->fp_status); + arch_fpop_end(env, pkt_need_commit); + RddV =3D lo | ((uint64_t)hi << 32); + return RddV; +} + int32_t HELPER(sfcmpeq)(CPUHexagonState *env, float32 RsV, float32 RtV, uint32_t pkt_need_commit) { diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index 88958b334d8..da0b1a648cf 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -728,6 +728,11 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { .removed =3D HEX_VER_NONE }, [A2_nop_rb] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, [J2_trap2] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NON= E }, + [F7_vsfadd] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, + [F7_vsfsub] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, + [F7_vsfmpy] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, + [F7_vsffma] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, + [F7_vsffms] =3D { .introduced =3D HEX_VER_V83, .removed =3D HEX_VER_NO= NE }, =20 [Y4_dcfetch_multi] =3D { .introduced =3D HEX_VER_V85, .removed =3D HEX_VER_NONE }, diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index 97af0fcb394..1e632050eac 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -1200,9 +1200,14 @@ MPY_ENC(A6_vminub_RdP, "1010","ddddd","0","1",= "1","1","ee") DEF_FIELDROW_DESC32(ICLASS_M" 1011 -------- PP------ --------","[#11] Rese= rved") MPY_ENC(F2_sfadd, "1011","ddddd","0","0","0","0","00") MPY_ENC(F2_sfsub, "1011","ddddd","0","0","0","0","01") +DEF_ENC32(F7_vsfadd, "11101011000sssssPP0ttttt010ddddd") +DEF_ENC32(F7_vsfsub, "11101011000sssssPP0ttttt011ddddd") MPY_ENC(F2_sfmax, "1011","ddddd","0","0","0","1","00") MPY_ENC(F2_sfmin, "1011","ddddd","0","0","0","1","01") MPY_ENC(F2_sfmpy, "1011","ddddd","0","0","1","0","00") +DEF_ENC32(F7_vsfmpy, "11101011010sssssPP0ttttt001ddddd") +DEF_ENC32(F7_vsffma, "11101011010sssssPP0ttttt010xxxxx") +DEF_ENC32(F7_vsffms, "11101011010sssssPP0ttttt011xxxxx") MPY_ENC(F2_sffixupn, "1011","ddddd","0","0","1","1","00") MPY_ENC(F2_sffixupd, "1011","ddddd","0","0","1","1","01") MPY_ENC(F2_sfrecipa, "1011","ddddd","1","1","1","1","ee") diff --git a/target/hexagon/imported/float.idef b/target/hexagon/imported/f= loat.idef index 3e75bc46047..e61b7f580d2 100644 --- a/target/hexagon/imported/float.idef +++ b/target/hexagon/imported/float.idef @@ -51,6 +51,55 @@ Q6INSN(F2_sffms,"Rx32-=3Dsfmpy(Rs32,Rt32)",ATTRIBS(), "Floating-Point Fused Multiply Add", { RxV=3DfUNFLOAT(fFMAF(-fFLOAT(RsV),fFLOAT(RtV),fFLOAT(RxV))); }) =20 +Q6INSN(F7_vsfadd,"Rdd32=3Dvsfadd(Rss32,Rtt32)",ATTRIBS(), + "Vector Floating-Point Add", +{ + fSETWORD(0,RddV,fUNFLOAT(fFLOAT(fGETUWORD(0,RssV)) + + fFLOAT(fGETUWORD(0,RttV)))); + fSETWORD(1,RddV,fUNFLOAT(fFLOAT(fGETUWORD(1,RssV)) + + fFLOAT(fGETUWORD(1,RttV)))); +}) + +Q6INSN(F7_vsfsub,"Rdd32=3Dvsfsub(Rss32,Rtt32)",ATTRIBS(), + "Vector Floating-Point Subtract", +{ + fSETWORD(0,RddV,fUNFLOAT(fFLOAT(fGETUWORD(0,RssV)) - + fFLOAT(fGETUWORD(0,RttV)))); + fSETWORD(1,RddV,fUNFLOAT(fFLOAT(fGETUWORD(1,RssV)) - + fFLOAT(fGETUWORD(1,RttV)))); +}) + +Q6INSN(F7_vsfmpy,"Rdd32=3Dvsfmpy(Rss32,Rtt32)",ATTRIBS(), + "Vector Floating-Point Multiply", +{ + fSETWORD(0,RddV,fUNFLOAT(fSFMPY(fFLOAT(fGETUWORD(0,RssV)), + fFLOAT(fGETUWORD(0,RttV))))); + fSETWORD(1,RddV,fUNFLOAT(fSFMPY(fFLOAT(fGETUWORD(1,RssV)), + fFLOAT(fGETUWORD(1,RttV))))); +}) + +Q6INSN(F7_vsffma,"Rxx32+=3Dvsfmpy(Rss32,Rtt32)",ATTRIBS(), + "Vector Floating-Point Fused Multiply Add", +{ + fSETWORD(0,RxxV,fUNFLOAT(fFMAF(fFLOAT(fGETUWORD(0,RssV)), + fFLOAT(fGETUWORD(0,RttV)), + fFLOAT(fGETUWORD(0,RxxV))))); + fSETWORD(1,RxxV,fUNFLOAT(fFMAF(fFLOAT(fGETUWORD(1,RssV)), + fFLOAT(fGETUWORD(1,RttV)), + fFLOAT(fGETUWORD(1,RxxV))))); +}) + +Q6INSN(F7_vsffms,"Rxx32-=3Dvsfmpy(Rss32,Rtt32)",ATTRIBS(), + "Vector Floating-Point Fused Multiply Subtract", +{ + fSETWORD(0,RxxV,fUNFLOAT(fFMAF(-fFLOAT(fGETUWORD(0,RssV)), + fFLOAT(fGETUWORD(0,RttV)), + fFLOAT(fGETUWORD(0,RxxV))))); + fSETWORD(1,RxxV,fUNFLOAT(fFMAF(-fFLOAT(fGETUWORD(1,RssV)), + fFLOAT(fGETUWORD(1,RttV)), + fFLOAT(fGETUWORD(1,RxxV))))); +}) + Q6INSN(F2_sffma_lib,"Rx32+=3Dsfmpy(Rs32,Rt32):lib",ATTRIBS(), "Floating-Point Fused Multiply Add for Library Routines", { fFPSETROUND_NEAREST(); fHIDE(int infinp; int infminusinf; size4s_t tmp;) --=20 2.34.1 From nobody Fri Oct 23 21:31:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792622705992158500 Add tests for: vallocframe, atomics, trap2, CFI/restricted branches, and scalar fp instructions. New instructions not yet supported by the toolchain are manually encoded with .word directives. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/cfi_tgts.h | 18 +++ tests/tcg/hexagon/atomics.c | 111 +++++++++++++++++ tests/tcg/hexagon/cfi_tlb.c | 99 +++++++++++++++ tests/tcg/hexagon/cfi_user.c | 73 +++++++++++ tests/tcg/hexagon/check_rev_gating.c | 10 ++ tests/tcg/hexagon/invalid-encoding.c | 20 +++ tests/tcg/hexagon/trap2.c | 34 +++++ tests/tcg/hexagon/v83_scalar_fp.c | 98 +++++++++++++++ tests/tcg/hexagon/vallocframe.c | 128 +++++++++++++++++++ tests/tcg/hexagon/cfi_tgts.S | 178 +++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 24 +++- 11 files changed, 791 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/hexagon/cfi_tgts.h create mode 100644 tests/tcg/hexagon/cfi_tlb.c create mode 100644 tests/tcg/hexagon/cfi_user.c create mode 100644 tests/tcg/hexagon/trap2.c create mode 100644 tests/tcg/hexagon/v83_scalar_fp.c create mode 100644 tests/tcg/hexagon/vallocframe.c create mode 100644 tests/tcg/hexagon/cfi_tgts.S diff --git a/tests/tcg/hexagon/cfi_tgts.h b/tests/tcg/hexagon/cfi_tgts.h new file mode 100644 index 00000000000..c1edc95d94a --- /dev/null +++ b/tests/tcg/hexagon/cfi_tgts.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef CFI_TGTS_H +#define CFI_TGTS_H + +#define CFI_TEST_CASES 13 + +void run_test_case(int valid, int test_case); +void run_callr_rb_lr_test(int valid); +void run_jumpr_rb_lr_test(void); +void run_jumpr_rb_nop_rb_test(void); +void run_trap0_target_test(void); +void run_allocframe_test(void); + +#endif diff --git a/tests/tcg/hexagon/atomics.c b/tests/tcg/hexagon/atomics.c index 5017ca003f1..c912170cd50 100644 --- a/tests/tcg/hexagon/atomics.c +++ b/tests/tcg/hexagon/atomics.c @@ -109,6 +109,43 @@ static inline int64_t atomic_dec64(int64_t *x) return old; } =20 +static uint32_t v85_atomic_inc(uint32_t *counter) +{ + uint32_t old_val; + + asm volatile("r0 =3D %0\n" + "r1 =3D %1\n" + "r2 =3D #1\n" + ".word 0x9001e220\n" /* r0 =3D atomw_add(r1,r2):aq */ + "%0 =3D r0\n" + : "=3Dr"(old_val) + : "r"(counter) + : "r0", "r1", "r2"); + return old_val; +} + +static uint64_t v85_atomic_swap64(uint64_t *addr, uint64_t val) +{ + asm volatile("r1:0 =3D %0\n" + "r2 =3D %1\n" + ".word 0x90c2e0a0\n" /* r1:0 =3D atomd_swap(r2,r1:0):aq */ + "%0 =3D r1:0\n" + : "+r"(val) + : "r"(addr) + : "r0", "r1", "r2"); + return val; +} + +static void v85_dcfetch_multi(const void *addr) +{ + asm volatile("r0 =3D %0\n" + "r1 =3D #0\n" + ".word 0x9400c840\n" /* dcfetch_multi(r0,r1) */ + : + : "r"(addr) + : "r0", "r1", "memory"); +} + #define LOOP_CNT 1000 volatile int32_t tick32 =3D 1; /* Using volatile because we are testing at= omics */ volatile int64_t tick64 =3D 1; /* Using volatile because we are testing at= omics */ @@ -159,10 +196,84 @@ void test_pthread(void) check64(tick64, 1); } =20 +static void test_v85_swap64(void) +{ +#define INITIAL_V1 0xffffffffffffffff +#define INITIAL_V2 0x1111111111111111 + + uint64_t v1 =3D INITIAL_V1; + uint64_t v2 =3D INITIAL_V2; + + v2 =3D v85_atomic_swap64(&v1, v2); + check64(v1, INITIAL_V2); + check64(v2, INITIAL_V1); + + v2 =3D v85_atomic_swap64(&v1, v2); + check64(v1, INITIAL_V1); + check64(v2, INITIAL_V2); + +#undef INITIAL_V1 +#undef INITIAL_V2 +} + +#define V85_ROUNDS 1000 +#define V85_THREADS 10 +static uint32_t v85_global_counter =3D 1; +static uint32_t v85_started_threads; + +static void *v85_counter_thread(void *arg) +{ + uint32_t previous; + + v85_atomic_inc(&v85_started_threads); + while (v85_started_threads !=3D V85_THREADS) { + asm volatile("pause(#0)"); + } + previous =3D 0; + for (int i =3D 0; i < V85_ROUNDS; i++) { + uint32_t current =3D v85_atomic_inc(&v85_global_counter); + + if (current <=3D previous) { + printf("ERROR: counter is not strictly growing. " + "Before: %" PRIu32 ", Now: %" PRIu32 "\n", + previous, current); + err =3D 1; + return arg; + } + previous =3D current; + } + return arg; +} + +static void test_v85_race(void) +{ + pthread_t tids[V85_THREADS]; + + for (int i =3D 0; i < V85_THREADS; i++) { + pthread_create(&tids[i], NULL, v85_counter_thread, NULL); + } + for (int i =3D 0; i < V85_THREADS; i++) { + pthread_join(tids[i], NULL); + } + check32(v85_global_counter, 1 + V85_THREADS * V85_ROUNDS); +} + +static void test_v85_inc32(void) +{ + uint32_t counter =3D UINT32_MAX; + + check32(v85_atomic_inc(&counter), UINT32_MAX); + check32(counter, 0); +} + int main(int argc, char **argv) { test_reservations(); test_pthread(); + v85_dcfetch_multi(&v85_global_counter); + test_v85_swap64(); + test_v85_race(); + test_v85_inc32(); puts(err ? "FAIL" : "PASS"); return err; } diff --git a/tests/tcg/hexagon/cfi_tlb.c b/tests/tcg/hexagon/cfi_tlb.c new file mode 100644 index 00000000000..1deb59756ce --- /dev/null +++ b/tests/tcg/hexagon/cfi_tlb.c @@ -0,0 +1,99 @@ +/* + * Test a restricted branch interrupted by a data TLB miss. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include + +static sigjmp_buf cfi_jmp; +static volatile sig_atomic_t sigsegv_count; +static volatile sig_atomic_t sigill_count; +static void *target; + +static void *landing_pad(int valid_target) +{ + void *pad; + + asm volatile( + "p0 =3D cmp.eq(%[valid_target], #1)\n\t" + "if (p0) %[pad] =3D ##valid_cfi_tlb_target\n\t" + "if (!p0) %[pad] =3D ##invalid_cfi_tlb_target\n\t" + : [pad] "=3Dr"(pad) : [valid_target] "r"(valid_target) : "p0"); + return pad; +} + +static __attribute__((noinline)) void run_cfi_tlb_test(int valid_target) +{ + asm volatile( + "p0 =3D cmp.eq(%[valid_target], #1)\n\t" + "if (p0) r0 =3D ##valid_cfi_tlb_target\n\t" + "if (!p0) r0 =3D ##invalid_cfi_tlb_target\n\t" + "r1 =3D #0\n\t" + "r2 =3D #0\n\t" + ".word 0x52004000\n\t" /* { jumpr_rb r0 */ + ".word 0xa181c200\n\t" /* memw(r1 + #0) =3D r2 } */ + "valid_cfi_tlb_target:\n\t" + ".word 0x7f80c000\n\t" /* nop_rb */ + "jump 1f\n\t" + "invalid_cfi_tlb_target:\n\t" + "nop\n\t" + "1:\n\t" + : : [valid_target] "r"(valid_target) + : "r0", "r1", "r2", "p0", "memory"); +} + +static void handle_sigsegv(int sig, siginfo_t *info, void *context) +{ + ucontext_t *uc =3D context; + + assert(sig =3D=3D SIGSEGV); + sigsegv_count++; + uc->uc_mcontext.pc =3D (unsigned long)target; +} + +static void handle_sigill(int sig, siginfo_t *info, void *context) +{ + assert(sig =3D=3D SIGILL); + sigill_count++; + siglongjmp(cfi_jmp, 1); +} + +int main(void) +{ + struct sigaction action; + + action.sa_sigaction =3D handle_sigsegv; + sigemptyset(&action.sa_mask); + action.sa_flags =3D SA_SIGINFO; + assert(sigaction(SIGSEGV, &action, NULL) =3D=3D 0); + + action.sa_sigaction =3D handle_sigill; + sigemptyset(&action.sa_mask); + action.sa_flags =3D SA_SIGINFO; + assert(sigaction(SIGILL, &action, NULL) =3D=3D 0); + + target =3D landing_pad(1); + run_cfi_tlb_test(1); + assert(sigsegv_count =3D=3D 1); + assert(sigill_count =3D=3D 0); + + target =3D landing_pad(0); + if (sigsetjmp(cfi_jmp, 1) =3D=3D 0) { + run_cfi_tlb_test(0); + abort(); + } + assert(sigsegv_count =3D=3D 2); + assert(sigill_count =3D=3D 1); + + puts("PASS"); + return EXIT_SUCCESS; +} diff --git a/tests/tcg/hexagon/cfi_user.c b/tests/tcg/hexagon/cfi_user.c new file mode 100644 index 00000000000..deac763b5a0 --- /dev/null +++ b/tests/tcg/hexagon/cfi_user.c @@ -0,0 +1,73 @@ +/* + * Test v83 restricted indirect control-flow forms and restricted targets. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +#include "cfi_tgts.h" + +static sigjmp_buf cfi_jmp; +static volatile sig_atomic_t cfi_signal; + +static void handle_sigill(int sig, siginfo_t *info, void *context) +{ + assert(sig =3D=3D SIGILL); + cfi_signal =3D sig; + siglongjmp(cfi_jmp, 1); +} + +int main(void) +{ + struct sigaction action; + int i; + + action.sa_sigaction =3D handle_sigill; + sigemptyset(&action.sa_mask); + action.sa_flags =3D SA_SIGINFO; + assert(sigaction(SIGILL, &action, NULL) =3D=3D 0); + + for (i =3D 0; i < CFI_TEST_CASES; i++) { + run_test_case(1, i); + } + + for (i =3D 0; i < CFI_TEST_CASES; i++) { + cfi_signal =3D 0; + if (sigsetjmp(cfi_jmp, 1) =3D=3D 0) { + run_test_case(0, i); + abort(); + } + assert(cfi_signal =3D=3D SIGILL); + } + + run_jumpr_rb_lr_test(); + + cfi_signal =3D 0; + if (sigsetjmp(cfi_jmp, 1) =3D=3D 0) { + run_jumpr_rb_nop_rb_test(); + abort(); + } + assert(cfi_signal =3D=3D SIGILL); + + run_trap0_target_test(); + + run_callr_rb_lr_test(1); + + cfi_signal =3D 0; + if (sigsetjmp(cfi_jmp, 1) =3D=3D 0) { + run_callr_rb_lr_test(0); + abort(); + } + assert(cfi_signal =3D=3D SIGILL); + + run_allocframe_test(); + + puts("PASS"); + return EXIT_SUCCESS; +} diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check= _rev_gating.c index ad22a93bdaf..3a5ed9c71ca 100644 --- a/tests/tcg/hexagon/check_rev_gating.c +++ b/tests/tcg/hexagon/check_rev_gating.c @@ -122,6 +122,13 @@ TRY_FUNC(v79_dczeroa_nt, TRY_FUNC(v79_dcfetchbo_nt, ".word 0x9402e000 /* dcfetch(r2+#0):nt */\n") =20 +TRY_FUNC(v83_callr_rb, + ".word 0x5020c000 /* callr_rb r0 */\n") +TRY_FUNC(v83_nop_rb, + ".word 0x7f80c000 /* nop_rb */\n") +TRY_FUNC(v83_vsfadd, + ".word 0xeb02c440 /* r1:0 =3D vsfadd(r3:2, r5:4) */\n") + TRY_FUNC(v79hvx_vmerge_qf, ".word 0x1f01e0e2 /* v2 =3D vmerge(v0.x, v1.w) */\n") =20 @@ -165,6 +172,9 @@ int main(void) assert(try_v79_pstorerif_pi_nt() =3D=3D SIGILL); assert(try_v79_dczeroa_nt() =3D=3D SIGILL); assert(try_v79_dcfetchbo_nt() =3D=3D SIGILL); + assert(try_v83_callr_rb() =3D=3D SIGILL); + assert(try_v83_nop_rb() =3D=3D SIGILL); + assert(try_v83_vsfadd() =3D=3D SIGILL); =20 assert(try_v79hvx_vmerge_qf() =3D=3D SIGILL); =20 diff --git a/tests/tcg/hexagon/invalid-encoding.c b/tests/tcg/hexagon/inval= id-encoding.c index 639d7f24959..4c85342c772 100644 --- a/tests/tcg/hexagon/invalid-encoding.c +++ b/tests/tcg/hexagon/invalid-encoding.c @@ -89,6 +89,25 @@ static int test_invalid_nonduplex(void) return sig; } =20 +/* L4_loadw_phys bit 7 was reserved beginning with v83. */ +static int test_v83_loadw_phys_reserved_bit(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x9200e080\n" /* r0 =3D memw_phys(r0, r0), bit 7 =3D 1 */ + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + int main() { struct sigaction act; @@ -100,6 +119,7 @@ int main() =20 assert(test_invalid_duplex() =3D=3D SIGILL); assert(test_invalid_nonduplex() =3D=3D SIGILL); + assert(test_v83_loadw_phys_reserved_bit() =3D=3D SIGILL); =20 puts("PASS"); return EXIT_SUCCESS; diff --git a/tests/tcg/hexagon/trap2.c b/tests/tcg/hexagon/trap2.c new file mode 100644 index 00000000000..8180d23ed04 --- /dev/null +++ b/tests/tcg/hexagon/trap2.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +uint32_t err; + +#include "hex_test.h" + +static int trap2_getpid(void) +{ + int pid; + + asm volatile("r6 =3D #172\n" /* __NR_getpid */ + ".word 0x54c0c004\n" /* trap2(#1) */ + "%0 =3D r0\n" + : "=3Dr"(pid) + : + : "r0", "r6"); + return pid; +} + +int main(void) +{ + if (trap2_getpid() <=3D 0) { + err++; + } + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/v83_scalar_fp.c b/tests/tcg/hexagon/v83_scal= ar_fp.c new file mode 100644 index 00000000000..722491c1f62 --- /dev/null +++ b/tests/tcg/hexagon/v83_scalar_fp.c @@ -0,0 +1,98 @@ +/* + * Test the v83 scalar two-lane floating-point instructions. + * + * The assembler does not yet know these instructions, so use their encodi= ngs. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +uint32_t err; + +#include "hex_test.h" + +static uint64_t vsfadd(uint64_t a, uint64_t b) +{ + uint64_t result; + + asm volatile("r3:2 =3D %1\n" + "r5:4 =3D %2\n" + ".word 0xeb02c440\n" /* r1:0 =3D vsfadd(r3:2, r5:4) */ + "%0 =3D r1:0\n" + : "=3Dr"(result) : "r"(a), "r"(b) : "r0", "r1", "r2", + "r3", "r4", "r5"); + return result; +} + +static uint64_t vsfsub(uint64_t a, uint64_t b) +{ + uint64_t result; + + asm volatile("r3:2 =3D %1\n" + "r5:4 =3D %2\n" + ".word 0xeb02c460\n" /* r1:0 =3D vsfsub(r3:2, r5:4) */ + "%0 =3D r1:0\n" + : "=3Dr"(result) : "r"(a), "r"(b) : "r0", "r1", "r2", + "r3", "r4", "r5"); + return result; +} + +static uint64_t vsfmpy(uint64_t a, uint64_t b) +{ + uint64_t result; + + asm volatile("r3:2 =3D %1\n" + "r5:4 =3D %2\n" + ".word 0xeb42c420\n" /* r1:0 =3D vsfmpy(r3:2, r5:4) */ + "%0 =3D r1:0\n" + : "=3Dr"(result) : "r"(a), "r"(b) : "r0", "r1", "r2", + "r3", "r4", "r5"); + return result; +} + +static uint64_t vsffma(uint64_t a, uint64_t b, uint64_t acc) +{ + uint64_t result; + + asm volatile("r1:0 =3D %3\n" + "r3:2 =3D %1\n" + "r5:4 =3D %2\n" + ".word 0xeb42c440\n" /* r1:0 +=3D vsfmpy(r3:2, r5:4) */ + "%0 =3D r1:0\n" + : "=3Dr"(result) : "r"(a), "r"(b), "r"(acc) : "r0", "r1", + "r2", "r3", "r4", "r5"); + return result; +} + +static uint64_t vsffms(uint64_t a, uint64_t b, uint64_t acc) +{ + uint64_t result; + + asm volatile("r1:0 =3D %3\n" + "r3:2 =3D %1\n" + "r5:4 =3D %2\n" + ".word 0xeb42c460\n" /* r1:0 -=3D vsfmpy(r3:2, r5:4) */ + "%0 =3D r1:0\n" + : "=3Dr"(result) : "r"(a), "r"(b), "r"(acc) : "r0", "r1", + "r2", "r3", "r4", "r5"); + return result; +} + +int main(void) +{ + uint64_t a =3D 0x400000003fc00000ULL; + uint64_t b =3D 0x4080000040000000ULL; + uint64_t acc =3D 0x40a000003f800000ULL; + + check64(vsfadd(a, b), 0x40c0000040600000ULL); + check64(vsfsub(a, b), 0xc0000000bf000000ULL); + check64(vsfmpy(a, b), 0x4100000040400000ULL); + check64(vsffma(a, b, acc), 0x4150000040800000ULL); + check64(vsffms(a, b, acc), 0xc0400000c0000000ULL); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/vallocframe.c b/tests/tcg/hexagon/vallocfram= e.c new file mode 100644 index 00000000000..9288e894bf8 --- /dev/null +++ b/tests/tcg/hexagon/vallocframe.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +uint32_t err; + +#include "hex_test.h" + +#define VSP_INITIAL_OFFSET (5 * 1024) +#define VALLOCFRAME_VALUE 2 +#define VSP_AFTER_VALLOCFRAME \ + (VSP_INITIAL_OFFSET - (VALLOCFRAME_VALUE * 2 * 1024)) + +#define VALLOCFRAME_IMM ".word 0x6080c802\n" /* vallocframe(#2) */ +#define VALLOCFRAME_REG ".word 0x6080d000\n" /* vallocframe(r0) */ +#define VDEALLOCFRAME_IMM ".word 0x6a80c802\n" /* vdeallocframe(#2) */ +#define VDEALLOCFRAME_REG ".word 0x6940d000\n" /* vdeallocframe(r0) */ + +static uint32_t read_vsp(void) +{ + uint32_t value; + + asm volatile(".word 0x6a1dc000\n" /* r0 =3D vsp */ + "%0 =3D r0\n" + : "=3Dr"(value)); + return value; +} + +static void write_vsp(uint32_t value) +{ + asm volatile("r0 =3D %0\n" + ".word 0x6220c01d\n" /* vsp =3D r0 */ + : + : "r"(value) + : "r0"); +} + +static void write_vframelimit(uint32_t value) +{ + asm volatile("r0 =3D %0\n" + ".word 0x6220c01c\n" /* vframelimit =3D r0 */ + : + : "r"(value) + : "r0"); +} + +static uint32_t __attribute__((noinline)) keep(uint32_t a, uint32_t b) +{ + write_vsp(b); + return a * 3; +} + +static sigjmp_buf overflow_jmp; +static int overflow_sig; +static int overflow_code; + +static void overflow_handler(int sig, siginfo_t *info, void *context) +{ + overflow_sig =3D sig; + overflow_code =3D info->si_code; + siglongjmp(overflow_jmp, 1); +} + +static void test_vallocframe_imm(void) +{ + write_vsp(VSP_INITIAL_OFFSET); + write_vframelimit(0); + asm volatile(VALLOCFRAME_IMM); + check32(VSP_AFTER_VALLOCFRAME, read_vsp()); + asm volatile(VDEALLOCFRAME_IMM); + check32(VSP_INITIAL_OFFSET, read_vsp()); +} + +static void test_vallocframe_reg(void) +{ + uint32_t value =3D VALLOCFRAME_VALUE; + + write_vsp(VSP_INITIAL_OFFSET); + write_vframelimit(0); + asm volatile("r0 =3D %0\n" VALLOCFRAME_REG : : "r"(value) : "r0"); + check32(VSP_AFTER_VALLOCFRAME, read_vsp()); + asm volatile("r0 =3D %0\n" VDEALLOCFRAME_REG : : "r"(value) : "r0"); + check32(VSP_INITIAL_OFFSET, read_vsp()); +} + +static void test_write_vsp_clobber(void) +{ + /* Prevent constant folding so a remains live across write_vsp(). */ + static volatile uint32_t x =3D 111, y =3D 222; + + check32(keep(x, y), 333); +} + +static void test_vallocframe_overflow(void) +{ + struct sigaction action =3D { + .sa_sigaction =3D overflow_handler, + .sa_flags =3D SA_SIGINFO, + }; + + sigemptyset(&action.sa_mask); + sigaction(SIGSEGV, &action, NULL); + if (sigsetjmp(overflow_jmp, 1) =3D=3D 0) { + write_vsp(VSP_INITIAL_OFFSET); + write_vframelimit(VSP_AFTER_VALLOCFRAME + 1); + asm volatile(VALLOCFRAME_IMM); + check32(1, 0); + } + check32(SIGSEGV, overflow_sig); + check32(SEGV_BNDERR, overflow_code); +} + +int main(void) +{ + test_write_vsp_clobber(); + test_vallocframe_imm(); + test_vallocframe_reg(); + test_vallocframe_overflow(); + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/cfi_tgts.S b/tests/tcg/hexagon/cfi_tgts.S new file mode 100644 index 00000000000..21ede45f3b2 --- /dev/null +++ b/tests/tcg/hexagon/cfi_tgts.S @@ -0,0 +1,178 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + .text +valid_tgt: + .word 0x7f80c000 /* nop_rb */ + jumpr r2 + +invalid_tgt: + nop + jumpr r2 + +valid_call_tgt: + .word 0x7f80c000 /* nop_rb */ + jumpr r31 + +invalid_call_tgt: + nop + jumpr r31 + +.macro set_pred reg, id + r4 =3D \id + r3 =3D xor(\reg, r4) + p0 =3D !cmp.eq(r3, #0) +.endm + +.macro set_pred_in_packet reg, id + r4 =3D \id + r3 =3D xor(\reg, r4) + .word 0x75034010 /* { p0 =3D !cmp.eq(r3, #0) */ +.endm + +/* + * r0: nonzero for a valid target, zero for an invalid target + * r1: test case number + */ +.global run_test_case +run_test_case: + r5 =3D r31 + p1 =3D cmp.eq(r0, #1) + if (p1) r0 =3D #valid_tgt + if (!p1) r0 =3D #invalid_tgt + r2 =3D #return + + set_pred r1, #0 + .word 0x53e0c000 /* if (!p0) jumpr_rb:nt r0 */ + + set_pred r1, #1 + .word 0x53e0d000 /* if (!p0) jumpr_rb:t r0 */ + + set_pred_in_packet r1, #2 + .word 0x53e0c800 /* if (!p0.new) jumpr_rb:nt r0 } */ + + set_pred_in_packet r1, #3 + .word 0x53e0d800 /* if (!p0.new) jumpr_rb:t r0 } */ + + p0 =3D cmp.eq(r1, #4) + .word 0x53c0c000 /* if (p0) jumpr_rb:nt r0 */ + + p0 =3D cmp.eq(r1, #5) + .word 0x53c0d000 /* if (p0) jumpr_rb:t r0 */ + + .word 0x750140c0 /* { p0 =3D cmp.eq(r1, #6) */ + .word 0x53c0c800 /* if (p0.new) jumpr_rb:nt r0 } */ + + .word 0x750140e0 /* { p0 =3D cmp.eq(r1, #7) */ + .word 0x53c0d800 /* if (p0.new) jumpr_rb:t r0 } */ + + p0 =3D cmp.eq(r1, #9) + if (p0) jump callr_case + p0 =3D cmp.eq(r1, #10) + if (p0) jump callrh_case + p0 =3D cmp.eq(r1, #11) + if (p0) jump callrt_case + p0 =3D cmp.eq(r1, #12) + if (p0) jump callrf_case + + .word 0x5200c000 /* jumpr_rb r0 */ + +callr_case: + if (p1) r0 =3D #valid_call_tgt + if (!p1) r0 =3D #invalid_call_tgt + .word 0x5020c000 /* callr_rb r0 */ + jump return + +callrh_case: + if (p1) r0 =3D #valid_call_tgt + if (!p1) r0 =3D #invalid_call_tgt + .word 0x5040c000 /* callrh_rb r0 */ + jump return + +callrt_case: + if (p1) r0 =3D #valid_call_tgt + if (!p1) r0 =3D #invalid_call_tgt + p0 =3D cmp.eq(r0, r0) + .word 0x5180c000 /* if (p0) callr_rb r0 */ + jump return + +callrf_case: + if (p1) r0 =3D #valid_call_tgt + if (!p1) r0 =3D #invalid_call_tgt + p0 =3D cmp.eq(r0, #0) + .word 0x51a0c000 /* if (!p0) callr_rb r0 */ + jump return + +return: + jumpr r5 + +/* jumpr_rb r31 is a return, not a restricted branch. */ +.global run_jumpr_rb_lr_test +run_jumpr_rb_lr_test: + .word 0x521fc000 /* jumpr_rb r31 */ + +/* A target marker and restricted branch in the same packet. */ +.global run_jumpr_rb_nop_rb_test +run_jumpr_rb_nop_rb_test: + r0 =3D #1f + .word 0x7f804000 /* { nop_rb */ + .word 0x5200c000 /* jumpr_rb r0 } */ +1: + nop + +/* A trap0(#0xdb) landing pad: the syscall must not leave CFI armed. */ +.global run_trap0_target_test +run_trap0_target_test: + r5 =3D r31 + r6 =3D #172 /* __NR_getpid */ + r0 =3D #1f + .word 0x5200c000 /* jumpr_rb r0 */ +1: + trap0(#0xdb) + nop + jumpr r5 + +/* + * callr_rb r31 remains restricted: it must branch to a landing pad even + * though it overwrites r31 with its return address. + */ +.global run_callr_rb_lr_test +run_callr_rb_lr_test: + r2 =3D r31 + p0 =3D cmp.eq(r0, #1) + if (p0) r31 =3D #valid_callr_rb_lr_tgt + if (!p0) r31 =3D #invalid_callr_rb_lr_tgt + .word 0x503fc000 /* callr_rb r31 */ + jumpr r2 + +valid_callr_rb_lr_tgt: + .word 0x7f80c000 /* nop_rb */ + jumpr r31 + +invalid_callr_rb_lr_tgt: + nop + jumpr r31 + +/* + * Enter each restricted allocframe instruction with CFI active. The + * following ordinary instructions show that the restricted target reset i= t. + */ +.global run_allocframe_test +run_allocframe_test: + r0 =3D #allocframe_rb_reg + r2 =3D #allocframe_rb_duplex + .word 0x5200c000 /* jumpr_rb r0 */ + +allocframe_rb_reg: + .word 0xa09de000 /* allocframe_rb(r29, #0):raw */ + deallocframe + nop + jumpr r2 + +allocframe_rb_duplex: + .word 0x70003e00 /* r0 =3D r0; allocframe_rb(#0) */ + deallocframe + nop + jumpr r31 diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index a6ace4c77c2..d5fc803debb 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -25,8 +25,20 @@ foreach t: tcg_tests['multiarch-linux-user']['tests'] endforeach =20 tests +=3D { - 'atomics.c': {'cflags': cflags}, + # The cross assembler does not know v85; v85 instructions in atomics.c + # are encoded with .word directives. + 'atomics.c': {'cflags': cflags, 'qemu_args': ['-cpu', 'v85']}, 'brev.c': {'cflags': cflags}, + # The cross assembler does not know v83; cfi_tlb.c uses raw encodings. + 'cfi_tlb.c': { + 'cflags': cflags, + 'qemu_args': ['-cpu', 'v85'], + }, + # The cross assembler does not know v83; cfi_tgts.S uses raw encodings. + 'cfi_user.c': { + 'cflags': [cflags, files('cfi_tgts.S')], + 'qemu_args': ['-cpu', 'v85'], + }, # Compile for v66 so that the ELF selects a v66 CPU; the test then # exercises revision gating by executing a v68 .word instruction. 'check_rev_gating.c': { @@ -57,7 +69,7 @@ tests +=3D { 'cflags': [cflags, '-mhvx', '-Wno-gnu-folding-constant', files('hvx_histogram_row.S')] }, - 'invalid-encoding.c': {'cflags': cflags}, + 'invalid-encoding.c': {'cflags': cflags, 'qemu_args': ['-cpu', 'v85']}, 'invalid-slots.c': {'cflags': cflags}, 'icinva.c': {'cflags': cflags}, 'load_align.c': {'cflags': cflags}, @@ -106,6 +118,8 @@ tests +=3D { 'test_vpmpyh.S': {'cflags': asmflags}, 'test_vspliceb.S': {'cflags': asmflags}, 'test_vwhist.c': {'cflags': [cflags, '-mhvx']}, + # The cross assembler does not know trap2; the test uses its raw encodin= g. + 'trap2.c': {'cflags': cflags, 'qemu_args': ['-cpu', 'v85']}, 'unaligned_pc.c': {'cflags': cflags}, 'unaligned_data.c': {'cflags': cflags}, 'usr.c': { @@ -117,6 +131,12 @@ tests +=3D { 'v69_hvx.c': {'cflags': [cflags, '-mhvx', '-Wno-unused-function', '-mv69= ']}, 'v73_scalar.c': {'cflags': [cflags, '-Wno-unused-function', '-mv73']}, 'v79_scalar.c': {'cflags': [cflags, '-Wno-unused-function', '-mv79']}, + 'v83_scalar_fp.c': {'cflags': [cflags, '-mv67'], + 'qemu_args': ['-cpu', 'v85']}, + # The cross assembler does not know v83; the vallocframe instructions in + # this test are encoded with .word directives. + 'vallocframe.c': {'cflags': [cflags, '-mv67', '-O2'], + 'qemu_args': ['-cpu', 'v85']}, 'valid-slots.c': {'cflags': cflags}, 'vector_add_int.c': {'cflags': [cflags, '-mhvx', '-fvectorize']}, } --=20 2.34.1