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Wed, 21 Oct 2026 12:36:19 -0700 (PDT) From: Harshit Mukhedkar To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Harshit Mukhedkar , qemu-stable@nongnu.org Subject: [PATCH] target/riscv: make sstateen1-3 reserved bits read-only zero Date: Thu, 22 Oct 2026 01:05:38 +0530 Message-ID: <20261021193538.80383-1-harshit007k@gmail.com> X-Mailer: git-send-email 2.56.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::122a; envelope-from=harshit007k@gmail.com; helo=mail-dl1-x122a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792611440021158500 Content-Type: text/plain; charset="utf-8" write_sstateen_1_3() passes SMSTATEEN_STATEEN (bit 63) as the write mask to write_sstateen(). That bit is the SE control bit only in mstateenN/hstateenN, where it gates access to sstateenN. The sstateen1-3 CSRs have no defined bits, and reserved bits must be read-only zero, so bit 63 must not be writable on RV64. Use a write mask of 0 for sstateen1-3 until bits are defined there. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/4726 Fixes: 3bee0e40106d ("target/riscv: Add smstateen support") Cc: qemu-stable@nongnu.org Signed-off-by: Harshit Mukhedkar Reviewed-by: Alistair Francis Reviewed-by: Chao Liu --- target/riscv/tcg/csr.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 063590f56a..d9731421af 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3941,7 +3941,12 @@ static RISCVException write_sstateen0(CPURISCVState = *env, int csrno, static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno, target_ulong new_val, uintptr_t r= a) { - return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); + /* + * sstateen1-3 have no defined bits yet, so they are read only zero. + * Bit 63 is the SE bit only in mstateenN/hstateenN, where it gates + * access to sstateenN. + */ + return write_sstateen(env, csrno, 0, new_val); } =20 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, --=20 2.56.0