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Wed, 21 Oct 2026 07:16:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 001/100] include/qemu/compiler: Add QEMU_*_NONNULL attributes Date: Wed, 21 Oct 2026 16:15:13 +0200 Message-ID: <20261021141652.363109-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592278286158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/qemu/compiler.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 4c49f52eb0..f871298d8d 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -25,6 +25,14 @@ #define QEMU_PACKED __attribute__((packed)) #define QEMU_ALIGNED(X) __attribute__((aligned(X))) =20 +#define QEMU_ARG_NONNULL __attribute__((nonnull)) +#define QEMU_ARG_LIST_NONNULL(...) __attribute__((nonnull(__VA_ARGS__= ))) +#define QEMU_RET_NONNULL __attribute__((returns_nonnull)) +#define QEMU_RET_ARG_NONNULL \ + __attribute__((returns_nonnull, nonnull)) +#define QEMU_RET_ARG_LIST_NONNULL(...) \ + __attribute__((returns_nonnull, nonnull(__VA_ARGS__))) + #ifndef glue #define xglue(x, y) x ## y #define glue(x, y) xglue(x, y) --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:16:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 002/100] tcg: Annontate functions in tcg.h with QEMU_*_NONNULL Date: Wed, 21 Oct 2026 16:15:14 +0200 Message-ID: <20261021141652.363109-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592272490158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg.h | 58 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 2e00518934..e131345170 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -489,9 +489,10 @@ static inline TCGTemp *arg_temp(TCGArg a) } =20 #ifdef CONFIG_DEBUG_TCG -size_t temp_idx(TCGTemp *ts); -TCGTemp *tcgv_i32_temp(TCGv_i32 v); +QEMU_ARG_NONNULL size_t temp_idx(TCGTemp *ts); +QEMU_RET_ARG_NONNULL TCGTemp *tcgv_i32_temp(TCGv_i32 v); #else +QEMU_ARG_NONNULL static inline size_t temp_idx(TCGTemp *ts) { return ts - tcg_ctx->temps; @@ -502,104 +503,124 @@ static inline size_t temp_idx(TCGTemp *ts) * its index means that we don't use 0. That leaves offset 0 free for * a NULL representation without having to leave index 0 unused. */ +QEMU_RET_ARG_NONNULL static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) { return (void *)tcg_ctx + (uintptr_t)v; } #endif =20 +QEMU_RET_ARG_NONNULL static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) { return tcgv_i32_temp((TCGv_i32)v); } =20 +QEMU_RET_ARG_NONNULL static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) { return tcgv_i32_temp((TCGv_i32)v); } =20 +QEMU_RET_ARG_NONNULL static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { return tcgv_i32_temp((TCGv_i32)v); } =20 +QEMU_RET_ARG_NONNULL static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) { return tcgv_i32_temp((TCGv_i32)v); } =20 +QEMU_ARG_NONNULL static inline TCGArg tcgv_i32_arg(TCGv_i32 v) { return temp_arg(tcgv_i32_temp(v)); } =20 +QEMU_ARG_NONNULL static inline TCGArg tcgv_i64_arg(TCGv_i64 v) { return temp_arg(tcgv_i64_temp(v)); } =20 +QEMU_ARG_NONNULL static inline TCGArg tcgv_i128_arg(TCGv_i128 v) { return temp_arg(tcgv_i128_temp(v)); } =20 +QEMU_ARG_NONNULL static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); } =20 +QEMU_ARG_NONNULL static inline TCGArg tcgv_vec_arg(TCGv_vec v) { return temp_arg(tcgv_vec_temp(v)); } =20 +QEMU_RET_ARG_NONNULL static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) { (void)temp_idx(t); /* trigger embedded assert */ return (TCGv_i32)((void *)t - (void *)tcg_ctx); } =20 +QEMU_RET_ARG_NONNULL static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) { return (TCGv_i64)temp_tcgv_i32(t); } =20 +QEMU_RET_ARG_NONNULL static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) { return (TCGv_i128)temp_tcgv_i32(t); } =20 +QEMU_RET_ARG_NONNULL static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { return (TCGv_ptr)temp_tcgv_i32(t); } =20 +QEMU_RET_ARG_NONNULL static inline TCGv_vaddr temp_tcgv_vaddr(TCGTemp *t) { return (TCGv_vaddr)temp_tcgv_i32(t); } =20 +QEMU_RET_ARG_NONNULL static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) { return (TCGv_vec)temp_tcgv_i32(t); } =20 +QEMU_ARG_NONNULL static inline TCGArg tcg_get_insn_param(TCGOp *op, unsigned arg) { return op->args[arg]; } =20 +QEMU_ARG_NONNULL static inline void tcg_set_insn_param(TCGOp *op, unsigned arg, TCGArg v) { op->args[arg] =3D v; } =20 +QEMU_ARG_NONNULL static inline uint64_t tcg_get_insn_start_param(TCGOp *op, unsigned arg) { tcg_debug_assert(arg < INSN_START_WORDS); return tcg_get_insn_param(op, arg); } =20 +QEMU_ARG_NONNULL static inline void tcg_set_insn_start_param(TCGOp *op, unsigned arg, uint6= 4_t v) { tcg_debug_assert(arg < INSN_START_WORDS); @@ -628,9 +649,9 @@ static inline bool tcg_op_buf_full(void) /* pool based memory allocation */ =20 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ -void *tcg_malloc_internal(TCGContext *s, int size); -void tcg_pool_reset(TCGContext *s); -TranslationBlock *tcg_tb_alloc(TCGContext *s); +QEMU_RET_ARG_NONNULL void *tcg_malloc_internal(TCGContext *s, int size); +QEMU_ARG_NONNULL void tcg_pool_reset(TCGContext *s); +QEMU_ARG_NONNULL TranslationBlock *tcg_tb_alloc(TCGContext *s); =20 void tcg_region_reset_all(void); =20 @@ -643,7 +664,7 @@ size_t tcg_code_capacity(void); * * Insert @tb into the region trees. */ -void tcg_tb_insert(TranslationBlock *tb); +QEMU_ARG_NONNULL void tcg_tb_insert(TranslationBlock *tb); =20 /** * tcg_tb_remove: @@ -651,7 +672,7 @@ void tcg_tb_insert(TranslationBlock *tb); * * Remove @tb from the region trees. */ -void tcg_tb_remove(TranslationBlock *tb); +QEMU_ARG_NONNULL void tcg_tb_remove(TranslationBlock *tb); =20 /** * tcg_tb_lookup: @@ -685,6 +706,7 @@ void tcg_tb_foreach(GTraverseFunc func, gpointer user_d= ata); size_t tcg_nb_tbs(void); =20 /* user-mode: Called with mmap_lock held. */ +QEMU_RET_NONNULL static inline void *tcg_malloc(int size) { TCGContext *s =3D tcg_ctx; @@ -703,8 +725,10 @@ static inline void *tcg_malloc(int size) } } =20 +QEMU_ARG_NONNULL void tcg_func_start(TCGContext *s); =20 +QEMU_ARG_NONNULL int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); =20 void tb_target_set_jmp_target(const TranslationBlock *, int, @@ -794,7 +818,10 @@ void tcg_gen_call7(void *func, TCGHelperInfo *, TCGTem= p *ret, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); =20 +QEMU_RET_NONNULL TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); + +QEMU_ARG_NONNULL void tcg_op_remove(TCGContext *s, TCGOp *op); =20 /** @@ -805,10 +832,13 @@ void tcg_op_remove(TCGContext *s, TCGOp *op); * a starting point with tcg_last_op(), speculatively emit opcodes, * then decide whether or not to keep those opcodes after the fact. */ +QEMU_ARG_NONNULL void tcg_remove_ops_after(TCGOp *op); =20 +QEMU_ARG_NONNULL void tcg_optimize(TCGContext *s); =20 +QEMU_RET_NONNULL TCGLabel *gen_new_label(void); =20 /** @@ -817,7 +847,7 @@ TCGLabel *gen_new_label(void); * * Encode a label for storage in the TCG opcode stream. */ - +QEMU_ARG_NONNULL static inline TCGArg label_arg(TCGLabel *l) { return (uintptr_t)l; @@ -848,7 +878,7 @@ static inline TCGLabel *arg_label(TCGArg i) * This version relies on GCC's void pointer arithmetic to get the * correct result. */ - +QEMU_ARG_NONNULL static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) { return a - b; @@ -862,7 +892,7 @@ static inline ptrdiff_t tcg_ptr_byte_diff(const void *a= , const void *b) * Produce a pc-relative difference, from the current code_ptr * to the destination address. */ - +QEMU_ARG_NONNULL static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) { return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); @@ -876,6 +906,7 @@ static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, c= onst void *target) * Produce a difference, from the beginning of the current TB code * to the destination address. */ +QEMU_ARG_NONNULL static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) { return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); @@ -888,7 +919,7 @@ static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, c= onst void *target) * Compute the current code size within the translation block. * This is used to fill in qemu's data structures for goto_tb. */ - +QEMU_ARG_NONNULL static inline size_t tcg_current_code_size(TCGContext *s) { return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); @@ -946,12 +977,15 @@ static inline size_t tcg_current_code_size(TCGContext= *s) #define TB_EXIT_REQUESTED 3 =20 #ifdef CONFIG_TCG_INTERPRETER +QEMU_ARG_NONNULL uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); #else -typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 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Wed, 21 Oct 2026 07:17:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 003/100] tcg: Annontate functions in tcg-op-mem.h with QEMU_*_NONNULL Date: Wed, 21 Oct 2026 16:15:15 +0200 Message-ID: <20261021141652.363109-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592971143158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-mem.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h index ea35a02fb4..29e7c02f25 100644 --- a/include/tcg/tcg-op-mem.h +++ b/include/tcg/tcg-op-mem.h @@ -28,50 +28,50 @@ typedef TCGv_i64 TCGv_va; #error #endif =20 -static inline void +QEMU_ARG_NONNULL static inline void tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m) { tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 -static inline void +QEMU_ARG_NONNULL static inline void tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m) { tcg_gen_qemu_st_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 -static inline void +QEMU_ARG_NONNULL static inline void tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m) { tcg_gen_qemu_ld_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 -static inline void +QEMU_ARG_NONNULL static inline void tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m) { tcg_gen_qemu_st_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 -static inline void +QEMU_ARG_NONNULL static inline void tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m) { tcg_gen_qemu_ld_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 -static inline void +QEMU_ARG_NONNULL static inline void tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m) { tcg_gen_qemu_st_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 #define DEF_ATOMIC2(N, S) \ - static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, \ - TCGArg i, MemOp m) \ + QEMU_ARG_NONNULL static inline void \ + N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, TCGArg i, MemOp m) \ { N##_##S##_chk(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); } =20 #define DEF_ATOMIC3(N, S) \ - static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, \ - TCGv_##S n, TCGArg i, MemOp m) \ + QEMU_ARG_NONNULL static inline void \ + N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, TCGv_##S n, TCGArg i, MemOp= m) \ { N##_##S##_chk(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); } =20 DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 21 Oct 2026 07:17:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 004/100] tcg: Annontate functions in tcg-internal.h with QEMU_*_NONNULL Date: Wed, 21 Oct 2026 16:15:16 +0200 Message-ID: <20261021141652.363109-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592268530158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/tcg-internal.h | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index e35440dc8c..2620c23b44 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -41,53 +41,55 @@ extern unsigned int tcg_max_ctxs; #endif =20 void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads); -bool tcg_region_alloc(TCGContext *s); -void tcg_region_thread_initial_alloc(TCGContext *s); -void tcg_region_prologue_set(TCGContext *s); +QEMU_ARG_NONNULL bool tcg_region_alloc(TCGContext *s); +QEMU_ARG_NONNULL void tcg_region_thread_initial_alloc(TCGContext *s); +QEMU_ARG_NONNULL void tcg_region_prologue_set(TCGContext *s); =20 -static inline void *tcg_call_func(TCGOp *op) +QEMU_RET_ARG_NONNULL static inline void *tcg_call_func(TCGOp *op) { return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op)]; } =20 -static inline const TCGHelperInfo *tcg_call_info(TCGOp *op) +QEMU_RET_ARG_NONNULL static inline const TCGHelperInfo *tcg_call_info(TCGO= p *op) { return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) += 1]; } =20 -static inline unsigned tcg_call_flags(TCGOp *op) +QEMU_ARG_NONNULL static inline unsigned tcg_call_flags(TCGOp *op) { return tcg_call_info(op)->flags; } =20 -static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) +QEMU_RET_ARG_NONNULL static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) { return temp_tcgv_i64(tcgv_i128_temp(t) + HOST_BIG_ENDIAN); } =20 -static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) +QEMU_RET_ARG_NONNULL static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) { return temp_tcgv_i64(tcgv_i128_temp(t) + !HOST_BIG_ENDIAN); } =20 bool tcg_target_has_memory_bswap(MemOp memop); =20 -TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind); +QEMU_RET_NONNULL TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind = kind); =20 /* * Locate or create a read-only temporary that is a constant. * This kind of temporary need not be freed, but for convenience * will be silently ignored by tcg_temp_free_*. */ -TCGTemp *tcg_constant_internal(TCGType type, int64_t val); +QEMU_RET_NONNULL TCGTemp *tcg_constant_internal(TCGType type, int64_t val); =20 -TCGOp *tcg_gen_op1(TCGOpcode, TCGType, TCGArg); -TCGOp *tcg_gen_op2(TCGOpcode, TCGType, TCGArg, TCGArg); -TCGOp *tcg_gen_op3(TCGOpcode, TCGType, TCGArg, TCGArg, TCGArg); -TCGOp *tcg_gen_op4(TCGOpcode, TCGType, TCGArg, TCGArg, TCGArg, TCGArg); -TCGOp *tcg_gen_op5(TCGOpcode, TCGType, TCGArg, TCGArg, TCGArg, TCGArg, TCG= Arg); -TCGOp *tcg_gen_op6(TCGOpcode, TCGType, TCGArg, TCGArg, - TCGArg, TCGArg, TCGArg, TCGArg); +QEMU_RET_NONNULL TCGOp *tcg_gen_op1(TCGOpcode, TCGType, TCGArg); +QEMU_RET_NONNULL TCGOp *tcg_gen_op2(TCGOpcode, TCGType, TCGArg, TCGArg); +QEMU_RET_NONNULL TCGOp *tcg_gen_op3(TCGOpcode, TCGType, TCGArg, TCGArg, TC= GArg); +QEMU_RET_NONNULL TCGOp *tcg_gen_op4(TCGOpcode, TCGType, TCGArg, TCGArg, + TCGArg, TCGArg); +QEMU_RET_NONNULL TCGOp *tcg_gen_op5(TCGOpcode, TCGType, TCGArg, TCGArg, + TCGArg, TCGArg, TCGArg); +QEMU_RET_NONNULL TCGOp *tcg_gen_op6(TCGOpcode, TCGType, TCGArg, TCGArg, + TCGArg, TCGArg, TCGArg, TCGArg); =20 void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); @@ -95,8 +97,10 @@ void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCG= Arg, TCGArg, TCGArg); void vec_gen_6(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a, TCGArg b, TCGArg c, TCGArg d, TCGArg e); =20 +QEMU_RET_ARG_NONNULL TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode, TCGType, unsigned nargs); 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Wed, 21 Oct 2026 07:17:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 005/100] tcg: Prepare for easy temp lifetimes Date: Wed, 21 Oct 2026 16:15:17 +0200 Message-ID: <20261021141652.363109-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592803893158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-temp-internal.h | 2 ++ tcg/tcg-internal.h | 5 +++++ tcg/tcg.c | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-interna= l.h index 98f91e68b7..932ad1aeeb 100644 --- a/include/tcg/tcg-temp-internal.h +++ b/include/tcg/tcg-temp-internal.h @@ -31,6 +31,8 @@ =20 void tcg_temp_free_internal(TCGTemp *); =20 +G_DEFINE_AUTOPTR_CLEANUP_FUNC(TCGTemp, tcg_temp_free_internal) + void tcg_temp_free_i32(TCGv_i32 arg); void tcg_temp_free_i64(TCGv_i64 arg); void tcg_temp_free_i128(TCGv_i128 arg); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2620c23b44..d480d10878 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -74,6 +74,11 @@ bool tcg_target_has_memory_bswap(MemOp memop); =20 QEMU_RET_NONNULL TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind = kind); =20 +static inline TCGTemp *tcg_temp_new_ebb(TCGType type) +{ + return tcg_temp_new_internal(type, TEMP_EBB); +} + /* * Locate or create a read-only temporary that is a constant. * This kind of temporary need not be freed, but for convenience diff --git a/tcg/tcg.c b/tcg/tcg.c index 65d3190a8e..c3fdcfbe68 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2201,6 +2201,10 @@ void tcg_temp_free_internal(TCGTemp *ts) { TCGContext *s =3D tcg_ctx; =20 + if (ts =3D=3D NULL) { + return; + } + switch (ts->kind) { case TEMP_CONST: case TEMP_TB: --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index c3fdcfbe68..1cd6d41d31 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2257,6 +2257,10 @@ TCGTemp *tcg_constant_internal(TCGType type, int64_t= val) s->const_table[type] =3D h; } =20 + if (type =3D=3D TCG_TYPE_I32) { + val =3D (int32_t)val; + } + ts =3D g_hash_table_lookup(h, &val); if (ts =3D=3D NULL) { ts =3D tcg_temp_alloc(s); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592334; cv=none; d=zohomail.com; s=zohoarc; b=Yh+Zy42pROsujK1ccynhtTHjqZnwTxBybik60m+rT1V/sRzHoLovSOA2RqiJg0RyTM1kRHrPyX04bSKa65RCF9pV0toMpsrH8D9i6/cIYIC9xWubBqDUWGAVpBXvxIbcjDiynJv6r2BZoyRjr214fd6D5e6HUW5UULwgj8wQ+Lw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792592334; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7AdHOG3Y/1Jsu71pfexDPLdxdygNiIf6lrCs+e2S2fs=; b=KgDrIf0Z4HHj6CZ1O3vsHcMKSLbKo2fPluOBO09doJ6e7uO38Sm/UJiD269FkEBWDP1pWxTS+haBwW8UO8WqgKOVpu04w4JulJtBFsNQwKP6+CcNMyExihhiwPVvA45NZ7q5Pa8UzWGW25MYE90bBYhDEaGFm2bebW9E9gGykYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792592334621108.95231318253082; Wed, 21 Oct 2026 07:18:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJX8B-00036E-4h; Wed, 21 Oct 2026 10:17:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJX83-00035I-Ic for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:17:19 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xJX81-0001V2-KY for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:17:19 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4a1cef0439aso7689875e9.0 for ; Wed, 21 Oct 2026 07:17:17 -0700 (PDT) Received: from stoup.fritz.box (pd95f64ec.dip0.t-ipconnect.de. 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 34 +++++++++++++--- tcg/tcg-internal.h | 23 +++++++++++ include/tcg/tcg-op-def.h.inc | 4 ++ tcg/tcg-op.c | 76 +++++++++++++++++++++++++++++------- 4 files changed, 117 insertions(+), 20 deletions(-) create mode 100644 include/tcg/tcg-op-def.h.inc diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9b321f959c..deec10159a 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -88,6 +88,33 @@ void tcg_gen_lookup_and_goto_ptr(void); void tcg_gen_plugin_cb(unsigned from); void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo); =20 +/* + * Construct operations from templates. + */ + +#define DEF2(NAME, T1, T2) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2); + +#define TCGV glue(TCGv,TExt) +#define TExt _i32 +#define TINT int32_t + +#include "tcg-op-def.h.inc" + +#undef TExt +#undef TINT + +#define TExt _i64 +#define TINT int64_t + +#include "tcg-op-def.h.inc" + +#undef TExt +#undef TINT +#undef TCGV + +#undef DEF2 + /* 32 bit ops */ =20 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); @@ -172,7 +199,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 void tcg_gen_discard_i32(TCGv_i32 arg); -void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg); =20 void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); @@ -294,7 +320,6 @@ void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_= i64 arg2); void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); =20 void tcg_gen_discard_i64(TCGv_i64 arg); -void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); @@ -533,10 +558,7 @@ static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_p= tr a, intptr_t b) glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); } =20 -static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) -{ - glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); -} +QEMU_ARG_NONNULL void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s); =20 static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) { diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index d480d10878..3568157ebb 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -102,6 +102,12 @@ void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, T= CGArg, TCGArg, TCGArg); void vec_gen_6(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a, TCGArg b, TCGArg c, TCGArg d, TCGArg e); =20 +static inline void tcg_gen_op_tt(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1) +{ + tcg_gen_op2(opc, type, temp_arg(t0), temp_arg(t1)); +} + QEMU_RET_ARG_NONNULL TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode, TCGType, unsigned nargs); @@ -114,4 +120,21 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, */ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_target_ulong imm); =20 +/* + * Declarations of templated TCGv_i32 and TCGv_i64 operations. + */ + +#define DEF2(NAME, T1, T2) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2); + +#define TCGV TCGTemp * +#define TINT int64_t + +#include "tcg/tcg-op-def.h.inc" + +#undef TINT +#undef TCGV + +#undef DEF2 + #endif /* TCG_INTERNAL_H */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc new file mode 100644 index 0000000000..c76e83396a --- /dev/null +++ b/include/tcg/tcg-op-def.h.inc @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: MIT */ +/* Templated TCGv_i32 and TCGv_i64 operations */ + +DEF2(mov, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2c88f4f7ca..4b8dfba8a9 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -315,6 +315,61 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) tcg_gen_op2(INDEX_op_plugin_mem_cb, 0, tcgv_i64_arg(addr), meminfo); } =20 +/* + * Templated TCGv_i32 and TCGv_i64 operations. + */ + +#define DEF2(NAME, T1, T2) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b)); } + +#define C_TCGv_i32 tcgv_i32_temp +#define C_TCGv_i64 tcgv_i64_temp +#define C_int32_t +#define C_int64_t + +#define TCGV glue(TCGv,TExt) +#define TExt _i32 +#define TINT int32_t +#define TYPE TCG_TYPE_I32 + +#include "tcg/tcg-op-def.h.inc" + +#undef TExt +#undef TINT +#undef TYPE + +#define TExt _i64 +#define TINT int64_t +#define TYPE TCG_TYPE_I64 + +#include "tcg/tcg-op-def.h.inc" + +#undef TExt +#undef TINT +#undef TCGV +#undef TYPE + +#undef C_TCGv_i32 +#undef C_TCGv_i64 +#undef C_int32_t +#undef C_int64_t + +#undef DEF2 + +/* + * Generic expansions for templated operations. + * We have used compiler type checks to ensure all TCGTemp + * are of the proper type. + */ + +void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + if (src !=3D dst) { + tcg_gen_op_tt(INDEX_op_mov, type, dst, src); + } +} + /* 32 bit ops */ =20 void tcg_gen_discard_i32(TCGv_i32 arg) @@ -322,13 +377,6 @@ void tcg_gen_discard_i32(TCGv_i32 arg) tcg_gen_op1_i32(INDEX_op_discard, TCG_TYPE_I32, arg); } =20 -void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (ret !=3D arg) { - tcg_gen_op2_i32(INDEX_op_mov, ret, arg); - } -} - void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) { tcg_gen_mov_i32(ret, tcg_constant_i32(arg)); @@ -1396,13 +1444,6 @@ void tcg_gen_discard_i64(TCGv_i64 arg) tcg_gen_op1_i64(INDEX_op_discard, TCG_TYPE_I64, arg); } =20 -void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (ret !=3D arg) { - tcg_gen_op2_i64(INDEX_op_mov, ret, arg); - } -} - void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) { tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); @@ -2730,3 +2771,10 @@ void tcg_gen_lookup_and_goto_ptr(void) tcg_gen_op1i(INDEX_op_goto_ptr, TCG_TYPE_PTR, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } + +/* Host pointer operations */ + +void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) +{ + tcg_gen_mov(TCG_TYPE_PTR, tcgv_ptr_temp(d), tcgv_ptr_temp(s)); +} --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:17:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 008/100] tcg: Generic expansion of tcg_gen_movi_* Date: Wed, 21 Oct 2026 16:15:20 +0200 Message-ID: <20261021141652.363109-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592284444158501 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 8 +------- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 20 ++++++++++---------- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index deec10159a..9dc05cc7b7 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -117,7 +117,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -224,7 +223,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); @@ -559,11 +557,7 @@ static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_p= tr a, intptr_t b) } =20 QEMU_ARG_NONNULL void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s); - -static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) -{ - glue(tcg_gen_movi_,PTR)((NAT)d, s); -} +QEMU_ARG_NONNULL void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s); =20 static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, intptr_t b, TCGLabel *label) diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index c76e83396a..e55a9f9993 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -2,3 +2,4 @@ /* Templated TCGv_i32 and TCGv_i64 operations */ =20 DEF2(mov, TCGV, TCGV) +DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4b8dfba8a9..d7272b08cd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -370,6 +370,11 @@ void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *= src) } } =20 +void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t src) +{ + tcg_gen_op_tt(INDEX_op_mov, type, dst, tcg_constant_internal(type, src= )); +} + /* 32 bit ops */ =20 void tcg_gen_discard_i32(TCGv_i32 arg) @@ -377,11 +382,6 @@ void tcg_gen_discard_i32(TCGv_i32 arg) tcg_gen_op1_i32(INDEX_op_discard, TCG_TYPE_I32, arg); } =20 -void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) -{ - tcg_gen_mov_i32(ret, tcg_constant_i32(arg)); -} - void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_add, ret, arg1, arg2); @@ -1444,11 +1444,6 @@ void tcg_gen_discard_i64(TCGv_i64 arg) tcg_gen_op1_i64(INDEX_op_discard, TCG_TYPE_I64, arg); } =20 -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) -{ - tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); -} - void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld8u, ret, arg2, offset); @@ -2778,3 +2773,8 @@ void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) { tcg_gen_mov(TCG_TYPE_PTR, tcgv_ptr_temp(d), tcgv_ptr_temp(s)); } + +void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) +{ + tcg_gen_movi(TCG_TYPE_PTR, tcgv_ptr_temp(d), s); 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Wed, 21 Oct 2026 07:17:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 009/100] tcg: Generic expansion of tcg_gen_discard_* Date: Wed, 21 Oct 2026 16:15:21 +0200 Message-ID: <20261021141652.363109-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592345520158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 11 ++++------- tcg/tcg-internal.h | 3 +++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 35 +++++++++++++++-------------------- 4 files changed, 23 insertions(+), 27 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9dc05cc7b7..6168af878a 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -92,6 +92,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminf= o); * Construct operations from templates. */ =20 +#define DEF1(NAME, T1) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1); #define DEF2(NAME, T1, T2) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2); =20 @@ -113,6 +115,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); #undef TINT #undef TCGV =20 +#undef DEF1 #undef DEF2 =20 /* 32 bit ops */ @@ -197,8 +200,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 -void tcg_gen_discard_i32(TCGv_i32 arg); - void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); @@ -317,7 +318,6 @@ void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); =20 -void tcg_gen_discard_i64(TCGv_i64 arg); void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); @@ -541,10 +541,7 @@ static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr= a, intptr_t o) glue(tcg_gen_st_, PTR)((NAT)r, a, o); } =20 -static inline void tcg_gen_discard_ptr(TCGv_ptr a) -{ - glue(tcg_gen_discard_,PTR)((NAT)a); -} +QEMU_ARG_NONNULL void tcg_gen_discard_ptr(TCGv_ptr a); =20 static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) { diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 3568157ebb..ed1f5f20f8 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -124,6 +124,8 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); * Declarations of templated TCGv_i32 and TCGv_i64 operations. */ =20 +#define DEF1(NAME, T1) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1); #define DEF2(NAME, T1, T2) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2); =20 @@ -135,6 +137,7 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); #undef TINT #undef TCGV =20 +#undef DEF1 #undef DEF2 =20 #endif /* TCG_INTERNAL_H */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index e55a9f9993..8c61a75cd0 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* Templated TCGv_i32 and TCGv_i64 operations */ =20 +DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index d7272b08cd..ffddb3c19d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -114,16 +114,6 @@ TCGOp * NI tcg_gen_op6(TCGOpcode opc, TCGType type, TC= GArg a1, TCGArg a2, # define DNI #endif =20 -static void DNI tcg_gen_op1_i32(TCGOpcode opc, TCGType type, TCGv_i32 a1) -{ - tcg_gen_op1(opc, type, tcgv_i32_arg(a1)); -} - -static void DNI tcg_gen_op1_i64(TCGOpcode opc, TCGType type, TCGv_i64 a1) -{ - tcg_gen_op1(opc, type, tcgv_i64_arg(a1)); -} - static TCGOp * DNI tcg_gen_op1i(TCGOpcode opc, TCGType type, TCGArg a1) { return tcg_gen_op1(opc, type, a1); @@ -319,6 +309,10 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) * Templated TCGv_i32 and TCGv_i64 operations. */ =20 +#define DEF1(NAME, T1) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a)); } + #define DEF2(NAME, T1, T2) \ void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b) \ { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b)); } @@ -355,6 +349,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #undef C_int32_t #undef C_int64_t =20 +#undef DEF1 #undef DEF2 =20 /* @@ -363,6 +358,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) * are of the proper type. */ =20 +void tcg_gen_discard(TCGType type, TCGTemp *src) +{ + tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -377,11 +377,6 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t = src) =20 /* 32 bit ops */ =20 -void tcg_gen_discard_i32(TCGv_i32 arg) -{ - tcg_gen_op1_i32(INDEX_op_discard, TCG_TYPE_I32, arg); -} - void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_add, ret, arg1, arg2); @@ -1439,11 +1434,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tc= g_target_long offset) =20 /* 64-bit ops */ =20 -void tcg_gen_discard_i64(TCGv_i64 arg) -{ - tcg_gen_op1_i64(INDEX_op_discard, TCG_TYPE_I64, arg); -} - void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld8u, ret, arg2, offset); @@ -2769,6 +2759,11 @@ void tcg_gen_lookup_and_goto_ptr(void) =20 /* Host pointer operations */ =20 +void tcg_gen_discard_ptr(TCGv_ptr s) +{ + tcg_gen_discard(TCG_TYPE_PTR, tcgv_ptr_temp(s)); +} + void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) { tcg_gen_mov(TCG_TYPE_PTR, tcgv_ptr_temp(d), tcgv_ptr_temp(s)); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:17:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 010/100] tcg: Generic expansion of tcg_gen_add_* Date: Wed, 21 Oct 2026 16:15:22 +0200 Message-ID: <20261021141652.363109-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592871243158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 11 ++++------- tcg/tcg-internal.h | 9 +++++++++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 26 ++++++++++++++++---------- 4 files changed, 30 insertions(+), 17 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 6168af878a..879cc85bc9 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -96,6 +96,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminf= o); QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1); #define DEF2(NAME, T1, T2) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2); +#define DEF3(NAME, T1, T2, T3) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3); =20 #define TCGV glue(TCGv,TExt) #define TExt _i32 @@ -117,6 +119,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 #undef DEF1 #undef DEF2 +#undef DEF3 =20 /* 32 bit ops */ =20 @@ -210,7 +213,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -315,7 +317,6 @@ void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 -void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); =20 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); @@ -542,11 +543,7 @@ static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr= a, intptr_t o) } =20 QEMU_ARG_NONNULL void tcg_gen_discard_ptr(TCGv_ptr a); - -static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) -{ - glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); -} +QEMU_ARG_NONNULL void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b); =20 static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) { diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index ed1f5f20f8..0da1a9c440 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -108,6 +108,12 @@ static inline void tcg_gen_op_tt(TCGOpcode opc, TCGTyp= e type, tcg_gen_op2(opc, type, temp_arg(t0), temp_arg(t1)); } =20 +static inline void tcg_gen_op_ttt(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1, TCGTemp *t2) +{ + tcg_gen_op3(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2)); +} + QEMU_RET_ARG_NONNULL TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode, TCGType, unsigned nargs); @@ -128,6 +134,8 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1); #define DEF2(NAME, T1, T2) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2); +#define DEF3(NAME, T1, T2, T3) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3); =20 #define TCGV TCGTemp * #define TINT int64_t @@ -139,5 +147,6 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); =20 #undef DEF1 #undef DEF2 +#undef DEF3 =20 #endif /* TCG_INTERNAL_H */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 8c61a75cd0..73b1ec3d05 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: MIT */ /* Templated TCGv_i32 and TCGv_i64 operations */ =20 +DEF3(add, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ffddb3c19d..83ecbaae8b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -317,6 +317,10 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b) \ { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b)); } =20 +#define DEF3(NAME, T1, T2, T3) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), glue(C_,T3)(c))= ; } + #define C_TCGv_i32 tcgv_i32_temp #define C_TCGv_i64 tcgv_i64_temp #define C_int32_t @@ -351,6 +355,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) =20 #undef DEF1 #undef DEF2 +#undef DEF3 =20 /* * Generic expansions for templated operations. @@ -358,6 +363,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) * are of the proper type. */ =20 +void tcg_gen_add(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_add, type, dst, src1, src2); +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -377,11 +387,6 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t = src) =20 /* 32 bit ops */ =20 -void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_add, ret, arg1, arg2); -} - void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* some cases can be optimized here */ @@ -1489,11 +1494,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_add, ret, arg1, arg2); -} - void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_sub, ret, arg1, arg2); @@ -2759,6 +2759,12 @@ void tcg_gen_lookup_and_goto_ptr(void) =20 /* Host pointer operations */ =20 +void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) +{ + tcg_gen_add(TCG_TYPE_PTR, tcgv_ptr_temp(r), + tcgv_ptr_temp(a), tcgv_ptr_temp(b)); +} + void tcg_gen_discard_ptr(TCGv_ptr s) { tcg_gen_discard(TCG_TYPE_PTR, tcgv_ptr_temp(s)); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:17:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 011/100] tcg: Generic expansion of tcg_gen_addi_* Date: Wed, 21 Oct 2026 16:15:23 +0200 Message-ID: <20261021141652.363109-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592304701158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 9 +-------- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 34 ++++++++++++++-------------------- 3 files changed, 16 insertions(+), 28 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 879cc85bc9..61eced5ad1 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -226,7 +225,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); @@ -544,12 +542,7 @@ static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr= a, intptr_t o) =20 QEMU_ARG_NONNULL void tcg_gen_discard_ptr(TCGv_ptr a); QEMU_ARG_NONNULL void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b); - -static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) -{ - glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); -} - +QEMU_ARG_NONNULL void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b); QEMU_ARG_NONNULL void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s); QEMU_ARG_NONNULL void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s); =20 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 73b1ec3d05..faa83a09b2 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -2,6 +2,7 @@ /* Templated TCGv_i32 and TCGv_i64 operations */ =20 DEF3(add, TCGV, TCGV, TCGV) +DEF3(addi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 83ecbaae8b..9544688daf 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -368,6 +368,15 @@ void tcg_gen_add(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_add, type, dst, src1, src2); } =20 +void tcg_gen_addi(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else { + tcg_gen_add(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -387,16 +396,6 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t = src) =20 /* 32 bit ops */ =20 -void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else { - tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_sub, ret, arg1, arg2); @@ -1534,16 +1533,6 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); } =20 -void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* some cases can be optimized here */ - if (arg2 =3D=3D 0) { - tcg_gen_mov_i64(ret, arg1); - } else { - tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); - } -} - void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) { if (arg1 =3D=3D 0) { @@ -2765,6 +2754,11 @@ void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_pt= r b) tcgv_ptr_temp(a), tcgv_ptr_temp(b)); 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Wed, 21 Oct 2026 07:17:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 012/100] tcg: Generic expansion of tcg_gen_sub_* Date: Wed, 21 Oct 2026 16:15:24 +0200 Message-ID: <20261021141652.363109-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592365853158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 3 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 13 ++++--------- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 61eced5ad1..e2e8c66d01 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -212,7 +212,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -315,8 +314,6 @@ void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 -void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); - void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index faa83a09b2..51d5ec6e06 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -6,3 +6,4 @@ DEF3(addi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) +DEF3(sub, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 9544688daf..563c3bb038 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -394,13 +394,13 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t= src) tcg_gen_op_tt(INDEX_op_mov, type, dst, tcg_constant_internal(type, src= )); } =20 -/* 32 bit ops */ - -void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { - tcg_gen_op3_i32(INDEX_op_sub, ret, arg1, arg2); + tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); } =20 +/* 32 bit ops */ + void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) { if (arg1 =3D=3D 0) { @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_sub, ret, arg1, arg2); -} - void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_and, ret, arg1, arg2); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:17:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 013/100] tcg: Generic expansion of tcg_gen_subi_* Date: Wed, 21 Oct 2026 16:15:25 +0200 Message-ID: <20261021141652.363109-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592294539158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index e2e8c66d01..372be70504 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -124,7 +124,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); -void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -225,7 +224,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); /* 64 bit ops */ =20 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); -void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 51d5ec6e06..55249c4dd6 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -7,3 +7,4 @@ DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF3(sub, TCGV, TCGV, TCGV) +DEF3(subi, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 563c3bb038..4239219279 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -399,6 +399,11 @@ void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); } =20 +void tcg_gen_subi(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + tcg_gen_addi(type, dst, src1, -src2); +} + /* 32 bit ops */ =20 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) @@ -410,11 +415,6 @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCG= v_i32 arg2) } } =20 -void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_gen_addi_i32(ret, arg1, -arg2); -} - void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) { tcg_gen_op2_i32(INDEX_op_neg, ret, arg); @@ -1537,11 +1537,6 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, T= CGv_i64 arg2) } } =20 -void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_addi_i64(ret, arg1, -arg2); -} - void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_op2_i64(INDEX_op_neg, ret, arg); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:17:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 014/100] tcg: Generic expansion of tcg_gen_neg_* Date: Wed, 21 Oct 2026 16:15:26 +0200 Message-ID: <20261021141652.363109-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592514532158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 3 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 13 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 372be70504..d7b40e6705 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -218,7 +218,6 @@ void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_= i32 arg2); void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ @@ -327,8 +326,6 @@ void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_= i64 arg2); void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg); - =20 /* Size changing operations. */ =20 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 55249c4dd6..b5ede94511 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -6,5 +6,6 @@ DEF3(addi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) +DEF2(neg, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4239219279..bb34f883e8 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -394,6 +394,11 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t = src) tcg_gen_op_tt(INDEX_op_mov, type, dst, tcg_constant_internal(type, src= )); } =20 +void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_op_tt(INDEX_op_neg, type, dst, src); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -415,11 +420,6 @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCG= v_i32 arg2) } } =20 -void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - tcg_gen_op2_i32(INDEX_op_neg, ret, arg); -} - void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_and, ret, arg1, arg2); @@ -1537,11 +1537,6 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, T= CGv_i64 arg2) } } =20 -void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_op2_i64(INDEX_op_neg, ret, arg); -} - void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { /* Some cases can be optimized here. */ --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Wed, 21 Oct 2026 07:17:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 015/100] tcg: Generic expansion of tcg_gen_subfi_* Date: Wed, 21 Oct 2026 16:15:27 +0200 Message-ID: <20261021141652.363109-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592341446158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 21 ++++++--------------- 3 files changed, 7 insertions(+), 17 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index d7b40e6705..03f3cba216 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -222,7 +221,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index b5ede94511..487ee5936e 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -9,3 +9,4 @@ DEF2(movi, TCGV, TINT) DEF2(neg, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) +DEF3(subfi, TCGV, TINT, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index bb34f883e8..cdb9774ca6 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -409,17 +409,17 @@ void tcg_gen_subi(TCGType type, TCGTemp *dst, TCGTemp= *src1, int64_t src2) tcg_gen_addi(type, dst, src1, -src2); } =20 -/* 32 bit ops */ - -void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) +void tcg_gen_subfi(TCGType type, TCGTemp *dst, int64_t src1, TCGTemp *src2) { - if (arg1 =3D=3D 0) { - tcg_gen_neg_i32(ret, arg2); + if (src1 =3D=3D 0) { + tcg_gen_neg(type, dst, src2); } else { - tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); + tcg_gen_sub(type, dst, tcg_constant_internal(type, src1), src2); } } =20 +/* 32 bit ops */ + void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_op3_i32(INDEX_op_and, ret, arg1, arg2); @@ -1528,15 +1528,6 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); } =20 -void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) -{ - if (arg1 =3D=3D 0) { - tcg_gen_neg_i64(ret, arg2); - } else { - tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); - } -} - void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { /* Some cases can be optimized here. */ --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:17:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 016/100] tcg: Generic expansion of tcg_gen_and_* Date: Wed, 21 Oct 2026 16:15:28 +0200 Message-ID: <20261021141652.363109-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592771268158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 03f3cba216..54ed9c9f6e 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -317,7 +316,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 487ee5936e..d6b45004a2 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -3,6 +3,7 @@ =20 DEF3(add, TCGV, TCGV, TCGV) DEF3(addi, TCGV, TCGV, TINT) +DEF3(and, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cdb9774ca6..4e7ff03b34 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -377,6 +377,11 @@ void tcg_gen_addi(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_and(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_and, type, dst, src1, src2); +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -420,11 +425,6 @@ void tcg_gen_subfi(TCGType type, TCGTemp *dst, int64_t= src1, TCGTemp *src2) =20 /* 32 bit ops */ =20 -void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_and, ret, arg1, arg2); -} - void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* Some cases can be optimized here. */ @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_and, ret, arg1, arg2); -} - void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_or, ret, arg1, arg2); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592517; cv=none; d=zohomail.com; s=zohoarc; b=KXowNlsVnK83txuB21TdYg101pR1YtRdnNIXH5YOFEBsrueFInx3jhCHZXQ86dWiyOArYYip7tzY8UODvQWsl1pl8lstyQzdSdOJW4d1xywmSxtOLxgyy2P6Y8kn8FE0Q909xnPJmv9Le4qv/ELRqXJmY9QvFpLBqFQhUZU2Yjo= ARC-Message-Signature: i=1; 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Wed, 21 Oct 2026 07:17:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 017/100] tcg: Generic expansion of tcg_gen_or_* Date: Wed, 21 Oct 2026 16:15:29 +0200 Message-ID: <20261021141652.363109-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592518553158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 54ed9c9f6e..9cb9089a90 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -316,7 +315,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index d6b45004a2..8dd3929060 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -8,6 +8,7 @@ DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF2(neg, TCGV, TCGV) +DEF3(or, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4e7ff03b34..b330d0fdb5 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -404,6 +404,11 @@ void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *= src) tcg_gen_op_tt(INDEX_op_neg, type, dst, src); } =20 +void tcg_gen_or(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_or, type, dst, src1, src2); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -455,11 +460,6 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int= 32_t arg2) tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2)); 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Wed, 21 Oct 2026 07:17:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 018/100] tcg: Generic expansion of tcg_gen_xor_* Date: Wed, 21 Oct 2026 16:15:30 +0200 Message-ID: <20261021141652.363109-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592606330158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9cb9089a90..7ff99a7671 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -315,7 +314,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 8dd3929060..ad298b7e30 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -12,3 +12,4 @@ DEF3(or, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) +DEF3(xor, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b330d0fdb5..5a0c7246d1 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -428,6 +428,11 @@ void tcg_gen_subfi(TCGType type, TCGTemp *dst, int64_t= src1, TCGTemp *src2) } } =20 +void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_xor, type, dst, src1, src2); +} + /* 32 bit ops */ =20 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) @@ -472,11 +477,6 @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int3= 2_t arg2) } } =20 -void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_xor, ret, arg1, arg2); -} - void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* Some cases can be optimized here. */ @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_xor, ret, arg1, arg2); -} - void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_shl, ret, arg1, arg2); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592541; cv=none; d=zohomail.com; s=zohoarc; b=FXaXYDn42aEucXer1bf2IE8VK7Nbmbmdv4lgfsWvU5rwnfzj5wP/L/ocDckBIivicVYn6oRh/KahNvHuSp46lwqyDCM8DghtNKsdLb/B3NVEtO36y3pLHrLPpO+ePAQHrIhtyJ/5BYzxYYb5LLOo5TNS6kxsI42R5SWS+StHdPc= ARC-Message-Signature: i=1; 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Wed, 21 Oct 2026 07:18:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 019/100] tcg: Generic expansion of tcg_gen_shl_* Date: Wed, 21 Oct 2026 16:15:31 +0200 Message-ID: <20261021141652.363109-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592543015158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 7ff99a7671..e1c59b1915 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -314,7 +313,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index ad298b7e30..3e6dd1eaf9 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -9,6 +9,7 @@ DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) +DEF3(shl, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 5a0c7246d1..7cbfcad24a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -409,6 +409,11 @@ void tcg_gen_or(TCGType type, TCGTemp *dst, TCGTemp *s= rc1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_or, type, dst, src1, src2); } =20 +void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -500,11 +505,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_shl, ret, arg1, arg2); -} - void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_shl, ret, arg1, arg2); -} - void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_shr, ret, arg1, arg2); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592654; cv=none; d=zohomail.com; s=zohoarc; b=UxSuHpPmVTJi85nuHVkx4okqi9xsnk/SrLSxmzEmvVmOiS8tjnQpiTlBV8H6xR6iyWJKRTYT+QFXEVmDTnBpjx6HDXVSyTY3yMkseEOnxGp1uR8r5niI1Go9GoUnL77PX8B7PD/cJ1Nure/dESydYYlX36ltdaoFCCbzJhnZDz8= ARC-Message-Signature: i=1; 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Wed, 21 Oct 2026 07:18:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 020/100] tcg: Generic expansion of tcg_gen_shr_* Date: Wed, 21 Oct 2026 16:15:32 +0200 Message-ID: <20261021141652.363109-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592655369158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index e1c59b1915..96d351e634 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -313,7 +312,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); =20 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 3e6dd1eaf9..573a4963b4 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -10,6 +10,7 @@ DEF2(movi, TCGV, TINT) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(shl, TCGV, TCGV, TCGV) +DEF3(shr, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7cbfcad24a..3c98d204d4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -414,6 +414,11 @@ void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); } =20 +void tcg_gen_shr(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_shr, type, dst, src1, src2); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -515,11 +520,6 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int= 32_t arg2) } } =20 -void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_shr, ret, arg1, arg2); -} - void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_shr, ret, arg1, arg2); -} - void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_sar, ret, arg1, arg2); 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Wed, 21 Oct 2026 07:18:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 021/100] tcg: Generic expansion of tcg_gen_sar_* Date: Wed, 21 Oct 2026 16:15:33 +0200 Message-ID: <20261021141652.363109-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593329215158501 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 96d351e634..74cff518ce 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 @@ -312,7 +311,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); =20 /* Size changing operations. */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 573a4963b4..96bd6abd74 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -9,6 +9,7 @@ DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) +DEF3(sar, TCGV, TCGV, TCGV) DEF3(shl, TCGV, TCGV, TCGV) DEF3(shr, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3c98d204d4..07e7c83ffb 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -409,6 +409,11 @@ void tcg_gen_or(TCGType type, TCGTemp *dst, TCGTemp *s= rc1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_or, type, dst, src1, src2); } =20 +void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); +} + void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); @@ -530,11 +535,6 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int= 32_t arg2) } } =20 -void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_sar, ret, arg1, arg2); -} - void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_sar, ret, arg1, arg2); -} - void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); 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Wed, 21 Oct 2026 07:18:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 022/100] tcg: Generic expansion of tcg_gen_mul_* Date: Wed, 21 Oct 2026 16:15:34 +0200 Message-ID: <20261021141652.363109-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592384116158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 74cff518ce..76e67acab8 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -210,7 +210,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ @@ -311,7 +310,6 @@ void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); =20 /* Size changing operations. */ =20 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 96bd6abd74..c1273a1019 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -7,6 +7,7 @@ DEF3(and, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) +DEF3(mul, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 07e7c83ffb..1e85ff545b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -399,6 +399,11 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t = src) tcg_gen_op_tt(INDEX_op_mov, type, dst, tcg_constant_internal(type, src= )); } =20 +void tcg_gen_mul(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + tcg_gen_op_ttt(INDEX_op_mul, type, dst, src1, src2); +} + void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *src) { tcg_gen_op_tt(INDEX_op_neg, type, dst, src); @@ -601,11 +606,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_mul, ret, arg1, arg2); -} - void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { if (arg2 =3D=3D 0) { @@ -1493,11 +1493,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); -} - void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { /* Some cases can be optimized here. */ --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:18:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 023/100] tcg: Generic expansion of tcg_gen_shli_* Date: Wed, 21 Oct 2026 16:15:35 +0200 Message-ID: <20261021141652.363109-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592704144158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 30 ++++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 76e67acab8..dec1bb522c 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -126,7 +126,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -217,7 +216,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index c1273a1019..c47de1a3a4 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -12,6 +12,7 @@ DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(shl, TCGV, TCGV, TCGV) +DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1e85ff545b..8fcbbef694 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -424,6 +424,16 @@ void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); } =20 +void tcg_gen_shli(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + tcg_debug_assert(src2 >=3D 0 && src2 < tcg_type_bits(type)); + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else { + tcg_gen_shl(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_shr(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_shr, type, dst, src1, src2); @@ -520,16 +530,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else { - tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1549,16 +1549,6 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) } } =20 -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); 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Wed, 21 Oct 2026 07:18:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 024/100] tcg: Generic expansion of tcg_gen_shri_* Date: Wed, 21 Oct 2026 16:15:36 +0200 Message-ID: <20261021141652.363109-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592394339158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 30 ++++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index dec1bb522c..e0a93144cb 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -126,7 +126,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -216,7 +215,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index c47de1a3a4..ea641158ae 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -14,6 +14,7 @@ DEF3(sar, TCGV, TCGV, TCGV) DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) +DEF3(shri, TCGV, TCGV, TINT) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8fcbbef694..b3f688228d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -439,6 +439,16 @@ void tcg_gen_shr(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_shr, type, dst, src1, src2); } =20 +void tcg_gen_shri(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + tcg_debug_assert(src2 >=3D 0 && src2 < tcg_type_bits(type)); + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else { + tcg_gen_shr(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -530,16 +540,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else { - tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1549,16 +1549,6 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) } } =20 -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); 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Wed, 21 Oct 2026 07:18:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 025/100] tcg: Generic expansion of tcg_gen_sari_* Date: Wed, 21 Oct 2026 16:15:37 +0200 Message-ID: <20261021141652.363109-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592993298158501 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 30 ++++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index e0a93144cb..7ca448b922 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -126,7 +126,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -215,7 +214,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index ea641158ae..2108082ce6 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -11,6 +11,7 @@ DEF3(mul, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) +DEF3(sari, TCGV, TCGV, TINT) DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b3f688228d..8c298ae79a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -419,6 +419,16 @@ void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); } =20 +void tcg_gen_sari(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + tcg_debug_assert(src2 >=3D 0 && src2 < tcg_type_bits(type)); + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else { + tcg_gen_sar(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); @@ -540,16 +550,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else { - tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *l) { if (cond =3D=3D TCG_COND_ALWAYS) { @@ -1549,16 +1549,6 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, i= nt64_t arg2) } } =20 -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); 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Wed, 21 Oct 2026 07:18:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 026/100] tcg: Generic expansion of tcg_gen_andi_* Date: Wed, 21 Oct 2026 16:15:38 +0200 Message-ID: <20261021141652.363109-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592384181158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 - tcg/tcg-internal.h | 6 +++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 84 +++++++++++------------------------- 4 files changed, 31 insertions(+), 62 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 7ca448b922..1108d185e8 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -211,7 +210,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 0da1a9c440..76c8f026a6 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -114,6 +114,12 @@ static inline void tcg_gen_op_ttt(TCGOpcode opc, TCGTy= pe type, tcg_gen_op3(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2)); } =20 +static inline TCGOp *tcg_gen_op_ttii(TCGOpcode opc, TCGType type, TCGTemp = *t0, + TCGTemp *t1, TCGArg a2, TCGArg a3) +{ + return tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), a2, a3); +} + QEMU_RET_ARG_NONNULL TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode, TCGType, unsigned nargs); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 2108082ce6..f7e7f4d2a1 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -4,6 +4,7 @@ DEF3(add, TCGV, TCGV, TCGV) DEF3(addi, TCGV, TCGV, TINT) DEF3(and, TCGV, TCGV, TCGV) +DEF3(andi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8c298ae79a..34e1e736be 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -382,6 +382,30 @@ void tcg_gen_and(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_and, type, dst, src1, src2); } =20 +void tcg_gen_andi(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + if (src2 =3D=3D 0) { + tcg_gen_movi(type, dst, 0); + } else if (src2 =3D=3D -1) { + tcg_gen_mov(type, dst, src1); + } else { + /* + * Canonicalize on extract, if valid. This aids x86 with its + * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode + * which does not require matching operands. Other backends can + * trivially expand the extract to AND during code generation. + */ + if (is_power_of_2(src2 + 1)) { + unsigned len =3D cto64(src2); + if (TCG_TARGET_extract_valid(type, 0, len)) { + tcg_gen_op_ttii(INDEX_op_extract, type, dst, src1, 0, len); + return; + } + } + tcg_gen_and(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -485,36 +509,6 @@ void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) =20 /* 32 bit ops */ =20 -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* Some cases can be optimized here. */ - switch (arg2) { - case 0: - tcg_gen_movi_i32(ret, 0); - return; - case -1: - tcg_gen_mov_i32(ret, arg1); - return; - default: - /* - * Canonicalize on extract, if valid. This aids x86 with its - * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode - * which does not require matching operands. Other backends can - * trivially expand the extract to AND during code generation. - */ - if (!(arg2 & (arg2 + 1))) { - unsigned len =3D ctz32(~arg2); - if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, len)) { - tcg_gen_extract_i32(ret, arg1, 0, len); - return; - } - } - break; - } - - tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2)); -} - void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* Some cases can be optimized here. */ @@ -1493,36 +1487,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* Some cases can be optimized here. */ - switch (arg2) { - case 0: - tcg_gen_movi_i64(ret, 0); - return; - case -1: - tcg_gen_mov_i64(ret, arg1); - return; - default: - /* - * Canonicalize on extract, if valid. This aids x86 with its - * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode - * which does not require matching operands. Other backends can - * trivially expand the extract to AND during code generation. - */ - if (!(arg2 & (arg2 + 1))) { - unsigned len =3D ctz64(~arg2); - if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, len)) { - tcg_gen_extract_i64(ret, arg1, 0, len); - return; - } - } - break; - } - - tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2)); -} - void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { /* Some cases can be optimized here. */ --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592468; cv=none; d=zohomail.com; s=zohoarc; b=IgXD0ZlbtmycQBjtf+dO904lGvT3mbstjQBTYmb5al3MX03rOBp2cyjcMkd+sY4NJ+QladyVE9aKEcQx/mvGZaRE7HWKBOygBdBC0t3RQgZ3QFVHEbM+iuA3f9vT8zQWi3d0wRJpwp9rTuEIsKzD8UyqFvbJCDal+M9tdu8ooqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792592468; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0ES8mmtHULSKmA9zK4IaqJ2RmQ11CWJa0mSyK5YF43E=; b=R7Ze8XfA1vJAWOYgzhQv/6MWjTzosl4tvyA26bDyMGLfbcbIzp9TT7ESIDI2k8vD1m75Pn/3DbWXi3ym6wsaLO7bM74/AOwdoQUCiGsT5sR5DYyneVLKgRTtn/NQYWUG966M4NKp2K/DsJsD+V15mO8kpkvCk/EkbBwE1huQX8c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792592468469172.74394773878782; Wed, 21 Oct 2026 07:21:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJXAM-0006jq-En; Wed, 21 Oct 2026 10:19:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJX9j-00057Q-PL for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:19:09 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xJX9h-0001gC-Vg for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:19:03 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-48df4e9d2d4so504054f8f.3 for ; Wed, 21 Oct 2026 07:19:01 -0700 (PDT) Received: from stoup.fritz.box (pd95f64ec.dip0.t-ipconnect.de. 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Wed, 21 Oct 2026 07:19:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 027/100] tcg: Generic expansion of tcg_gen_ori_* Date: Wed, 21 Oct 2026 16:15:39 +0200 Message-ID: <20261021141652.363109-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592469822158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 35 +++++++++++------------------------ 3 files changed, 12 insertions(+), 26 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 1108d185e8..dc5c7f7cb2 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -210,7 +209,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index f7e7f4d2a1..f7a7dc69c9 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -11,6 +11,7 @@ DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) +DEF3(ori, TCGV, TCGV, TINT) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF3(shl, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 34e1e736be..668c946c03 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -438,6 +438,17 @@ void tcg_gen_or(TCGType type, TCGTemp *dst, TCGTemp *s= rc1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_or, type, dst, src1, src2); } =20 +void tcg_gen_ori(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + if (src2 =3D=3D -1) { + tcg_gen_movi(type, dst, -1); + } else if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else { + tcg_gen_or(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); @@ -509,18 +520,6 @@ void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) =20 /* 32 bit ops */ =20 -void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - /* Some cases can be optimized here. */ - if (arg2 =3D=3D -1) { - tcg_gen_movi_i32(ret, -1); - } else if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else { - tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { /* Some cases can be optimized here. */ @@ -1487,18 +1486,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); 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Wed, 21 Oct 2026 07:19:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 028/100] tcg: Generic expansion of tcg_gen_xori_* Date: Wed, 21 Oct 2026 16:15:40 +0200 Message-ID: <20261021141652.363109-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592594088158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 34 +++++++++------------------------- 3 files changed, 10 insertions(+), 27 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index dc5c7f7cb2..dd4e7f6686 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -209,7 +208,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index f7a7dc69c9..b38969478a 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -22,3 +22,4 @@ DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) DEF3(xor, TCGV, TCGV, TCGV) +DEF3(xori, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 668c946c03..cc34e0f31f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -518,22 +518,20 @@ void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_xor, type, dst, src1, src2); } =20 -/* 32 bit ops */ - -void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) { - /* Some cases can be optimized here. */ - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else if (arg2 =3D=3D -1 && - tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) { - /* Don't recurse with tcg_gen_not_i32. */ - tcg_gen_op2_i32(INDEX_op_not, ret, arg1); + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else if (src2 =3D=3D -1 && tcg_op_supported(INDEX_op_not, type, 0)) { + /* Do not recurse with gen_not. */ + tcg_gen_op_tt(INDEX_op_not, type, dst, src1); } else { - tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2)); + tcg_gen_xor(type, dst, src1, tcg_constant_internal(type, src2)); } } =20 +/* 32 bit ops */ + void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) { if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) { @@ -1486,20 +1484,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - /* Some cases can be optimized here. */ - if (arg2 =3D=3D 0) { - tcg_gen_mov_i64(ret, arg1); - } else if (arg2 =3D=3D -1 && - tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { - /* Don't recurse with tcg_gen_not_i64. */ - tcg_gen_op2_i64(INDEX_op_not, ret, arg1); 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Wed, 21 Oct 2026 07:19:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 029/100] tcg: Generic expansion of tcg_gen_muli_* Date: Wed, 21 Oct 2026 16:15:41 +0200 Message-ID: <20261021141652.363109-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592862896158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 33 +++++++++++---------------------- 3 files changed, 12 insertions(+), 24 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index dd4e7f6686..2b2653d07c 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -208,7 +207,6 @@ void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 -void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index b38969478a..abea00e7e0 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -9,6 +9,7 @@ DEF1(discard, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) +DEF3(muli, TCGV, TCGV, TINT) DEF2(neg, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cc34e0f31f..23aeea8026 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -428,6 +428,17 @@ void tcg_gen_mul(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_gen_op_ttt(INDEX_op_mul, type, dst, src1, src2); } =20 +void tcg_gen_muli(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + if (src2 =3D=3D 0) { + tcg_gen_movi(type, dst, 0); + } else if (is_power_of_2(src2)) { + tcg_gen_shli(type, dst, src1, ctz64(src2)); + } else { + tcg_gen_mul(type, dst, src1, tcg_constant_internal(type, src2)); + } +} + void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *src) { tcg_gen_op_tt(INDEX_op_neg, type, dst, src); @@ -597,17 +608,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - if (arg2 =3D=3D 0) { - tcg_gen_movi_i32(ret, 0); - } else if (is_power_of_2(arg2)) { - tcg_gen_shli_i32(ret, arg1, ctz32(arg2)); - } else { - tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) { @@ -1536,17 +1536,6 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 r= et, } } =20 -void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - if (arg2 =3D=3D 0) { - tcg_gen_movi_i64(ret, 0); - } else if (is_power_of_2(arg2)) { - tcg_gen_shli_i64(ret, arg1, ctz64(arg2)); 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Wed, 21 Oct 2026 07:19:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 030/100] tcg: Generic expansion of tcg_gen_not_* Date: Wed, 21 Oct 2026 16:15:42 +0200 Message-ID: <20261021141652.363109-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592543016158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 3 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 28 ++++++++++------------------ 3 files changed, 11 insertions(+), 21 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 2b2653d07c..df6563af9b 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -203,8 +203,6 @@ void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 -void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg); - /* 64 bit ops */ =20 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); @@ -258,7 +256,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, = TCGv_i64 *b); void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); -void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index abea00e7e0..8c9d3d99c4 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -11,6 +11,7 @@ DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) DEF2(neg, TCGV, TCGV) +DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) DEF3(sar, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 23aeea8026..9b3974fb8a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -444,6 +444,16 @@ void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *= src) tcg_gen_op_tt(INDEX_op_neg, type, dst, src); } =20 +void tcg_gen_not(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + if (tcg_op_supported(INDEX_op_not, type, 0)) { + tcg_gen_op_tt(INDEX_op_not, type, dst, src); + } else { + /* Do not recurse with gen_xori. */ + tcg_gen_xor(type, dst, src, tcg_constant_internal(type, -1)); + } +} + void tcg_gen_or(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_or, type, dst, src1, src2); @@ -543,15 +553,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) { - tcg_gen_op2_i32(INDEX_op_not, ret, arg); - } else { - tcg_gen_xori_i32(ret, arg, -1); - } -} - void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *l) { if (cond =3D=3D TCG_COND_ALWAYS) { @@ -1803,15 +1804,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { - tcg_gen_op2_i64(INDEX_op_not, ret, arg); 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- accel/tcg/tcg-runtime.h | 10 ---------- accel/tcg/tcg-runtime.c | 44 ----------------------------------------- tcg/tcg-op.c | 16 +++++++-------- 3 files changed, 8 insertions(+), 62 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 0b832176b3..003c963bc7 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -1,13 +1,3 @@ -DEF_HELPER_FLAGS_2(div_i32, TCG_CALL_NO_RWG_SE, s32, s32, s32) -DEF_HELPER_FLAGS_2(rem_i32, TCG_CALL_NO_RWG_SE, s32, s32, s32) -DEF_HELPER_FLAGS_2(divu_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_FLAGS_2(remu_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32) - -DEF_HELPER_FLAGS_2(div_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) -DEF_HELPER_FLAGS_2(rem_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) -DEF_HELPER_FLAGS_2(divu_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(remu_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) - DEF_HELPER_FLAGS_2(mulsh_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_2(muluh_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) =20 diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 7c0aab98a8..77c4024148 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -32,50 +32,6 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 -/* 32-bit helpers */ - -int32_t HELPER(div_i32)(int32_t arg1, int32_t arg2) -{ - return arg1 / arg2; -} - -int32_t HELPER(rem_i32)(int32_t arg1, int32_t arg2) -{ - return arg1 % arg2; -} - -uint32_t HELPER(divu_i32)(uint32_t arg1, uint32_t arg2) -{ - return arg1 / arg2; -} - -uint32_t HELPER(remu_i32)(uint32_t arg1, uint32_t arg2) -{ - return arg1 % arg2; -} - -/* 64-bit helpers */ - -int64_t HELPER(div_i64)(int64_t arg1, int64_t arg2) -{ - return arg1 / arg2; -} - -int64_t HELPER(rem_i64)(int64_t arg1, int64_t arg2) -{ - return arg1 % arg2; -} - -uint64_t HELPER(divu_i64)(uint64_t arg1, uint64_t arg2) -{ - return arg1 / arg2; -} - -uint64_t HELPER(remu_i64)(uint64_t arg1, uint64_t arg2) -{ - return arg1 % arg2; -} - uint64_t HELPER(muluh_i64)(uint64_t arg1, uint64_t arg2) { uint64_t l, h; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 9b3974fb8a..09e417b760 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -619,7 +619,7 @@ void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_= i32 arg2) tcg_gen_op5_i32(INDEX_op_divs2, ret, t0, arg1, t0, arg2); tcg_temp_free_i32(t0); } else { - gen_helper_div_i32(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -639,7 +639,7 @@ void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_= i32 arg2) tcg_gen_op5_i32(INDEX_op_divs2, t0, ret, arg1, t0, arg2); tcg_temp_free_i32(t0); } else { - gen_helper_rem_i32(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -653,7 +653,7 @@ void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv= _i32 arg2) tcg_gen_op5_i32(INDEX_op_divu2, ret, t0, arg1, zero, arg2); tcg_temp_free_i32(t0); } else { - gen_helper_divu_i32(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -673,7 +673,7 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv= _i32 arg2) tcg_gen_op5_i32(INDEX_op_divu2, t0, ret, arg1, zero, arg2); tcg_temp_free_i32(t0); } else { - gen_helper_remu_i32(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -1547,7 +1547,7 @@ void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCG= v_i64 arg2) tcg_gen_op5_i64(INDEX_op_divs2, ret, t0, arg1, t0, arg2); tcg_temp_free_i64(t0); } else { - gen_helper_div_i64(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -1567,7 +1567,7 @@ void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCG= v_i64 arg2) tcg_gen_op5_i64(INDEX_op_divs2, t0, ret, arg1, t0, arg2); tcg_temp_free_i64(t0); } else { - gen_helper_rem_i64(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -1581,7 +1581,7 @@ void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) tcg_gen_op5_i64(INDEX_op_divu2, ret, t0, arg1, zero, arg2); tcg_temp_free_i64(t0); } else { - gen_helper_divu_i64(ret, arg1, arg2); + g_assert_not_reached(); } } =20 @@ -1601,7 +1601,7 @@ void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) tcg_gen_op5_i64(INDEX_op_divu2, t0, ret, arg1, zero, arg2); tcg_temp_free_i64(t0); } else { - gen_helper_remu_i64(ret, arg1, arg2); + g_assert_not_reached(); } } =20 --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:19:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 032/100] tcg: Generic expansion of tcg_gen_div_* Date: Wed, 21 Oct 2026 16:15:44 +0200 Message-ID: <20261021141652.363109-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593182694158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- tcg/tcg-internal.h | 8 +++++++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 42 ++++++++++++------------------------ 4 files changed, 23 insertions(+), 30 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index df6563af9b..b0c5a1f5cf 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -205,7 +204,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 76c8f026a6..6b65228241 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -120,6 +120,14 @@ static inline TCGOp *tcg_gen_op_ttii(TCGOpcode opc, TC= GType type, TCGTemp *t0, return tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), a2, a3); } =20 +static inline void tcg_gen_op_ttttt(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, + TCGTemp *t3, TCGTemp *t4) +{ + tcg_gen_op5(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2), + temp_arg(t3), temp_arg(t4)); +} + QEMU_RET_ARG_NONNULL TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode, TCGType, unsigned nargs); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 8c9d3d99c4..778854286c 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -6,6 +6,7 @@ DEF3(addi, TCGV, TCGV, TINT) DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) DEF1(discard, TCGV) +DEF3(div, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 09e417b760..8854006022 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -411,6 +411,20 @@ void tcg_gen_discard(TCGType type, TCGTemp *src) tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); } =20 +void tcg_gen_div(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_divs, type, 0)) { + tcg_gen_op_ttt(INDEX_op_divs, type, dst, src1, src2); + } else if (tcg_op_supported(INDEX_op_divs2, type, 0)) { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_sari(type, tmp, src1, tcg_type_bits(type) - 1); + tcg_gen_op_ttttt(INDEX_op_divs2, type, dst, tmp, src1, tmp, src2); + } else { + g_assert_not_reached(); + } +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -609,20 +623,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_divs, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_sari_i32(t0, arg1, 31); - tcg_gen_op5_i32(INDEX_op_divs2, ret, t0, arg1, t0, arg2); - tcg_temp_free_i32(t0); - } else { - g_assert_not_reached(); - } -} - void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I32, 0)) { @@ -1537,20 +1537,6 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 r= et, } } =20 -void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_divs, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_sari_i64(t0, arg1, 63); - tcg_gen_op5_i64(INDEX_op_divs2, ret, t0, arg1, t0, arg2); - tcg_temp_free_i64(t0); - } else { - g_assert_not_reached(); - } -} - void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:19:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 033/100] tcg: Generic expansion of tcg_gen_rem_* Date: Wed, 21 Oct 2026 16:15:45 +0200 Message-ID: <20261021141652.363109-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593267959158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 60 ++++++++++++------------------------ 3 files changed, 21 insertions(+), 42 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index b0c5a1f5cf..eb090984e9 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -204,7 +203,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 778854286c..50d725b72c 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -15,6 +15,7 @@ DEF2(neg, TCGV, TCGV) DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) +DEF3(rem, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF3(shl, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8854006022..e194c33eb7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -484,6 +484,26 @@ void tcg_gen_ori(TCGType type, TCGTemp *dst, TCGTemp *= src1, int64_t src2) } } =20 +void tcg_gen_rem(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_rems, type, 0)) { + tcg_gen_op_ttt(INDEX_op_rems, type, dst, src1, src2); + } else { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + if (tcg_op_supported(INDEX_op_divs, type, 0)) { + tcg_gen_op_ttt(INDEX_op_divs, type, tmp, src1, src2); + tcg_gen_mul(type, tmp, tmp, src2); + tcg_gen_sub(type, dst, src1, tmp); + } else if (tcg_op_supported(INDEX_op_divs2, type, 0)) { + tcg_gen_sari(type, tmp, src1, tcg_type_bits(type) - 1); + tcg_gen_op_ttttt(INDEX_op_divs2, type, tmp, dst, src1, tmp, sr= c2); + } else { + g_assert_not_reached(); + } + } +} + void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); @@ -623,26 +643,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_rems, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_op3_i32(INDEX_op_divs, t0, arg1, arg2); - tcg_gen_mul_i32(t0, t0, arg2); - tcg_gen_sub_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); - } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_sari_i32(t0, arg1, 31); - tcg_gen_op5_i32(INDEX_op_divs2, t0, ret, arg1, t0, arg2); - tcg_temp_free_i32(t0); - } else { - g_assert_not_reached(); - } -} - void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) { @@ -1537,26 +1537,6 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 r= et, } } =20 -void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_rems, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_op3_i64(INDEX_op_divs, t0, arg1, arg2); - tcg_gen_mul_i64(t0, t0, arg2); - tcg_gen_sub_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); 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Wed, 21 Oct 2026 07:19:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 034/100] tcg: Generic expansion of tcg_gen_divu_* Date: Wed, 21 Oct 2026 16:15:46 +0200 Message-ID: <20261021141652.363109-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592441243158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 42 ++++++++++++------------------------ 3 files changed, 15 insertions(+), 30 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index eb090984e9..9024963c06 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -203,7 +202,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 50d725b72c..1b108d9f14 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -7,6 +7,7 @@ DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) +DEF3(divu, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e194c33eb7..1bfefb9d65 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -425,6 +425,20 @@ void tcg_gen_div(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) } } =20 +void tcg_gen_divu(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_divu, type, 0)) { + tcg_gen_op_ttt(INDEX_op_divu, type, dst, src1, src2); + } else if (tcg_op_supported(INDEX_op_divu2, type, 0)) { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_op_ttttt(INDEX_op_divu2, type, dst, tmp, src1, + tcg_constant_internal(type, 0), src2); + } else { + g_assert_not_reached(); + } +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -643,20 +657,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_divu, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 zero =3D tcg_constant_i32(0); - tcg_gen_op5_i32(INDEX_op_divu2, ret, t0, arg1, zero, arg2); - tcg_temp_free_i32(t0); - } else { - g_assert_not_reached(); - } -} - void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_remu, TCG_TYPE_I32, 0)) { @@ -1537,20 +1537,6 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 r= et, } } =20 -void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_divu, ret, arg1, arg2); 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Wed, 21 Oct 2026 07:19:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 035/100] tcg: Generic expansion of tcg_gen_remu_* Date: Wed, 21 Oct 2026 16:15:47 +0200 Message-ID: <20261021141652.363109-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592693918158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 - include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 74 ++++++++++-------------------------- 3 files changed, 21 insertions(+), 56 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9024963c06..d4d670dfed 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -202,7 +201,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 1b108d9f14..cfa19a0a81 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -17,6 +17,7 @@ DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) DEF3(rem, TCGV, TCGV, TCGV) +DEF3(remu, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF3(shl, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1bfefb9d65..fa6c152164 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -211,20 +211,6 @@ static TCGOp * DNI tcg_gen_op4ii_i64(TCGOpcode opc, TC= Gv_i64 a1, TCGv_i64 a2, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); } =20 -static void DNI tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) -{ - tcg_gen_op5(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); -} - -static void DNI tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) -{ - tcg_gen_op5(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); -} - static void DNI tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { @@ -518,6 +504,26 @@ void tcg_gen_rem(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) } } =20 +void tcg_gen_remu(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_remu, type, 0)) { + tcg_gen_op_ttt(INDEX_op_remu, type, dst, src1, src2); + } else { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + if (tcg_op_supported(INDEX_op_divu, type, 0)) { + tcg_gen_op_ttt(INDEX_op_divu, type, tmp, src1, src2); + tcg_gen_mul(type, tmp, tmp, src2); + tcg_gen_sub(type, dst, src1, tmp); + } else if (tcg_op_supported(INDEX_op_divu2, type, 0)) { + tcg_gen_op_ttttt(INDEX_op_divu2, type, tmp, dst, src1, + tcg_constant_internal(type, 0), src2); + } else { + g_assert_not_reached(); + } + } +} + void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); @@ -657,26 +663,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_remu, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_remu, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_op3_i32(INDEX_op_divu, t0, arg1, arg2); - tcg_gen_mul_i32(t0, t0, arg2); - tcg_gen_sub_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); - } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 zero =3D tcg_constant_i32(0); - tcg_gen_op5_i32(INDEX_op_divu2, t0, ret, arg1, zero, arg2); - tcg_temp_free_i32(t0); - } else { - g_assert_not_reached(); - } -} - void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0)) { @@ -1537,26 +1523,6 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 r= et, } } =20 -void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_remu, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_remu, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_op3_i64(INDEX_op_divu, t0, arg1, arg2); - tcg_gen_mul_i64(t0, t0, arg2); - tcg_gen_sub_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); - } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 zero =3D tcg_constant_i64(0); - tcg_gen_op5_i64(INDEX_op_divu2, t0, ret, arg1, zero, arg2); - tcg_temp_free_i64(t0); - } else { - g_assert_not_reached(); - } -} - void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_sextract_i64(ret, arg, 0, 8); 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Wed, 21 Oct 2026 07:19:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 036/100] tcg: Generic expansion of tcg_gen_andc_* Date: Wed, 21 Oct 2026 16:15:48 +0200 Message-ID: <20261021141652.363109-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592422972158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 36 ++++++++++++------------------------ 3 files changed, 13 insertions(+), 26 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index d4d670dfed..70d5b991b3 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -201,7 +200,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index cfa19a0a81..7386332658 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -5,6 +5,7 @@ DEF3(add, TCGV, TCGV, TCGV) DEF3(addi, TCGV, TCGV, TINT) DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) +DEF3(andc, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index fa6c152164..860c9678f9 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -392,6 +392,18 @@ void tcg_gen_andi(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_andc(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_andc, type, 0)) { + tcg_gen_op_ttt(INDEX_op_andc, type, dst, src1, src2); + } else { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_not(type, tmp, src2); + tcg_gen_and(type, dst, src1, tmp); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -663,18 +675,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_andc, ret, arg1, arg2); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_not_i32(t0, arg2); - tcg_gen_and_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); - } -} - void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I32, 0)) { @@ -1722,18 +1722,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_andc, ret, arg1, arg2); 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Wed, 21 Oct 2026 07:19:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 037/100] tcg: Generic expansion of tcg_gen_eqv_* Date: Wed, 21 Oct 2026 16:15:49 +0200 Message-ID: <20261021141652.363109-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592549143158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 30 ++++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 70d5b991b3..4eb35775a0 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -200,7 +199,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 7386332658..6a4d726b79 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -9,6 +9,7 @@ DEF3(andc, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) +DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 860c9678f9..c38accac75 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -437,6 +437,16 @@ void tcg_gen_divu(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_eqv(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_eqv, type, 0)) { + tcg_gen_op_ttt(INDEX_op_eqv, type, dst, src1, src2); + } else { + tcg_gen_xor(type, dst, src1, src2); + tcg_gen_not(type, dst, dst); + } +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -675,16 +685,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_eqv, ret, arg1, arg2); - } else { - tcg_gen_xor_i32(ret, arg1, arg2); - tcg_gen_not_i32(ret, ret); - } -} - void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I32, 0)) { @@ -1722,16 +1722,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_eqv, ret, arg1, arg2); - } else { - tcg_gen_xor_i64(ret, arg1, arg2); - tcg_gen_not_i64(ret, ret); - } -} - void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:19:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 038/100] tcg: Generic expansion of tcg_gen_nand_* Date: Wed, 21 Oct 2026 16:15:50 +0200 Message-ID: <20261021141652.363109-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593044184158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 30 ++++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 4eb35775a0..2d9b0704a0 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -199,7 +198,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 6a4d726b79..fc40bca553 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -14,6 +14,7 @@ DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) +DEF3(nand, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c38accac75..587fe0d280 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -475,6 +475,16 @@ void tcg_gen_muli(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_nand(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_nand, type, 0)) { + tcg_gen_op_ttt(INDEX_op_nand, type, dst, src1, src2); + } else { + tcg_gen_and(type, dst, src1, src2); + tcg_gen_not(type, dst, dst); + } +} + void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *src) { tcg_gen_op_tt(INDEX_op_neg, type, dst, src); @@ -685,16 +695,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_nand, ret, arg1, arg2); - } else { - tcg_gen_and_i32(ret, arg1, arg2); - tcg_gen_not_i32(ret, ret); - } -} - void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I32, 0)) { @@ -1722,16 +1722,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_nand, ret, arg1, arg2); - } else { - tcg_gen_and_i64(ret, arg1, arg2); - tcg_gen_not_i64(ret, ret); - } -} - void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:19:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 039/100] tcg: Generic expansion of tcg_gen_nor_* Date: Wed, 21 Oct 2026 16:15:51 +0200 Message-ID: <20261021141652.363109-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592602138158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 30 ++++++++++-------------------- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 2d9b0704a0..f959f82e08 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -198,7 +197,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index fc40bca553..7d94e0cdfe 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -16,6 +16,7 @@ DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) DEF3(nand, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) +DEF3(nor, TCGV, TCGV, TCGV) DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 587fe0d280..1ec1cc1e97 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -490,6 +490,16 @@ void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *= src) tcg_gen_op_tt(INDEX_op_neg, type, dst, src); } =20 +void tcg_gen_nor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_nor, type, 0)) { + tcg_gen_op_ttt(INDEX_op_nor, type, dst, src1, src2); + } else { + tcg_gen_or(type, dst, src1, src2); + tcg_gen_not(type, dst, dst); + } +} + void tcg_gen_not(TCGType type, TCGTemp *dst, TCGTemp *src) { if (tcg_op_supported(INDEX_op_not, type, 0)) { @@ -695,16 +705,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_nor, ret, arg1, arg2); - } else { - tcg_gen_or_i32(ret, arg1, arg2); - tcg_gen_not_i32(ret, ret); - } -} - void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I32, 0)) { @@ -1722,16 +1722,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_nor, ret, arg1, arg2); - } else { - tcg_gen_or_i64(ret, arg1, arg2); - tcg_gen_not_i64(ret, ret); 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Wed, 21 Oct 2026 07:22:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 040/100] tcg: Generic expansion of tcg_gen_orc_* Date: Wed, 21 Oct 2026 16:15:52 +0200 Message-ID: <20261021141652.363109-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592594089158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 36 ++++++++++++------------------------ 3 files changed, 13 insertions(+), 26 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f959f82e08..e62459b5f0 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); @@ -197,7 +196,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 7d94e0cdfe..fa33d41e3d 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -20,6 +20,7 @@ DEF3(nor, TCGV, TCGV, TCGV) DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) +DEF3(orc, TCGV, TCGV, TCGV) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1ec1cc1e97..8fb04d3c6e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -526,6 +526,18 @@ void tcg_gen_ori(TCGType type, TCGTemp *dst, TCGTemp *= src1, int64_t src2) } } =20 +void tcg_gen_orc(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_orc, type, 0)) { + tcg_gen_op_ttt(INDEX_op_orc, type, dst, src1, src2); + } else { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_not(type, tmp, src2); + tcg_gen_or(type, dst, src1, tmp); + } +} + void tcg_gen_rem(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_rems, type, 0)) { @@ -705,18 +717,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 re= t, tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } =20 -void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_orc, ret, arg1, arg2); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_not_i32(t0, arg2); - tcg_gen_or_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); - } -} - void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I32, 0)) { @@ -1722,18 +1722,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_orc, ret, arg1, arg2); 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Wed, 21 Oct 2026 07:22:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 041/100] tcg: Generic expansion of tcg_gen_brcond_* Date: Wed, 21 Oct 2026 16:15:53 +0200 Message-ID: <20261021141652.363109-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593013941158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 5 ++-- include/tcg/tcg.h | 1 + tcg/tcg-internal.h | 3 +++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 44 ++++++++++++++++++------------------ 5 files changed, 30 insertions(+), 24 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index e62459b5f0..ca249b999f 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -98,6 +98,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminf= o); QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2); #define DEF3(NAME, T1, T2, T3) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3); +#define DEF4(NAME, T1, T2, T3, T4) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4); =20 #define TCGV glue(TCGv,TExt) #define TExt _i32 @@ -120,6 +122,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); #undef DEF1 #undef DEF2 #undef DEF3 +#undef DEF4 =20 /* 32 bit ops */ =20 @@ -143,7 +146,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *); void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *); void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -216,7 +218,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *); void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *); void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e131345170..09d20064fc 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -97,6 +97,7 @@ struct TCGLabelUse { }; =20 typedef struct TCGLabel TCGLabel; +typedef struct TCGLabel *TCGLabelPtr; struct TCGLabel { bool present; bool has_value; diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 6b65228241..cd481dfd27 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -150,6 +150,8 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2); #define DEF3(NAME, T1, T2, T3) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3); +#define DEF4(NAME, T1, T2, T3, T4) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4); =20 #define TCGV TCGTemp * #define TINT int64_t @@ -162,5 +164,6 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); #undef DEF1 #undef DEF2 #undef DEF3 +#undef DEF4 =20 #endif /* TCG_INTERNAL_H */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index fa33d41e3d..10ed0438fd 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -6,6 +6,7 @@ DEF3(addi, TCGV, TCGV, TINT) DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) DEF3(andc, TCGV, TCGV, TCGV) +DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8fb04d3c6e..a8752e916a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -307,10 +307,17 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned me= minfo) void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c) \ { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), glue(C_,T3)(c))= ; } =20 +#define DEF4(NAME, T1, T2, T3, T4) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c, T4 d) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), \ + glue(C_,T3)(c), glue(C_,T4)(d)); } + #define C_TCGv_i32 tcgv_i32_temp #define C_TCGv_i64 tcgv_i64_temp #define C_int32_t #define C_int64_t +#define C_TCGCond +#define C_TCGLabelPtr =20 #define TCGV glue(TCGv,TExt) #define TExt _i32 @@ -338,10 +345,13 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned me= minfo) #undef C_TCGv_i64 #undef C_int32_t #undef C_int64_t +#undef C_TCGCond +#undef C_TCGLabelPtr =20 #undef DEF1 #undef DEF2 #undef DEF3 +#undef DEF4 =20 /* * Generic expansions for templated operations. @@ -404,6 +414,18 @@ void tcg_gen_andc(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_brcond(TCGType type, TCGCond cond, TCGTemp *src1, + TCGTemp *src2, TCGLabel *l) +{ + if (cond =3D=3D TCG_COND_ALWAYS) { + tcg_gen_br(l); + } else if (cond !=3D TCG_COND_NEVER) { + TCGOp *op =3D tcg_gen_op_ttii(INDEX_op_brcond, type, + src1, src2, cond, label_arg(l)); + add_as_label_use(l, op); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -661,17 +683,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *l) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_br(l); - } else if (cond !=3D TCG_COND_NEVER) { - TCGOp *op =3D tcg_gen_op4ii_i32(INDEX_op_brcond, - arg1, arg2, cond, label_arg(l)); - add_as_label_use(l, op); - } -} - void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *l) { if (cond =3D=3D TCG_COND_ALWAYS) { @@ -1471,17 +1482,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *l) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_br(l); - } else if (cond !=3D TCG_COND_NEVER) { - TCGOp *op =3D tcg_gen_op4ii_i64(INDEX_op_brcond, arg1, arg2, cond, - label_arg(l)); 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Wed, 21 Oct 2026 07:22:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 042/100] tcg: Generic expansion of tcg_gen_brcondi_* Date: Wed, 21 Oct 2026 16:15:54 +0200 Message-ID: <20261021141652.363109-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592647242158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 10 ++-------- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 25 +++++++++++-------------- 3 files changed, 14 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index ca249b999f..cad36f76eb 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,7 +146,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *); void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, @@ -218,7 +217,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *); void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, @@ -487,12 +485,8 @@ QEMU_ARG_NONNULL void tcg_gen_add_ptr(TCGv_ptr r, TCGv= _ptr a, TCGv_ptr b); QEMU_ARG_NONNULL void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b); QEMU_ARG_NONNULL void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s); QEMU_ARG_NONNULL void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s); - -static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, - intptr_t b, TCGLabel *label) -{ - glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); -} +QEMU_ARG_NONNULL void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, + intptr_t b, TCGLabel *label); =20 static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) { diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 10ed0438fd..a863215ffe 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -7,6 +7,7 @@ DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) DEF3(andc, TCGV, TCGV, TCGV) DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) +DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a8752e916a..1039104ca6 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -426,6 +426,12 @@ void tcg_gen_brcond(TCGType type, TCGCond cond, TCGTem= p *src1, } } =20 +void tcg_gen_brcondi(TCGType type, TCGCond cond, TCGTemp *src1, + int64_t src2, TCGLabel *l) +{ + tcg_gen_brcond(type, cond, src1, tcg_constant_internal(type, src2), l); +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -683,15 +689,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *l) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_br(l); - } else if (cond !=3D TCG_COND_NEVER) { - tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l); - } -} - void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { @@ -1482,11 +1479,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *l) -{ - tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); -} - void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { @@ -2450,6 +2442,11 @@ void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr= _t b) tcg_gen_addi(TCG_TYPE_PTR, tcgv_ptr_temp(r), tcgv_ptr_temp(a), b); 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Wed, 21 Oct 2026 07:22:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 043/100] tcg: Generic expansion of tcg_gen_setcond_* Date: Wed, 21 Oct 2026 16:15:55 +0200 Message-ID: <20261021141652.363109-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593306710158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 ---- tcg/tcg-internal.h | 6 ++++++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 36 ++++++++++++------------------------ 4 files changed, 19 insertions(+), 28 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index cad36f76eb..117d66ef59 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,8 +146,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, @@ -217,8 +215,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index cd481dfd27..0de8516447 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -120,6 +120,12 @@ static inline TCGOp *tcg_gen_op_ttii(TCGOpcode opc, TC= GType type, TCGTemp *t0, return tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), a2, a3); } =20 +static inline void tcg_gen_op_ttti(TCGOpcode opc, TCGType type, TCGTemp *t= 0, + TCGTemp *t1, TCGTemp *t2, TCGArg a3) +{ + tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2), a3); +} + static inline void tcg_gen_op_ttttt(TCGOpcode opc, TCGType type, TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index a863215ffe..4934f117bb 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -27,6 +27,7 @@ DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) +DEF4(setcond, TCGCond, TCGV, TCGV, TCGV) DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1039104ca6..a45244e64c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -621,6 +621,18 @@ void tcg_gen_sari(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_setcond(TCGType type, TCGCond cond, TCGTemp *dst, + TCGTemp *src1, TCGTemp *src2) +{ + if (cond =3D=3D TCG_COND_ALWAYS) { + tcg_gen_movi(type, dst, 1); + } else if (cond =3D=3D TCG_COND_NEVER) { + tcg_gen_movi(type, dst, 0); + } else { + tcg_gen_op_ttti(INDEX_op_setcond, type, dst, src1, src2, cond); + } +} + void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); @@ -689,18 +701,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_movi_i32(ret, 1); - } else if (cond =3D=3D TCG_COND_NEVER) { - tcg_gen_movi_i32(ret, 0); - } else { - tcg_gen_op4i_i32(INDEX_op_setcond, ret, arg1, arg2, cond); - } -} - void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { @@ -1479,18 +1479,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_movi_i64(ret, 1); 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Wed, 21 Oct 2026 07:22:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 044/100] tcg: Generic expansion of tcg_gen_setcondi_* Date: Wed, 21 Oct 2026 16:15:56 +0200 Message-ID: <20261021141652.363109-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593092974158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 ---- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 18 ++++++------------ 3 files changed, 7 insertions(+), 16 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 117d66ef59..c7ca7a493d 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,8 +146,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2); void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret, @@ -215,8 +213,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2); void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 4934f117bb..92a35e83f8 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -28,6 +28,7 @@ DEF3(remu, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF4(setcond, TCGCond, TCGV, TCGV, TCGV) +DEF4(setcondi, TCGCond, TCGV, TCGV, TINT) DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a45244e64c..94451fcfd9 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -633,6 +633,12 @@ void tcg_gen_setcond(TCGType type, TCGCond cond, TCGTe= mp *dst, } } =20 +void tcg_gen_setcondi(TCGType type, TCGCond cond, TCGTemp *dst, + TCGTemp *src1, int64_t src2) +{ + tcg_gen_setcond(type, cond, dst, src1, tcg_constant_internal(type, src= 2)); +} + void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); @@ -701,12 +707,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2) -{ - tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); -} - void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { @@ -1479,12 +1479,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); -} - void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 045/100] tcg: Generic expansion of tcg_gen_negsetcond_* Date: Wed, 21 Oct 2026 16:15:57 +0200 Message-ID: <20261021141652.363109-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593359829158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 ---- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 36 ++++++++++++------------------------ 3 files changed, 13 insertions(+), 28 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index c7ca7a493d..923d6eadee 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,8 +146,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, @@ -213,8 +211,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 92a35e83f8..1ab2c69cbe 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -18,6 +18,7 @@ DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) DEF3(nand, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) +DEF4(negsetcond, TCGCond, TCGV, TCGV, TCGV) DEF3(nor, TCGV, TCGV, TCGV) DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 94451fcfd9..40156e4113 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -518,6 +518,18 @@ void tcg_gen_neg(TCGType type, TCGTemp *dst, TCGTemp *= src) tcg_gen_op_tt(INDEX_op_neg, type, dst, src); } =20 +void tcg_gen_negsetcond(TCGType type, TCGCond cond, TCGTemp *dst, + TCGTemp *src1, TCGTemp *src2) +{ + if (cond =3D=3D TCG_COND_ALWAYS) { + tcg_gen_movi(type, dst, -1); + } else if (cond =3D=3D TCG_COND_NEVER) { + tcg_gen_movi(type, dst, 0); + } else { + tcg_gen_op_ttti(INDEX_op_negsetcond, type, dst, src1, src2, cond); + } +} + void tcg_gen_nor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_nor, type, 0)) { @@ -707,18 +719,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_movi_i32(ret, -1); - } else if (cond =3D=3D TCG_COND_NEVER) { - tcg_gen_movi_i32(ret, 0); - } else { - tcg_gen_op4i_i32(INDEX_op_negsetcond, ret, arg1, arg2, cond); - } -} - void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { @@ -1485,18 +1485,6 @@ void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 = ret, tcg_gen_negsetcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); } =20 -void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_movi_i64(ret, -1); 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Wed, 21 Oct 2026 07:22:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 046/100] tcg: Generic expansion of tcg_gen_negsetcondi_* Date: Wed, 21 Oct 2026 16:15:58 +0200 Message-ID: <20261021141652.363109-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593316973158501 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 ---- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 19 +++++++------------ 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 923d6eadee..fad2933425 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,8 +146,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2); void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, @@ -211,8 +209,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2); void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 1ab2c69cbe..846b781c83 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -19,6 +19,7 @@ DEF3(muli, TCGV, TCGV, TINT) DEF3(nand, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) DEF4(negsetcond, TCGCond, TCGV, TCGV, TCGV) +DEF4(negsetcondi, TCGCond, TCGV, TCGV, TINT) DEF3(nor, TCGV, TCGV, TCGV) DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 40156e4113..6be1141c08 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -530,6 +530,13 @@ void tcg_gen_negsetcond(TCGType type, TCGCond cond, TC= GTemp *dst, } } =20 +void tcg_gen_negsetcondi(TCGType type, TCGCond cond, TCGTemp *dst, + TCGTemp *src1, int64_t src2) +{ + tcg_gen_negsetcond(type, cond, dst, src1, + tcg_constant_internal(type, src2)); +} + void tcg_gen_nor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_nor, type, 0)) { @@ -719,12 +726,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2) -{ - tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); -} - void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I32, 0)) { @@ -1479,12 +1480,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_negsetcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); -} - void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_sextract_i64(ret, arg, 0, 8); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 047/100] tcg: Generic expansion of tcg_gen_movcond_* Date: Wed, 21 Oct 2026 16:15:59 +0200 Message-ID: <20261021141652.363109-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592728597158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 7 ++--- tcg/tcg-internal.h | 11 +++++++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 58 +++++++++++------------------------- 4 files changed, 33 insertions(+), 44 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index fad2933425..9988e9f66b 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -100,6 +100,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3); #define DEF4(NAME, T1, T2, T3, T4) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4); +#define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4, T= 5, T6); =20 #define TCGV glue(TCGv,TExt) #define TExt _i32 @@ -123,6 +125,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); #undef DEF2 #undef DEF3 #undef DEF4 +#undef DEF6 =20 /* 32 bit ops */ =20 @@ -146,8 +149,6 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); -void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, - TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, @@ -209,8 +210,6 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); -void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, - TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 0de8516447..cd5028104a 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -134,6 +134,14 @@ static inline void tcg_gen_op_ttttt(TCGOpcode opc, TCG= Type type, temp_arg(t3), temp_arg(t4)); } =20 +static inline void tcg_gen_op_ttttti(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, + TCGTemp *t3, TCGTemp *t4, TCGArg a5) +{ + tcg_gen_op6(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2), + temp_arg(t3), temp_arg(t4), a5); +} + QEMU_RET_ARG_NONNULL TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode, TCGType, unsigned nargs); @@ -158,6 +166,8 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3); #define DEF4(NAME, T1, T2, T3, T4) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4); +#define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5,= T6); =20 #define TCGV TCGTemp * #define TINT int64_t @@ -171,5 +181,6 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); #undef DEF2 #undef DEF3 #undef DEF4 +#undef DEF6 =20 #endif /* TCG_INTERNAL_H */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 846b781c83..a1c1e9b918 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -14,6 +14,7 @@ DEF3(divu, TCGV, TCGV, TCGV) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) +DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) DEF3(nand, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 6be1141c08..ed7dd8c7c1 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -225,22 +225,6 @@ static void DNI tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_= i64 a1, TCGv_i64 a2, tcgv_i64_arg(a3), a4, a5); } =20 -static void DNI tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGArg a6) -{ - tcg_gen_op6(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); -} - -static void DNI tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGArg a6) -{ - tcg_gen_op6(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); -} - /* Generic ops. */ =20 void gen_set_label(TCGLabel *l) @@ -312,6 +296,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), \ glue(C_,T3)(c), glue(C_,T4)(d)); } =20 +#define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c, T4 d, T5 e, T6 f= ) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), glue(C_,T3)(c),= \ + glue(C_,T4)(d), glue(C_,T5)(e), glue(C_,T6)(f)); } + #define C_TCGv_i32 tcgv_i32_temp #define C_TCGv_i64 tcgv_i64_temp #define C_int32_t @@ -352,6 +341,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #undef DEF2 #undef DEF3 #undef DEF4 +#undef DEF6 =20 /* * Generic expansions for templated operations. @@ -487,6 +477,18 @@ void tcg_gen_movi(TCGType type, TCGTemp *dst, int64_t = src) tcg_gen_op_tt(INDEX_op_mov, type, dst, tcg_constant_internal(type, src= )); } =20 +void tcg_gen_movcond(TCGType type, TCGCond cond, TCGTemp *dst, + TCGTemp *c1, TCGTemp *c2, TCGTemp *v1, TCGTemp *v2) +{ + if (cond =3D=3D TCG_COND_ALWAYS) { + tcg_gen_mov(type, dst, v1); + } else if (cond =3D=3D TCG_COND_NEVER) { + tcg_gen_mov(type, dst, v2); + } else { + tcg_gen_op_ttttti(INDEX_op_movcond, type, dst, c1, c2, v1, v2, con= d); + } +} + void tcg_gen_mul(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_mul, type, dst, src1, src2); @@ -1035,18 +1037,6 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al,= TCGv_i32 ah, } } =20 -void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, - TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_mov_i32(ret, v1); - } else if (cond =3D=3D TCG_COND_NEVER) { - tcg_gen_mov_i32(ret, v2); - } else { - tcg_gen_op6i_i32(INDEX_op_movcond, ret, c1, c2, v1, v2, cond); - } -} - void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { @@ -1960,18 +1950,6 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al,= TCGv_i64 ah, } } =20 -void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, - TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) -{ - if (cond =3D=3D TCG_COND_ALWAYS) { - tcg_gen_mov_i64(ret, v1); - } else if (cond =3D=3D TCG_COND_NEVER) { - tcg_gen_mov_i64(ret, v2); - } else { - tcg_gen_op6i_i64(INDEX_op_movcond, ret, c1, c2, v1, v2, cond); - } -} - void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/tcg-internal.h | 20 ++++++++++++++++++++ tcg/tcg-op.c | 12 ++++-------- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index cd5028104a..a0edf11292 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -183,4 +183,24 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_= target_ulong imm); #undef DEF4 #undef DEF6 =20 +static inline void tcg_gen_extrh(TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_op_tt(INDEX_op_extrh_i64_i32, TCG_TYPE_I32, dst, src); +} + +static inline void tcg_gen_extrl(TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_op_tt(INDEX_op_extrl_i64_i32, TCG_TYPE_I32, dst, src); +} + +static inline void tcg_gen_exts(TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_op_tt(INDEX_op_ext_i32_i64, TCG_TYPE_I64, dst, src); +} + +static inline void tcg_gen_extu(TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_op_tt(INDEX_op_extu_i32_i64, TCG_TYPE_I64, dst, src); +} + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ed7dd8c7c1..86f0c68c94 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2198,26 +2198,22 @@ void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) =20 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) { - tcg_gen_op2(INDEX_op_extrl_i64_i32, TCG_TYPE_I32, - tcgv_i32_arg(ret), tcgv_i64_arg(arg)); + tcg_gen_extrl(tcgv_i32_temp(ret), tcgv_i64_temp(arg)); } =20 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) { - tcg_gen_op2(INDEX_op_extrh_i64_i32, TCG_TYPE_I32, - tcgv_i32_arg(ret), tcgv_i64_arg(arg)); + tcg_gen_extrh(tcgv_i32_temp(ret), tcgv_i64_temp(arg)); } =20 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { - tcg_gen_op2(INDEX_op_extu_i32_i64, TCG_TYPE_I64, - tcgv_i64_arg(ret), tcgv_i32_arg(arg)); + tcg_gen_extu(tcgv_i64_temp(ret), tcgv_i32_temp(arg)); } =20 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { - tcg_gen_op2(INDEX_op_ext_i32_i64, TCG_TYPE_I64, - tcgv_i64_arg(ret), tcgv_i32_arg(arg)); + tcg_gen_exts(tcgv_i64_temp(ret), tcgv_i32_temp(arg)); } =20 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592604; cv=none; d=zohomail.com; s=zohoarc; b=jE9NiXaKXw5rzlT0cW9XHJ8P2+zVG81YMMPFIOSM3LRgiqD9MDePGBkxFv1U4GFwfyH11fpvo6uXDOpD+QyB/bbd7kfDEKkrSuK0oyVhesuwp3Z/f+72eJxFHYKDgwNzOYq5dwIkZNv0PK6KKAgwdLfKm3SFDrACzCTArj8xpzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792592604; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IjSaCTvqb6dQZALcoVAL/4hMYAAGMEbBuzq5yQHhTvk=; b=RiG3bGVLOJlsZg6WLK6dR8MQWeAw61Q76Ullp0uwkMlv8HvAccyzo6KYGj60GPr7+XyiqgXyCqlKZUdZW6DyQyKIrxLacnG2wDoya0Fm6n0rZHXBqk77Gehkq1cXyVxz+yqc9mrdnwAnAKZQSe8Pf+rxlBEwkjfnWYL+N7gNfYs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792592604743254.75358119077532; Wed, 21 Oct 2026 07:23:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJXDd-0001qg-0M; Wed, 21 Oct 2026 10:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJXD6-0001V0-4D for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:22:43 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xJXD3-00028S-Ta for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:22:31 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-487049569b6so548129f8f.1 for ; Wed, 21 Oct 2026 07:22:29 -0700 (PDT) Received: from stoup.fritz.box (pd95f64ec.dip0.t-ipconnect.de. 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 40 ++++--------------------------------- tcg/tcg-op.c | 20 +++++++++++++++++++ 2 files changed, 24 insertions(+), 36 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9988e9f66b..0ad0301e17 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -470,42 +470,10 @@ QEMU_ARG_NONNULL void tcg_gen_mov_ptr(TCGv_ptr d, TCG= v_ptr s); QEMU_ARG_NONNULL void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s); QEMU_ARG_NONNULL void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, intptr_t b, TCGLabel *label); - -static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_mov_i32((NAT)r, a); -#else - tcg_gen_ext_i32_i64((NAT)r, a); -#endif -} - -static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_extrl_i64_i32((NAT)r, a); -#else - tcg_gen_mov_i64((NAT)r, a); -#endif -} - -static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_extu_i32_i64(r, (NAT)a); -#else - tcg_gen_mov_i64(r, (NAT)a); -#endif -} - -static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_mov_i32(r, (NAT)a); -#else - tcg_gen_extrl_i64_i32(r, (NAT)a); -#endif -} +QEMU_ARG_NONNULL void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a); +QEMU_ARG_NONNULL void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a); +QEMU_ARG_NONNULL void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a); +QEMU_ARG_NONNULL void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a); =20 #undef PTR #undef NAT diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 86f0c68c94..75bc8a6a91 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2391,6 +2391,16 @@ void tcg_gen_discard_ptr(TCGv_ptr s) tcg_gen_discard(TCG_TYPE_PTR, tcgv_ptr_temp(s)); } =20 +void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) +{ + tcg_gen_exts(tcgv_ptr_temp(r), tcgv_i32_temp(a)); +} + +void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) +{ + tcg_gen_mov(TCG_TYPE_I64, tcgv_i64_temp(r), tcgv_ptr_temp(a)); +} + void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) { tcg_gen_mov(TCG_TYPE_PTR, tcgv_ptr_temp(d), tcgv_ptr_temp(s)); @@ -2400,3 +2410,13 @@ void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) { tcg_gen_movi(TCG_TYPE_PTR, tcgv_ptr_temp(d), s); } + +void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) +{ + tcg_gen_mov(TCG_TYPE_PTR, tcgv_ptr_temp(r), tcgv_i64_temp(a)); +} + +void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) +{ + tcg_gen_extrl(tcgv_i32_temp(r), tcgv_ptr_temp(a)); +} --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592771; cv=none; d=zohomail.com; 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Wed, 21 Oct 2026 07:22:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 050/100] tcg: Generic expansion of tcg_gen_clz_* Date: Wed, 21 Oct 2026 16:16:02 +0200 Message-ID: <20261021141652.363109-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592773318158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 52 ++++++++++++++++-------------------- 3 files changed, 24 insertions(+), 31 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 0ad0301e17..8dae7096aa 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -129,7 +129,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); @@ -190,7 +189,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index a1c1e9b918..74c68f46b7 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -8,6 +8,7 @@ DEF3(andi, TCGV, TCGV, TINT) DEF3(andc, TCGV, TCGV, TCGV) DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) +DEF3(clz, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 75bc8a6a91..ee80ab9323 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -422,6 +422,29 @@ void tcg_gen_brcondi(TCGType type, TCGCond cond, TCGTe= mp *src1, tcg_gen_brcond(type, cond, src1, tcg_constant_internal(type, src2), l); } =20 +void tcg_gen_clz(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_clz, type, 0)) { + tcg_gen_op_ttt(INDEX_op_clz, type, dst, src1, src2); + } else if (type =3D=3D TCG_TYPE_I64) { + gen_helper_clz_i64(temp_tcgv_i64(dst), temp_tcgv_i64(src1), + temp_tcgv_i64(src2)); + } else if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + g_autoptr(TCGTemp) t2 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + + tcg_gen_extu(t1, src1); + tcg_gen_extu(t2, src2); + tcg_gen_addi(TCG_TYPE_I64, t2, t2, 32); + tcg_gen_op_ttt(INDEX_op_clz, TCG_TYPE_I64, t1, t1, t2); + tcg_gen_extrl(dst, t1); + tcg_gen_addi(TCG_TYPE_I32, dst, dst, -32); + } else { + gen_helper_clz_i32(temp_tcgv_i32(dst), temp_tcgv_i32(src1), + temp_tcgv_i32(src2)); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -728,26 +751,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_clz, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t2 =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_i32_i64(t1, arg1); - tcg_gen_extu_i32_i64(t2, arg2); - tcg_gen_addi_i64(t2, t2, 32); - tcg_gen_clz_i64(t1, t1, t2); - tcg_gen_extrl_i64_i32(ret, t1); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_gen_subi_i32(ret, ret, 32); - } else { - gen_helper_clz_i32(ret, arg1, arg2); - } -} - void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); @@ -1669,15 +1672,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_clz, ret, arg1, arg2); - } else { - gen_helper_clz_i64(ret, arg1, arg2); - } -} - void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2)); 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 8 ++++---- tcg/tcg-op.c | 8 ++++---- target/ppc/translate/fixedpoint-impl.c.inc | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 8dae7096aa..b5575647d3 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -130,8 +130,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -190,8 +190,8 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); /* 64 bit ops */ =20 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ee80ab9323..e623f9bbc7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -751,7 +751,7 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp *= src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) +void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); } @@ -796,7 +796,7 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_= i32 arg2) tcg_temp_free_i32(t); } =20 -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) +void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { if (arg2 =3D=3D 32 && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0) @@ -1672,7 +1672,7 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) +void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2)); } @@ -1706,7 +1706,7 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCG= v_i64 arg2) tcg_temp_free_i64(t); } =20 -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) +void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { if (arg2 =3D=3D 64 && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index c3d8bbf267..5195db4e9a 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1551,7 +1551,7 @@ static bool trans_CMPB(DisasContext *ctx, arg_CMPB *a) } =20 static bool do_cntzw(DisasContext *ctx, arg_X_sa_rc *a, - void (*helper)(TCGv_i32, TCGv_i32, uint32_t)) + void (*helper)(TCGv_i32, TCGv_i32, int32_t)) { TCGv_i32 t =3D tcg_temp_new_i32(); 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Wed, 21 Oct 2026 07:22:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 052/100] tcg: Generic expansion of tcg_gen_clzi_* Date: Wed, 21 Oct 2026 16:16:04 +0200 Message-ID: <20261021141652.363109-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593672316158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index b5575647d3..d68362fd02 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -130,7 +130,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); @@ -190,7 +189,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); /* 64 bit ops */ =20 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 74c68f46b7..cf832a6dc0 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -9,6 +9,7 @@ DEF3(andc, TCGV, TCGV, TCGV) DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) DEF3(clz, TCGV, TCGV, TCGV) +DEF3(clzi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e623f9bbc7..efbbe4d8a1 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -445,6 +445,11 @@ void tcg_gen_clz(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) } } =20 +void tcg_gen_clzi(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + tcg_gen_clz(type, dst, src1, tcg_constant_internal(type, src2)); +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -751,11 +756,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); -} - void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { TCGv_i32 z, t; @@ -1672,11 +1672,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2)); -} - void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { TCGv_i64 z, t; --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592880; 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Wed, 21 Oct 2026 07:22:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 053/100] tcg: Generic expansion of tcg_gen_ctpop_* Date: Wed, 21 Oct 2026 16:16:05 +0200 Message-ID: <20261021141652.363109-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592881548158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 41 +++++++++++++++--------------------- 3 files changed, 18 insertions(+), 26 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index d68362fd02..8c1b7a1968 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,7 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -191,7 +190,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index cf832a6dc0..66977cada1 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -10,6 +10,7 @@ DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) DEF3(clz, TCGV, TCGV, TCGV) DEF3(clzi, TCGV, TCGV, TINT) +DEF2(ctpop, TCGV, TCGV) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index efbbe4d8a1..bad47af1c7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -450,6 +450,23 @@ void tcg_gen_clzi(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) tcg_gen_clz(type, dst, src1, tcg_constant_internal(type, src2)); } =20 +void tcg_gen_ctpop(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + if (tcg_op_supported(INDEX_op_ctpop, type, 0)) { + tcg_gen_op_tt(INDEX_op_ctpop, type, dst, src); + } else if (type =3D=3D TCG_TYPE_I64) { + gen_helper_ctpop_i64(temp_tcgv_i64(dst), temp_tcgv_i64(src)); + } else if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(TCG_TYPE_I64); + + tcg_gen_extu(tmp, src); + tcg_gen_op_tt(INDEX_op_ctpop, TCG_TYPE_I64, tmp, tmp); + tcg_gen_extrl(dst, tmp); + } else { + gen_helper_ctpop_i32(temp_tcgv_i32(dst), temp_tcgv_i32(src)); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -826,21 +843,6 @@ void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) -{ - if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I32, 0)) { - tcg_gen_op2_i32(INDEX_op_ctpop, ret, arg1); - } else if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_i32_i64(t, arg1); - tcg_gen_ctpop_i64(t, t); - tcg_gen_extrl_i64_i32(ret, t); - tcg_temp_free_i64(t); - } else { - gen_helper_ctpop_i32(ret, arg1); - } -} - void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { @@ -1731,15 +1733,6 @@ void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) -{ - if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { - tcg_gen_op2_i64(INDEX_op_ctpop, ret, arg1); - } else { - gen_helper_ctpop_i64(ret, arg1); - } -} - void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:22:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 054/100] tcg: Generic expansion of tcg_gen_ctz_* Date: Wed, 21 Oct 2026 16:16:06 +0200 Message-ID: <20261021141652.363109-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593796541158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 - include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 115 ++++++++++++++--------------------- 3 files changed, 47 insertions(+), 71 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 8c1b7a1968..4c8ef80474 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -129,7 +129,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -187,7 +186,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 66977cada1..2436fea04d 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -11,6 +11,7 @@ DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) DEF3(clz, TCGV, TCGV, TCGV) DEF3(clzi, TCGV, TCGV, TINT) DEF2(ctpop, TCGV, TCGV) +DEF3(ctz, TCGV, TCGV, TCGV) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index bad47af1c7..730962f052 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -467,6 +467,52 @@ void tcg_gen_ctpop(TCGType type, TCGTemp *dst, TCGTemp= *src) } } =20 +void tcg_gen_ctz(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + g_autoptr(TCGTemp) t1 =3D NULL; + + if (tcg_op_supported(INDEX_op_ctz, type, 0)) { + tcg_gen_op_ttt(INDEX_op_ctz, type, dst, src1, src2); + return; + } + if (tcg_op_supported(INDEX_op_ctpop, type, 0)) { + t1 =3D tcg_temp_new_ebb(type); + tcg_gen_addi(type, t1, src1, -1); + tcg_gen_andc(type, t1, t1, src1); + tcg_gen_ctpop(type, t1, t1); + } else if (tcg_op_supported(INDEX_op_clz, type, 0)) { + int width =3D tcg_type_bits(type); + + t1 =3D tcg_temp_new_ebb(type); + tcg_gen_neg(type, t1, src1); + tcg_gen_and(type, t1, t1, src1); + tcg_gen_clzi(type, t1, t1, width); + tcg_gen_xori(type, t1, t1, width - 1); + } else if (type =3D=3D TCG_TYPE_I64) { + gen_helper_ctz_i64(temp_tcgv_i64(dst), temp_tcgv_i64(src1), + temp_tcgv_i64(src2)); + return; + } else if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) || + tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0) || + tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { + g_autoptr(TCGTemp) t2 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + + t1 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + tcg_gen_extu(t1, src1); + tcg_gen_extu(t2, src2); + tcg_gen_ctz(TCG_TYPE_I64, t1, t1, t2); + tcg_gen_extrl(dst, t1); + return; + } else { + gen_helper_ctz_i32(temp_tcgv_i32(dst), temp_tcgv_i32(src1), + temp_tcgv_i32(src2)); + return; + } + + tcg_gen_movcond(type, TCG_COND_EQ, dst, src1, + tcg_constant_internal(type, 0), src2, t1); +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -773,46 +819,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - TCGv_i32 z, t; - - if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_ctz, ret, arg1, arg2); - return; - } - if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) { - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t2 =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_i32_i64(t1, arg1); - tcg_gen_extu_i32_i64(t2, arg2); - tcg_gen_ctz_i64(t1, t1, t2); - tcg_gen_extrl_i64_i32(ret, t1); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - return; - } - if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_REG, 0)) { - t =3D tcg_temp_ebb_new_i32(); - tcg_gen_subi_i32(t, arg1, 1); - tcg_gen_andc_i32(t, t, arg1); - tcg_gen_ctpop_i32(t, t); - } else if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { - t =3D tcg_temp_ebb_new_i32(); - tcg_gen_neg_i32(t, arg1); - tcg_gen_and_i32(t, t, arg1); - tcg_gen_clzi_i32(t, t, 32); - tcg_gen_xori_i32(t, t, 31); - } else { - gen_helper_ctz_i32(ret, arg1, arg2); - return; - } - - z =3D tcg_constant_i32(0); - tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); - tcg_temp_free_i32(t); -} - void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { if (arg2 =3D=3D 32 @@ -1674,35 +1680,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - TCGv_i64 z, t; - - if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2); - return; - } - if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { - t =3D tcg_temp_ebb_new_i64(); - tcg_gen_subi_i64(t, arg1, 1); - tcg_gen_andc_i64(t, t, arg1); - tcg_gen_ctpop_i64(t, t); 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Wed, 21 Oct 2026 07:22:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 055/100] tcg: Generic expansion of tcg_gen_ctzi_* Date: Wed, 21 Oct 2026 16:16:07 +0200 Message-ID: <20261021141652.363109-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593398715158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 45 +++++++++--------------------------- 3 files changed, 12 insertions(+), 36 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 4c8ef80474..b1a66149b5 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -129,7 +129,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -186,7 +185,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 2436fea04d..7ee00c9d53 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -12,6 +12,7 @@ DEF3(clz, TCGV, TCGV, TCGV) DEF3(clzi, TCGV, TCGV, TINT) DEF2(ctpop, TCGV, TCGV) DEF3(ctz, TCGV, TCGV, TCGV) +DEF3(ctzi, TCGV, TCGV, TINT) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 730962f052..476b8bbdfa 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -470,6 +470,7 @@ void tcg_gen_ctpop(TCGType type, TCGTemp *dst, TCGTemp = *src) void tcg_gen_ctz(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { g_autoptr(TCGTemp) t1 =3D NULL; + int width =3D tcg_type_bits(type); =20 if (tcg_op_supported(INDEX_op_ctz, type, 0)) { tcg_gen_op_ttt(INDEX_op_ctz, type, dst, src1, src2); @@ -479,10 +480,13 @@ void tcg_gen_ctz(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) t1 =3D tcg_temp_new_ebb(type); tcg_gen_addi(type, t1, src1, -1); tcg_gen_andc(type, t1, t1, src1); + if (src2->kind =3D=3D TEMP_CONST && src2->val =3D=3D width) { + /* No fixup required. */ + tcg_gen_ctpop(type, dst, t1); + return; + } tcg_gen_ctpop(type, t1, t1); } else if (tcg_op_supported(INDEX_op_clz, type, 0)) { - int width =3D tcg_type_bits(type); - t1 =3D tcg_temp_new_ebb(type); tcg_gen_neg(type, t1, src1); tcg_gen_and(type, t1, t1, src1); @@ -513,6 +517,11 @@ void tcg_gen_ctz(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) tcg_constant_internal(type, 0), src2, t1); } =20 +void tcg_gen_ctzi(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + tcg_gen_ctz(type, dst, src1, tcg_constant_internal(type, src2)); +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -819,22 +828,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - if (arg2 =3D=3D 32 - && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0) - && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_REG, 0)) { - /* This equivalence has the advantage of not requiring a fixup. */ - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - tcg_gen_subi_i32(t, arg1, 1); - tcg_gen_andc_i32(t, t, arg1); - tcg_gen_ctpop_i32(ret, t); - tcg_temp_free_i32(t); - } else { - tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2)); - } -} - void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) { if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { @@ -1680,22 +1673,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - if (arg2 =3D=3D 64 - && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) - && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { - /* This equivalence has the advantage of not requiring a fixup. */ - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - tcg_gen_subi_i64(t, arg1, 1); - tcg_gen_andc_i64(t, t, arg1); - tcg_gen_ctpop_i64(ret, t); - tcg_temp_free_i64(t); - } else { - tcg_gen_ctz_i64(ret, arg1, tcg_constant_i64(arg2)); - } -} - void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) { if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 056/100] tcg: Generic expansion of tcg_gen_clrsb_* Date: Wed, 21 Oct 2026 16:16:08 +0200 Message-ID: <20261021141652.363109-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592881546158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 45 ++++++++++++++---------------------- 3 files changed, 18 insertions(+), 30 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index b1a66149b5..b1448f8c08 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -129,7 +129,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -185,7 +184,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 7ee00c9d53..ef0ac5aece 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -8,6 +8,7 @@ DEF3(andi, TCGV, TCGV, TINT) DEF3(andc, TCGV, TCGV, TCGV) DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) +DEF2(clrsb, TCGV, TCGV) DEF3(clz, TCGV, TCGV, TCGV) DEF3(clzi, TCGV, TCGV, TINT) DEF2(ctpop, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 476b8bbdfa..97673524d1 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -422,6 +422,23 @@ void tcg_gen_brcondi(TCGType type, TCGCond cond, TCGTe= mp *src1, tcg_gen_brcond(type, cond, src1, tcg_constant_internal(type, src2), l); } =20 +void tcg_gen_clrsb(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + int width =3D tcg_type_bits(type); + + tcg_gen_sari(type, tmp, src, width - 1); + tcg_gen_xor(type, tmp, tmp, src); + tcg_gen_clzi(type, tmp, tmp, width); + tcg_gen_addi(type, dst, tmp, -1); + } else if (type =3D=3D TCG_TYPE_I32) { + gen_helper_clrsb_i32(temp_tcgv_i32(dst), temp_tcgv_i32(src)); + } else { + gen_helper_clrsb_i64(temp_tcgv_i64(dst), temp_tcgv_i64(src)); + } +} + void tcg_gen_clz(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_clz, type, 0)) { @@ -828,20 +845,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - tcg_gen_sari_i32(t, arg, 31); - tcg_gen_xor_i32(t, t, arg); - tcg_gen_clzi_i32(t, t, 32); - tcg_gen_subi_i32(ret, t, 1); - tcg_temp_free_i32(t); - } else { - gen_helper_clrsb_i32(ret, arg); - } -} - void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { @@ -1673,20 +1676,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - tcg_gen_sari_i64(t, arg, 63); - tcg_gen_xor_i64(t, t, arg); - tcg_gen_clzi_i64(t, t, 64); - tcg_gen_subi_i64(ret, t, 1); - tcg_temp_free_i64(t); - } else { - gen_helper_clrsb_i64(ret, arg); - } -} - void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792592807; cv=none; d=zohomail.com; s=zohoarc; b=JWK4p8VrG5s0R1eEm6xzJfsmtu8iHTyqzjZs0GSyDYf3R7R8s6tTjDkWkn7CLTX4PxvahjXlQijQoR97wXc+eS2r8SxMg4cOYZJivKGtxG3x0XMfBTl4afgjL2eDXGJs6kKfq2mhYgI9d/wfWoXG1iPc8eUUCsWNb8vI82vmZXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Wed, 21 Oct 2026 07:22:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 057/100] tcg: Generic expansion of tcg_gen_rotl_* Date: Wed, 21 Oct 2026 16:16:09 +0200 Message-ID: <20261021141652.363109-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592807923158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 62 ++++++++++++------------------------ 3 files changed, 21 insertions(+), 44 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index b1448f8c08..e653c12a18 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -129,7 +129,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); @@ -184,7 +183,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index ef0ac5aece..f832e286ab 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -34,6 +34,7 @@ DEF3(ori, TCGV, TCGV, TINT) DEF3(orc, TCGV, TCGV, TCGV) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) +DEF3(rotl, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF4(setcond, TCGCond, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 97673524d1..97acd9ebc8 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -744,6 +744,26 @@ void tcg_gen_remu(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_rotl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_rotl, type, 0)) { + tcg_gen_op_ttt(INDEX_op_rotl, type, dst, src1, src2); + } else if (tcg_op_supported(INDEX_op_rotr, type, 0)) { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_neg(type, tmp, src2); + tcg_gen_op_ttt(INDEX_op_rotr, type, dst, src1, tmp); + } else { + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + + tcg_gen_shl(type, t0, src1, src2); + tcg_gen_neg(type, t1, src2); + tcg_gen_shr(type, t1, src1, t1); + tcg_gen_or(type, dst, t0, t1); + } +} + void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); @@ -845,27 +865,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_neg_i32(t0, arg2); - tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0); - tcg_temp_free_i32(t0); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - tcg_gen_shl_i32(t0, arg1, arg2); - tcg_gen_neg_i32(t1, arg2); - tcg_gen_shr_i32(t1, arg1, t1); - tcg_gen_or_i32(ret, t0, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } -} - void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1676,27 +1675,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_neg_i64(t0, arg2); - tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0); - tcg_temp_free_i64(t0); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_shl_i64(t0, arg1, arg2); - tcg_gen_neg_i64(t1, arg2); - tcg_gen_shr_i64(t1, arg1, t1); - tcg_gen_or_i64(ret, t0, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } -} - void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593692; cv=none; d=zohomail.com; s=zohoarc; b=lkLrTG6GPxM+BTKfpu1tdOnp9l+/6ZABAyo/U3E0R/jVsMmVjSK6yRLpQuPxRzAJk3/75ISqtjIo2TK6q1CqhLA3pK3Q1jqfNbUhagG8dSQ3sGIDbqov5QWUvRbGrPfFpgDzvpubcK0IcncbIW+Osu4jbVM2VsWJrDaWCxoH438= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593692; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 21 Oct 2026 07:22:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 058/100] tcg: Generic expansion of tcg_gen_rotr_* Date: Wed, 21 Oct 2026 16:16:10 +0200 Message-ID: <20261021141652.363109-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593692991158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 62 ++++++++++++------------------------ 3 files changed, 21 insertions(+), 44 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index e653c12a18..2d05728a88 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -130,7 +130,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len); @@ -184,7 +183,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); /* 64 bit ops */ =20 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index f832e286ab..84ef1d5378 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -35,6 +35,7 @@ DEF3(orc, TCGV, TCGV, TCGV) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF3(rotl, TCGV, TCGV, TCGV) +DEF3(rotr, TCGV, TCGV, TCGV) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF4(setcond, TCGCond, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 97acd9ebc8..5a85dfbf70 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -764,6 +764,26 @@ void tcg_gen_rotl(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_rotr(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_rotr, type, 0)) { + tcg_gen_op_ttt(INDEX_op_rotr, type, dst, src1, src2); + } else if (tcg_op_supported(INDEX_op_rotl, type, 0)) { + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_neg(type, tmp, src2); + tcg_gen_op_ttt(INDEX_op_rotl, type, dst, src1, tmp); + } else { + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + + tcg_gen_shr(type, t0, src1, src2); + tcg_gen_neg(type, t1, src2); + tcg_gen_shl(type, t1, src1, t1); + tcg_gen_or(type, dst, t0, t1); + } +} + void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); @@ -877,27 +897,6 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, in= t32_t arg2) } } =20 -void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_neg_i32(t0, arg2); - tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0); - tcg_temp_free_i32(t0); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - tcg_gen_shr_i32(t0, arg1, arg2); - tcg_gen_neg_i32(t1, arg2); - tcg_gen_shl_i32(t1, arg1, t1); - tcg_gen_or_i32(ret, t0, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } -} - void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); @@ -1687,27 +1686,6 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, = int64_t arg2) } } =20 -void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_neg_i64(t0, arg2); - tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0); - tcg_temp_free_i64(t0); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); 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Wed, 21 Oct 2026 07:22:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 059/100] tcg: Generic expansion of tcg_gen_rotri_* Date: Wed, 21 Oct 2026 16:16:11 +0200 Message-ID: <20261021141652.363109-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592822223158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 49 ++++++++++++++---------------------- 3 files changed, 20 insertions(+), 32 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 2d05728a88..2d434ec8b5 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -130,7 +130,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -183,7 +182,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); /* 64 bit ops */ =20 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 84ef1d5378..88a8001601 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -36,6 +36,7 @@ DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF3(rotl, TCGV, TCGV, TCGV) DEF3(rotr, TCGV, TCGV, TCGV) +DEF3(rotri, TCGV, TCGV, TINT) DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF4(setcond, TCGCond, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 5a85dfbf70..0e294a2966 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -784,6 +784,25 @@ void tcg_gen_rotr(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_rotri(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + int width =3D tcg_type_bits(type); + + tcg_debug_assert(src2 >=3D 0 && src2 < width); + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else if (tcg_op_supported(INDEX_op_rotr, type, 0)) { + tcg_gen_op_ttt(INDEX_op_rotr, type, dst, src1, + tcg_constant_internal(type, src2)); + } else if (tcg_op_supported(INDEX_op_rotl, type, 0)) { + tcg_gen_op_ttt(INDEX_op_rotl, type, dst, src1, + tcg_constant_internal(type, width - src2)); + } else { + /* Do not recurse with the rotri simplification. */ + tcg_gen_op_ttti(INDEX_op_extract2, type, dst, src1, src1, src2); + } +} + void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2); @@ -897,21 +916,6 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, in= t32_t arg2) } } =20 -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, tcg_constant_i32(arg2)); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, tcg_constant_i32(32 - ar= g2)); - } else { - /* Do not recurse with the rotri simplification. */ - tcg_gen_op4i_i32(INDEX_op_extract2, ret, arg1, arg1, arg2); - } -} - void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { @@ -1686,21 +1690,6 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, = int64_t arg2) } } =20 -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i64(ret, arg1); - } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, tcg_constant_i64(arg2)); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, tcg_constant_i64(64 - ar= g2)); - } else { - /* Do not recurse with the rotri simplification. */ - tcg_gen_op4i_i64(INDEX_op_extract2, ret, arg1, arg1, arg2); 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Wed, 21 Oct 2026 07:22:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 060/100] tcg: Generic expansion of tcg_gen_rotli_* Date: Wed, 21 Oct 2026 16:16:12 +0200 Message-ID: <20261021141652.363109-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593361826158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 39 ++++++++++++++---------------------- 3 files changed, 16 insertions(+), 26 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 2d434ec8b5..d20ac150e4 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -129,7 +129,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -181,7 +180,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 88a8001601..9b88373ff2 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -35,6 +35,7 @@ DEF3(orc, TCGV, TCGV, TCGV) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF3(rotl, TCGV, TCGV, TCGV) +DEF3(rotli, TCGV, TCGV, TINT) DEF3(rotr, TCGV, TCGV, TCGV) DEF3(rotri, TCGV, TCGV, TINT) DEF3(sar, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0e294a2966..536095683f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -764,6 +764,21 @@ void tcg_gen_rotl(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_rotli(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2) +{ + int width =3D tcg_type_bits(type); + + tcg_debug_assert(src2 >=3D 0 && src2 < width); + if (src2 =3D=3D 0) { + tcg_gen_mov(type, dst, src1); + } else if (tcg_op_supported(INDEX_op_rotl, type, 0)) { + tcg_gen_op_ttt(INDEX_op_rotl, type, dst, src1, + tcg_constant_internal(type, src2)); + } else { + tcg_gen_rotri(type, dst, src1, width - src2); + } +} + void tcg_gen_rotr(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_rotr, type, 0)) { @@ -904,18 +919,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 32); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i32(ret, arg1); - } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, tcg_constant_i32(arg2)); - } else { - tcg_gen_rotri_i32(ret, arg1, -arg2 & 31); - } -} - void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { @@ -1678,18 +1681,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) -{ - tcg_debug_assert(arg2 >=3D 0 && arg2 < 64); - if (arg2 =3D=3D 0) { - tcg_gen_mov_i64(ret, arg1); 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Wed, 21 Oct 2026 07:22:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 061/100] tcg: Generic expansion of tcg_gen_deposit_* Date: Wed, 21 Oct 2026 16:16:13 +0200 Message-ID: <20261021141652.363109-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593072840158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 7 ++--- tcg/tcg-internal.h | 10 +++++++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 55 ++++++++++++++++-------------------- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index d20ac150e4..7cb1a4de52 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -100,6 +100,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3); #define DEF4(NAME, T1, T2, T3, T4) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4); +#define DEF5(NAME, T1, T2, T3, T4, T5) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4, T= 5); #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4, T= 5, T6); =20 @@ -125,12 +127,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned me= minfo); #undef DEF2 #undef DEF3 #undef DEF4 +#undef DEF5 #undef DEF6 =20 /* 32 bit ops */ =20 -void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, - unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -180,8 +181,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, - unsigned int ofs, unsigned int len); void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index a0edf11292..13c4be5a5c 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -126,6 +126,13 @@ static inline void tcg_gen_op_ttti(TCGOpcode opc, TCGT= ype type, TCGTemp *t0, tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2), a3); } =20 +static inline void tcg_gen_op_tttii(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, + TCGArg a3, TCGArg a4) +{ + tcg_gen_op5(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2), a3, a= 4); +} + static inline void tcg_gen_op_ttttt(TCGOpcode opc, TCGType type, TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) @@ -166,6 +173,8 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3); #define DEF4(NAME, T1, T2, T3, T4) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4); +#define DEF5(NAME, T1, T2, T3, T4, T5) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5); #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5,= T6); =20 @@ -181,6 +190,7 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); #undef DEF2 #undef DEF3 #undef DEF4 +#undef DEF5 #undef DEF6 =20 static inline void tcg_gen_extrh(TCGTemp *dst, TCGTemp *src) diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 9b88373ff2..95885d28d8 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -14,6 +14,7 @@ DEF3(clzi, TCGV, TCGV, TINT) DEF2(ctpop, TCGV, TCGV) DEF3(ctz, TCGV, TCGV, TCGV) DEF3(ctzi, TCGV, TCGV, TINT) +DEF5(deposit, TCGV, TCGV, TCGV, unsigned, unsigned) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 536095683f..62c2186d0c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -296,6 +296,11 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), \ glue(C_,T3)(c), glue(C_,T4)(d)); } =20 +#define DEF5(NAME, T1, T2, T3, T4, T5) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c, T4 d, T5 e) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), \ + glue(C_,T3)(c), glue(C_,T4)(d), glue(C_,T5)(e)); } + #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c, T4 d, T5 e, T6 f= ) \ { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), glue(C_,T3)(c),= \ @@ -307,6 +312,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #define C_int64_t #define C_TCGCond #define C_TCGLabelPtr +#define C_unsigned =20 #define TCGV glue(TCGv,TExt) #define TExt _i32 @@ -336,11 +342,13 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned me= minfo) #undef C_int64_t #undef C_TCGCond #undef C_TCGLabelPtr +#undef C_unsigned =20 #undef DEF1 #undef DEF2 #undef DEF3 #undef DEF4 +#undef DEF5 #undef DEF6 =20 /* @@ -539,6 +547,23 @@ void tcg_gen_ctzi(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) tcg_gen_ctz(type, dst, src1, tcg_constant_internal(type, src2)); } =20 +void tcg_gen_deposit(TCGType type, TCGTemp *dst, TCGTemp *src1, + TCGTemp *src2, unsigned ofs, unsigned len) +{ + unsigned width =3D tcg_type_bits(type); + + tcg_debug_assert(ofs < width); + tcg_debug_assert(len > 0); + tcg_debug_assert(len <=3D width); + tcg_debug_assert(ofs + len <=3D width); + + if (len =3D=3D width) { + tcg_gen_mov(type, dst, src2); + } else { + tcg_gen_op_tttii(INDEX_op_deposit, type, dst, src1, src2, ofs, len= ); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -919,21 +944,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, - unsigned int ofs, unsigned int len) -{ - tcg_debug_assert(ofs < 32); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 32); - tcg_debug_assert(ofs + len <=3D 32); - - if (len =3D=3D 32) { - tcg_gen_mov_i32(ret, arg2); - } else { - tcg_gen_op5ii_i32(INDEX_op_deposit, ret, arg1, arg2, ofs, len); - } -} - void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len) { @@ -1681,21 +1691,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, - unsigned int ofs, unsigned int len) -{ - tcg_debug_assert(ofs < 64); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 64); - tcg_debug_assert(ofs + len <=3D 64); - - if (len =3D=3D 64) { - tcg_gen_mov_i64(ret, arg2); - } else { - tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len); - } -} - void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 21 Oct 2026 07:22:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 062/100] tcg: Generic expansion of tcg_gen_extract_* Date: Wed, 21 Oct 2026 16:16:14 +0200 Message-ID: <20261021141652.363109-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593816963158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 131 ++++++++++++----------------------- 3 files changed, 46 insertions(+), 90 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 7cb1a4de52..77f9599115 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -134,8 +134,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); -void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, @@ -183,8 +181,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); -void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 95885d28d8..69f76f1d23 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -18,6 +18,7 @@ DEF5(deposit, TCGV, TCGV, TCGV, unsigned, unsigned) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) +DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 62c2186d0c..a58978dd02 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -607,6 +607,51 @@ void tcg_gen_eqv(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) } } =20 +void tcg_gen_extract(TCGType type, TCGTemp *dst, TCGTemp *src, + unsigned int ofs, unsigned int len) +{ + unsigned width =3D tcg_type_bits(type); + uint64_t mask; + + tcg_debug_assert(ofs < width); + tcg_debug_assert(len > 0); + tcg_debug_assert(len <=3D width); + tcg_debug_assert(ofs + len <=3D width); + + /* Canonicalize certain special cases, even if extract is supported. = */ + if (ofs + len =3D=3D width) { + tcg_gen_shri(type, dst, src, ofs); + return; + } + + if (TCG_TARGET_extract_valid(type, ofs, len)) { + tcg_gen_op_ttii(INDEX_op_extract, type, dst, src, ofs, len); + return; + } + + /* Assume that zero-extension, if available, is cheaper than a shift. = */ + if (TCG_TARGET_extract_valid(type, 0, ofs + len)) { + tcg_gen_op_ttii(INDEX_op_extract, type, dst, src, 0, ofs + len); + tcg_gen_shri(type, dst, dst, ofs); + return; + } + if (TCG_TARGET_extract_valid(type, 0, len)) { + tcg_gen_shri(type, dst, src, ofs); + tcg_gen_op_ttii(INDEX_op_extract, type, dst, dst, 0, len); + return; + } + + mask =3D MAKE_64BIT_MASK(0, len); + if (tcg_op_imm_match(INDEX_op_and, type, mask)) { + tcg_gen_shri(type, dst, src, ofs); + /* Do not recurse with gen_andi. */ + tcg_gen_and(type, dst, dst, tcg_constant_internal(type, mask)); + } else { + tcg_gen_shli(type, dst, src, width - len - ofs); + tcg_gen_shri(type, dst, dst, width - len); + } +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -962,49 +1007,6 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, } } =20 -void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len) -{ - uint32_t mask; - - tcg_debug_assert(ofs < 32); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 32); - tcg_debug_assert(ofs + len <=3D 32); - - /* Canonicalize certain special cases, even if extract is supported. = */ - if (ofs + len =3D=3D 32) { - tcg_gen_shri_i32(ret, arg, 32 - len); - return; - } - - if (TCG_TARGET_extract_valid(TCG_TYPE_I32, ofs, len)) { - tcg_gen_op4ii_i32(INDEX_op_extract, ret, arg, ofs, len); - return; - } - - mask =3D (1u << len) - 1; - if (ofs =3D=3D 0) { - tcg_gen_andi_i32(ret, arg, mask); - return; - } - - /* Assume that zero-extension, if available, is cheaper than a shift. = */ - if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, ofs + len)) { - tcg_gen_op4ii_i32(INDEX_op_extract, ret, arg, 0, ofs + len); - tcg_gen_shri_i32(ret, ret, ofs); - return; - } - - if (tcg_op_imm_match(INDEX_op_and, TCG_TYPE_I32, mask)) { - tcg_gen_shri_i32(ret, arg, ofs); - tcg_gen_andi_i32(ret, ret, mask); - } else { - tcg_gen_shli_i32(ret, arg, 32 - len - ofs); - tcg_gen_shri_i32(ret, ret, 32 - len); - } -} - void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len) { @@ -1709,49 +1711,6 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 ar= g, } } =20 -void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len) -{ - uint64_t mask; - - tcg_debug_assert(ofs < 64); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 64); - tcg_debug_assert(ofs + len <=3D 64); - - /* Canonicalize certain special cases, even if extract is supported. = */ - if (ofs + len =3D=3D 64) { - tcg_gen_shri_i64(ret, arg, 64 - len); - return; - } - - if (TCG_TARGET_extract_valid(TCG_TYPE_I64, ofs, len)) { - tcg_gen_op4ii_i64(INDEX_op_extract, ret, arg, ofs, len); - return; - } - - mask =3D (1ull << len) - 1; - if (ofs =3D=3D 0) { - tcg_gen_andi_i64(ret, arg, mask); - return; - } - - /* Assume that zero-extension, if available, is cheaper than a shift. = */ - if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, ofs + len)) { - tcg_gen_op4ii_i64(INDEX_op_extract, ret, arg, 0, ofs + len); - tcg_gen_shri_i64(ret, ret, ofs); - return; - } - - if (tcg_op_imm_match(INDEX_op_and, TCG_TYPE_I64, mask)) { - tcg_gen_shri_i64(ret, arg, ofs); - tcg_gen_andi_i64(ret, ret, mask); - } else { - tcg_gen_shli_i64(ret, arg, 64 - len - ofs); - tcg_gen_shri_i64(ret, ret, 64 - len); - } -} - void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 21 Oct 2026 07:22:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 063/100] tcg: Generic expansion of tcg_gen_sextract_* Date: Wed, 21 Oct 2026 16:16:15 +0200 Message-ID: <20261021141652.363109-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593672320158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 121 +++++++++++------------------------ 3 files changed, 38 insertions(+), 88 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 77f9599115..34a79c5818 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -134,8 +134,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, @@ -181,8 +179,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 69f76f1d23..338ecce6fc 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -44,6 +44,7 @@ DEF3(sar, TCGV, TCGV, TCGV) DEF3(sari, TCGV, TCGV, TINT) DEF4(setcond, TCGCond, TCGV, TCGV, TCGV) DEF4(setcondi, TCGCond, TCGV, TCGV, TINT) +DEF4(sextract, TCGV, TCGV, unsigned, unsigned) DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a58978dd02..f2928ae8e7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -197,20 +197,6 @@ static void DNI tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i= 64 a1, TCGv_i64 a2, tcgv_i64_arg(a3), a4); } =20 -static TCGOp * DNI tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, - TCGArg a3, TCGArg a4) -{ - return tcg_gen_op4(opc, TCG_TYPE_I32, - tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); -} - -static TCGOp * DNI tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, - TCGArg a3, TCGArg a4) -{ - return tcg_gen_op4(opc, TCG_TYPE_I64, - tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); -} - static void DNI tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { @@ -921,6 +907,43 @@ void tcg_gen_setcondi(TCGType type, TCGCond cond, TCGT= emp *dst, tcg_gen_setcond(type, cond, dst, src1, tcg_constant_internal(type, src= 2)); } =20 +void tcg_gen_sextract(TCGType type, TCGTemp *dst, TCGTemp *src, + unsigned int ofs, unsigned int len) +{ + unsigned width =3D tcg_type_bits(type); + + tcg_debug_assert(ofs < width); + tcg_debug_assert(len > 0); + tcg_debug_assert(len <=3D width); + tcg_debug_assert(ofs + len <=3D width); + + /* Canonicalize certain special cases, even if extract is supported. = */ + if (ofs + len =3D=3D width) { + tcg_gen_sari(type, dst, src, width - len); + return; + } + + if (TCG_TARGET_sextract_valid(type, ofs, len)) { + tcg_gen_op_ttii(INDEX_op_sextract, type, dst, src, ofs, len); + return; + } + + /* Assume that sign-extension, if available, is cheaper than a shift. = */ + if (TCG_TARGET_sextract_valid(type, 0, ofs + len)) { + tcg_gen_op_ttii(INDEX_op_sextract, type, dst, src, 0, ofs + len); + tcg_gen_sari(type, dst, dst, ofs); + return; + } + if (TCG_TARGET_sextract_valid(type, 0, len)) { + tcg_gen_shri(type, dst, src, ofs); + tcg_gen_op_ttii(INDEX_op_sextract, type, dst, dst, 0, len); + return; + } + + tcg_gen_shli(type, dst, src, width - len - ofs); + tcg_gen_sari(type, dst, dst, width - len); +} + void tcg_gen_shl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_shl, type, dst, src1, src2); @@ -1007,41 +1030,6 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 ar= g, } } =20 -void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len) -{ - tcg_debug_assert(ofs < 32); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 32); - tcg_debug_assert(ofs + len <=3D 32); - - /* Canonicalize certain special cases, even if extract is supported. = */ - if (ofs + len =3D=3D 32) { - tcg_gen_sari_i32(ret, arg, 32 - len); - return; - } - - if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, ofs, len)) { - tcg_gen_op4ii_i32(INDEX_op_sextract, ret, arg, ofs, len); - return; - } - - /* Assume that sign-extension, if available, is cheaper than a shift. = */ - if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, 0, ofs + len)) { - tcg_gen_op4ii_i32(INDEX_op_sextract, ret, arg, 0, ofs + len); - tcg_gen_sari_i32(ret, ret, ofs); - return; - } - if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, 0, len)) { - tcg_gen_shri_i32(ret, arg, ofs); - tcg_gen_op4ii_i32(INDEX_op_sextract, ret, ret, 0, len); - return; - } - - tcg_gen_shli_i32(ret, arg, 32 - len - ofs); - tcg_gen_sari_i32(ret, ret, 32 - len); -} - /* * Extract 32-bits from a 64-bit input, ah:al, starting from ofs. * Unlike tcg_gen_extract_i32 above, len is fixed at 32. @@ -1711,41 +1699,6 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 ar= g, } } =20 -void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len) -{ - tcg_debug_assert(ofs < 64); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 64); - tcg_debug_assert(ofs + len <=3D 64); - - /* Canonicalize certain special cases, even if sextract is supported. = */ - if (ofs + len =3D=3D 64) { - tcg_gen_sari_i64(ret, arg, 64 - len); - return; - } - - if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, ofs, len)) { - tcg_gen_op4ii_i64(INDEX_op_sextract, ret, arg, ofs, len); - return; - } - - /* Assume that sign-extension, if available, is cheaper than a shift. = */ - if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, 0, ofs + len)) { - tcg_gen_op4ii_i64(INDEX_op_sextract, ret, arg, 0, ofs + len); - tcg_gen_sari_i64(ret, ret, ofs); - return; - } - if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, 0, len)) { - tcg_gen_shri_i64(ret, arg, ofs); - tcg_gen_op4ii_i64(INDEX_op_sextract, ret, ret, 0, len); - return; - } - - tcg_gen_shli_i64(ret, arg, 64 - len - ofs); - tcg_gen_sari_i64(ret, ret, 64 - len); -} - /* * Extract 64 bits from a 128-bit input, ah:al, starting from ofs. * Unlike tcg_gen_extract_i64 above, len is fixed at 64. --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 064/100] tcg: Generic expansion of tcg_gen_deposit_z_* Date: Wed, 21 Oct 2026 16:16:16 +0200 Message-ID: <20261021141652.363109-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593082898158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 70 +++++++++++------------------------- 3 files changed, 21 insertions(+), 54 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 34a79c5818..85af0d4b6c 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,8 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, unsigned int ofs); void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, @@ -177,8 +175,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, unsigned int ofs); void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 338ecce6fc..88e87ebc2f 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -15,6 +15,7 @@ DEF2(ctpop, TCGV, TCGV) DEF3(ctz, TCGV, TCGV, TCGV) DEF3(ctzi, TCGV, TCGV, TINT) DEF5(deposit, TCGV, TCGV, TCGV, unsigned, unsigned) +DEF4(deposit_z, TCGV, TCGV, unsigned, unsigned) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f2928ae8e7..1d154fc12d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -197,20 +197,6 @@ static void DNI tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i= 64 a1, TCGv_i64 a2, tcgv_i64_arg(a3), a4); } =20 -static void DNI tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4, a5); -} - -static void DNI tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4, a5); -} - /* Generic ops. */ =20 void gen_set_label(TCGLabel *l) @@ -550,6 +536,26 @@ void tcg_gen_deposit(TCGType type, TCGTemp *dst, TCGTe= mp *src1, } } =20 +void tcg_gen_deposit_z(TCGType type, TCGTemp *dst, TCGTemp *src, + unsigned int ofs, unsigned int len) +{ + unsigned width =3D tcg_type_bits(type); + + tcg_debug_assert(ofs < width); + tcg_debug_assert(len > 0); + tcg_debug_assert(len <=3D width); + tcg_debug_assert(ofs + len <=3D width); + + if (ofs + len =3D=3D width) { + tcg_gen_shli(type, dst, src, ofs); + } else if (ofs =3D=3D 0) { + tcg_gen_extract(type, dst, src, 0, len); + } else { + TCGTemp *zero =3D tcg_constant_internal(type, 0); + tcg_gen_op_tttii(INDEX_op_deposit, type, dst, zero, src, ofs, len); + } +} + void tcg_gen_discard(TCGType type, TCGTemp *src) { tcg_gen_op1(INDEX_op_discard, type, temp_arg(src)); @@ -1012,24 +1018,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len) -{ - tcg_debug_assert(ofs < 32); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 32); - tcg_debug_assert(ofs + len <=3D 32); - - if (ofs + len =3D=3D 32) { - tcg_gen_shli_i32(ret, arg, ofs); - } else if (ofs =3D=3D 0) { - tcg_gen_extract_i32(ret, arg, 0, len); - } else { - TCGv_i32 zero =3D tcg_constant_i32(0); - tcg_gen_op5ii_i32(INDEX_op_deposit, ret, zero, arg, ofs, len); - } -} - /* * Extract 32-bits from a 64-bit input, ah:al, starting from ofs. * Unlike tcg_gen_extract_i32 above, len is fixed at 32. @@ -1681,24 +1669,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len) -{ - tcg_debug_assert(ofs < 64); - tcg_debug_assert(len > 0); - tcg_debug_assert(len <=3D 64); - tcg_debug_assert(ofs + len <=3D 64); - - if (ofs + len =3D=3D 64) { - tcg_gen_shli_i64(ret, arg, ofs); - } else if (ofs =3D=3D 0) { - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else { - TCGv_i64 zero =3D tcg_constant_i64(0); - tcg_gen_op5ii_i64(INDEX_op_deposit, ret, zero, arg, ofs, len); - } -} - /* * Extract 64 bits from a 128-bit input, ah:al, starting from ofs. * Unlike tcg_gen_extract_i64 above, len is fixed at 64. --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593463; cv=none; d=zohomail.com; s=zohoarc; b=NTChAWI6po/J8/jrvw+14RZ6BGquGKDhms4w1yyFOPO/1Ux3M2cBvJ18Qr1YC4ryuiFgOGfKeNsIH/6iYZTVcD3We7tzVldf7QY42Uh2gMta8FQ6ULg/ceYWt1uMIXhQPRmgSQDe2BV4uClWPJbDq3Zv0L2Uh83B3BtApu1JcEw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593463; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 21 Oct 2026 07:22:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 065/100] tcg: Generic expansion of tcg_gen_ext8s_* Date: Wed, 21 Oct 2026 16:16:17 +0200 Message-ID: <20261021141652.363109-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593465690158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 85af0d4b6c..f2e69a21e1 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -143,7 +143,6 @@ void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -187,7 +186,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, = TCGv_i64 *b); void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); -void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 88e87ebc2f..a5b2bdcb43 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -19,6 +19,7 @@ DEF4(deposit_z, TCGV, TCGV, unsigned, unsigned) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) +DEF2(ext8s, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1d154fc12d..3c1e1fa958 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -599,6 +599,11 @@ void tcg_gen_eqv(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) } } =20 +void tcg_gen_ext8s(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_sextract(type, dst, src, 0, 8); +} + void tcg_gen_extract(TCGType type, TCGTemp *dst, TCGTemp *src, unsigned int ofs, unsigned int len) { @@ -1164,11 +1169,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TC= Gv_i32 arg1, TCGv_i32 arg2) tcg_temp_free_i64(t1); } =20 -void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - tcg_gen_sextract_i32(ret, arg, 0, 8); -} - void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) { tcg_gen_sextract_i32(ret, arg, 0, 16); @@ -1470,11 +1470,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_sextract_i64(ret, arg, 0, 8); -} - void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_sextract_i64(ret, arg, 0, 16); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:22:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 066/100] tcg: Generic expansion of tcg_gen_ext8u_* Date: Wed, 21 Oct 2026 16:16:18 +0200 Message-ID: <20261021141652.363109-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593050333158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f2e69a21e1..798785bc7b 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -144,7 +144,6 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i= 32 arg1, TCGv_i32 arg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); @@ -188,7 +187,6 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i= 64 arg1, TCGv_i64 arg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index a5b2bdcb43..1cdcf3aeec 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -20,6 +20,7 @@ DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) DEF2(ext8s, TCGV, TCGV) +DEF2(ext8u, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3c1e1fa958..120dbe11dd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -604,6 +604,11 @@ void tcg_gen_ext8s(TCGType type, TCGTemp *dst, TCGTemp= *src) tcg_gen_sextract(type, dst, src, 0, 8); } =20 +void tcg_gen_ext8u(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_extract(type, dst, src, 0, 8); +} + void tcg_gen_extract(TCGType type, TCGTemp *dst, TCGTemp *src, unsigned int ofs, unsigned int len) { @@ -1174,11 +1179,6 @@ void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_gen_sextract_i32(ret, arg, 0, 16); } =20 -void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - tcg_gen_extract_i32(ret, arg, 0, 8); -} - void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) { tcg_gen_extract_i32(ret, arg, 0, 16); @@ -1480,11 +1480,6 @@ void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_gen_sextract_i64(ret, arg, 0, 32); } =20 -void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_extract_i64(ret, arg, 0, 8); -} - void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_extract_i64(ret, arg, 0, 16); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 07:22:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 067/100] tcg: Generic expansion of tcg_gen_ext16s_* Date: Wed, 21 Oct 2026 16:16:19 +0200 Message-ID: <20261021141652.363109-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592842551158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 798785bc7b..cbeae67794 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -143,7 +143,6 @@ void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); @@ -185,7 +184,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, = TCGv_i64 *b); void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); -void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 1cdcf3aeec..4c1fc9633c 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -21,6 +21,7 @@ DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) DEF2(ext8s, TCGV, TCGV) DEF2(ext8u, TCGV, TCGV) +DEF2(ext16s, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 120dbe11dd..55bd8ccf8f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -609,6 +609,11 @@ void tcg_gen_ext8u(TCGType type, TCGTemp *dst, TCGTemp= *src) tcg_gen_extract(type, dst, src, 0, 8); } =20 +void tcg_gen_ext16s(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_sextract(type, dst, src, 0, 16); +} + void tcg_gen_extract(TCGType type, TCGTemp *dst, TCGTemp *src, unsigned int ofs, unsigned int len) { @@ -1174,11 +1179,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TC= Gv_i32 arg1, TCGv_i32 arg2) tcg_temp_free_i64(t1); } =20 -void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - tcg_gen_sextract_i32(ret, arg, 0, 16); -} - void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) { tcg_gen_extract_i32(ret, arg, 0, 16); @@ -1470,11 +1470,6 @@ void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tc= g_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); } =20 -void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_sextract_i64(ret, arg, 0, 16); -} - void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_sextract_i64(ret, arg, 0, 32); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 068/100] tcg: Generic expansion of tcg_gen_ext16u_* Date: Wed, 21 Oct 2026 16:16:20 +0200 Message-ID: <20261021141652.363109-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593105104158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index cbeae67794..3af56710cb 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -143,7 +143,6 @@ void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -185,7 +184,6 @@ void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i= 64 arg1, TCGv_i64 arg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc); void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 4c1fc9633c..6208a51f53 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -22,6 +22,7 @@ DEF3(divu, TCGV, TCGV, TCGV) DEF2(ext8s, TCGV, TCGV) DEF2(ext8u, TCGV, TCGV) DEF2(ext16s, TCGV, TCGV) +DEF2(ext16u, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 55bd8ccf8f..3c34f503e7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -614,6 +614,11 @@ void tcg_gen_ext16s(TCGType type, TCGTemp *dst, TCGTem= p *src) tcg_gen_sextract(type, dst, src, 0, 16); } =20 +void tcg_gen_ext16u(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + tcg_gen_extract(type, dst, src, 0, 16); +} + void tcg_gen_extract(TCGType type, TCGTemp *dst, TCGTemp *src, unsigned int ofs, unsigned int len) { @@ -1179,11 +1184,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TC= Gv_i32 arg1, TCGv_i32 arg2) tcg_temp_free_i64(t1); } =20 -void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - tcg_gen_extract_i32(ret, arg, 0, 16); -} - /* * Internal helper for bit and byte reversal. * Given a repeating matched block of 1's and 0's, swap the bits within @@ -1475,11 +1475,6 @@ void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_gen_sextract_i64(ret, arg, 0, 32); } =20 -void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - tcg_gen_extract_i64(ret, arg, 0, 16); -} - void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_extract_i64(ret, arg, 0, 32); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op-ldst.c | 54 ------------------------------------ tcg/tcg-op.c | 13 +++++++++ 4 files changed, 14 insertions(+), 56 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 3af56710cb..911b94f9c4 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -143,7 +143,6 @@ void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -185,7 +184,6 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i= 64 arg1, TCGv_i64 arg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc); void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 6208a51f53..f9812c1f88 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -19,6 +19,7 @@ DEF4(deposit_z, TCGV, TCGV, unsigned, unsigned) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) +DEF3(ext, TCGV, TCGV, MemOp) DEF2(ext8s, TCGV, TCGV) DEF2(ext8u, TCGV, TCGV) DEF2(ext16s, TCGV, TCGV) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 22211ccb45..031c5ce926 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -760,60 +760,6 @@ void tcg_gen_qemu_st_i128_chk(TCGv_i128 val, TCGTemp *= addr, TCGArg idx, tcg_gen_qemu_st_i128_int(val, addr, idx, memop); } =20 -void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) -{ - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_gen_ext8s_i32(ret, val); - break; - case MO_UB: - tcg_gen_ext8u_i32(ret, val); - break; - case MO_SW: - tcg_gen_ext16s_i32(ret, val); - break; - case MO_UW: - tcg_gen_ext16u_i32(ret, val); - break; - case MO_UL: - case MO_SL: - tcg_gen_mov_i32(ret, val); - break; - default: - g_assert_not_reached(); - } -} - -void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc) -{ - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_gen_ext8s_i64(ret, val); - break; - case MO_UB: - tcg_gen_ext8u_i64(ret, val); - break; - case MO_SW: - tcg_gen_ext16s_i64(ret, val); - break; - case MO_UW: - tcg_gen_ext16u_i64(ret, val); - break; - case MO_SL: - tcg_gen_ext32s_i64(ret, val); - break; - case MO_UL: - tcg_gen_ext32u_i64(ret, val); - break; - case MO_UQ: - case MO_SQ: - tcg_gen_mov_i64(ret, val); - break; - default: - g_assert_not_reached(); - } -} - typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv_i64, TCGv_i32, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv_i64, diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3c34f503e7..11676eff30 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -282,6 +282,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #define C_TCGv_i64 tcgv_i64_temp #define C_int32_t #define C_int64_t +#define C_MemOp #define C_TCGCond #define C_TCGLabelPtr #define C_unsigned @@ -312,6 +313,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #undef C_TCGv_i64 #undef C_int32_t #undef C_int64_t +#undef C_MemOp #undef C_TCGCond #undef C_TCGLabelPtr #undef C_unsigned @@ -599,6 +601,17 @@ void tcg_gen_eqv(TCGType type, TCGTemp *dst, TCGTemp *= src1, TCGTemp *src2) } } =20 +void tcg_gen_ext(TCGType type, TCGTemp *dst, TCGTemp *src, MemOp mop) +{ + unsigned width =3D memop_size(mop) * 8; + + if (mop & MO_SIGN) { + tcg_gen_sextract(type, dst, src, 0, width); + } else { + tcg_gen_extract(type, dst, src, 0, width); + } +} + void tcg_gen_ext8s(TCGType type, TCGTemp *dst, TCGTemp *src) { tcg_gen_sextract(type, dst, src, 0, 8); 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Wed, 21 Oct 2026 07:22:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 070/100] tcg: Generic expansion of tcg_gen_smin_* Date: Wed, 21 Oct 2026 16:16:22 +0200 Message-ID: <20261021141652.363109-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593623658158501 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 27 +++++++++------------------ 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 911b94f9c4..54ad54b0da 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,7 +146,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_= i32 arg1, TCGv_i32 arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); @@ -189,7 +188,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, in= t flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index f9812c1f88..1486066728 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -55,6 +55,7 @@ DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) DEF3(shri, TCGV, TCGV, TINT) +DEF3(smin, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 11676eff30..24e7d6da50 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1013,6 +1013,15 @@ void tcg_gen_shri(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) } } =20 +void tcg_gen_smin(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_smin, type, 0)) { + tcg_gen_op_ttt(INDEX_op_smin, type, dst, src1, src2); + } else { + tcg_gen_movcond(type, TCG_COND_LT, dst, src1, src2, src1, src2); + } +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -1329,15 +1338,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ - if (tcg_op_supported(INDEX_op_smin, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_smin, ret, a, b); - } else { - tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); - } -} - void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I32, 0)) { @@ -1869,15 +1869,6 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TC= Gv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } =20 -void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ - if (tcg_op_supported(INDEX_op_smin, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_smin, ret, a, b); - } else { - tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); 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Wed, 21 Oct 2026 07:22:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 071/100] tcg: Generic expansion of tcg_gen_smax_* Date: Wed, 21 Oct 2026 16:16:23 +0200 Message-ID: <20261021141652.363109-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593398717158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 27 +++++++++------------------ 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 54ad54b0da..7214846b81 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,7 +146,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_= i32 arg1, TCGv_i32 arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); @@ -188,7 +187,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, in= t flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ussub_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 1486066728..de3feeabdb 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -55,6 +55,7 @@ DEF3(shl, TCGV, TCGV, TCGV) DEF3(shli, TCGV, TCGV, TINT) DEF3(shr, TCGV, TCGV, TCGV) DEF3(shri, TCGV, TCGV, TINT) +DEF3(smax, TCGV, TCGV, TCGV) DEF3(smin, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 24e7d6da50..c97b0ad64a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1013,6 +1013,15 @@ void tcg_gen_shri(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) } } =20 +void tcg_gen_smax(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_smax, type, 0)) { + tcg_gen_op_ttt(INDEX_op_smax, type, dst, src1, src2); + } else { + tcg_gen_movcond(type, TCG_COND_GT, dst, src1, src2, src1, src2); + } +} + void tcg_gen_smin(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_smin, type, 0)) { @@ -1347,15 +1356,6 @@ void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv= _i32 b) } } =20 -void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ - if (tcg_op_supported(INDEX_op_smax, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_smax, ret, a, b); - } else { - tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); - } -} - void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I32, 0)) { @@ -1878,15 +1878,6 @@ void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv= _i64 b) } } =20 -void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ - if (tcg_op_supported(INDEX_op_smax, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_smax, ret, a, b); - } else { - tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); - } -} - void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) { if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 072/100] tcg: Generic expansion of tcg_gen_umin_* Date: Wed, 21 Oct 2026 16:16:24 +0200 Message-ID: <20261021141652.363109-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593582713158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 27 +++++++++------------------ 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 7214846b81..e23f247b90 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,7 +146,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_= i32 arg1, TCGv_i32 arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); @@ -187,7 +186,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, in= t flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ussub_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index de3feeabdb..7d1035a8c8 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -60,5 +60,6 @@ DEF3(smin, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) +DEF3(umin, TCGV, TCGV, TCGV) DEF3(xor, TCGV, TCGV, TCGV) DEF3(xori, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c97b0ad64a..7a5e992557 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1050,6 +1050,15 @@ void tcg_gen_subfi(TCGType type, TCGTemp *dst, int64= _t src1, TCGTemp *src2) } } =20 +void tcg_gen_umin(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_umin, type, 0)) { + tcg_gen_op_ttt(INDEX_op_umin, type, dst, src1, src2); + } else { + tcg_gen_movcond(type, TCG_COND_LTU, dst, src1, src2, src1, src2); + } +} + void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_xor, type, dst, src1, src2); @@ -1347,15 +1356,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ - if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_umin, ret, a, b); - } else { - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); - } -} - void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I32, 0)) { @@ -1869,15 +1869,6 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TC= Gv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } =20 -void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ - if (tcg_op_supported(INDEX_op_umin, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_umin, ret, a, b); - } else { - tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); 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Wed, 21 Oct 2026 07:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 073/100] tcg: Generic expansion of tcg_gen_umax_* Date: Wed, 21 Oct 2026 16:16:25 +0200 Message-ID: <20261021141652.363109-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592702128158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 27 +++++++++------------------ 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index e23f247b90..4a79e3e1f6 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,7 +146,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_= i32 arg1, TCGv_i32 arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -186,7 +185,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, in= t flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_ussub_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 7d1035a8c8..3c93c20704 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -60,6 +60,7 @@ DEF3(smin, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) +DEF3(umax, TCGV, TCGV, TCGV) DEF3(umin, TCGV, TCGV, TCGV) DEF3(xor, TCGV, TCGV, TCGV) DEF3(xori, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7a5e992557..a288c14813 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1050,6 +1050,15 @@ void tcg_gen_subfi(TCGType type, TCGTemp *dst, int64= _t src1, TCGTemp *src2) } } =20 +void tcg_gen_umax(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_umax, type, 0)) { + tcg_gen_op_ttt(INDEX_op_umax, type, dst, src1, src2); + } else { + tcg_gen_movcond(type, TCG_COND_GTU, dst, src1, src2, src1, src2); + } +} + void tcg_gen_umin(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_umin, type, 0)) { @@ -1356,15 +1365,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ - if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_umax, ret, a, b); - } else { - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); - } -} - void tcg_gen_ussub_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) { TCGv_i32 t =3D tcg_temp_ebb_new_i32(); @@ -1869,15 +1869,6 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TC= Gv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } =20 -void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ - if (tcg_op_supported(INDEX_op_umax, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_umax, ret, a, b); - } else { - tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); 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Wed, 21 Oct 2026 07:22:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 074/100] tcg: Generic expansion of tcg_gen_abs_* Date: Wed, 21 Oct 2026 16:16:26 +0200 Message-ID: <20261021141652.363109-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593310825158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 34 ++++++++++++++-------------------- 3 files changed, 15 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 4a79e3e1f6..9491879685 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -147,7 +147,6 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, in= t flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); =20 @@ -186,7 +185,6 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ussub_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 3c93c20704..19c6347fa7 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: MIT */ /* Templated TCGv_i32 and TCGv_i64 operations */ =20 +DEF2(abs, TCGV, TCGV) DEF3(add, TCGV, TCGV, TCGV) DEF3(addi, TCGV, TCGV, TINT) DEF3(and, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a288c14813..c1ce4172ef 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -331,6 +331,20 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) * are of the proper type. */ =20 +void tcg_gen_abs(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + if (tcg_op_supported(INDEX_op_smax, type, 0)) { + tcg_gen_neg(type, tmp, src); + tcg_gen_smax(type, dst, tmp, src); + } else { + tcg_gen_sari(type, tmp, src, tcg_type_bits(type) - 1); + tcg_gen_xor(type, dst, src, tmp); + tcg_gen_sub(type, dst, dst, tmp); + } +} + void tcg_gen_add(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_add, type, dst, src1, src2); @@ -1375,16 +1389,6 @@ void tcg_gen_ussub_i32(TCGv_i32 ret, TCGv_i32 a, TCG= v_i32 b) tcg_temp_free_i32(t); } =20 -void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) -{ - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - - tcg_gen_sari_i32(t, a, 31); - tcg_gen_xor_i32(ret, a, t); - tcg_gen_sub_i32(ret, ret, t); - tcg_temp_free_i32(t); -} - void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld8u, ret, arg2, offset); @@ -1879,16 +1883,6 @@ void tcg_gen_ussub_i64(TCGv_i64 ret, TCGv_i64 a, TCG= v_i64 b) tcg_temp_free_i64(t); } =20 -void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) -{ - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); 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Wed, 21 Oct 2026 07:22:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 075/100] tcg: Generic expansion of tcg_gen_ussub_* Date: Wed, 21 Oct 2026 16:16:27 +0200 Message-ID: <20261021141652.363109-76-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593302583158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 29 +++++++++-------------------- 3 files changed, 10 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9491879685..6942012787 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -146,7 +146,6 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_= i32 arg1, TCGv_i32 arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ussub_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); =20 @@ -184,7 +183,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, in= t flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ussub_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 19c6347fa7..82dfc90009 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -63,5 +63,6 @@ DEF3(subi, TCGV, TCGV, TINT) DEF3(subfi, TCGV, TINT, TCGV) DEF3(umax, TCGV, TCGV, TCGV) DEF3(umin, TCGV, TCGV, TCGV) +DEF3(ussub, TCGV, TCGV, TCGV) DEF3(xor, TCGV, TCGV, TCGV) DEF3(xori, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c1ce4172ef..c5329a8d95 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1082,6 +1082,15 @@ void tcg_gen_umin(TCGType type, TCGTemp *dst, TCGTem= p *src1, TCGTemp *src2) } } =20 +void tcg_gen_ussub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src= 2) +{ + g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); + + tcg_gen_sub(type, tmp, src1, src2); + tcg_gen_movcond(type, TCG_COND_LTU, dst, src1, src2, + tcg_constant_internal(type, 0), tmp); +} + void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_xor, type, dst, src1, src2); @@ -1379,16 +1388,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_ussub_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - TCGv_i32 z =3D tcg_constant_i32(0); - - tcg_gen_sub_i32(t, a, b); - tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, z, t); - tcg_temp_free_i32(t); -} - void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld8u, ret, arg2, offset); @@ -1873,16 +1872,6 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TC= Gv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } =20 -void tcg_gen_ussub_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) -{ - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - TCGv_i64 z =3D tcg_constant_i64(0); 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Wed, 21 Oct 2026 07:22:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 076/100] tcg: Use umax in ussub if available Date: Wed, 21 Oct 2026 16:16:28 +0200 Message-ID: <20261021141652.363109-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593335305158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/tcg-op.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c5329a8d95..f6cc56661d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1086,9 +1086,18 @@ void tcg_gen_ussub(TCGType type, TCGTemp *dst, TCGTe= mp *src1, TCGTemp *src2) { g_autoptr(TCGTemp) tmp =3D tcg_temp_new_ebb(type); =20 - tcg_gen_sub(type, tmp, src1, src2); - tcg_gen_movcond(type, TCG_COND_LTU, dst, src1, src2, - tcg_constant_internal(type, 0), tmp); + if (tcg_op_supported(INDEX_op_umax, type, 0)) { + tcg_gen_umax(type, tmp, src1, src2); + tcg_gen_sub(type, dst, tmp, src2); + } else { + /* + * While umax can be expanded with movcond, some hosts can + * perform movcond with a zero source in fewer insns. + */ + tcg_gen_sub(type, tmp, src1, src2); + tcg_gen_movcond(type, TCG_COND_LTU, dst, src1, src2, + tcg_constant_internal(type, 0), tmp); + } } =20 void tcg_gen_xor(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 077/100] tcg: Generic expansion of tcg_gen_extract2_* Date: Wed, 21 Oct 2026 16:16:29 +0200 Message-ID: <20261021141652.363109-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593323181158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 69 +++++++++--------------------------- 3 files changed, 18 insertions(+), 56 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 6942012787..c1c41a03f3 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,8 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, - unsigned int ofs); void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, @@ -164,8 +162,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, - unsigned int ofs); void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 82dfc90009..a237ccd0c5 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -26,6 +26,7 @@ DEF2(ext8u, TCGV, TCGV) DEF2(ext16s, TCGV, TCGV) DEF2(ext16u, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) +DEF4(extract2, TCGV, TCGV, TCGV, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f6cc56661d..712536cfc2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -183,20 +183,6 @@ static void DNI tcg_gen_op4_i64(TCGOpcode opc, TCGv_i6= 4 a1, TCGv_i64 a2, tcgv_i64_arg(a3), tcgv_i64_arg(a4)); } =20 -static void DNI tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGArg a4) -{ - tcg_gen_op4(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4); -} - -static void DNI tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGArg a4) -{ - tcg_gen_op4(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4); -} - /* Generic ops. */ =20 void gen_set_label(TCGLabel *l) @@ -691,6 +677,23 @@ void tcg_gen_extract(TCGType type, TCGTemp *dst, TCGTe= mp *src, } } =20 +void tcg_gen_extract2(TCGType type, TCGTemp *dst, TCGTemp *lo, TCGTemp *hi, + unsigned int ofs) +{ + unsigned width =3D tcg_type_bits(type); + + tcg_debug_assert(ofs <=3D width); + if (ofs =3D=3D 0) { + tcg_gen_mov(type, dst, lo); + } else if (ofs =3D=3D width) { + tcg_gen_mov(type, dst, hi); + } else if (lo =3D=3D hi) { + tcg_gen_rotri(type, dst, lo, ofs); + } else { + tcg_gen_op_ttti(INDEX_op_extract2, type, dst, lo, hi, ofs); + } +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -1119,25 +1122,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) =20 /* 32 bit ops */ =20 -/* - * Extract 32-bits from a 64-bit input, ah:al, starting from ofs. - * Unlike tcg_gen_extract_i32 above, len is fixed at 32. - */ -void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, - unsigned int ofs) -{ - tcg_debug_assert(ofs <=3D 32); - if (ofs =3D=3D 0) { - tcg_gen_mov_i32(ret, al); - } else if (ofs =3D=3D 32) { - tcg_gen_mov_i32(ret, ah); - } else if (al =3D=3D ah) { - tcg_gen_rotri_i32(ret, al, ofs); - } else { - tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs); - } -} - void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { @@ -1674,25 +1658,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -/* - * Extract 64 bits from a 128-bit input, ah:al, starting from ofs. - * Unlike tcg_gen_extract_i64 above, len is fixed at 64. - */ -void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, - unsigned int ofs) -{ - tcg_debug_assert(ofs <=3D 64); - if (ofs =3D=3D 0) { - tcg_gen_mov_i64(ret, al); - } else if (ofs =3D=3D 64) { - tcg_gen_mov_i64(ret, ah); - } else if (al =3D=3D ah) { - tcg_gen_rotri_i64(ret, al, ofs); - } else { - tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs); - } -} - void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:22:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 078/100] tcg: Generic expansion of tcg_gen_addcio_* Date: Wed, 21 Oct 2026 16:16:30 +0200 Message-ID: <20261021141652.363109-79-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593074706158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 77 +++++++++++------------------------- 3 files changed, 24 insertions(+), 58 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index c1c41a03f3..84fdadc63b 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -136,8 +136,6 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i3= 2 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); -void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, - TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci); void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); @@ -166,8 +164,6 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i6= 4 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co, - TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci); void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index a237ccd0c5..003384b65d 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -4,6 +4,7 @@ DEF2(abs, TCGV, TCGV) DEF3(add, TCGV, TCGV, TCGV) DEF3(addi, TCGV, TCGV, TINT) +DEF5(addcio, TCGV, TCGV, TCGV, TCGV, TCGV) DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) DEF3(andc, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 712536cfc2..51d5f70ebb 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -345,6 +345,29 @@ void tcg_gen_addi(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_addcio(TCGType type, TCGTemp *r, TCGTemp *co, + TCGTemp *a, TCGTemp *b, TCGTemp *ci) +{ + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + + if (tcg_op_supported(INDEX_op_addci, type, 0)) { + TCGTemp *zero =3D tcg_constant_internal(type, 0); + TCGTemp *mone =3D tcg_constant_internal(type, -1); + + tcg_gen_op_ttt(INDEX_op_addco, type, t0, ci, mone); + tcg_gen_op_ttt(INDEX_op_addcio, type, r, a, b); + tcg_gen_op_ttt(INDEX_op_addci, type, co, zero, zero); + } else { + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + + tcg_gen_add(type, t0, a, b); + tcg_gen_setcond(type, TCG_COND_LTU, t1, t0, a); + tcg_gen_add(type, r, t0, ci); + tcg_gen_setcond(type, TCG_COND_LTU, t0, r, t0); + tcg_gen_or(type, co, t0, t1); + } +} + void tcg_gen_and(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_and, type, dst, src1, src2); @@ -1144,33 +1167,6 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv= _i32 al, } } =20 -void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co, - TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci) -{ - if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 zero =3D tcg_constant_i32(0); - TCGv_i32 mone =3D tcg_constant_i32(-1); - - tcg_gen_op3_i32(INDEX_op_addco, t0, ci, mone); - tcg_gen_op3_i32(INDEX_op_addcio, r, a, b); - tcg_gen_op3_i32(INDEX_op_addci, co, zero, zero); - tcg_temp_free_i32(t0); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - - tcg_gen_add_i32(t0, a, b); - tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, a); - tcg_gen_add_i32(r, t0, ci); - tcg_gen_setcond_i32(TCG_COND_LTU, t0, r, t0); - tcg_gen_or_i32(co, t0, t1); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } -} - void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { @@ -1681,33 +1677,6 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv= _i64 al, } } =20 -void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co, - TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci) -{ - if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I64, 0)) { - TCGv_i64 discard =3D tcg_temp_ebb_new_i64(); - TCGv_i64 zero =3D tcg_constant_i64(0); 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Wed, 21 Oct 2026 07:22:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 079/100] tcg: Generic expansion of tcg_gen_add2_* Date: Wed, 21 Oct 2026 16:16:31 +0200 Message-ID: <20261021141652.363109-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593586817158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 64 +++++++++++------------------------- 3 files changed, 20 insertions(+), 49 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 84fdadc63b..109cad57ea 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,8 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); @@ -160,8 +158,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 003384b65d..e9f0b971a2 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -4,6 +4,7 @@ DEF2(abs, TCGV, TCGV) DEF3(add, TCGV, TCGV, TCGV) DEF3(addi, TCGV, TCGV, TINT) +DEF6(add2, TCGV, TCGV, TCGV, TCGV, TCGV, TCGV) DEF5(addcio, TCGV, TCGV, TCGV, TCGV, TCGV) DEF3(and, TCGV, TCGV, TCGV) DEF3(andi, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 51d5f70ebb..ff4dc6c531 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -345,6 +345,25 @@ void tcg_gen_addi(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_add2(TCGType type, TCGTemp *rl, TCGTemp *rh, TCGTemp *al, + TCGTemp *ah, TCGTemp *bl, TCGTemp *bh) +{ + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + + if (tcg_op_supported(INDEX_op_addci, type, 0)) { + tcg_gen_op_ttt(INDEX_op_addco, type, t0, al, bl); + tcg_gen_op_ttt(INDEX_op_addci, type, rh, ah, bh); + } else { + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + + tcg_gen_add(type, t0, al, bl); + tcg_gen_setcond(type, TCG_COND_LTU, t1, t0, al); + tcg_gen_add(type, rh, ah, bh); + tcg_gen_add(type, rh, rh, t1); + } + tcg_gen_mov(type, rl, t0); +} + void tcg_gen_addcio(TCGType type, TCGTemp *r, TCGTemp *co, TCGTemp *a, TCGTemp *b, TCGTemp *ci) { @@ -1145,28 +1164,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) -{ - if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_op3_i32(INDEX_op_addco, t0, al, bl); - tcg_gen_op3_i32(INDEX_op_addci, rh, ah, bh); - tcg_gen_mov_i32(rl, t0); - tcg_temp_free_i32(t0); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - tcg_gen_add_i32(t0, al, bl); - tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, al); - tcg_gen_add_i32(rh, ah, bh); - tcg_gen_add_i32(rh, rh, t1); - tcg_gen_mov_i32(rl, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } -} - void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) { @@ -1654,29 +1651,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) } } =20 -void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ - if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_REG, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - - tcg_gen_op3_i64(INDEX_op_addco, t0, al, bl); - tcg_gen_op3_i64(INDEX_op_addci, rh, ah, bh); - tcg_gen_mov_i64(rl, t0); - tcg_temp_free_i64(t0); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_add_i64(t0, al, bl); - tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al); - tcg_gen_add_i64(rh, ah, bh); - tcg_gen_add_i64(rh, rh, t1); - tcg_gen_mov_i64(rl, t0); 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Wed, 21 Oct 2026 07:26:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 080/100] tcg: Generic expansion of tcg_gen_sub2_* Date: Wed, 21 Oct 2026 16:16:32 +0200 Message-ID: <20261021141652.363109-81-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792592887601158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 64 +++++++++++------------------------- 3 files changed, 20 insertions(+), 49 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 109cad57ea..036b3de920 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,8 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); @@ -158,8 +156,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); =20 /* 64 bit ops */ =20 -void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index e9f0b971a2..14bdabb2f1 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -63,6 +63,7 @@ DEF3(smax, TCGV, TCGV, TCGV) DEF3(smin, TCGV, TCGV, TCGV) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) +DEF6(sub2, TCGV, TCGV, TCGV, TCGV, TCGV, TCGV) DEF3(subfi, TCGV, TINT, TCGV) DEF3(umax, TCGV, TCGV, TCGV) DEF3(umin, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ff4dc6c531..aaf18b58f7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1100,6 +1100,25 @@ void tcg_gen_subi(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) tcg_gen_addi(type, dst, src1, -src2); } =20 +void tcg_gen_sub2(TCGType type, TCGTemp *rl, TCGTemp *rh, TCGTemp *al, + TCGTemp *ah, TCGTemp *bl, TCGTemp *bh) +{ + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + + if (tcg_op_supported(INDEX_op_subbi, type, 0)) { + tcg_gen_op_ttt(INDEX_op_subbo, type, t0, al, bl); + tcg_gen_op_ttt(INDEX_op_subbi, type, rh, ah, bh); + } else { + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + + tcg_gen_sub(type, t0, al, bl); + tcg_gen_setcond(type, TCG_COND_LTU, t1, al, bl); + tcg_gen_sub(type, rh, ah, bh); + tcg_gen_sub(type, rh, rh, t1); + } + tcg_gen_mov(type, rl, t0); +} + void tcg_gen_subfi(TCGType type, TCGTemp *dst, int64_t src1, TCGTemp *src2) { if (src1 =3D=3D 0) { @@ -1164,28 +1183,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) -{ - if (tcg_op_supported(INDEX_op_subbi, TCG_TYPE_I32, 0)) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_op3_i32(INDEX_op_subbo, t0, al, bl); - tcg_gen_op3_i32(INDEX_op_subbi, rh, ah, bh); - tcg_gen_mov_i32(rl, t0); - tcg_temp_free_i32(t0); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - tcg_gen_sub_i32(t0, al, bl); - tcg_gen_setcond_i32(TCG_COND_LTU, t1, al, bl); - tcg_gen_sub_i32(rh, ah, bh); - tcg_gen_sub_i32(rh, rh, t1); - tcg_gen_mov_i32(rl, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } -} - void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2) { if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I32, 0)) { @@ -1693,29 +1690,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *= a, TCGv_i64 *b) } } =20 -void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) -{ - if (tcg_op_supported(INDEX_op_subbi, TCG_TYPE_REG, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - - tcg_gen_op3_i64(INDEX_op_subbo, t0, al, bl); - tcg_gen_op3_i64(INDEX_op_subbi, rh, ah, bh); - tcg_gen_mov_i64(rl, t0); - tcg_temp_free_i64(t0); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_sub_i64(t0, al, bl); - tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl); 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Wed, 21 Oct 2026 07:26:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 081/100] tcg: Generic expansion of tcg_gen_mulu2_* Date: Wed, 21 Oct 2026 16:16:33 +0200 Message-ID: <20261021141652.363109-82-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593298693158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 - tcg/tcg-internal.h | 7 ++++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 72 ++++++++++++++++-------------------- 4 files changed, 39 insertions(+), 43 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 036b3de920..cd30395c70 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,7 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); @@ -157,7 +156,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); /* 64 bit ops */ =20 void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); -void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 13c4be5a5c..09899cb309 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -126,6 +126,13 @@ static inline void tcg_gen_op_ttti(TCGOpcode opc, TCGT= ype type, TCGTemp *t0, tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), temp_arg(t2), a3); } =20 +static inline void tcg_gen_op_tttt(TCGOpcode opc, TCGType type, TCGTemp *t= 0, + TCGTemp *t1, TCGTemp *t2, TCGTemp *t3) +{ + tcg_gen_op4(opc, type, temp_arg(t0), temp_arg(t1), + temp_arg(t2), temp_arg(t3)); +} + static inline void tcg_gen_op_tttii(TCGOpcode opc, TCGType type, TCGTemp *t0, TCGTemp *t1, TCGTemp *t2, TCGArg a3, TCGArg a4) diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 14bdabb2f1..b24122173a 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -35,6 +35,7 @@ DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) +DEF4(mulu2, TCGV, TCGV, TCGV, TCGV) DEF3(nand, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) DEF4(negsetcond, TCGCond, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index aaf18b58f7..822ac56c08 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -776,6 +776,37 @@ void tcg_gen_muli(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_mulu2(TCGType type, TCGTemp *rl, TCGTemp *rh, + TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_mulu2, type, 0)) { + tcg_gen_op_tttt(INDEX_op_mulu2, type, rl, rh, src1, src2); + } else if (tcg_op_supported(INDEX_op_muluh, type, 0)) { + g_autoptr(TCGTemp) t =3D tcg_temp_new_ebb(type); + + tcg_gen_mul(type, t, src1, src2); + tcg_gen_op_ttt(INDEX_op_muluh, type, rh, src1, src2); + tcg_gen_mov(type, rl, t); + } else if (type =3D=3D TCG_TYPE_I32) { + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + + /* Simply extend and use host 64-bit multiply. */ + tcg_gen_extu(t0, src1); + tcg_gen_extu(t1, src2); + tcg_gen_mul(TCG_TYPE_I64, t0, t0, t1); + tcg_gen_extrl(rl, t0); + tcg_gen_extrh(rh, t0); + } else { + g_autoptr(TCGTemp) t =3D tcg_temp_new_ebb(type); + + tcg_gen_mul(TCG_TYPE_I64, t, src1, src2); + gen_helper_muluh_i64(temp_tcgv_i64(rh), temp_tcgv_i64(src1), + temp_tcgv_i64(src2)); + tcg_gen_mov(TCG_TYPE_I64, rl, t); + } +} + void tcg_gen_nand(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_nand, type, 0)) { @@ -1183,28 +1214,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I32, 0)) { - tcg_gen_op4_i32(INDEX_op_mulu2, rl, rh, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I32, 0)) { - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2); - tcg_gen_op3_i32(INDEX_op_muluh, rh, arg1, arg2); - tcg_gen_mov_i32(rl, t); - tcg_temp_free_i32(t); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_i32_i64(t0, arg1); - tcg_gen_extu_i32_i64(t1, arg2); - tcg_gen_mul_i64(t0, t0, t1); - tcg_gen_extr_i64_i32(rl, rh, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } -} - void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2) { if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I32, 0)) { @@ -1690,25 +1699,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *= a, TCGv_i64 *b) } } =20 -void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I64, 0)) { - tcg_gen_op4_i64(INDEX_op_mulu2, rl, rh, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I64, 0)) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); 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Wed, 21 Oct 2026 07:26:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 082/100] tcg: Generic expansion of tcg_gen_muls2_* Date: Wed, 21 Oct 2026 16:16:34 +0200 Message-ID: <20261021141652.363109-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593698845158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 - include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 131 +++++++++++++---------------------- 3 files changed, 51 insertions(+), 83 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index cd30395c70..d3271c5a66 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -132,7 +132,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); =20 /* 32 bit ops */ =20 -void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -156,7 +155,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_t= arget_long offset); /* 64 bit ops */ =20 void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); -void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index b24122173a..b606aaab12 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -35,6 +35,7 @@ DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) DEF3(mul, TCGV, TCGV, TCGV) DEF3(muli, TCGV, TCGV, TINT) +DEF4(muls2, TCGV, TCGV, TCGV, TCGV) DEF4(mulu2, TCGV, TCGV, TCGV, TCGV) DEF3(nand, TCGV, TCGV, TCGV) DEF2(neg, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 822ac56c08..94befedb69 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -129,13 +129,6 @@ static void DNI tcg_gen_op2_i64(TCGOpcode opc, TCGv_i6= 4 a1, TCGv_i64 a2) tcg_gen_op2(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); } =20 -static void DNI tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGv_i32 a3) -{ - tcg_gen_op3(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), - tcgv_i32_arg(a2), tcgv_i32_arg(a3)); -} - static void DNI tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3) { @@ -169,20 +162,6 @@ static void DNI tcg_gen_ldst_op_i64(TCGOpcode opc, TCG= v_i64 val, tcgv_ptr_arg(base), offset); } =20 -static void DNI tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4) -{ - tcg_gen_op4(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4)); -} - -static void DNI tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4) -{ - tcg_gen_op4(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4)); -} - /* Generic ops. */ =20 void gen_set_label(TCGLabel *l) @@ -776,6 +755,56 @@ void tcg_gen_muli(TCGType type, TCGTemp *dst, TCGTemp = *src1, int64_t src2) } } =20 +void tcg_gen_muls2(TCGType type, TCGTemp *rl, TCGTemp *rh, + TCGTemp *src1, TCGTemp *src2) +{ + if (tcg_op_supported(INDEX_op_muls2, type, 0)) { + tcg_gen_op_tttt(INDEX_op_muls2, type, rl, rh, src1, src2); + } else if (tcg_op_supported(INDEX_op_mulsh, type, 0)) { + g_autoptr(TCGTemp) t =3D tcg_temp_new_ebb(type); + + tcg_gen_mul(type, t, src1, src2); + tcg_gen_op_ttt(INDEX_op_mulsh, type, rh, src1, src2); + tcg_gen_mov(type, rl, t); + } else if (type =3D=3D TCG_TYPE_I32) { + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(TCG_TYPE_I64); + + /* Simply extend and use host 64-bit multiply. */ + tcg_gen_exts(t0, src1); + tcg_gen_exts(t1, src2); + tcg_gen_mul(TCG_TYPE_I64, t0, t0, t1); + tcg_gen_extrl(rl, t0); + tcg_gen_extrh(rh, t0); + } else if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I64, 0) || + tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I64, 0)) { + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t2 =3D NULL; + g_autoptr(TCGTemp) t3 =3D NULL; + + tcg_gen_mulu2(TCG_TYPE_I64, t0, t1, src1, src2); + + /* Adjust for negative inputs. */ + t2 =3D tcg_temp_new_ebb(type); + t3 =3D tcg_temp_new_ebb(type); + tcg_gen_sari(TCG_TYPE_I64, t2, src1, 63); + tcg_gen_sari(TCG_TYPE_I64, t3, src2, 63); + tcg_gen_and(TCG_TYPE_I64, t2, t2, src2); + tcg_gen_and(TCG_TYPE_I64, t3, t3, src1); + tcg_gen_sub(TCG_TYPE_I64, rh, t1, t2); + tcg_gen_sub(TCG_TYPE_I64, rh, rh, t3); + tcg_gen_mov(TCG_TYPE_I64, rl, t0); + } else { + g_autoptr(TCGTemp) t =3D tcg_temp_new_ebb(type); + + tcg_gen_mul(TCG_TYPE_I64, t, src1, src2); + gen_helper_mulsh_i64(temp_tcgv_i64(rh), temp_tcgv_i64(src1), + temp_tcgv_i64(src2)); + tcg_gen_mov(TCG_TYPE_I64, rl, t); + } +} + void tcg_gen_mulu2(TCGType type, TCGTemp *rl, TCGTemp *rh, TCGTemp *src1, TCGTemp *src2) { @@ -1214,28 +1243,6 @@ void tcg_gen_xori(TCGType type, TCGTemp *dst, TCGTem= p *src1, int64_t src2) =20 /* 32 bit ops */ =20 -void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I32, 0)) { - tcg_gen_op4_i32(INDEX_op_muls2, rl, rh, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I32, 0)) { - TCGv_i32 t =3D tcg_temp_ebb_new_i32(); - tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2); - tcg_gen_op3_i32(INDEX_op_mulsh, rh, arg1, arg2); - tcg_gen_mov_i32(rl, t); - tcg_temp_free_i32(t); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - tcg_gen_ext_i32_i64(t0, arg1); - tcg_gen_ext_i32_i64(t1, arg2); - tcg_gen_mul_i64(t0, t0, t1); - tcg_gen_extr_i64_i32(rl, rh, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } -} - void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -1699,44 +1706,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *= a, TCGv_i64 *b) } } =20 -void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I64, 0)) { - tcg_gen_op4_i64(INDEX_op_muls2, rl, rh, arg1, arg2); - } else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I64, 0)) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2); - tcg_gen_op3_i64(INDEX_op_mulsh, rh, arg1, arg2); - tcg_gen_mov_i64(rl, t); - tcg_temp_free_i64(t); - } else if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I64, 0) || - tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I64, 0)) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t2 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t3 =3D tcg_temp_ebb_new_i64(); - tcg_gen_mulu2_i64(t0, t1, arg1, arg2); - /* Adjust for negative inputs. */ - tcg_gen_sari_i64(t2, arg1, 63); - tcg_gen_sari_i64(t3, arg2, 63); - tcg_gen_and_i64(t2, t2, arg2); - tcg_gen_and_i64(t3, t3, arg1); - tcg_gen_sub_i64(rh, t1, t2); - tcg_gen_sub_i64(rh, rh, t3); - tcg_gen_mov_i64(rl, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_mul_i64(t0, arg1, arg2); - gen_helper_mulsh_i64(rh, arg1, arg2); - tcg_gen_mov_i64(rl, t0); - tcg_temp_free_i64(t0); - } -} - void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); 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Wed, 21 Oct 2026 07:26:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 083/100] tcg: Use unsigned for flags for bswap and revbit operations Date: Wed, 21 Oct 2026 16:16:35 +0200 Message-ID: <20261021141652.363109-84-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593263960158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 8 ++++---- tcg/tcg-op.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index d3271c5a66..9f5cae36c5 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -133,7 +133,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); +void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -158,13 +158,13 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a= , TCGv_i64 *b); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); -void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); +void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); =20 /* Replicate a value of size @vece from @in to all the lanes in @out */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 94befedb69..c3a8a04a4d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1302,7 +1302,7 @@ static void gen_bitswap_i64(TCGv_i64 ret, TCGv_i64 ar= g, uint64_t mask) * With TCG_BSWAP_IZ, x =3D=3D zero, else undefined. * With TCG_BSWAP_OZ, y =3D=3D zero, with TCG_BSWAP_OS y =3D=3D sign, else= undefined. */ -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags) +void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned flags) { /* Only one extension flag may be present. */ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); @@ -1503,7 +1503,7 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) * With TCG_BSWAP_IZ, x =3D=3D zero, else undefined. * With TCG_BSWAP_OZ, y =3D=3D zero, with TCG_BSWAP_OS y =3D=3D sign, else= undefined. */ -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) +void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags) { /* Only one extension flag may be present. */ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); @@ -1546,7 +1546,7 @@ void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, = int flags) * With TCG_BSWAP_IZ, x =3D=3D zero, else undefined. * With TCG_BSWAP_OZ, y =3D=3D zero, with TCG_BSWAP_OS y =3D=3D sign, else= undefined. */ -void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) +void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags) { /* Only one extension flag may be present. */ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); @@ -1613,7 +1613,7 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_gen_rotli_i64(ret, arg, 32); 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Wed, 21 Oct 2026 07:26:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 084/100] tcg: Generic expansion of tcg_gen_bswap16_* Date: Wed, 21 Oct 2026 16:16:36 +0200 Message-ID: <20261021141652.363109-85-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593766200158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 - tcg/tcg-internal.h | 6 ++ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 120 ++++++++++------------------------- 4 files changed, 41 insertions(+), 88 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 9f5cae36c5..8f8560023a 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -133,7 +133,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); /* 32 bit ops */ =20 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned flags); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); @@ -158,7 +157,6 @@ void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, = TCGv_i64 *b); void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 09899cb309..d6ea11d8fc 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -108,6 +108,12 @@ static inline void tcg_gen_op_tt(TCGOpcode opc, TCGTyp= e type, tcg_gen_op2(opc, type, temp_arg(t0), temp_arg(t1)); } =20 +static inline void tcg_gen_op_tti(TCGOpcode opc, TCGType type, + TCGTemp *t0, TCGTemp *t1, TCGArg a2) +{ + tcg_gen_op3(opc, type, temp_arg(t0), temp_arg(t1), a2); +} + static inline void tcg_gen_op_ttt(TCGOpcode opc, TCGType type, TCGTemp *t0, TCGTemp *t1, TCGTemp *t2) { diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index b606aaab12..2ebcf4a066 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -11,6 +11,7 @@ DEF3(andi, TCGV, TCGV, TINT) DEF3(andc, TCGV, TCGV, TCGV) DEF4(brcond, TCGCond, TCGV, TCGV, TCGLabelPtr) DEF4(brcondi, TCGCond, TCGV, TINT, TCGLabelPtr) +DEF3(bswap16, TCGV, TCGV, unsigned) DEF2(clrsb, TCGV, TCGV) DEF3(clz, TCGV, TCGV, TCGV) DEF3(clzi, TCGV, TCGV, TINT) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c3a8a04a4d..f1a79dc921 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -425,6 +425,40 @@ void tcg_gen_brcondi(TCGType type, TCGCond cond, TCGTe= mp *src1, tcg_gen_brcond(type, cond, src1, tcg_constant_internal(type, src2), l); } =20 +void tcg_gen_bswap16(TCGType type, TCGTemp *dst, TCGTemp *src, unsigned fl= ags) +{ + /* Only one extension flag may be present. */ + tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); + + if (tcg_op_supported(INDEX_op_bswap16, type, 0)) { + tcg_gen_op_tti(INDEX_op_bswap16, type, dst, src, flags); + } else { + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + int width =3D tcg_type_bits(type); + + if (flags & TCG_BSWAP_IZ) { /* t0 =3D ...a */ + tcg_gen_shri(type, t0, src, 8); + } else { + tcg_gen_extract(type, t0, src, 8, 8); + } + + if (flags & TCG_BSWAP_OS) { + tcg_gen_shli(type, t1, src, width - 8); /* t1 =3D b... */ + tcg_gen_sari(type, t1, t1, width - 16); /* t1 =3D ssb. */ + } else if (flags & TCG_BSWAP_OZ) { + tcg_gen_ext8u(type, t1, src); /* t1 =3D ...b */ + tcg_gen_shli(type, t1, t1, 8); /* t1 =3D ..b. */ + } else { + tcg_gen_shli(type, t1, src, 8); /* t1 =3D xab. */ + } + + tcg_gen_or(type, dst, t0, t1); /* ret =3D ..ba (O= Z) */ + /* =3D ssba (O= S) */ + /* =3D xaba (0= ) */ + } +} + void tcg_gen_clrsb(TCGType type, TCGTemp *dst, TCGTemp *src) { if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { @@ -1294,49 +1328,6 @@ static void gen_bitswap_i64(TCGv_i64 ret, TCGv_i64 a= rg, uint64_t mask) tcg_temp_free_i64(t1); } =20 -/* - * bswap16_i32: 16-bit byte swap on the low bits of a 32-bit value. - * - * Byte pattern: xxab -> yyba - * - * With TCG_BSWAP_IZ, x =3D=3D zero, else undefined. - * With TCG_BSWAP_OZ, y =3D=3D zero, with TCG_BSWAP_OS y =3D=3D sign, else= undefined. - */ -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned flags) -{ - /* Only one extension flag may be present. */ - tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); - - if (tcg_op_supported(INDEX_op_bswap16, TCG_TYPE_I32, 0)) { - tcg_gen_op3i_i32(INDEX_op_bswap16, ret, arg, flags); - } else { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - - /* arg =3D ..ab (IZ) xxab (!IZ= ) */ - tcg_gen_shri_i32(t0, arg, 8); /* t0 =3D ...a (IZ) .xxa (!IZ= ) */ - if (!(flags & TCG_BSWAP_IZ)) { - tcg_gen_ext8u_i32(t0, t0); /* t0 =3D ...a */ - } - - if (flags & TCG_BSWAP_OS) { - tcg_gen_shli_i32(t1, arg, 24); /* t1 =3D b... */ - tcg_gen_sari_i32(t1, t1, 16); /* t1 =3D ssb. */ - } else if (flags & TCG_BSWAP_OZ) { - tcg_gen_ext8u_i32(t1, arg); /* t1 =3D ...b */ - tcg_gen_shli_i32(t1, t1, 8); /* t1 =3D ..b. */ - } else { - tcg_gen_shli_i32(t1, arg, 8); /* t1 =3D xab. */ - } - - tcg_gen_or_i32(ret, t0, t1); /* ret =3D ..ba (OZ) */ - /* =3D ssba (OS) */ - /* =3D xaba (no flag) */ - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - } -} - /* * bswap32_i32: 32-bit byte swap on a 32-bit value. * @@ -1495,49 +1486,6 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) tcg_gen_extract_i64(ret, arg, 0, 32); } =20 -/* - * bswap16_i64: 16-bit byte swap on the low bits of a 64-bit value. - * - * Byte pattern: xxxxxxxxab -> yyyyyyyyba - * - * With TCG_BSWAP_IZ, x =3D=3D zero, else undefined. - * With TCG_BSWAP_OZ, y =3D=3D zero, with TCG_BSWAP_OS y =3D=3D sign, else= undefined. - */ -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags) -{ - /* Only one extension flag may be present. */ - tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); - - if (tcg_op_supported(INDEX_op_bswap16, TCG_TYPE_I64, 0)) { - tcg_gen_op3i_i64(INDEX_op_bswap16, ret, arg, flags); - } else { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - - /* arg =3D ......ab or xxxxxxa= b */ - tcg_gen_shri_i64(t0, arg, 8); /* t0 =3D .......a or .xxxxxx= a */ - if (!(flags & TCG_BSWAP_IZ)) { - tcg_gen_ext8u_i64(t0, t0); /* t0 =3D .......a */ - } - - if (flags & TCG_BSWAP_OS) { - tcg_gen_shli_i64(t1, arg, 56); /* t1 =3D b....... */ - tcg_gen_sari_i64(t1, t1, 48); /* t1 =3D ssssssb. */ - } else if (flags & TCG_BSWAP_OZ) { - tcg_gen_ext8u_i64(t1, arg); /* t1 =3D .......b */ - tcg_gen_shli_i64(t1, t1, 8); /* t1 =3D ......b. */ - } else { - tcg_gen_shli_i64(t1, arg, 8); /* t1 =3D xxxxxab. */ - } - - tcg_gen_or_i64(ret, t0, t1); /* ret =3D ......ba (OZ) */ - /* ssssssba (OS) */ - /* xxxxxaba (no flag) */ - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } -} - /* * bswap32_i64: 32-bit byte swap on the low bits of a 64-bit value. * --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- tcg/tcg-op.c | 58 ++++++++++++++++++++++------------------------------ 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f1a79dc921..2d24e21f3c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -290,6 +290,27 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) #undef DEF5 #undef DEF6 =20 +/* + * Internal helper for bit and byte reversal. + * Given a repeating matched block of 1's and 0's, swap the bits within + * those two blocks. E.g. mask=3D00ff00ff, shift the input bits left and + * right 8 bits. + */ +static void tcg_gen_bitswap(TCGType type, TCGTemp *dst, + TCGTemp *src, uint64_t mask) +{ + g_autoptr(TCGTemp) t0 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + TCGTemp *tmask =3D tcg_constant_internal(type, mask); + TCGTemp *tshift =3D tcg_constant_internal(type, cto64(mask)); + + tcg_gen_and(type, t0, src, tmask); + tcg_gen_shr(type, t1, src, tshift); + tcg_gen_shl(type, t0, t0, tshift); + tcg_gen_and(type, t1, t1, tmask); + tcg_gen_or(type, dst, t0, t1); +} + /* * Generic expansions for templated operations. * We have used compiler type checks to ensure all TCGTemp @@ -1289,43 +1310,14 @@ void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, T= CGv_i32 arg1, TCGv_i32 arg2) tcg_temp_free_i64(t1); } =20 -/* - * Internal helper for bit and byte reversal. - * Given a repeating matched block of 1's and 0's, swap the bits within - * those two blocks. E.g. mask=3D00ff00ff, shift the input bits left and - * right 8 bits. - */ -static void gen_bitswap_i32(TCGv_i32 ret, TCGv_i32 arg, uint32_t mask) +static void gen_bitswap_i32(TCGv_i32 dst, TCGv_i32 src, uint32_t mask) { - TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - int sh =3D cto32(mask); - - tcg_gen_andi_i32(t0, arg, mask); - tcg_gen_shri_i32(t1, arg, sh); - tcg_gen_shli_i32(t0, t0, sh); - tcg_gen_andi_i32(t1, t1, mask); - tcg_gen_or_i32(ret, t0, t1); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); + tcg_gen_bitswap(TCG_TYPE_I32, tcgv_i32_temp(dst), tcgv_i32_temp(src), = mask); } =20 -/* Similarly for 64-bit operands. */ -static void gen_bitswap_i64(TCGv_i64 ret, TCGv_i64 arg, uint64_t mask) +static void gen_bitswap_i64(TCGv_i64 dst, TCGv_i64 src, uint64_t mask) { - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - int sh =3D cto64(mask); - - tcg_gen_andi_i64(t0, arg, mask); - tcg_gen_shri_i64(t1, arg, sh); - tcg_gen_shli_i64(t0, t0, sh); - tcg_gen_andi_i64(t1, t1, mask); - tcg_gen_or_i64(ret, t0, t1); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); + tcg_gen_bitswap(TCG_TYPE_I64, tcgv_i64_temp(dst), tcgv_i64_temp(src), = mask); } =20 /* --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593663; cv=none; d=zohomail.com; s=zohoarc; b=gqejYGnhg1GcNbUHcu4baX2gtlyRjfIt7cYoubMPWTRKLtDb/eeFZX6kfwo2j8853cp5ApCIPmCOhk/PgSDOBsq4xdei+ycj3osewo2PgEfN+BvCUQhl8ZEBBk09ydIE5ULfLGIpn2pO4onTp1qMBKc+5wM7AmyirQpWPRHi+ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593663; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uDWghHyOGU8lSxUQ2Lkf846sJIbWq3EndeBV+dYuxpY=; b=TTcbX0q2qYJ+NuoRgz1e80Hq0b3zK4zL6+cCtO229DkL5xcz6MoaXGr4Z5b0coRv7qesnR0Y9nV771qjKm1VVKwEM3/p8AvRdItsu0VmyEzY8122a/1IvV1BNSeOOZnm7S23kI/BXm6v443G3/ky+WyUe/d86E1g59iJI3fQUsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179259366372734.70193348213843; Wed, 21 Oct 2026 07:41:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJXKO-00021T-3a; Wed, 21 Oct 2026 10:30:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJXGc-0006Ob-B7 for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:26:12 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xJXGa-0002Xr-5r for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:26:10 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-48df4e9d2d4so509588f8f.3 for ; Wed, 21 Oct 2026 07:26:07 -0700 (PDT) Received: from stoup.fritz.box (pd95f64ec.dip0.t-ipconnect.de. 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Wed, 21 Oct 2026 07:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 086/100] tcg: Generic expansion of tcg_gen_revbit8_* Date: Wed, 21 Oct 2026 16:16:38 +0200 Message-ID: <20261021141652.363109-87-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593664278158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 51 +++++++++++++----------------------- 3 files changed, 19 insertions(+), 35 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 8f8560023a..3a577beef4 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -135,7 +135,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* Replicate a value of size @vece from @in to all the lanes in @out */ @@ -161,7 +160,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, un= signed flags); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); =20 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 2ebcf4a066..ab1bf25929 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -49,6 +49,7 @@ DEF3(ori, TCGV, TCGV, TINT) DEF3(orc, TCGV, TCGV, TCGV) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) +DEF2(revbit8, TCGV, TCGV) DEF3(rotl, TCGV, TCGV, TCGV) DEF3(rotli, TCGV, TCGV, TINT) DEF3(rotr, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2d24e21f3c..7bb0bceaef 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -119,11 +119,6 @@ static TCGOp * DNI tcg_gen_op1i(TCGOpcode opc, TCGType= type, TCGArg a1) return tcg_gen_op1(opc, type, a1); } =20 -static void DNI tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) -{ - tcg_gen_op2(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); -} - static void DNI tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { tcg_gen_op2(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); @@ -1013,6 +1008,24 @@ void tcg_gen_remu(TCGType type, TCGTemp *dst, TCGTem= p *src1, TCGTemp *src2) } } =20 +void tcg_gen_revbit8(TCGType type, TCGTemp *dst, TCGTemp *src) +{ + static const TCGOpcode revw[2] =3D { INDEX_op_revbit32, INDEX_op_revbi= t64 }; + static const TCGOpcode bswapw[2] =3D { INDEX_op_bswap32, INDEX_op_bswa= p64 }; + + if (tcg_op_supported(INDEX_op_revbit8, type, 0)) { + tcg_gen_op_tt(INDEX_op_revbit8, type, dst, src); + } else if (tcg_op_supported(revw[type], type, 0) && + tcg_op_supported(bswapw[type], type, 0)) { + tcg_gen_op_tt(revw[type], type, dst, src); + tcg_gen_op_tti(bswapw[type], type, dst, dst, 0); + } else { + tcg_gen_bitswap(type, dst, src, 0x5555555555555555ull); + tcg_gen_bitswap(type, dst, dst, 0x3333333333333333ull); + tcg_gen_bitswap(type, dst, dst, 0x0f0f0f0f0f0f0f0full); + } +} + void tcg_gen_rotl(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_rotl, type, 0)) { @@ -1346,20 +1359,6 @@ void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg) tcg_gen_rotli_i32(ret, arg, 16); } =20 -void tcg_gen_revbit8_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (tcg_op_supported(INDEX_op_revbit8, TCG_TYPE_I32, 0)) { - tcg_gen_op2_i32(INDEX_op_revbit8, ret, arg); - } else if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I32, 0)) { - tcg_gen_op2_i32(INDEX_op_revbit32, ret, arg); - tcg_gen_bswap32_i32(ret, ret); - } else { - gen_bitswap_i32(ret, arg, 0x55555555u); - gen_bitswap_i32(ret, ret, 0x33333333u); - gen_bitswap_i32(ret, ret, 0x0f0f0f0fu); - } -} - void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) { if (tcg_op_supported(INDEX_op_revbit32, TCG_TYPE_I32, 0)) { @@ -1580,20 +1579,6 @@ void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg= , unsigned flags) } } =20 -void tcg_gen_revbit8_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (tcg_op_supported(INDEX_op_revbit8, TCG_TYPE_I64, 0)) { - tcg_gen_op2_i64(INDEX_op_revbit8, ret, arg); - } else if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) { - tcg_gen_op2_i64(INDEX_op_revbit64, ret, arg); - tcg_gen_bswap64_i64(ret, ret); - } else { - gen_bitswap_i64(ret, arg, 0x5555555555555555ull); - gen_bitswap_i64(ret, ret, 0x3333333333333333ull); - gen_bitswap_i64(ret, ret, 0x0f0f0f0f0f0f0f0full); - } -} - void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg) { if (tcg_op_supported(INDEX_op_revbit64, TCG_TYPE_I64, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593141; cv=none; d=zohomail.com; s=zohoarc; b=jy1jk2QB8Ls7AQWc/uw8DtIzu/r0xuEF45DK9V4jV3VF7ljMX7cvsa3LUFcaFut7WV12yV/Ullq7huKNAjJRuAw54fvgBjw8RXhgVZkfXdb05nTsU4dmhxiDUtw/3qC4L/VuV9DfqvS8FveV24DxsE2p3mb1q1k2NR9EhAamdwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593141; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 21 Oct 2026 07:26:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 087/100] tcg: Generic expansion of tcg_gen_ld_* Date: Wed, 21 Oct 2026 16:16:39 +0200 Message-ID: <20261021141652.363109-88-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593141787158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 7 +------ tcg/tcg-internal.h | 6 ++++-- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 24 ++++++++++++++---------- 4 files changed, 20 insertions(+), 18 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 3a577beef4..697de0e1f0 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -144,7 +144,6 @@ void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); =20 void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); @@ -176,7 +175,6 @@ void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 /* Size changing operations. */ @@ -374,10 +372,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg= offset, TCGType t); TCGv_ptr tcg_constant_ptr_int(intptr_t x); #define tcg_constant_ptr(X) tcg_constant_ptr_int((intptr_t)(X)) =20 -static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_ld_,PTR)((NAT)r, a, o); -} +QEMU_ARG_NONNULL void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o); =20 static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) { diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index d6ea11d8fc..bfd34905ee 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -191,13 +191,15 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg= _target_ulong imm); #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5,= T6); =20 -#define TCGV TCGTemp * -#define TINT int64_t +#define TCGV TCGTemp * +#define TINT int64_t +#define TCGv_ptr TCGTemp * =20 #include "tcg/tcg-op-def.h.inc" =20 #undef TINT #undef TCGV +#undef TCGv_ptr =20 #undef DEF1 #undef DEF2 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index ab1bf25929..6284358a13 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -31,6 +31,7 @@ DEF2(ext16u, TCGV, TCGV) DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF4(extract2, TCGV, TCGV, TCGV, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) +DEF3(ld, TCGV, TCGv_ptr, tcg_target_long) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7bb0bceaef..a329ed79a6 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -240,11 +240,13 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned me= minfo) =20 #define C_TCGv_i32 tcgv_i32_temp #define C_TCGv_i64 tcgv_i64_temp +#define C_TCGv_ptr tcgv_ptr_temp #define C_int32_t #define C_int64_t #define C_MemOp #define C_TCGCond #define C_TCGLabelPtr +#define C_tcg_target_long #define C_unsigned =20 #define TCGV glue(TCGv,TExt) @@ -271,11 +273,13 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned me= minfo) =20 #undef C_TCGv_i32 #undef C_TCGv_i64 +#undef C_TCGv_ptr #undef C_int32_t #undef C_int64_t #undef C_MemOp #undef C_TCGCond #undef C_TCGLabelPtr +#undef C_tcg_target_long #undef C_unsigned =20 #undef DEF1 @@ -765,6 +769,11 @@ void tcg_gen_extract2(TCGType type, TCGTemp *dst, TCGT= emp *lo, TCGTemp *hi, } } =20 +void tcg_gen_ld(TCGType type, TCGTemp *dst, TCGTemp *base, tcg_target_long= ofs) +{ + tcg_gen_op_tti(INDEX_op_ld, type, dst, base, ofs); +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -1389,11 +1398,6 @@ void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i32(INDEX_op_ld16s, ret, arg2, offset); } =20 -void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld, ret, arg2, offset); -} - void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st8, arg1, arg2, offset); @@ -1442,11 +1446,6 @@ void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_ld32s, ret, arg2, offset); } =20 -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld, ret, arg2, offset); -} - void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_st8, arg1, arg2, offset); @@ -1864,6 +1863,11 @@ void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) tcg_gen_movi(TCG_TYPE_PTR, tcgv_ptr_temp(d), s); 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Wed, 21 Oct 2026 07:26:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 088/100] tcg: Generic expansion of tcg_gen_ld8s_* Date: Wed, 21 Oct 2026 16:16:40 +0200 Message-ID: <20261021141652.363109-89-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593814901158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 16 ++++++---------- 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 697de0e1f0..32128ad997 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -141,7 +141,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); =20 @@ -170,7 +169,6 @@ void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 6284358a13..a110e64510 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -32,6 +32,7 @@ DEF4(extract, TCGV, TCGV, unsigned, unsigned) DEF4(extract2, TCGV, TCGV, TCGV, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF3(ld, TCGV, TCGv_ptr, tcg_target_long) +DEF3(ld8s, TCGV, TCGv_ptr, tcg_target_long) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a329ed79a6..749e0d5f06 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -774,6 +774,12 @@ void tcg_gen_ld(TCGType type, TCGTemp *dst, TCGTemp *b= ase, tcg_target_long ofs) tcg_gen_op_tti(INDEX_op_ld, type, dst, base, ofs); } =20 +void tcg_gen_ld8s(TCGType type, TCGTemp *dst, + TCGTemp *base, tcg_target_long ofs) +{ + tcg_gen_op_tti(INDEX_op_ld8s, type, dst, base, ofs); +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -1383,11 +1389,6 @@ void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, t= cg_target_long offset) tcg_gen_ldst_op_i32(INDEX_op_ld8u, ret, arg2, offset); } =20 -void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld8s, ret, arg2, offset); -} - void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld16u, ret, arg2, offset); @@ -1421,11 +1422,6 @@ void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, t= cg_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_ld8u, ret, arg2, offset); } =20 -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld8s, ret, arg2, offset); -} - void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld16u, ret, arg2, offset); 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Wed, 21 Oct 2026 07:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 089/100] tcg: Generic expansion of tcg_gen_ld8u_* Date: Wed, 21 Oct 2026 16:16:41 +0200 Message-ID: <20261021141652.363109-90-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593052580158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 16 ++++++---------- 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 32128ad997..744211c4c6 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -140,7 +140,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 -void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); =20 @@ -168,7 +167,6 @@ void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index a110e64510..75bb38a07e 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -33,6 +33,7 @@ DEF4(extract2, TCGV, TCGV, TCGV, unsigned) DEF3(eqv, TCGV, TCGV, TCGV) DEF3(ld, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8s, TCGV, TCGv_ptr, tcg_target_long) +DEF3(ld8u, TCGV, TCGv_ptr, tcg_target_long) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 749e0d5f06..74ddc74191 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -780,6 +780,12 @@ void tcg_gen_ld8s(TCGType type, TCGTemp *dst, tcg_gen_op_tti(INDEX_op_ld8s, type, dst, base, ofs); } =20 +void tcg_gen_ld8u(TCGType type, TCGTemp *dst, + TCGTemp *base, tcg_target_long ofs) +{ + tcg_gen_op_tti(INDEX_op_ld8u, type, dst, base, ofs); +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -1384,11 +1390,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld8u, ret, arg2, offset); -} - void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_ld16u, ret, arg2, offset); @@ -1417,11 +1418,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tc= g_target_long offset) =20 /* 64-bit ops */ =20 -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld8u, ret, arg2, offset); -} - void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld16u, ret, arg2, offset); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 090/100] tcg: Generic expansion of tcg_gen_ld16s_* Date: Wed, 21 Oct 2026 16:16:42 +0200 Message-ID: <20261021141652.363109-91-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593560448158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 16 ++++++---------- 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 744211c4c6..c12217f68e 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -141,7 +141,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); =20 void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); @@ -168,7 +167,6 @@ void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg= _target_long offset); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 75bb38a07e..785c417a74 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -34,6 +34,7 @@ DEF3(eqv, TCGV, TCGV, TCGV) DEF3(ld, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8s, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8u, TCGV, TCGv_ptr, tcg_target_long) +DEF3(ld16s, TCGV, TCGv_ptr, tcg_target_long) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 74ddc74191..73dba6a15d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -786,6 +786,12 @@ void tcg_gen_ld8u(TCGType type, TCGTemp *dst, tcg_gen_op_tti(INDEX_op_ld8u, type, dst, base, ofs); } =20 +void tcg_gen_ld16s(TCGType type, TCGTemp *dst, + TCGTemp *base, tcg_target_long ofs) +{ + tcg_gen_op_tti(INDEX_op_ld16s, type, dst, base, ofs); +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -1395,11 +1401,6 @@ void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i32(INDEX_op_ld16u, ret, arg2, offset); } =20 -void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld16s, ret, arg2, offset); -} - void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st8, arg1, arg2, offset); @@ -1423,11 +1424,6 @@ void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_ld16u, ret, arg2, offset); } =20 -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld16s, ret, arg2, offset); -} - void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld32u, ret, arg2, offset); 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Wed, 21 Oct 2026 07:26:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 091/100] tcg: Generic expansion of tcg_gen_ld16u_* Date: Wed, 21 Oct 2026 16:16:43 +0200 Message-ID: <20261021141652.363109-92-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593300876158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 3 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 16 ++++++---------- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index c12217f68e..d0d508ced6 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -140,8 +140,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 -void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset= ); - void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); @@ -166,7 +164,6 @@ void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_= target_long offset); void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 785c417a74..98a07a70f0 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -35,6 +35,7 @@ DEF3(ld, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8s, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld8u, TCGV, TCGv_ptr, tcg_target_long) DEF3(ld16s, TCGV, TCGv_ptr, tcg_target_long) +DEF3(ld16u, TCGV, TCGv_ptr, tcg_target_long) DEF2(mov, TCGV, TCGV) DEF2(movi, TCGV, TINT) DEF6(movcond, TCGCond, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 73dba6a15d..f1c33afc02 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -792,6 +792,12 @@ void tcg_gen_ld16s(TCGType type, TCGTemp *dst, tcg_gen_op_tti(INDEX_op_ld16s, type, dst, base, ofs); } =20 +void tcg_gen_ld16u(TCGType type, TCGTemp *dst, + TCGTemp *base, tcg_target_long ofs) +{ + tcg_gen_op_tti(INDEX_op_ld16u, type, dst, base, ofs); +} + void tcg_gen_mov(TCGType type, TCGTemp *dst, TCGTemp *src) { if (src !=3D dst) { @@ -1396,11 +1402,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld16u, ret, arg2, offset); -} - void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st8, arg1, arg2, offset); @@ -1419,11 +1420,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tc= g_target_long offset) =20 /* 64-bit ops */ =20 -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld16u, ret, arg2, offset); -} - void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_ld32u, ret, arg2, offset); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:26:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 092/100] tcg: Generic expansion of tcg_gen_st_* Date: Wed, 21 Oct 2026 16:16:44 +0200 Message-ID: <20261021141652.363109-93-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593139737158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 20 +------------------- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 21 ++++++++++----------- 3 files changed, 12 insertions(+), 30 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index d0d508ced6..469b925fe0 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -142,7 +142,6 @@ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_= i32 in); =20 void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 /* 64 bit ops */ =20 @@ -166,7 +165,6 @@ void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg= _target_long offset); =20 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); =20 /* Size changing operations. */ =20 @@ -352,24 +350,11 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); =20 /* Host pointer ops */ =20 -#if UINTPTR_MAX =3D=3D UINT32_MAX -# define PTR i32 -# define NAT TCGv_i32 -#else -# define PTR i64 -# define NAT TCGv_i64 -#endif - TCGv_ptr tcg_constant_ptr_int(intptr_t x); #define tcg_constant_ptr(X) tcg_constant_ptr_int((intptr_t)(X)) =20 QEMU_ARG_NONNULL void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o); - -static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_st_, PTR)((NAT)r, a, o); -} - +QEMU_ARG_NONNULL void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o); QEMU_ARG_NONNULL void tcg_gen_discard_ptr(TCGv_ptr a); QEMU_ARG_NONNULL void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b); QEMU_ARG_NONNULL void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b); @@ -382,7 +367,4 @@ QEMU_ARG_NONNULL void tcg_gen_trunc_i64_ptr(TCGv_ptr r,= TCGv_i64 a); QEMU_ARG_NONNULL void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a); QEMU_ARG_NONNULL void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a); =20 -#undef PTR -#undef NAT - #endif /* TCG_TCG_OP_COMMON_H */ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 98a07a70f0..514967f91d 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -70,6 +70,7 @@ DEF3(shr, TCGV, TCGV, TCGV) DEF3(shri, TCGV, TCGV, TINT) DEF3(smax, TCGV, TCGV, TCGV) DEF3(smin, TCGV, TCGV, TCGV) +DEF3(st, TCGV, TCGv_ptr, tcg_target_long) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF6(sub2, TCGV, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f1c33afc02..68e31fe5ca 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1251,6 +1251,11 @@ void tcg_gen_smin(TCGType type, TCGTemp *dst, TCGTem= p *src1, TCGTemp *src2) } } =20 +void tcg_gen_st(TCGType type, TCGTemp *dst, TCGTemp *base, tcg_target_long= ofs) +{ + tcg_gen_op_tti(INDEX_op_st, type, dst, base, ofs); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -1412,12 +1417,6 @@ void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i32(INDEX_op_st16, arg1, arg2, offset); } =20 -void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st, arg1, arg2, offset); -} - - /* 64-bit ops */ =20 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) @@ -1445,11 +1444,6 @@ void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_st32, arg1, arg2, offset); } =20 -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset); -} - void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) { tcg_gen_sextract_i64(ret, arg, 0, 32); @@ -1852,6 +1846,11 @@ void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t= o) tcg_gen_ld(TCG_TYPE_PTR, tcgv_ptr_temp(r), tcgv_ptr_temp(a), o); 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charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 2 -- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 15 +++++---------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 469b925fe0..cd66b0d7de 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -140,7 +140,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 -void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 /* 64 bit ops */ @@ -159,7 +158,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); =20 -void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 514967f91d..90bcf9e5ab 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -71,6 +71,7 @@ DEF3(shri, TCGV, TCGV, TINT) DEF3(smax, TCGV, TCGV, TCGV) DEF3(smin, TCGV, TCGV, TCGV) DEF3(st, TCGV, TCGv_ptr, tcg_target_long) +DEF3(st8, TCGV, TCGv_ptr, tcg_target_long) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF6(sub2, TCGV, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 68e31fe5ca..cc70c03b1f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1256,6 +1256,11 @@ void tcg_gen_st(TCGType type, TCGTemp *dst, TCGTemp = *base, tcg_target_long ofs) tcg_gen_op_tti(INDEX_op_st, type, dst, base, ofs); } =20 +void tcg_gen_st8(TCGType type, TCGTemp *dst, TCGTemp *base, tcg_target_lon= g ofs) +{ + tcg_gen_op_tti(INDEX_op_st8, type, dst, base, ofs); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -1407,11 +1412,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st8, arg1, arg2, offset); -} - void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i32(INDEX_op_st16, arg1, arg2, offset); @@ -1429,11 +1429,6 @@ void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_ld32s, ret, arg2, offset); } =20 -void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st8, arg1, arg2, offset); -} - void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) { tcg_gen_ldst_op_i64(INDEX_op_st16, arg1, arg2, offset); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 094/100] tcg: Generic expansion of tcg_gen_st16_* Date: Wed, 21 Oct 2026 16:16:46 +0200 Message-ID: <20261021141652.363109-95-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593361825158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 3 --- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op.c | 23 ++++++----------------- 3 files changed, 7 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index cd66b0d7de..1fe791d5f5 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -140,8 +140,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); =20 -void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset= ); - /* 64 bit ops */ =20 void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); @@ -158,7 +156,6 @@ void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); /* Replicate a value of size @vece from @in to all the lanes in @out */ void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); =20 -void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 90bcf9e5ab..f9dab50a91 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -72,6 +72,7 @@ DEF3(smax, TCGV, TCGV, TCGV) DEF3(smin, TCGV, TCGV, TCGV) DEF3(st, TCGV, TCGv_ptr, tcg_target_long) DEF3(st8, TCGV, TCGv_ptr, tcg_target_long) +DEF3(st16, TCGV, TCGv_ptr, tcg_target_long) DEF3(sub, TCGV, TCGV, TCGV) DEF3(subi, TCGV, TCGV, TINT) DEF6(sub2, TCGV, TCGV, TCGV, TCGV, TCGV, TCGV) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cc70c03b1f..0162817d5d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -143,13 +143,6 @@ static void DNI tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i= 64 a1, tcg_gen_op3(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); } =20 -static void DNI tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, - TCGv_ptr base, TCGArg offset) -{ - tcg_gen_op3(opc, TCG_TYPE_I32, tcgv_i32_arg(val), - tcgv_ptr_arg(base), offset); -} - static void DNI tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { @@ -1261,6 +1254,12 @@ void tcg_gen_st8(TCGType type, TCGTemp *dst, TCGTemp= *base, tcg_target_long ofs) tcg_gen_op_tti(INDEX_op_st8, type, dst, base, ofs); } =20 +void tcg_gen_st16(TCGType type, TCGTemp *dst, + TCGTemp *base, tcg_target_long ofs) +{ + tcg_gen_op_tti(INDEX_op_st16, type, dst, base, ofs); +} + void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2); @@ -1412,11 +1411,6 @@ void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg) } } =20 -void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st16, arg1, arg2, offset); -} - /* 64-bit ops */ =20 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) @@ -1429,11 +1423,6 @@ void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, = tcg_target_long offset) tcg_gen_ldst_op_i64(INDEX_op_ld32s, ret, arg2, offset); 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Wed, 21 Oct 2026 07:26:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 095/100] tcg: Generic expansion of tcg_gen_dup_* Date: Wed, 21 Oct 2026 16:16:47 +0200 Message-ID: <20261021141652.363109-96-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593313844158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 6 ------ include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op-gvec.c | 41 ------------------------------------ tcg/tcg-op.c | 16 ++++++++++++++ 4 files changed, 17 insertions(+), 47 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 1fe791d5f5..75194c1906 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -137,9 +137,6 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); =20 -/* Replicate a value of size @vece from @in to all the lanes in @out */ -void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); - /* 64 bit ops */ =20 void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); @@ -153,9 +150,6 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); =20 -/* Replicate a value of size @vece from @in to all the lanes in @out */ -void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); - void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index f9dab50a91..556f7470cd 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -23,6 +23,7 @@ DEF4(deposit_z, TCGV, TCGV, unsigned, unsigned) DEF1(discard, TCGV) DEF3(div, TCGV, TCGV, TCGV) DEF3(divu, TCGV, TCGV, TCGV) +DEF3(dup, unsigned, TCGV, TCGV) DEF3(ext, TCGV, TCGV, MemOp) DEF2(ext8s, TCGV, TCGV) DEF2(ext8u, TCGV, TCGV) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0d649cc13b..72abb0a08e 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -434,47 +434,6 @@ uint64_t (dup_const)(unsigned vece, uint64_t c) } } =20 -/* Duplicate IN into OUT as per VECE. */ -void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) -{ - switch (vece) { - case MO_8: - tcg_gen_ext8u_i32(out, in); - tcg_gen_muli_i32(out, out, 0x01010101); - break; - case MO_16: - tcg_gen_deposit_i32(out, in, in, 16, 16); - break; - case MO_32: - tcg_gen_mov_i32(out, in); - break; - default: - g_assert_not_reached(); - } -} - -void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) -{ - switch (vece) { - case MO_8: - tcg_gen_ext8u_i64(out, in); - tcg_gen_muli_i64(out, out, 0x0101010101010101ull); - break; - case MO_16: - tcg_gen_ext16u_i64(out, in); - tcg_gen_muli_i64(out, out, 0x0001000100010001ull); - break; - case MO_32: - tcg_gen_deposit_i64(out, in, in, 32, 32); - break; - case MO_64: - tcg_gen_mov_i64(out, in); - break; - default: - g_assert_not_reached(); - } -} - /* Select a supported vector type for implementing an operation on SIZE * bytes. If OP is 0, assume that the real operation to be performed is * required by all backends. Otherwise, make sure than OP can be performed diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0162817d5d..df769dd975 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -659,6 +659,22 @@ void tcg_gen_divu(TCGType type, TCGTemp *dst, TCGTemp = *src1, TCGTemp *src2) } } =20 +void tcg_gen_dup(TCGType type, unsigned vece, TCGTemp *dst, TCGTemp *src) +{ + unsigned t_width =3D tcg_type_bits(type); + unsigned e_width =3D memop_size(vece) * 8; + + tcg_debug_assert(e_width <=3D t_width); + if (t_width =3D=3D e_width) { + tcg_gen_mov(type, dst, src); + } else if (t_width =3D=3D e_width * 2) { + tcg_gen_deposit(type, dst, src, src, e_width, e_width); + } else { + tcg_gen_extract(type, dst, src, 0, e_width); + tcg_gen_muli(type, dst, dst, dup_const(vece, 1)); + } +} + void tcg_gen_eqv(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2) { if (tcg_op_supported(INDEX_op_eqv, type, 0)) { --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593320; cv=none; d=zohomail.com; s=zohoarc; b=ZNj2X8v1YvZgVfQPM0psTbWH2mrEv+CzkL7GJdD+6aII29AfX2JBU9aQlAavzYKFWjWTB71b8HsacFEzo55iYWVoeDkXvMLnRiN/QbsvwMIgMbNKnTv1VbK5lm2S28oCn/ACUBNLKnJSB/ZcnC4L8kdPP2IGwHU8zbHp/D/mj70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593320; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ypz06w1EORJFZkqvpnT5iPOQzdJAwHMVWz9pF2jqVL8=; b=PHzjbmCFSjprh8Naq2sF1HC8oS/02N1DFogD4rvCitOkwslzTBQ6M8ht44A1wAmvJ9xJpFMjhATcBaAZ5pc0/LdXyE2oIKBPRK1WM92vuCf1ywrC1oJcXr/Aj11IF/1fnozIY4uNhaGKLM8Xu52eY4FDjv5pFTdlhIp/FZ7dV0Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792593320163967.466986414692; Wed, 21 Oct 2026 07:35:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJXJU-0001EN-FA; Wed, 21 Oct 2026 10:29:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJXGp-0006eS-5c for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:26:26 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xJXGl-0002Zs-Cd for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:26:22 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-48df54150dfso512174f8f.0 for ; Wed, 21 Oct 2026 07:26:18 -0700 (PDT) Received: from stoup.fritz.box (pd95f64ec.dip0.t-ipconnect.de. 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Wed, 21 Oct 2026 07:26:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 096/100] tcg: Generic expansion of tcg_gen_qemu_ld_chk Date: Wed, 21 Oct 2026 16:16:48 +0200 Message-ID: <20261021141652.363109-97-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593321041158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 4 +- include/tcg/tcg-op-mem.h | 6 +- include/tcg/tcg.h | 2 + include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op-ldst.c | 164 ++++++++++++++--------------------- tcg/tcg-op.c | 4 + 6 files changed, 75 insertions(+), 106 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 75194c1906..ce47bebb2b 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -177,11 +177,9 @@ void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tcg= _target_long offset); =20 /* Local load/store bit ops */ =20 -void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_ld_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_ld_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); =20 /* Atomic ops */ diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h index 29e7c02f25..76955d27c1 100644 --- a/include/tcg/tcg-op-mem.h +++ b/include/tcg/tcg-op-mem.h @@ -31,7 +31,7 @@ typedef TCGv_i64 TCGv_va; QEMU_ARG_NONNULL static inline void tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m) { - tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); + tcg_gen_qemu_ld_chk_i32(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 QEMU_ARG_NONNULL static inline void @@ -43,7 +43,7 @@ tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemO= p m) QEMU_ARG_NONNULL static inline void tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m) { - tcg_gen_qemu_ld_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); + tcg_gen_qemu_ld_chk_i64(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 QEMU_ARG_NONNULL static inline void @@ -55,7 +55,7 @@ tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemO= p m) QEMU_ARG_NONNULL static inline void tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m) { - tcg_gen_qemu_ld_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); + tcg_gen_qemu_ld_chk_i128(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 QEMU_ARG_NONNULL static inline void diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 09d20064fc..8f409b23b7 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -304,6 +304,8 @@ typedef struct TCGTemp { void *state_ptr; } TCGTemp; =20 +typedef TCGTemp *TCGTempPtr; + typedef struct TCGContext TCGContext; =20 typedef struct TCGTempSet { diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 556f7470cd..e2da3ddef6 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -53,6 +53,7 @@ DEF2(not, TCGV, TCGV) DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) DEF3(orc, TCGV, TCGV, TCGV) +DEF5(qemu_ld_chk, TCGV, TCGTempPtr, unsigned, MemOp, TCGType) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF2(revbit8, TCGV, TCGV) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 031c5ce926..7d3fe60d89 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -191,33 +191,37 @@ plugin_gen_mem_callbacks(TCGv_i64 copy_addr, TCGTemp = *orig_addr, MemOpIdx oi, #endif =20 static void -plugin_gen_mem_callbacks_i32(TCGv_i32 val, +plugin_gen_mem_callbacks_tmp(TCGType type, TCGTemp *val, TCGv_i64 copy_addr, TCGTemp *orig_addr, MemOpIdx oi, enum qemu_plugin_mem_rw rw) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { - tcg_gen_st_i32(val, tcg_env, - offsetof(CPUState, neg.plugin_mem_value_low) - - sizeof(CPUState) + (HOST_BIG_ENDIAN * 4)); + tcg_gen_st(type, val, tcgv_ptr_temp(tcg_env), + offsetof(CPUState, neg.plugin_mem_value_low) + - sizeof(CPUState) + + (HOST_BIG_ENDIAN && type =3D=3D TCG_TYPE_I32 ? 4 : 0)= ); plugin_gen_mem_callbacks(copy_addr, orig_addr, oi, rw); } #endif } =20 +static void +plugin_gen_mem_callbacks_i32(TCGv_i32 val, + TCGv_i64 copy_addr, TCGTemp *orig_addr, + MemOpIdx oi, enum qemu_plugin_mem_rw rw) +{ + plugin_gen_mem_callbacks_tmp(TCG_TYPE_I32, tcgv_i32_temp(val), copy_ad= dr, + orig_addr, oi, rw); +} + static void plugin_gen_mem_callbacks_i64(TCGv_i64 val, TCGv_i64 copy_addr, TCGTemp *orig_addr, MemOpIdx oi, enum qemu_plugin_mem_rw rw) { -#ifdef CONFIG_PLUGIN - if (tcg_ctx->plugin_insn !=3D NULL) { - tcg_gen_st_i64(val, tcg_env, - offsetof(CPUState, neg.plugin_mem_value_low) - - sizeof(CPUState)); - plugin_gen_mem_callbacks(copy_addr, orig_addr, oi, rw); - } -#endif + plugin_gen_mem_callbacks_tmp(TCG_TYPE_I64, tcgv_i64_temp(val), copy_ad= dr, + orig_addr, oi, rw); } =20 static void @@ -238,8 +242,31 @@ plugin_gen_mem_callbacks_i128(TCGv_i128 val, #endif } =20 -static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTemp *addr, - TCGArg idx, MemOp memop) +static void tcg_gen_bswap(TCGType type, TCGTemp *dst, + TCGTemp *src, unsigned flags, MemOp memop) +{ + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16(type, dst, src, flags); + break; + case MO_32: + if (type =3D=3D TCG_TYPE_I32) { + tcg_gen_bswap32_i32(temp_tcgv_i32(dst), temp_tcgv_i32(src)); + } else { + tcg_gen_bswap32_i64(temp_tcgv_i64(dst), temp_tcgv_i64(src), fl= ags); + } + break; + case MO_64: + tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + tcg_gen_bswap64_i64(temp_tcgv_i64(dst), temp_tcgv_i64(src)); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_gen_qemu_ld_int(TCGType type, TCGTemp *val, + TCGTemp *addr, TCGArg idx, MemOp memop) { MemOp orig_memop; MemOpIdx orig_oi, oi; @@ -247,48 +274,40 @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCG= Temp *addr, TCGTemp *addr_new; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 0, 0); + memop =3D tcg_canonicalize_memop(memop, type !=3D TCG_TYPE_I32, 0); + orig_memop =3D memop; orig_oi =3D oi =3D make_memop_idx(memop, idx); =20 if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - memop &=3D ~MO_BSWAP; /* The bswap primitive benefits from zero-extended input. */ - if ((memop & MO_SSIZE) =3D=3D MO_SW) { - memop &=3D ~MO_SIGN; - } + memop &=3D ~(MO_BSWAP | MO_SIGN); oi =3D make_memop_idx(memop, idx); } =20 addr_new =3D tci_extend_addr(addr); copy_addr =3D plugin_maybe_preserve_addr(addr); - gen_ldst1(INDEX_op_qemu_ld, TCG_TYPE_I32, tcgv_i32_temp(val), addr_new= , oi); + tcg_gen_op_tti(INDEX_op_qemu_ld, type, val, addr_new, oi); =20 if ((orig_memop ^ memop) & MO_BSWAP) { - switch (orig_memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i32(val, val, (orig_memop & MO_SIGN - ? TCG_BSWAP_IZ | TCG_BSWAP_OS - : TCG_BSWAP_IZ | TCG_BSWAP_OZ)); - break; - case MO_32: - tcg_gen_bswap32_i32(val, val); - break; - default: - g_assert_not_reached(); - } + int flags =3D (orig_memop & MO_SIGN + ? TCG_BSWAP_IZ | TCG_BSWAP_OS + : TCG_BSWAP_IZ | TCG_BSWAP_OZ); + tcg_gen_bswap(type, val, val, flags, orig_memop); } =20 - plugin_gen_mem_callbacks_i32(val, copy_addr, addr, orig_oi, - QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks_tmp(type, val, copy_addr, addr, + orig_oi, QEMU_PLUGIN_MEM_R); maybe_free_addr(addr, addr_new); } =20 -void tcg_gen_qemu_ld_i32_chk(TCGv_i32 val, TCGTemp *addr, TCGArg idx, - MemOp memop, TCGType addr_type) +void tcg_gen_qemu_ld_chk(TCGType val_type, TCGTemp *val, TCGTemp *addr, + unsigned idx, MemOp memop, TCGType addr_type) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); - tcg_gen_qemu_ld_i32_int(val, addr, idx, memop); + tcg_debug_assert(memop_size(memop) <=3D tcg_type_size(val_type)); + tcg_debug_assert(idx < NB_MMU_MODES); + + tcg_gen_qemu_ld_int(val_type, val, addr, idx, memop); } =20 static void tcg_gen_qemu_st_i32_int(TCGv_i32 orig_val, TCGTemp *addr, @@ -337,63 +356,6 @@ void tcg_gen_qemu_st_i32_chk(TCGv_i32 val, TCGTemp *ad= dr, TCGArg idx, tcg_gen_qemu_st_i32_int(val, addr, idx, memop); } =20 -static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTemp *addr, - TCGArg idx, MemOp memop) -{ - MemOp orig_memop; - MemOpIdx orig_oi, oi; - TCGv_i64 copy_addr; - TCGTemp *addr_new; - - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 1, 0); - orig_oi =3D oi =3D make_memop_idx(memop, idx); - - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - memop &=3D ~MO_BSWAP; - /* The bswap primitive benefits from zero-extended input. */ - if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { - memop &=3D ~MO_SIGN; - } - oi =3D make_memop_idx(memop, idx); - } - - addr_new =3D tci_extend_addr(addr); - copy_addr =3D plugin_maybe_preserve_addr(addr); - gen_ld_i64(val, addr_new, oi); - - if ((orig_memop ^ memop) & MO_BSWAP) { - int flags =3D (orig_memop & MO_SIGN - ? TCG_BSWAP_IZ | TCG_BSWAP_OS - : TCG_BSWAP_IZ | TCG_BSWAP_OZ); - switch (orig_memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i64(val, val, flags); - break; - case MO_32: - tcg_gen_bswap32_i64(val, val, flags); - break; - case MO_64: - tcg_gen_bswap64_i64(val, val); - break; - default: - g_assert_not_reached(); - } - } - - plugin_gen_mem_callbacks_i64(val, copy_addr, addr, orig_oi, - QEMU_PLUGIN_MEM_R); - maybe_free_addr(addr, addr_new); -} - -void tcg_gen_qemu_ld_i64_chk(TCGv_i64 val, TCGTemp *addr, TCGArg idx, - MemOp memop, TCGType addr_type) -{ - tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); - tcg_gen_qemu_ld_i64_int(val, addr, idx, memop); -} - static void tcg_gen_qemu_st_i64_int(TCGv_i64 orig_val, TCGTemp *addr, TCGArg idx, MemOp memop) { @@ -638,7 +600,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, QEMU_PLUGIN_MEM_R); } =20 -void tcg_gen_qemu_ld_i128_chk(TCGv_i128 val, TCGTemp *addr, TCGArg idx, +void tcg_gen_qemu_ld_chk_i128(TCGv_i128 val, TCGTemp *addr, TCGArg idx, MemOp memop, TCGType addr_type) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); @@ -800,7 +762,8 @@ static void tcg_gen_nonatomic_cmpxchg_i32_int(TCGv_i32 = retv, TCGTemp *addr, =20 tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); =20 - tcg_gen_qemu_ld_i32_int(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_qemu_ld_int(TCG_TYPE_I32, tcgv_i32_temp(t1), + addr, idx, memop & ~MO_SIGN); tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); tcg_gen_qemu_st_i32_int(t2, addr, idx, memop); tcg_temp_free_i32(t2); @@ -871,7 +834,8 @@ static void tcg_gen_nonatomic_cmpxchg_i64_int(TCGv_i64 = retv, TCGTemp *addr, =20 tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); =20 - tcg_gen_qemu_ld_i64_int(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_qemu_ld_int(TCG_TYPE_I64, tcgv_i64_temp(t1), + addr, idx, memop & ~MO_SIGN); tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); tcg_gen_qemu_st_i64_int(t2, addr, idx, memop); tcg_temp_free_i64(t2); @@ -1047,7 +1011,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGTemp= *addr, TCGv_i32 val, =20 memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - tcg_gen_qemu_ld_i32_int(t1, addr, idx, memop); + tcg_gen_qemu_ld_int(TCG_TYPE_I32, tcgv_i32_temp(t1), addr, idx, memop); tcg_gen_ext_i32(t2, val, memop); gen(t2, t1, t2); tcg_gen_qemu_st_i32_int(t2, addr, idx, memop); @@ -1088,7 +1052,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGTemp= *addr, TCGv_i64 val, =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - tcg_gen_qemu_ld_i64_int(t1, addr, idx, memop); + tcg_gen_qemu_ld_int(TCG_TYPE_I64, tcgv_i64_temp(t1), addr, idx, memop); tcg_gen_ext_i64(t2, val, memop); gen(t2, t1, t2); tcg_gen_qemu_st_i64_int(t2, addr, idx, memop); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index df769dd975..679cf87995 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -239,6 +239,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #define C_MemOp #define C_TCGCond #define C_TCGLabelPtr +#define C_TCGTempPtr +#define C_TCGType #define C_tcg_target_long #define C_unsigned =20 @@ -272,6 +274,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #undef C_MemOp #undef C_TCGCond #undef C_TCGLabelPtr +#undef C_TCGTempPtr +#undef C_TCGType #undef C_tcg_target_long #undef C_unsigned =20 --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 07:26:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 097/100] tcg: Generic expansion of tcg_gen_qemu_st_chk Date: Wed, 21 Oct 2026 16:16:49 +0200 Message-ID: <20261021141652.363109-98-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593115270158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 6 +- include/tcg/tcg-op-mem.h | 6 +- include/tcg/tcg-op-def.h.inc | 1 + tcg/tcg-op-ldst.c | 114 ++++++----------------------------- 4 files changed, 25 insertions(+), 102 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index ce47bebb2b..711eb96a86 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -175,12 +175,8 @@ void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); void tcg_gen_ld_i128(TCGv_i128 ret, TCGv_ptr base, tcg_target_long offset); void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tcg_target_long offset); =20 -/* Local load/store bit ops */ - void tcg_gen_qemu_ld_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); -void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); +void tcg_gen_qemu_st_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); =20 /* Atomic ops */ =20 diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h index 76955d27c1..e8425e1059 100644 --- a/include/tcg/tcg-op-mem.h +++ b/include/tcg/tcg-op-mem.h @@ -37,7 +37,7 @@ tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemO= p m) QEMU_ARG_NONNULL static inline void tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m) { - tcg_gen_qemu_st_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); + tcg_gen_qemu_st_chk_i32(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 QEMU_ARG_NONNULL static inline void @@ -49,7 +49,7 @@ tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemO= p m) QEMU_ARG_NONNULL static inline void tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m) { - tcg_gen_qemu_st_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); + tcg_gen_qemu_st_chk_i64(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 QEMU_ARG_NONNULL static inline void @@ -61,7 +61,7 @@ tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, Me= mOp m) QEMU_ARG_NONNULL static inline void tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m) { - tcg_gen_qemu_st_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); + tcg_gen_qemu_st_chk_i128(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); } =20 #define DEF_ATOMIC2(N, S) \ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index e2da3ddef6..552f62b7f4 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -54,6 +54,7 @@ DEF3(or, TCGV, TCGV, TCGV) DEF3(ori, TCGV, TCGV, TINT) DEF3(orc, TCGV, TCGV, TCGV) DEF5(qemu_ld_chk, TCGV, TCGTempPtr, unsigned, MemOp, TCGType) +DEF5(qemu_st_chk, TCGV, TCGTempPtr, unsigned, MemOp, TCGType) DEF3(rem, TCGV, TCGV, TCGV) DEF3(remu, TCGV, TCGV, TCGV) DEF2(revbit8, TCGV, TCGV) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 7d3fe60d89..d9133e611e 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -206,24 +206,6 @@ plugin_gen_mem_callbacks_tmp(TCGType type, TCGTemp *va= l, #endif } =20 -static void -plugin_gen_mem_callbacks_i32(TCGv_i32 val, - TCGv_i64 copy_addr, TCGTemp *orig_addr, - MemOpIdx oi, enum qemu_plugin_mem_rw rw) -{ - plugin_gen_mem_callbacks_tmp(TCG_TYPE_I32, tcgv_i32_temp(val), copy_ad= dr, - orig_addr, oi, rw); -} - -static void -plugin_gen_mem_callbacks_i64(TCGv_i64 val, - TCGv_i64 copy_addr, TCGTemp *orig_addr, - MemOpIdx oi, enum qemu_plugin_mem_rw rw) -{ - plugin_gen_mem_callbacks_tmp(TCG_TYPE_I64, tcgv_i64_temp(val), copy_ad= dr, - orig_addr, oi, rw); -} - static void plugin_gen_mem_callbacks_i128(TCGv_i128 val, TCGv_i64 copy_addr, TCGTemp *orig_addr, @@ -310,99 +292,43 @@ void tcg_gen_qemu_ld_chk(TCGType val_type, TCGTemp *v= al, TCGTemp *addr, tcg_gen_qemu_ld_int(val_type, val, addr, idx, memop); } =20 -static void tcg_gen_qemu_st_i32_int(TCGv_i32 orig_val, TCGTemp *addr, - TCGArg idx, MemOp memop) +static void tcg_gen_qemu_st_int(TCGType type, TCGTemp *orig_val, + TCGTemp *addr, unsigned idx, MemOp memop) { - TCGv_i32 val =3D orig_val; + TCGTemp *val =3D orig_val; MemOpIdx orig_oi, oi; TCGTemp *addr_new; =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - memop =3D tcg_canonicalize_memop(memop, 0, 1); + memop =3D tcg_canonicalize_memop(memop, type !=3D TCG_TYPE_I32, 1); orig_oi =3D oi =3D make_memop_idx(memop, idx); =20 if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - val =3D tcg_temp_ebb_new_i32(); - switch (memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i32(val, orig_val, 0); - break; - case MO_32: - tcg_gen_bswap32_i32(val, orig_val); - break; - default: - g_assert_not_reached(); - } + val =3D tcg_temp_new_ebb(type); + tcg_gen_bswap(type, val, orig_val, 0, memop); memop &=3D ~MO_BSWAP; oi =3D make_memop_idx(memop, idx); } =20 addr_new =3D tci_extend_addr(addr); - gen_ldst1(INDEX_op_qemu_st, TCG_TYPE_I32, tcgv_i32_temp(val), addr_new= , oi); - plugin_gen_mem_callbacks_i32(orig_val, NULL, addr, orig_oi, - QEMU_PLUGIN_MEM_W); + tcg_gen_op_tti(INDEX_op_qemu_st, type, val, addr_new, oi); + plugin_gen_mem_callbacks_tmp(type, orig_val, NULL, addr, + orig_oi, QEMU_PLUGIN_MEM_W); maybe_free_addr(addr, addr_new); =20 if (val !=3D orig_val) { - tcg_temp_free_i32(val); + tcg_temp_free_internal(val); } } =20 -void tcg_gen_qemu_st_i32_chk(TCGv_i32 val, TCGTemp *addr, TCGArg idx, - MemOp memop, TCGType addr_type) +void tcg_gen_qemu_st_chk(TCGType val_type, TCGTemp *val, TCGTemp *addr, + unsigned idx, MemOp memop, TCGType addr_type) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); - tcg_gen_qemu_st_i32_int(val, addr, idx, memop); -} + tcg_debug_assert(memop_size(memop) <=3D tcg_type_size(val_type)); + tcg_debug_assert(idx < NB_MMU_MODES); =20 -static void tcg_gen_qemu_st_i64_int(TCGv_i64 orig_val, TCGTemp *addr, - TCGArg idx, MemOp memop) -{ - TCGv_i64 val =3D orig_val; - MemOpIdx orig_oi, oi; - TCGTemp *addr_new; - - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - memop =3D tcg_canonicalize_memop(memop, 1, 1); - orig_oi =3D oi =3D make_memop_idx(memop, idx); - - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - val =3D tcg_temp_ebb_new_i64(); - switch (memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i64(val, orig_val, 0); - break; - case MO_32: - tcg_gen_bswap32_i64(val, orig_val, 0); - break; - case MO_64: - tcg_gen_bswap64_i64(val, orig_val); - break; - default: - g_assert_not_reached(); - } - memop &=3D ~MO_BSWAP; - oi =3D make_memop_idx(memop, idx); - } - - addr_new =3D tci_extend_addr(addr); - gen_st_i64(val, addr_new, oi); - plugin_gen_mem_callbacks_i64(orig_val, NULL, addr, orig_oi, - QEMU_PLUGIN_MEM_W); - maybe_free_addr(addr, addr_new); - - if (val !=3D orig_val) { - tcg_temp_free_i64(val); - } -} - -void tcg_gen_qemu_st_i64_chk(TCGv_i64 val, TCGTemp *addr, TCGArg idx, - MemOp memop, TCGType addr_type) -{ - tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); - tcg_gen_qemu_st_i64_int(val, addr, idx, memop); + tcg_gen_qemu_st_int(val_type, val, addr, idx, memop); } =20 /* @@ -713,7 +639,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, QEMU_PLUGIN_MEM_W); } =20 -void tcg_gen_qemu_st_i128_chk(TCGv_i128 val, TCGTemp *addr, TCGArg idx, +void tcg_gen_qemu_st_chk_i128(TCGv_i128 val, TCGTemp *addr, TCGArg idx, MemOp memop, TCGType addr_type) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); @@ -765,7 +691,7 @@ static void tcg_gen_nonatomic_cmpxchg_i32_int(TCGv_i32 = retv, TCGTemp *addr, tcg_gen_qemu_ld_int(TCG_TYPE_I32, tcgv_i32_temp(t1), addr, idx, memop & ~MO_SIGN); tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32_int(t2, addr, idx, memop); + tcg_gen_qemu_st_int(TCG_TYPE_I32, tcgv_i32_temp(t2), addr, idx, memop); tcg_temp_free_i32(t2); =20 if (memop & MO_SIGN) { @@ -837,7 +763,7 @@ static void tcg_gen_nonatomic_cmpxchg_i64_int(TCGv_i64 = retv, TCGTemp *addr, tcg_gen_qemu_ld_int(TCG_TYPE_I64, tcgv_i64_temp(t1), addr, idx, memop & ~MO_SIGN); tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64_int(t2, addr, idx, memop); + tcg_gen_qemu_st_int(TCG_TYPE_I64, tcgv_i64_temp(t2), addr, idx, memop); tcg_temp_free_i64(t2); =20 if (memop & MO_SIGN) { @@ -1014,7 +940,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGTemp = *addr, TCGv_i32 val, tcg_gen_qemu_ld_int(TCG_TYPE_I32, tcgv_i32_temp(t1), addr, idx, memop); tcg_gen_ext_i32(t2, val, memop); gen(t2, t1, t2); - tcg_gen_qemu_st_i32_int(t2, addr, idx, memop); + tcg_gen_qemu_st_int(TCG_TYPE_I32, tcgv_i32_temp(t2), addr, idx, memop); =20 tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); tcg_temp_free_i32(t1); @@ -1055,7 +981,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGTemp = *addr, TCGv_i64 val, tcg_gen_qemu_ld_int(TCG_TYPE_I64, tcgv_i64_temp(t1), addr, idx, memop); tcg_gen_ext_i64(t2, val, memop); gen(t2, t1, t2); - tcg_gen_qemu_st_i64_int(t2, addr, idx, memop); + tcg_gen_qemu_st_int(TCG_TYPE_I64, tcgv_i64_temp(t2), addr, idx, memop); =20 tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); tcg_temp_free_i64(t1); --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593086; cv=none; d=zohomail.com; s=zohoarc; b=W4t2fbrzEN1Cd6uy63qWIB7L7l0SLujHNecptDVj9AQZBcUurL2tpHxzThLsGhHERPvqQsE+ntFIByYBeHS2QYZiJOfkw1y4QUFA0cJERQ1Blf7NoZJgYdD+3yj1IOxGMgt6p2YtguhU3nUpqL8TUelCKYw+FuAQvOoN3SJF3Xk= ARC-Message-Signature: i=1; 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Wed, 21 Oct 2026 07:26:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com Subject: [PATCH v6 098/100] tcg: Generic expansion of tcg_gen_{non}atomic_qemu_cmpxchg_chk Date: Wed, 21 Oct 2026 16:16:50 +0200 Message-ID: <20261021141652.363109-99-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593088993158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 16 +-- include/tcg/tcg-op-mem.h | 2 +- tcg/tcg-internal.h | 3 + include/tcg/tcg-op-def.h.inc | 3 + tcg/tcg-op-ldst.c | 237 ++++++++++++++--------------------- tcg/tcg-op.c | 8 ++ 6 files changed, 115 insertions(+), 154 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 711eb96a86..06991b9fa3 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -104,6 +104,8 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4, T= 5); #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4, T= 5, T6); +#define DEF7(NAME, T1, T2, T3, T4, T5, T6, T7) \ + QEMU_ARG_NONNULL void glue(glue(tcg_gen_,NAME),TExt)(T1, T2, T3, T4, T= 5, T6, T7); =20 #define TCGV glue(TCGv,TExt) #define TExt _i32 @@ -129,6 +131,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo); #undef DEF4 #undef DEF5 #undef DEF6 +#undef DEF7 =20 /* 32 bit ops */ =20 @@ -180,18 +183,9 @@ void tcg_gen_qemu_st_chk_i128(TCGv_i128, TCGTemp *, TC= GArg, MemOp, TCGType); =20 /* Atomic ops */ =20 -void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i3= 2, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i6= 4, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, +void tcg_gen_atomic_cmpxchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv= _i32, - TCGArg, MemOp, TCGType); -void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv= _i64, - TCGArg, MemOp, TCGType); -void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, +void tcg_gen_nonatomic_cmpxchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGv_i128, TCGArg, MemOp, TCGType); =20 void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h index e8425e1059..935860f144 100644 --- a/include/tcg/tcg-op-mem.h +++ b/include/tcg/tcg-op-mem.h @@ -72,7 +72,7 @@ tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, Me= mOp m) #define DEF_ATOMIC3(N, S) \ QEMU_ARG_NONNULL static inline void \ N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, TCGv_##S n, TCGArg i, MemOp= m) \ - { N##_##S##_chk(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); } + { N##_chk_##S(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); } =20 DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index bfd34905ee..da1b9c9bab 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -190,6 +190,8 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5); #define DEF6(NAME, T1, T2, T3, T4, T5, T6) \ QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5,= T6); +#define DEF7(NAME, T1, T2, T3, T4, T5, T6, T7) \ + QEMU_ARG_NONNULL void glue(tcg_gen_,NAME)(TCGType, T1, T2, T3, T4, T5,= T6, T7); =20 #define TCGV TCGTemp * #define TINT int64_t @@ -207,6 +209,7 @@ bool tcg_op_imm_match(TCGOpcode op, TCGType type, tcg_t= arget_ulong imm); #undef DEF4 #undef DEF5 #undef DEF6 +#undef DEF7 =20 static inline void tcg_gen_extrh(TCGTemp *dst, TCGTemp *src) { diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index 552f62b7f4..e0ffd0da67 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -85,3 +85,6 @@ DEF3(umin, TCGV, TCGV, TCGV) DEF3(ussub, TCGV, TCGV, TCGV) DEF3(xor, TCGV, TCGV, TCGV) DEF3(xori, TCGV, TCGV, TINT) + +DEF7(atomic_cmpxchg_chk, TCGV, TCGTempPtr, TCGV, TCGV, unsigned, MemOp, TC= GType) +DEF7(nonatomic_cmpxchg_chk, TCGV, TCGTempPtr, TCGV, TCGV, unsigned, MemOp,= TCGType) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index d9133e611e..886d632f75 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -667,181 +667,129 @@ typedef void (*gen_atomic_op_i128)(TCGv_i128, TCGv_= env, TCGv_i64, # define WITH_ATOMIC128(X) #endif =20 -static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_8] =3D gen_helper_atomic_cmpxchgb, - [MO_16 | MO_LE] =3D gen_helper_atomic_cmpxchgw_le, - [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, - [MO_32 | MO_LE] =3D gen_helper_atomic_cmpxchgl_le, - [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, - [MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le, - [MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be, - WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) - WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) -}; - -static void tcg_gen_nonatomic_cmpxchg_i32_int(TCGv_i32 retv, TCGTemp *addr, - TCGv_i32 cmpv, TCGv_i32 newv, - TCGArg idx, MemOp memop) +static void tcg_gen_nonatomic_cmpxchg_int(TCGType type, TCGTemp *retv, + TCGTemp *addr, TCGTemp *cmpv, + TCGTemp *newv, unsigned idx, + MemOp memop) { - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t2 =3D tcg_temp_new_ebb(type); =20 - tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); + tcg_gen_ext(type, t2, cmpv, memop & MO_SIZE); =20 - tcg_gen_qemu_ld_int(TCG_TYPE_I32, tcgv_i32_temp(t1), - addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_int(TCG_TYPE_I32, tcgv_i32_temp(t2), addr, idx, memop); - tcg_temp_free_i32(t2); + tcg_gen_qemu_ld_int(type, t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond(type, TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_int(type, t2, addr, idx, memop); =20 if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, t1, memop); + tcg_gen_ext(type, retv, t1, memop); } else { - tcg_gen_mov_i32(retv, t1); + tcg_gen_mov(type, retv, t1); } - tcg_temp_free_i32(t1); } =20 -void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32 retv, TCGTemp *addr, - TCGv_i32 cmpv, TCGv_i32 newv, - TCGArg idx, MemOp memop, - TCGType addr_type) +void tcg_gen_nonatomic_cmpxchg_chk(TCGType val_type, TCGTemp *retv, + TCGTemp *addr, TCGTemp *cmpv, TCGTemp *= newv, + unsigned idx, MemOp memop, TCGType addr= _type) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); - tcg_gen_nonatomic_cmpxchg_i32_int(retv, addr, cmpv, newv, idx, memop); + tcg_debug_assert(memop_size(memop) <=3D tcg_type_size(val_type)); + tcg_debug_assert(idx < NB_MMU_MODES); + + tcg_gen_nonatomic_cmpxchg_int(val_type, retv, addr, cmpv, newv, idx, m= emop); } =20 -static void tcg_gen_atomic_cmpxchg_i32_int(TCGv_i32 retv, TCGTemp *addr, - TCGv_i32 cmpv, TCGv_i32 newv, - TCGArg idx, MemOp memop) +static void tcg_gen_atomic_cmpxchg_int(TCGType type, TCGTemp *retv, + TCGTemp *addr, TCGTemp *cmpv, + TCGTemp *newv, unsigned idx, + MemOp orig_memop) { - gen_atomic_cx_i32 gen; + MemOp memop =3D orig_memop; TCGv_i64 a64; MemOpIdx oi; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i32_int(retv, addr, cmpv, newv, idx, mem= op); + tcg_gen_nonatomic_cmpxchg_int(type, retv, addr, cmpv, + newv, idx, memop); return; } =20 - memop =3D tcg_canonicalize_memop(memop, 0, 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); a64 =3D maybe_extend_addr64(addr); - gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi)); - maybe_free_addr64(a64); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, retv, memop); - } -} - -void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32 retv, TCGTemp *addr, - TCGv_i32 cmpv, TCGv_i32 newv, - TCGArg idx, MemOp memop, - TCGType addr_type) -{ - tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); - tcg_gen_atomic_cmpxchg_i32_int(retv, addr, cmpv, newv, idx, memop); -} - -static void tcg_gen_nonatomic_cmpxchg_i64_int(TCGv_i64 retv, TCGTemp *addr, - TCGv_i64 cmpv, TCGv_i64 newv, - TCGArg idx, MemOp memop) -{ - TCGv_i64 t1, t2; - - t1 =3D tcg_temp_ebb_new_i64(); - t2 =3D tcg_temp_ebb_new_i64(); - - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_int(TCG_TYPE_I64, tcgv_i64_temp(t1), - addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_int(TCG_TYPE_I64, tcgv_i64_temp(t2), addr, idx, memop); - tcg_temp_free_i64(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, t1, memop); - } else { - tcg_gen_mov_i64(retv, t1); - } - tcg_temp_free_i64(t1); -} - -void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64 retv, TCGTemp *addr, - TCGv_i64 cmpv, TCGv_i64 newv, - TCGArg idx, MemOp memop, - TCGType addr_type) -{ - tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); - tcg_gen_nonatomic_cmpxchg_i64_int(retv, addr, cmpv, newv, idx, memop); -} - -static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 retv, TCGTemp *addr, - TCGv_i64 cmpv, TCGv_i64 newv, - TCGArg idx, MemOp memop) -{ - if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i64_int(retv, addr, cmpv, newv, idx, mem= op); - return; - } =20 if ((memop & MO_SIZE) =3D=3D MO_64) { gen_atomic_cx_i64 gen; =20 + tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + memop =3D tcg_canonicalize_memop(memop, 1, 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - if (gen) { - MemOpIdx oi =3D make_memop_idx(memop, idx); - TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi)); - maybe_free_addr64(a64); - return; + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + + gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE + ? gen_helper_atomic_cmpxchgq_le + : gen_helper_atomic_cmpxchgq_be); + + gen(temp_tcgv_i64(retv), tcg_env, a64, temp_tcgv_i64(cmpv), + temp_tcgv_i64(newv), tcg_constant_i32(oi)); + } else { + static gen_atomic_cx_i32 const table_cmpxchg[(MO_SIZE | MO_BSWAP) = + 1] =3D { + [MO_8] =3D gen_helper_atomic_cmpxchgb, + [MO_16 | MO_LE] =3D gen_helper_atomic_cmpxchgw_le, + [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, + [MO_32 | MO_LE] =3D gen_helper_atomic_cmpxchgl_le, + [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, + }; + + g_autoptr(TCGTemp) c32 =3D NULL; + g_autoptr(TCGTemp) n32 =3D NULL; + g_autoptr(TCGTemp) r32 =3D NULL; + TCGTemp *retv_orig =3D retv; + gen_atomic_cx_i32 gen; + + if (type =3D=3D TCG_TYPE_I64) { + c32 =3D tcg_temp_new_ebb(TCG_TYPE_I32); + n32 =3D tcg_temp_new_ebb(TCG_TYPE_I32); + r32 =3D tcg_temp_new_ebb(TCG_TYPE_I32); + + tcg_gen_extrl(c32, cmpv); + tcg_gen_extrl(n32, newv); + + cmpv =3D c32; + newv =3D n32; + retv =3D r32; } =20 - gen_helper_exit_atomic(tcg_env); + memop =3D tcg_canonicalize_memop(memop, 0, 0); + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); =20 - /* - * Produce a result for a well-formed opcode stream. This satisfi= es - * liveness for set before used, which happens before this dead co= de - * is removed. - */ - tcg_gen_movi_i64(retv, 0); - } else { - TCGv_i32 c32 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 n32 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); =20 - tcg_gen_extrl_i64_i32(c32, cmpv); - tcg_gen_extrl_i64_i32(n32, newv); - tcg_gen_atomic_cmpxchg_i32_int(r32, addr, c32, n32, - idx, memop & ~MO_SIGN); - tcg_temp_free_i32(c32); - tcg_temp_free_i32(n32); - - tcg_gen_extu_i32_i64(retv, r32); - tcg_temp_free_i32(r32); + gen(temp_tcgv_i32(retv), tcg_env, a64, temp_tcgv_i32(cmpv), + temp_tcgv_i32(newv), tcg_constant_i32(oi)); =20 if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, retv, memop); + tcg_gen_ext(TCG_TYPE_I32, retv, retv, memop); + } + if (retv !=3D retv_orig) { + if (orig_memop & MO_SIGN) { + tcg_gen_exts(retv_orig, retv); + } else { + tcg_gen_extu(retv_orig, retv); + } } } + maybe_free_addr64(a64); } =20 -void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64 retv, TCGTemp *addr, - TCGv_i64 cmpv, TCGv_i64 newv, - TCGArg idx, MemOp memop, TCGType addr_= type) +void tcg_gen_atomic_cmpxchg_chk(TCGType val_type, TCGTemp *retv, TCGTemp *= addr, + TCGTemp *cmpv, TCGTemp *newv, + unsigned idx, MemOp memop, TCGType addr_ty= pe) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); - tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); - tcg_gen_atomic_cmpxchg_i64_int(retv, addr, cmpv, newv, idx, memop); + tcg_debug_assert(memop_size(memop) <=3D tcg_type_size(val_type)); + tcg_debug_assert(idx < NB_MMU_MODES); + + tcg_gen_atomic_cmpxchg_int(val_type, retv, addr, cmpv, newv, idx, memo= p); } =20 static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv_i128 retv, TCGTemp *ad= dr, @@ -877,7 +825,7 @@ static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv_i12= 8 retv, TCGTemp *addr, tcg_temp_free_i128(oldv); } =20 -void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128 retv, TCGTemp *addr, +void tcg_gen_nonatomic_cmpxchg_chk_i128(TCGv_i128 retv, TCGTemp *addr, TCGv_i128 cmpv, TCGv_i128 newv, TCGArg idx, MemOp memop, TCGType addr_type) @@ -887,18 +835,23 @@ void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128 ret= v, TCGTemp *addr, tcg_gen_nonatomic_cmpxchg_i128_int(retv, addr, cmpv, newv, idx, memop); } =20 -static void tcg_gen_atomic_cmpxchg_i128_int(TCGv_i128 retv, TCGTemp *addr, +static void tcg_gen_atomic_cmpxchg_int_i128(TCGv_i128 retv, TCGTemp *addr, TCGv_i128 cmpv, TCGv_i128 newv, TCGArg idx, MemOp memop) { - gen_atomic_cx_i128 gen; + gen_atomic_cx_i128 gen =3D NULL; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { tcg_gen_nonatomic_cmpxchg_i128_int(retv, addr, cmpv, newv, idx, me= mop); return; } =20 - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; +#if HAVE_CMPXCHG128 + gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE + ? gen_helper_atomic_cmpxchgo_le + : gen_helper_atomic_cmpxchgo_be); +#endif + if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); @@ -918,14 +871,14 @@ static void tcg_gen_atomic_cmpxchg_i128_int(TCGv_i128= retv, TCGTemp *addr, tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); } =20 -void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128 retv, TCGTemp *addr, +void tcg_gen_atomic_cmpxchg_chk_i128(TCGv_i128 retv, TCGTemp *addr, TCGv_i128 cmpv, TCGv_i128 newv, TCGArg idx, MemOp memop, TCGType addr_type) { tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); tcg_debug_assert((memop & (MO_SIZE | MO_SIGN)) =3D=3D MO_128); - tcg_gen_atomic_cmpxchg_i128_int(retv, addr, cmpv, newv, idx, memop); + tcg_gen_atomic_cmpxchg_int_i128(retv, addr, cmpv, newv, idx, memop); } =20 static void do_nonatomic_op_i32(TCGv_i32 ret, TCGTemp *addr, TCGv_i32 val, diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 679cf87995..0a0597968e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -231,6 +231,13 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned mem= info) { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), glue(C_,T3)(c),= \ glue(C_,T4)(d), glue(C_,T5)(e), glue(C_,T6)(f)); } =20 +#define DEF7(NAME, T1, T2, T3, T4, T5, T6, T7) \ + void glue(glue(tcg_gen_,NAME),TExt)(T1 a, T2 b, T3 c, T4 d, T5 e, \ + T6 f, T7 g) \ + { tcg_gen_##NAME(TYPE, glue(C_,T1)(a), glue(C_,T2)(b), \ + glue(C_,T3)(c), glue(C_,T4)(d), glue(C_,T5)(e), \ + glue(C_,T6)(f), glue(C_,T7)(g)); } + #define C_TCGv_i32 tcgv_i32_temp #define C_TCGv_i64 tcgv_i64_temp #define C_TCGv_ptr tcgv_ptr_temp @@ -285,6 +292,7 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned memi= nfo) #undef DEF4 #undef DEF5 #undef DEF6 +#undef DEF7 =20 /* * Internal helper for bit and byte reversal. --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593829; cv=none; d=zohomail.com; s=zohoarc; b=DRR0LZwOHa0PADutA15n73GVpx7y4UKDeTmV/2iczz1HqJFOnYRkOrUi5dDUcRJF7V30tVuRoMOvgiMoHF+HI9gsD0VFE6ORRR1+s9Z7K3elqkcNLLynZLq7XMIM5qcdqjnErWPcXr8ClBFZGnV8xUtLHF044WGXgHx9h+yuOpU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593829; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PhmTY6SzYbdQKcWgUA4HvjqnFrSbrYvSqh70eBxbYSU=; b=i4noi00kJtA+S8tcIMoF+MuQ5sGuTvmPWy84yhjlCA8JPPKYM8n3hvK/wSZeqziAaVXTSfatl9kLkDCikY8Fv7+0ZCt5mkBWqCqJ3etUZVAAKOuiz1hT9X2dMEsOrHJaKnyMrMFedKQ8vLnVJEYFU5MEpO1NzHpM+aNJ1cfNFnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792593829380928.3366354765066; Wed, 21 Oct 2026 07:43:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJXIV-0000XP-4n; Wed, 21 Oct 2026 10:28:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJXGt-0006fh-7N for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:26:33 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xJXGo-0002aM-Tp for qemu-devel@nongnu.org; Wed, 21 Oct 2026 10:26:26 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-48e20ed3b9dso816824f8f.2 for ; Wed, 21 Oct 2026 07:26:22 -0700 (PDT) Received: from stoup.fritz.box (pd95f64ec.dip0.t-ipconnect.de. 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Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 80 +------------ include/tcg/tcg-op-mem.h | 2 +- include/tcg/tcg-op-def.h.inc | 20 ++++ tcg/tcg-op-ldst.c | 211 ++++++++++++++--------------------- 4 files changed, 107 insertions(+), 206 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 06991b9fa3..633be35a93 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -181,89 +181,15 @@ void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tc= g_target_long offset); void tcg_gen_qemu_ld_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); void tcg_gen_qemu_st_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); =20 -/* Atomic ops */ - void tcg_gen_atomic_cmpxchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGv_i128, TCGArg, MemOp, TCGType); void tcg_gen_nonatomic_cmpxchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, +void tcg_gen_atomic_xchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_fetch_add_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_add_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_and_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_and_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_xor_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_xor_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, +void tcg_gen_atomic_fetch_and_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_add_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_add_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_and_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_and_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_or_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_or_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xor_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xor_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_fetch_and_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, +void tcg_gen_atomic_fetch_or_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGArg, MemOp, TCGType); =20 /* Vector ops */ diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h index 935860f144..6533704082 100644 --- a/include/tcg/tcg-op-mem.h +++ b/include/tcg/tcg-op-mem.h @@ -67,7 +67,7 @@ tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, Me= mOp m) #define DEF_ATOMIC2(N, S) \ QEMU_ARG_NONNULL static inline void \ N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, TCGArg i, MemOp m) \ - { N##_##S##_chk(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); } + { N##_chk_##S(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); } =20 #define DEF_ATOMIC3(N, S) \ QEMU_ARG_NONNULL static inline void \ diff --git a/include/tcg/tcg-op-def.h.inc b/include/tcg/tcg-op-def.h.inc index e0ffd0da67..e694f0e38c 100644 --- a/include/tcg/tcg-op-def.h.inc +++ b/include/tcg/tcg-op-def.h.inc @@ -88,3 +88,23 @@ DEF3(xori, TCGV, TCGV, TINT) =20 DEF7(atomic_cmpxchg_chk, TCGV, TCGTempPtr, TCGV, TCGV, unsigned, MemOp, TC= GType) DEF7(nonatomic_cmpxchg_chk, TCGV, TCGTempPtr, TCGV, TCGV, unsigned, MemOp,= TCGType) + +DEF6(atomic_xchg_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGType) + +DEF6(atomic_fetch_add_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTyp= e) +DEF6(atomic_fetch_and_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTyp= e) +DEF6(atomic_fetch_or_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGType) +DEF6(atomic_fetch_smax_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_fetch_smin_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_fetch_umax_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_fetch_umin_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_fetch_xor_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTyp= e) + +DEF6(atomic_add_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTyp= e) +DEF6(atomic_and_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTyp= e) +DEF6(atomic_or_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGType) +DEF6(atomic_smax_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_smin_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_umax_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_umin_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTy= pe) +DEF6(atomic_xor_fetch_chk, TCGV, TCGTempPtr, TCGV, unsigned, MemOp, TCGTyp= e) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 886d632f75..5690bec6bd 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -881,113 +881,97 @@ void tcg_gen_atomic_cmpxchg_chk_i128(TCGv_i128 retv,= TCGTemp *addr, tcg_gen_atomic_cmpxchg_int_i128(retv, addr, cmpv, newv, idx, memop); } =20 -static void do_nonatomic_op_i32(TCGv_i32 ret, TCGTemp *addr, TCGv_i32 val, - TCGArg idx, MemOp memop, bool new_val, - void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +static void do_nonatomic_op(TCGType type, TCGTemp *ret, TCGTemp *addr, + TCGTemp *val, unsigned idx, MemOp memop, + bool new_val, + void (*gen)(TCGType, TCGTemp *, + TCGTemp *, TCGTemp *)) { - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); + g_autoptr(TCGTemp) t1 =3D tcg_temp_new_ebb(type); + g_autoptr(TCGTemp) t2 =3D tcg_temp_new_ebb(type); =20 - memop =3D tcg_canonicalize_memop(memop, 0, 0); + memop =3D tcg_canonicalize_memop(memop, type !=3D TCG_TYPE_I32, 0); =20 - tcg_gen_qemu_ld_int(TCG_TYPE_I32, tcgv_i32_temp(t1), addr, idx, memop); - tcg_gen_ext_i32(t2, val, memop); - gen(t2, t1, t2); - tcg_gen_qemu_st_int(TCG_TYPE_I32, tcgv_i32_temp(t2), addr, idx, memop); + tcg_gen_qemu_ld_int(type, t1, addr, idx, memop); + tcg_gen_ext(type, t2, val, memop); + gen(type, t2, t1, t2); + tcg_gen_qemu_st_int(type, t2, addr, idx, memop); =20 - tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); + tcg_gen_ext(type, ret, (new_val ? t2 : t1), memop); } =20 -static void do_atomic_op_i32(TCGv_i32 ret, TCGTemp *addr, TCGv_i32 val, - TCGArg idx, MemOp memop, void * const table[]) +static void do_atomic_op(TCGType type, TCGTemp *ret, TCGTemp *addr, + TCGTemp *val, unsigned idx, MemOp orig_memop, + void * const table[]) { - gen_atomic_op_i32 gen; - TCGv_i64 a64; + TCGv_i64 a64 =3D maybe_extend_addr64(addr); + MemOp memop =3D orig_memop; MemOpIdx oi; =20 - memop =3D tcg_canonicalize_memop(memop, 0, 0); - - gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - a64 =3D maybe_extend_addr64(addr); - gen(ret, tcg_env, a64, val, tcg_constant_i32(oi)); - maybe_free_addr64(a64); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(ret, ret, memop); - } -} - -static void do_nonatomic_op_i64(TCGv_i64 ret, TCGTemp *addr, TCGv_i64 val, - TCGArg idx, MemOp memop, bool new_val, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t2 =3D tcg_temp_ebb_new_i64(); - - memop =3D tcg_canonicalize_memop(memop, 1, 0); - - tcg_gen_qemu_ld_int(TCG_TYPE_I64, tcgv_i64_temp(t1), addr, idx, memop); - tcg_gen_ext_i64(t2, val, memop); - gen(t2, t1, t2); - tcg_gen_qemu_st_int(TCG_TYPE_I64, tcgv_i64_temp(t2), addr, idx, memop); - - tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); -} - -static void do_atomic_op_i64(TCGv_i64 ret, TCGTemp *addr, TCGv_i64 val, - TCGArg idx, MemOp memop, void * const table[]) -{ - memop =3D tcg_canonicalize_memop(memop, 1, 0); - if ((memop & MO_SIZE) =3D=3D MO_64) { - gen_atomic_op_i64 gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; + gen_atomic_op_i64 gen; =20 - if (gen) { - MemOpIdx oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen(ret, tcg_env, a64, val, tcg_constant_i32(oi)); - maybe_free_addr64(a64); - return; + tcg_debug_assert(type =3D=3D TCG_TYPE_I64); + + memop =3D tcg_canonicalize_memop(memop, 1, 0); + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + + gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + gen(temp_tcgv_i64(ret), tcg_env, a64, + temp_tcgv_i64(val), tcg_constant_i32(oi)); + } else { + g_autoptr(TCGTemp) v32 =3D NULL; + g_autoptr(TCGTemp) r32 =3D NULL; + TCGTemp *ret_orig =3D ret; + gen_atomic_op_i32 gen; + + if (type =3D=3D TCG_TYPE_I64) { + v32 =3D tcg_temp_new_ebb(TCG_TYPE_I32); + r32 =3D tcg_temp_new_ebb(TCG_TYPE_I32); + + tcg_gen_extrl(v32, val); + val =3D v32; + ret =3D r32; } =20 - gen_helper_exit_atomic(tcg_env); - /* Produce a result, so that we have a well-formed opcode stream - with respect to uses of the result in the (dead) code following= . */ - tcg_gen_movi_i64(ret, 0); - } else { - TCGv_i32 v32 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); + memop =3D tcg_canonicalize_memop(memop, 0, 0); + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); =20 - tcg_gen_extrl_i64_i32(v32, val); - do_atomic_op_i32(r32, addr, v32, idx, memop & ~MO_SIGN, table); - tcg_temp_free_i32(v32); + gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); =20 - tcg_gen_extu_i32_i64(ret, r32); - tcg_temp_free_i32(r32); + gen(temp_tcgv_i32(ret), tcg_env, a64, + temp_tcgv_i32(val), tcg_constant_i32(oi)); =20 if (memop & MO_SIGN) { - tcg_gen_ext_i64(ret, ret, memop); + tcg_gen_ext(TCG_TYPE_I32, ret, ret, memop); + } + if (ret !=3D ret_orig) { + if (orig_memop & MO_SIGN) { + tcg_gen_exts(ret_orig, ret); + } else { + tcg_gen_extu(ret_orig, ret); + } } } + maybe_free_addr64(a64); } =20 static void do_nonatomic_op_i128(TCGv_i128 ret, TCGTemp *addr, TCGv_i128 v= al, TCGArg idx, MemOp memop, bool new_val, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) + void (*gen)(TCGType, TCGTemp *, + TCGTemp *, TCGTemp *)) { TCGv_i128 t =3D tcg_temp_ebb_new_i128(); TCGv_i128 r =3D tcg_temp_ebb_new_i128(); =20 tcg_gen_qemu_ld_i128_int(r, addr, idx, memop); - gen(TCGV128_LOW(t), TCGV128_LOW(r), TCGV128_LOW(val)); - gen(TCGV128_HIGH(t), TCGV128_HIGH(r), TCGV128_HIGH(val)); + gen(TCG_TYPE_I64, tcgv_i64_temp(TCGV128_LOW(t)), + tcgv_i64_temp(TCGV128_LOW(r)), tcgv_i64_temp(TCGV128_LOW(val))); + gen(TCG_TYPE_I64, tcgv_i64_temp(TCGV128_HIGH(t)), + tcgv_i64_temp(TCGV128_HIGH(r)), tcgv_i64_temp(TCGV128_HIGH(val))); tcg_gen_qemu_st_i128_int(t, addr, idx, memop); =20 tcg_gen_mov_i128(ret, r); @@ -1026,33 +1010,21 @@ static void * const table_##NAME[(MO_SIZE | MO_BSWA= P) + 1] =3D { \ WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_##NAME##o_le) \ WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_##NAME##o_be) \ }; \ -void tcg_gen_atomic_##NAME##_i32_chk(TCGv_i32 ret, TCGTemp *addr, \ - TCGv_i32 val, TCGArg idx, \ - MemOp memop, TCGType addr_type) \ +void tcg_gen_atomic_##NAME##_chk(TCGType val_type, TCGTemp *ret, \ + TCGTemp *addr, TCGTemp *val, unsigned idx= , \ + MemOp memop, TCGType addr_type) \ { \ tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); = \ - tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); \ + tcg_debug_assert(memop_size(memop) <=3D tcg_type_size(val_type)); \ + tcg_debug_assert(idx < NB_MMU_MODES); \ if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ - do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ + do_atomic_op(val_type, ret, addr, val, idx, memop, table_##NAME); \ } else { \ - do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i32); \ + do_nonatomic_op(val_type, ret, addr, val, idx, memop, NEW, \ + tcg_gen_##OP); \ } \ } \ -void tcg_gen_atomic_##NAME##_i64_chk(TCGv_i64 ret, TCGTemp *addr, \ - TCGv_i64 val, TCGArg idx, \ - MemOp memop, TCGType addr_type) \ -{ \ - tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); = \ - tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); \ - if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ - do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ - } else { \ - do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i64); \ - } \ -} \ -void tcg_gen_atomic_##NAME##_i128_chk(TCGv_i128 ret, TCGTemp *addr, \ +void tcg_gen_atomic_##NAME##_chk_i128(TCGv_i128 ret, TCGTemp *addr, \ TCGv_i128 val, TCGArg idx, \ MemOp memop, TCGType addr_type) \ { \ @@ -1062,7 +1034,7 @@ void tcg_gen_atomic_##NAME##_i128_chk(TCGv_i128 ret, = TCGTemp *addr, \ do_atomic_op_i128(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i128(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i64); \ + tcg_gen_##OP); \ } \ } =20 @@ -1076,30 +1048,18 @@ static void * const table_##NAME[(MO_SIZE | MO_BSWA= P) + 1] =3D { \ [MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le, \ [MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be, \ }; \ -void tcg_gen_atomic_##NAME##_i32_chk(TCGv_i32 ret, TCGTemp *addr, \ - TCGv_i32 val, TCGArg idx, \ - MemOp memop, TCGType addr_type) \ +void tcg_gen_atomic_##NAME##_chk(TCGType val_type, TCGTemp *ret, \ + TCGTemp *addr, TCGTemp *val, unsigned idx= , \ + MemOp memop, TCGType addr_type) \ { \ tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); = \ - tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); \ + tcg_debug_assert(memop_size(memop) <=3D tcg_type_size(val_type)); \ + tcg_debug_assert(idx < NB_MMU_MODES); \ if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ - do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ + do_atomic_op(val_type, ret, addr, val, idx, memop, table_##NAME); \ } else { \ - do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i32); \ - } \ -} \ -void tcg_gen_atomic_##NAME##_i64_chk(TCGv_i64 ret, TCGTemp *addr, \ - TCGv_i64 val, TCGArg idx, \ - MemOp memop, TCGType addr_type) \ -{ \ - tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); = \ - tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); \ - if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ - do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ - } else { \ - do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i64); \ + do_nonatomic_op(val_type, ret, addr, val, idx, memop, NEW, \ + tcg_gen_##OP); \ } \ } =20 @@ -1121,14 +1081,9 @@ GEN_ATOMIC_HELPER(umin_fetch, umin, 1) GEN_ATOMIC_HELPER(smax_fetch, smax, 1) GEN_ATOMIC_HELPER(umax_fetch, umax, 1) =20 -static void tcg_gen_mov2_i32(TCGv_i32 r, TCGv_i32 a, TCGv_i32 b) +static void tcg_gen_mov2(TCGType type, TCGTemp *r, TCGTemp *a, TCGTemp *b) { - tcg_gen_mov_i32(r, b); -} - -static void tcg_gen_mov2_i64(TCGv_i64 r, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_mov_i64(r, b); + tcg_gen_mov(type, r, b); } =20 GEN_ATOMIC_HELPER128(xchg, mov2, 0) --=20 2.53.0 From nobody Fri Oct 23 21:32:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792593141; cv=none; d=zohomail.com; s=zohoarc; b=ibjnAdzXrCQhYime/lPUz7SPiQe8U2+EXbJB+vWlEgXacQ/C5GhrzPwV2/P8dfuh3noXdGy6dPyKuVFkGXxvS5J/MAeFMhGy862fCgGTdcYMgrx6coCr0AFUHCOVkVy0CPl1TXiCVGHmInVDuCC5K7P0SXEzQNgHELeWCDQyLRA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792593141; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u3M+yL4MDYWjDcjtOtPUy8hgLIHwFG9dqC9d1QTgvRI=; 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Wed, 21 Oct 2026 07:26:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mattst88@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 100/100] tcg: Annontate functions in tcg-op-common.h with QEMU_*_NONNULL Date: Wed, 21 Oct 2026 16:16:52 +0200 Message-ID: <20261021141652.363109-101-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261021141652.363109-1-richard.henderson@linaro.org> References: <20261021141652.363109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792593143824158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Matt Turner --- include/tcg/tcg-op-common.h | 104 +++++++++++++++++++++++++++++++++++- 1 file changed, 102 insertions(+), 2 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 633be35a93..f80a895685 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -12,23 +12,38 @@ #include "exec/helper-proto-common.h" #include "exec/helper-gen-common.h" =20 +QEMU_RET_NONNULL TCGv_i32 tcg_constant_i32(int32_t val); +QEMU_RET_NONNULL TCGv_i64 tcg_constant_i64(int64_t val); +QEMU_RET_NONNULL TCGv_vaddr tcg_constant_vaddr(uintptr_t val); +QEMU_RET_NONNULL TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); +QEMU_RET_NONNULL TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t = val); =20 +QEMU_RET_NONNULL TCGv_i128 tcg_zero_i128(void); =20 +QEMU_RET_NONNULL TCGv_i32 tcg_temp_new_i32(void); +QEMU_RET_NONNULL TCGv_i64 tcg_temp_new_i64(void); +QEMU_RET_NONNULL TCGv_ptr tcg_temp_new_ptr(void); +QEMU_RET_NONNULL TCGv_i128 tcg_temp_new_i128(void); +QEMU_RET_NONNULL TCGv_vec tcg_temp_new_vec(TCGType type); +QEMU_RET_NONNULL TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); =20 +QEMU_RET_NONNULL TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t off, const char *na= me); +QEMU_RET_NONNULL TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *na= me); +QEMU_RET_NONNULL TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *na= me); =20 /* Generic ops. */ @@ -41,8 +56,8 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64= _t a1, tcg_set_insn_start_param(op, 2, a2); } =20 -void gen_set_label(TCGLabel *l); -void tcg_gen_br(TCGLabel *l); +QEMU_ARG_NONNULL void gen_set_label(TCGLabel *l); +QEMU_ARG_NONNULL void tcg_gen_br(TCGLabel *l); void tcg_gen_mb(TCGBar); =20 /** @@ -86,6 +101,7 @@ void tcg_gen_goto_tb(unsigned idx); void tcg_gen_lookup_and_goto_ptr(void); =20 void tcg_gen_plugin_cb(unsigned from); +QEMU_ARG_NONNULL void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo); =20 /* @@ -135,120 +151,204 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned = meminfo); =20 /* 32 bit ops */ =20 +QEMU_ARG_NONNULL void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); +QEMU_ARG_NONNULL void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); +QEMU_ARG_NONNULL void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); +QEMU_ARG_NONNULL void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg); =20 /* 64 bit ops */ =20 +QEMU_ARG_NONNULL void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b); +QEMU_ARG_NONNULL void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); +QEMU_ARG_NONNULL void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); +QEMU_ARG_NONNULL void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags); +QEMU_ARG_NONNULL void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg); =20 +QEMU_ARG_NONNULL void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); =20 +QEMU_ARG_NONNULL void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); +QEMU_ARG_NONNULL void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); =20 /* Size changing operations. */ =20 +QEMU_ARG_NONNULL void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); +QEMU_ARG_NONNULL void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); +QEMU_ARG_NONNULL void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); +QEMU_ARG_NONNULL void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); +QEMU_ARG_NONNULL void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi); =20 +QEMU_ARG_NONNULL void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +QEMU_ARG_NONNULL void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); =20 /* 128 bit ops */ =20 +QEMU_ARG_NONNULL void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +QEMU_ARG_NONNULL void tcg_gen_ld_i128(TCGv_i128 ret, TCGv_ptr base, tcg_target_long offset); +QEMU_ARG_NONNULL void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tcg_target_long offset); =20 +QEMU_ARG_NONNULL void tcg_gen_qemu_ld_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); +QEMU_ARG_NONNULL void tcg_gen_qemu_st_chk_i128(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); =20 +QEMU_ARG_NONNULL void tcg_gen_atomic_cmpxchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGv_i128, TCGArg, MemOp, TCGType); +QEMU_ARG_NONNULL void tcg_gen_nonatomic_cmpxchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGv_i128, TCGArg, MemOp, TCGType); +QEMU_ARG_NONNULL void tcg_gen_atomic_xchg_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGArg, MemOp, TCGType); +QEMU_ARG_NONNULL void tcg_gen_atomic_fetch_and_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGArg, MemOp, TCGType); +QEMU_ARG_NONNULL void tcg_gen_atomic_fetch_or_chk_i128(TCGv_i128, TCGTemp *, TCGv_i128, TCGArg, MemOp, TCGType); =20 /* Vector ops */ =20 +QEMU_ARG_NONNULL void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); +QEMU_ARG_NONNULL void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); +QEMU_ARG_NONNULL void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +QEMU_ARG_NONNULL void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); +QEMU_ARG_NONNULL void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); +QEMU_ARG_NONNULL void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +QEMU_ARG_NONNULL void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +QEMU_ARG_NONNULL void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +QEMU_ARG_NONNULL void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +QEMU_ARG_NONNULL void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 +QEMU_ARG_NONNULL void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +QEMU_ARG_NONNULL void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +QEMU_ARG_NONNULL void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +QEMU_ARG_NONNULL void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +QEMU_ARG_NONNULL void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 +QEMU_ARG_NONNULL void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +QEMU_ARG_NONNULL void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +QEMU_ARG_NONNULL void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +QEMU_ARG_NONNULL void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); =20 +QEMU_ARG_NONNULL void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +QEMU_ARG_NONNULL void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +QEMU_ARG_NONNULL void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +QEMU_ARG_NONNULL void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +QEMU_ARG_NONNULL void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); =20 +QEMU_ARG_NONNULL void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 +QEMU_ARG_NONNULL void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGv_vec c); +QEMU_ARG_NONNULL void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); =20 +QEMU_ARG_NONNULL void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); +QEMU_ARG_NONNULL void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); +QEMU_ARG_NONNULL void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); =20 /* Host pointer ops */ --=20 2.53.0