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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543420729158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- docs/system/hexagon/emulation.rst | 2 +- target/hexagon/cpu-qom.h | 4 ++++ linux-user/hexagon/elfload.c | 4 ++++ target/hexagon/cpu.c | 2 ++ 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/docs/system/hexagon/emulation.rst b/docs/system/hexagon/emulat= ion.rst index 12385311aa4..fb57c77ae90 100644 --- a/docs/system/hexagon/emulation.rst +++ b/docs/system/hexagon/emulation.rst @@ -6,7 +6,7 @@ Hexagon CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 QEMU's TCG emulation includes support for v65, v66, v67, v68, v69, v71, v7= 3, -v75, v77, v79, v81. +v75, v77, v79, v81, v83, v85. It also has support for the following architecture extensions: =20 - HVX (Hexagon Vector eXtensions) diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h index 2bfa4d5d0fc..d4c8413ded3 100644 --- a/target/hexagon/cpu-qom.h +++ b/target/hexagon/cpu-qom.h @@ -28,6 +28,8 @@ typedef enum { HEX_VER_V75 =3D 0x75, HEX_VER_V79 =3D 0x79, HEX_VER_V81 =3D 0x81, + HEX_VER_V83 =3D 0x83, + HEX_VER_V85 =3D 0x85, HEX_VER_ANY =3D 0xff, } HexagonVersion; =20 @@ -55,6 +57,8 @@ typedef struct { #define TYPE_HEXAGON_CPU_V75 HEXAGON_CPU_TYPE_NAME("v75") #define TYPE_HEXAGON_CPU_V79 HEXAGON_CPU_TYPE_NAME("v79") #define TYPE_HEXAGON_CPU_V81 HEXAGON_CPU_TYPE_NAME("v81") +#define TYPE_HEXAGON_CPU_V83 HEXAGON_CPU_TYPE_NAME("v83") +#define TYPE_HEXAGON_CPU_V85 HEXAGON_CPU_TYPE_NAME("v85") =20 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) =20 diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c index 3a6ba4e1304..9f98ad8fb86 100644 --- a/linux-user/hexagon/elfload.c +++ b/linux-user/hexagon/elfload.c @@ -113,6 +113,10 @@ const char *get_elf_cpu_model(uint32_t eflags) return "v79"; case 0x81: return "v81"; + case 0x83: + return "v83"; + case 0x85: + return "v85"; } =20 err =3D snprintf(buf, sizeof(buf), "unknown (0x%x)", eflags); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f20d6de6f63..1e3df5d0d03 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -934,6 +934,8 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_HEXAGON_CPU_V75, HEX_VER_V75), DEFINE_CPU(TYPE_HEXAGON_CPU_V79, HEX_VER_V79), DEFINE_CPU(TYPE_HEXAGON_CPU_V81, HEX_VER_V81), + DEFINE_CPU(TYPE_HEXAGON_CPU_V83, HEX_VER_V83), + DEFINE_CPU(TYPE_HEXAGON_CPU_V85, HEX_VER_V85), }; =20 DEFINE_TYPES(hexagon_cpu_type_infos) --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792543406; cv=none; d=zohomail.com; s=zohoarc; b=amQf9SEy3wuyM0ptbcdWwpXh2TBIqgN0LeOxvC3PtvP5Q+Kg+7tXqG3HEmRMZUbzOR7n98+WZPu8HX29VOVpYpfuAwH6NIJ0esKjIRFYwRyp1IfnJ8cHwAtY6btiTxC/5hNPgJETdbFZzWEt65vKvTMXevlAyj8VWzpZiRsRsN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792543406; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mC8jl7vyVvYi+vhoijubMe1xPjMvd4/tlNPZMUbwGZ8=; b=CTei0uKADlCbzsNoSUuJrWsRvx75IZOwer+u4tm344ylpLmUa8clViwf8us7hqOCjMFLO5Iz2C/Z7SAqylwsXFJt0rgzkXQhUotJdo2DRuSOrkYZdAXKuytsmejdw+V8OzPf6yhB0Ld6mO+y+xGZZy99lFt0whtjPHIO/oiExg8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179254340690824.623578432250838; Tue, 20 Oct 2026 17:43:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJKP0-0002BA-78; Tue, 20 Oct 2026 20:41:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJKOx-0002Aq-CQ for qemu-devel@nongnu.org; Tue, 20 Oct 2026 20:41:56 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJKOv-0006yx-OO for qemu-devel@nongnu.org; Tue, 20 Oct 2026 20:41:55 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69KKth2h1716840 for ; Wed, 21 Oct 2026 00:41:52 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4heeb9903n-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 00:41:52 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-30c0d568830so361078eec.1 for ; Tue, 20 Oct 2026 17:41:52 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543408443158500 Reviewed-by: Pierrick Bouvier Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- linux-user/hexagon/target_elf.h | 2 ++ linux-user/hexagon/elfload.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/linux-user/hexagon/target_elf.h b/linux-user/hexagon/target_el= f.h index 90e5032d5aa..b1eb5ea5037 100644 --- a/linux-user/hexagon/target_elf.h +++ b/linux-user/hexagon/target_elf.h @@ -43,6 +43,8 @@ enum { HWCAP_HEXAGON_ISA_V77 =3D 16, HWCAP_HEXAGON_ISA_V79 =3D 17, HWCAP_HEXAGON_ISA_V81 =3D 18, + HWCAP_HEXAGON_ISA_V83 =3D 19, + HWCAP_HEXAGON_ISA_V85 =3D 20, HWCAP_HEXAGON_HVX =3D 1 << 7, HWCAP_HEXAGON_CABAC =3D 1 << 8, HWCAP_HEXAGON_HVX_LENGTH_128B =3D 1 << 9, diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c index 9f98ad8fb86..db0bf299cc0 100644 --- a/linux-user/hexagon/elfload.c +++ b/linux-user/hexagon/elfload.c @@ -62,6 +62,12 @@ abi_ulong get_elf_hwcap(CPUState *cs) case HEX_VER_V81: hwcaps =3D HWCAP_HEXAGON_ISA_V81; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543463521158500 hex_subsys_create() always maps the main DDR at address 0. This is appropr= iate for hexagon-sim-style machines, but real SoCs map it elsewhere. Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 2 ++ hw/hexagon/hex-subsys.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 9b5d33ffc3b..6955e600aee 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -145,6 +145,8 @@ union hexagon_config_table { }; =20 struct hexagon_machine_config { + /* Base address of the main DDR region */ + hwaddr ddr_base; /* Base address of config table */ uint32_t cfgbase; /* Size of L2 TCM */ diff --git a/hw/hexagon/hex-subsys.c b/hw/hexagon/hex-subsys.c index 9818cf58878..382f45bd09f 100644 --- a/hw/hexagon/hex-subsys.c +++ b/hw/hexagon/hex-subsys.c @@ -136,10 +136,10 @@ void hex_subsys_create(HexagonCommonMachineState *hms, MachineState *machine =3D MACHINE(hms); MemoryRegion *sysmem =3D get_system_memory(); =20 - /* Main DDR at the reset vector. */ + /* Main DDR. */ memory_region_init_ram(&hms->ram, NULL, "ddr.ram", machine->ram_size, &error_fatal); - memory_region_add_subregion(sysmem, 0x0, &hms->ram); + memory_region_add_subregion(sysmem, m_cfg->ddr_base, &hms->ram); =20 /* Config-table ROM and the blob that backs it. */ memory_region_init_rom(&hms->cfgtable_rom, NULL, "config_table.rom", --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792543427; cv=none; d=zohomail.com; s=zohoarc; b=AesH+rgeJPuxn8SU4QTfWb9fI64nt+REL/ATZ7O7CwQTTIi2evnfc+LItcMUxDgvXfRKKDVTbb5DFqB+5qG5/4pFkFvJtiEWTp8+GYdUfJyKcaTVX46NXpsQl+bWlFDf0j5Tq8yQoHGh3pg+k4iaggyFQt7XgJ+fU/ytuTY6uCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792543427; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FUnTTslZCqzz9xU/N3sz+unniMy2g1xIjXSP7tRTUXk=; b=IhXCcBHuP5wuTCz8n/LoPsaQgbDHphRn/j+X3LVAUpTD54FIZplbCQ9hitpm+Yf1zRsnLQ/J2HJoc2vh+ZbhGHmbdtsJxbQ0slgWuI4TwM+zcvAlWBzBoIKC/bfL39/viVMx/975PsBqAHbEkt9G9g+coBy/zmH3waWQjEi1Xjw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792543427138132.19222283783506; Tue, 20 Oct 2026 17:43:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJKP5-0002Ca-DU; Tue, 20 Oct 2026 20:42:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJKP2-0002Bx-Ct for qemu-devel@nongnu.org; Tue, 20 Oct 2026 20:42:00 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJKOz-0006zS-NQ for qemu-devel@nongnu.org; Tue, 20 Oct 2026 20:42:00 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69KM3oHV3376375 for ; Wed, 21 Oct 2026 00:41:56 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hegs00d45-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 00:41:56 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-33c35f5ca6cso272938eec.1 for ; Tue, 20 Oct 2026 17:41:56 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543429021158500 Move what virt.c does to build a board out of it into helpers in a new hex-board.c, so that other Hexagon machines that describe themselves with a generated device tree can reuse it. This will be used by future commits. Signed-off-by: Brian Cain --- MAINTAINERS | 2 + include/hw/hexagon/hex-board.h | 65 ++++++++ hw/hexagon/hex-board.c | 265 +++++++++++++++++++++++++++++++++ hw/hexagon/Kconfig | 9 +- hw/hexagon/meson.build | 1 + 5 files changed, 340 insertions(+), 2 deletions(-) create mode 100644 include/hw/hexagon/hex-board.h create mode 100644 hw/hexagon/hex-board.c diff --git a/MAINTAINERS b/MAINTAINERS index 33b4f7c259d..7c14d006f64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -256,6 +256,8 @@ F: tests/qtest/l2vic-test.c F: hw/timer/qct-qtimer.c F: include/hw/timer/qct-qtimer.h F: tests/qtest/qct-qtimer-test.c +F: hw/hexagon/hex-board.c +F: include/hw/hexagon/hex-board.h X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ diff --git a/include/hw/hexagon/hex-board.h b/include/hw/hexagon/hex-board.h new file mode 100644 index 00000000000..93a31cb2ecc --- /dev/null +++ b/include/hw/hexagon/hex-board.h @@ -0,0 +1,65 @@ +/* + * Board-construction helpers shared by the Hexagon machines. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_HEXAGON_HEX_BOARD_H +#define HW_HEXAGON_HEX_BOARD_H + +#include "hw/hexagon/hexagon.h" + +/* The L2VIC interrupt specifiers of the 32 per-cpu lines precede its line= s. */ +#define HEX_BOARD_L2VIC_SPI_BASE 32 + +/* + * Create the device tree with its root, /soc and /chosen (including an + * rng-seed) nodes. Returns its size in @fdt_size. + */ +void hex_board_create_fdt(MachineState *ms, const char *model, + const char *compatible, int *fdt_size); + +/* Add the L2VIC node and make it the interrupt parent of /soc. */ +int32_t hex_board_fdt_add_l2vic(MachineState *ms, + const struct hexagon_machine_config *cfg); + +/* Add the /soc/vtcm and /soc/hvx nodes, for what the config provides. */ +void hex_board_fdt_add_hvx(MachineState *ms, + const struct hexagon_machine_config *cfg); + +/* Add one /cpus/cpu@N node per CPU of the machine. */ +void hex_board_fdt_add_cpus(MachineState *ms); + +/* Create the L2 TCM RAM, if the config has any. */ +void hex_board_create_tcm(const struct hexagon_machine_config *cfg, + MemoryRegion *tcm); + +/* Create the PL011 console and its fixed clock, and describe them. */ +void hex_board_create_uart(MachineState *ms, hwaddr base, hwaddr size, + int irq, int32_t l2vic_phandle); + +/* Create @count virtio-mmio transports on consecutive lines and slots. */ +void hex_board_create_virtio(MachineState *ms, hwaddr base, hwaddr size, + int irq_base, int count, + int32_t l2vic_phandle); + +/* + * Load an ELF for the guest and return its entry point. If @translate is + * given it maps the ELF's addresses. The highest address used is returned + * in @high, if non-NULL. Exits on failure. + */ +uint64_t hex_board_load_elf(const char *filename, + uint64_t (*translate)(void *opaque, uint64_t a= ddr), + void *opaque, uint64_t *high); + +/* Copy the device tree to @addr and refresh its rng-seed on reset. */ +void hex_board_load_fdt(MachineState *ms, int fdt_size, hwaddr addr); + +/* + * Create the machine's CPUs, with CPU 0 starting at @start if @have_start, + * and realize the cluster. + */ +void hex_board_create_cpus(MachineState *ms, bool have_start, uint64_t sta= rt); + +#endif /* HW_HEXAGON_HEX_BOARD_H */ diff --git a/hw/hexagon/hex-board.c b/hw/hexagon/hex-board.c new file mode 100644 index 00000000000..3bf09e4e7c7 --- /dev/null +++ b/hw/hexagon/hex-board.c @@ -0,0 +1,265 @@ +/* + * Board-construction helpers shared by the Hexagon machines that describe + * themselves to the guest with a generated device tree. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "elf.h" +#include "hw/char/pl011.h" +#include "hw/core/boards.h" +#include "hw/core/clock.h" +#include "hw/core/loader.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/sysbus.h" +#include "hw/hexagon/hex-board.h" +#include "hw/hexagon/hex-subsys.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "system/address-spaces.h" +#include "system/device_tree.h" +#include "system/reset.h" +#include "system/system.h" +#include "target/hexagon/cpu.h" + +#define APB_CLK_HZ 24000000 + +void hex_board_create_fdt(MachineState *ms, const char *model, + const char *compatible, int *fdt_size) +{ + void *fdt =3D create_device_tree(fdt_size); + uint8_t rng_seed[32]; + + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + ms->fdt =3D fdt; + + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); + qemu_fdt_setprop_string(fdt, "/", "model", model); + qemu_fdt_setprop_string(fdt, "/", "compatible", compatible); + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + + qemu_fdt_add_subnode(fdt, "/chosen"); + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed= )); +} + +static void fdt_set_irq(MachineState *ms, const char *nodename, int irq) +{ + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", + HEX_BOARD_L2VIC_SPI_BASE + irq, 0); +} + +int32_t hex_board_fdt_add_l2vic(MachineState *ms, + const struct hexagon_machine_config *cfg) +{ + int32_t l2vic_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + g_autofree char *nodename =3D g_strdup_printf("/soc/interrupt-controll= er@%x", + cfg->l2vic_base); + static const char compat[] =3D "qcom,h2-pic\0hvm-pic"; + + qemu_fdt_setprop_cell(ms->fdt, "/soc", "interrupt-parent", l2vic_phand= le); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); + qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compa= t)); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, cfg->l2vic_base, + cfg->l2vic_size); + qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", l2vic_phandle); + + return l2vic_phandle; +} + +void hex_board_fdt_add_hvx(MachineState *ms, + const struct hexagon_machine_config *cfg) +{ + const union hexagon_config_table *t =3D &cfg->cfgtable; + + if (t->vtcm_size_kb > 0) { + qemu_fdt_add_subnode(ms->fdt, "/soc/vtcm"); + qemu_fdt_setprop_string(ms->fdt, "/soc/vtcm", "compatible", + "qcom,hexagon_vtcm"); + qemu_fdt_setprop_cells(ms->fdt, "/soc/vtcm", "reg", 0, + t->vtcm_base << 16, t->vtcm_size_kb * 1024); + } + + if (t->ext_contexts > 0) { + qemu_fdt_add_subnode(ms->fdt, "/soc/hvx"); + qemu_fdt_setprop_string(ms->fdt, "/soc/hvx", "compatible", + "qcom,hexagon-hvx"); + qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-max-ctxts", + t->ext_contexts); + qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-vlength", + t->hvx_vec_log_length); + } +} + +void hex_board_fdt_add_cpus(MachineState *ms) +{ + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + + for (int num =3D ms->smp.cpus - 1; num >=3D 0; num--) { + g_autofree char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + } +} + +void hex_board_create_tcm(const struct hexagon_machine_config *cfg, + MemoryRegion *tcm) +{ + if (cfg->l2tcm_size) { + memory_region_init_ram(tcm, NULL, "tcm.ram", cfg->l2tcm_size, + &error_fatal); + memory_region_add_subregion(get_system_memory(), + (hwaddr)cfg->cfgtable.l2tcm_base << 16, + tcm); + } +} + +void hex_board_create_uart(MachineState *ms, hwaddr base, hwaddr size, + int irq, int32_t l2vic_phandle) +{ + static const char compat[] =3D "arm,pl011\0arm,primecell"; + static const char clocknames[] =3D "uartclk\0apb_pclk"; + HexagonCommonMachineState *hms =3D HEXAGON_COMMON_MACHINE(ms); + int32_t clk_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + g_autofree char *nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); + Clock *apb_clk =3D clock_new(OBJECT(ms), "apb-pclk"); + DeviceState *dev =3D qdev_new(TYPE_PL011); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + + clock_set_hz(apb_clk, APB_CLK_HZ); + + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + qdev_connect_clock_in(dev, "clk", apb_clk); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, base); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(hms->l2vic, irq)); + + qemu_fdt_add_subnode(ms->fdt, "/apb-pclk"); + qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "compatible", "fixed-clo= ck"); + qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "#clock-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "clock-frequency", APB_CLK= _HZ); + qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "clock-output-names", + "clk24mhz"); + qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "phandle", clk_phandle); + + qemu_fdt_add_subnode(ms->fdt, nodename); + /* Can't use setprop_string because of the embedded NUL */ + qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compa= t)); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size); + fdt_set_irq(ms, nodename, irq); + qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", + l2vic_phandle); + qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", clk_phandle, + clk_phandle); + qemu_fdt_setprop(ms->fdt, nodename, "clock-names", clocknames, + sizeof(clocknames)); + + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_add_subnode(ms->fdt, "/aliases"); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); +} + +void hex_board_create_virtio(MachineState *ms, hwaddr base, hwaddr size, + int irq_base, int count, + int32_t l2vic_phandle) +{ + HexagonCommonMachineState *hms =3D HEXAGON_COMMON_MACHINE(ms); + + for (int i =3D 0; i < count; i++) { + int irq =3D irq_base + i; + hwaddr slot =3D base + i * size; + g_autofree char *nodename =3D g_strdup_printf("/soc/virtio_mmio@%"= PRIx64, + slot); + DeviceState *dev =3D qdev_new("virtio-mmio"); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + + object_property_add_child(OBJECT(ms), "virtio-mmio[*]", OBJECT(dev= )); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, slot); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(hms->l2vic, irq)); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", + "virtio,mmio"); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, slot, size); + fdt_set_irq(ms, nodename, irq); + qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", + l2vic_phandle); + } +} + +uint64_t hex_board_load_elf(const char *filename, + uint64_t (*translate)(void *opaque, uint64_t a= ddr), + void *opaque, uint64_t *high) +{ + uint64_t entry =3D 0; + + if (load_elf_ram_sym(filename, NULL, translate, opaque, &entry, NULL, + high, NULL, 0, EM_HEXAGON, 0, 0, + &address_space_memory, false, NULL) <=3D 0) { + error_report("error loading '%s'", filename); + exit(1); + } + return entry; +} + +void hex_board_load_fdt(MachineState *ms, int fdt_size, hwaddr addr) +{ + rom_add_blob_fixed_as("fdt", ms->fdt, fdt_size, addr, + &address_space_memory); + qemu_register_reset_nosnapshotload( + qemu_fdt_randomize_seeds, + rom_ptr_for_as(&address_space_memory, addr, fdt_size)); +} + +static void hex_board_cpu_reset(void *opaque) +{ + cpu_reset(CPU(opaque)); +} + +void hex_board_create_cpus(MachineState *ms, bool have_start, uint64_t sta= rt) +{ + HexagonCommonMachineState *hms =3D HEXAGON_COMMON_MACHINE(ms); + g_autofree HexagonCPU **cpus =3D g_new(HexagonCPU *, ms->smp.cpus); + + for (int i =3D 0; i < ms->smp.cpus; i++) { + HexagonCPU *cpu =3D HEXAGON_CPU(object_new(ms->cpu_type)); + + qemu_register_reset(hex_board_cpu_reset, cpu); + if (i =3D=3D 0 && have_start) { + qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", start); + } + qdev_prop_set_uint32(DEVICE(cpu), "htid", i); + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", i !=3D 0); + hex_subsys_add_cpu(hms, DEVICE(cpu)); + cpus[i] =3D cpu; + } + + hex_subsys_realize_cluster(hms); + for (int i =3D 0; i < ms->smp.cpus; i++) { + hex_subsys_realize_cpu(hms, DEVICE(cpus[i]), i =3D=3D 0); + } +} diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index bb8a254fd26..63ee8836aca 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -7,12 +7,17 @@ config HEX_DSP select HEX_QTIMER select ARM_COMPATIBLE_SEMIHOSTING =20 -config HEX_VIRT +config HEX_BOARD bool - default y depends on HEX_DSP && FDT select DEVICE_TREE select VIRTIO_MMIO select PL011 + +config HEX_VIRT + bool + default y + depends on HEX_DSP && FDT + select HEX_BOARD select VIRTIO_BLK select VIRTIO_SCSI diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index c4b257dfa28..57bff31ad00 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -4,6 +4,7 @@ hexagon_ss.add(files('hexagon_globalreg.c')) hexagon_ss.add(files('hexagon_hvx_context.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hex-subsys.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) +hexagon_ss.add(when: 'CONFIG_HEX_BOARD', if_true: files('hex-board.c')) hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c')) =20 hw_arch +=3D {'hexagon': hexagon_ss} --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543451250158500 Build the virt machine with the hex-board helpers instead of its own copies, and drop the machine state that nothing used. The machine, its device tree and its devices are unchanged; virt writes interrupts as the bare line number. Signed-off-by: Brian Cain --- include/hw/hexagon/virt.h | 6 - hw/hexagon/virt.c | 309 ++++---------------------------------- 2 files changed, 26 insertions(+), 289 deletions(-) diff --git a/include/hw/hexagon/virt.h b/include/hw/hexagon/virt.h index 4ca2f1ef859..dc9f22a83c4 100644 --- a/include/hw/hexagon/virt.h +++ b/include/hw/hexagon/virt.h @@ -17,15 +17,9 @@ struct HexagonVirtMachineState { HexagonCommonMachineState parent_obj; =20 int fdt_size; - MemoryRegion *sys; MemoryRegion tcm; - MemoryRegion bios; - Clock *apb_clk; - DeviceState *virtio_mmio[VIRTIO_DEV_COUNT]; }; =20 -void hexagon_load_fdt(const struct HexagonVirtMachineState *vms); - #define TYPE_HEXAGON_VIRT_MACHINE MACHINE_TYPE_NAME("virt") OBJECT_DECLARE_SIMPLE_TYPE(HexagonVirtMachineState, HEXAGON_VIRT_MACHINE) =20 diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c index b601cd77a92..d8e91770595 100644 --- a/hw/hexagon/virt.c +++ b/hw/hexagon/virt.c @@ -8,26 +8,15 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/hexagon/virt.h" -#include "elf.h" -#include "hw/char/pl011.h" -#include "hw/core/clock.h" -#include "hw/core/sysbus-fdt.h" #include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hex-board.h" #include "hw/hexagon/hex-subsys.h" #include "hw/core/loader.h" -#include "hw/core/qdev-properties.h" -#include "hw/core/qdev-clock.h" -#include "hw/core/register.h" #include "qemu/error-report.h" -#include "qemu/guest-random.h" #include "qemu/target-info.h" #include "qemu/units.h" #include "machine_cfg_v68n_1024.h.inc" -#include "system/address-spaces.h" #include "system/device_tree.h" -#include "system/reset.h" -#include "system/system.h" -#include =20 enum { VIRT_UART0, @@ -49,222 +38,9 @@ static const MemMapEntry base_memmap[] =3D { }; =20 =20 -static void create_fdt(HexagonVirtMachineState *vms) -{ - MachineState *ms =3D MACHINE(vms); - void *fdt =3D create_device_tree(&vms->fdt_size); - uint8_t rng_seed[32]; - - if (!fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - - ms->fdt =3D fdt; - - qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); - qemu_fdt_setprop_string(fdt, "/", "model", "hexagon-virt,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "qcom,sm8150"); - - qemu_fdt_add_subnode(fdt, "/soc"); - qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); - qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); - - qemu_fdt_add_subnode(fdt, "/chosen"); - qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed= )); -} - -static int32_t fdt_add_l2vic(HexagonVirtMachineState *vms, - const struct hexagon_machine_config *m_cfg) -{ - MachineState *ms =3D MACHINE(vms); - int32_t l2vic_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); - char *nodename =3D g_strdup_printf("/soc/interrupt-controller@%x", - m_cfg->l2vic_base); - const char compat[] =3D "qcom,h2-pic\0hvm-pic"; - - qemu_fdt_setprop_cell(ms->fdt, "/soc", "interrupt-parent", l2vic_phand= le); - - qemu_fdt_add_subnode(ms->fdt, nodename); - qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x0); - qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 0x1); - qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compa= t)); - qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, - m_cfg->l2vic_base, m_cfg->l2vic_size); - qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", l2vic_phandle); - - g_free(nodename); - return l2vic_phandle; -} - -static void fdt_add_hvx(HexagonVirtMachineState *vms, - const struct hexagon_machine_config *m_cfg) -{ - const MachineState *ms =3D MACHINE(vms); - uint32_t vtcm_size_bytes =3D m_cfg->cfgtable.vtcm_size_kb * 1024; - if (vtcm_size_bytes > 0) { - qemu_fdt_add_subnode(ms->fdt, "/soc/vtcm"); - qemu_fdt_setprop_string(ms->fdt, "/soc/vtcm", "compatible", - "qcom,hexagon_vtcm"); - - assert(sizeof(m_cfg->cfgtable.vtcm_base) =3D=3D sizeof(uint32_t)); - qemu_fdt_setprop_cells(ms->fdt, "/soc/vtcm", "reg", 0, - m_cfg->cfgtable.vtcm_base << 16, - vtcm_size_bytes); - } - - if (m_cfg->cfgtable.ext_contexts > 0) { - qemu_fdt_add_subnode(ms->fdt, "/soc/hvx"); - qemu_fdt_setprop_string(ms->fdt, "/soc/hvx", "compatible", - "qcom,hexagon-hvx"); - qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-max-ctxts", - m_cfg->cfgtable.ext_contexts); - qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-vlength", - m_cfg->cfgtable.hvx_vec_log_length); - } -} - -static int32_t fdt_add_clocks(const HexagonVirtMachineState *vms) -{ - MachineState *ms =3D MACHINE(vms); - int32_t clk_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); - - qemu_fdt_add_subnode(ms->fdt, "/apb-pclk"); - qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "compatible", "fixed-clo= ck"); - qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "#clock-cells", 0x0); - qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "clock-frequency", 2400000= 0); - qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "clock-output-names", - "clk24mhz"); - qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "phandle", clk_phandle); - - return clk_phandle; -} - -static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart, - int32_t clk_phandle, int32_t l2vic_phandle) -{ - char *nodename; - hwaddr base =3D base_memmap[uart].base; - hwaddr size =3D base_memmap[uart].size; - assert(uart =3D=3D 0); - const char compat[] =3D "arm,pl011\0arm,primecell"; - const char clocknames[] =3D "uartclk\0apb_pclk"; - MachineState *ms =3D MACHINE(vms); - DeviceState *dev; - SysBusDevice *s; - - dev =3D qdev_new(TYPE_PL011); - s =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_chr(dev, "chardev", serial_hd(0)); - qdev_connect_clock_in(dev, "clk", vms->apb_clk); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, base); - sysbus_connect_irq(s, 0, - qdev_get_gpio_in(vms->parent_obj.l2vic, VIRT_UART0_= IRQ)); - - nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); - qemu_fdt_add_subnode(ms->fdt, nodename); - - /* Note that we can't use setprop_string because of the embedded NUL */ - qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compa= t)); - qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size); - qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", VIRT_UART0_IRQ); - qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", - l2vic_phandle); - qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", clk_phandle, - clk_phandle); - qemu_fdt_setprop(ms->fdt, nodename, "clock-names", clocknames, - sizeof(clocknames)); - - qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); - qemu_fdt_add_subnode(ms->fdt, "/aliases"); - qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); - - g_free(nodename); -} - -static void fdt_add_cpu_nodes(const HexagonVirtMachineState *vms) -{ - MachineState *ms =3D MACHINE(vms); - qemu_fdt_add_subnode(ms->fdt, "/cpus"); - qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); - - /* cpu nodes */ - for (int num =3D ms->smp.cpus - 1; num >=3D 0; num--) { - char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); - qemu_fdt_add_subnode(ms->fdt, nodename); - qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); - qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", - qemu_fdt_alloc_phandle(ms->fdt)); - g_free(nodename); - } -} - -static void create_virtio_devices(HexagonVirtMachineState *vms, - int32_t l2vic_phandle) -{ - MachineState *ms =3D MACHINE(vms); - hwaddr size =3D base_memmap[VIRT_MMIO].size; - - for (int i =3D 0; i < VIRTIO_DEV_COUNT; i++) { - int irq =3D VIRTIO_IRQ_BASE + i; - hwaddr base =3D base_memmap[VIRT_MMIO].base + i * size; - char *nodename =3D g_strdup_printf("/soc/virtio_mmio@%" PRIx64, ba= se); - DeviceState *dev =3D qdev_new("virtio-mmio"); - SysBusDevice *s =3D SYS_BUS_DEVICE(dev); - - object_property_add_child(OBJECT(MACHINE(vms)), "virtio-mmio[*]", - OBJECT(dev)); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, base); - sysbus_connect_irq(s, 0, - qdev_get_gpio_in(vms->parent_obj.l2vic, irq)); - vms->virtio_mmio[i] =3D dev; - - qemu_fdt_add_subnode(ms->fdt, nodename); - qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", - "virtio,mmio"); - qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size); - qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", irq); - qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", - l2vic_phandle); - - g_free(nodename); - } -} - -void hexagon_load_fdt(const HexagonVirtMachineState *vms) -{ - MachineState *ms =3D MACHINE(vms); - hwaddr fdt_addr =3D base_memmap[VIRT_FDT].base; - uint32_t fdtsize =3D vms->fdt_size; - - g_assert(fdtsize <=3D base_memmap[VIRT_FDT].size); - /* copy in the device tree */ - rom_add_blob_fixed_as("fdt", ms->fdt, fdtsize, fdt_addr, - &address_space_memory); - qemu_register_reset_nosnapshotload( - qemu_fdt_randomize_seeds, - rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); -} - static uint64_t load_kernel(const HexagonVirtMachineState *vms) { - MachineState *ms =3D MACHINE(vms); - uint64_t entry =3D 0; - if (load_elf_ram_sym(ms->kernel_filename, NULL, NULL, NULL, &entry, NU= LL, - NULL, NULL, 0, EM_HEXAGON, 0, 0, &address_space_m= emory, - false, NULL) > 0) { - return entry; - } - error_report("error loading '%s'", ms->kernel_filename); - exit(1); + return hex_board_load_elf(MACHINE(vms)->kernel_filename, NULL, NULL, N= ULL); } =20 static uint64_t load_bios(HexagonVirtMachineState *vms) @@ -283,75 +59,42 @@ static uint64_t load_bios(HexagonVirtMachineState *vms) return bios_addr; /* Return entry point at address 0x0 */ } =20 -static void do_cpu_reset(void *opaque) -{ - HexagonCPU *cpu =3D opaque; - CPUState *cs =3D CPU(cpu); - cpu_reset(cs); -} - static void virt_init(MachineState *ms) { HexagonVirtMachineState *vms =3D HEXAGON_VIRT_MACHINE(ms); const struct hexagon_machine_config *m_cfg =3D &v68n_1024; - int32_t clk_phandle; int32_t l2vic_phandle; + uint64_t start =3D 0; + bool have_start =3D false; =20 - create_fdt(vms); + hex_board_create_fdt(ms, "hexagon-virt,qemu", "qcom,sm8150", + &vms->fdt_size); qemu_fdt_setprop_string(ms->fdt, "/chosen", "bootargs", ms->kernel_cmd= line); =20 - vms->sys =3D get_system_memory(); - - /* Create APB clock for peripherals */ - vms->apb_clk =3D clock_new(OBJECT(ms), "apb-pclk"); - clock_set_hz(vms->apb_clk, 24000000); - hex_subsys_create(&vms->parent_obj, m_cfg, v68_rev); - - if (m_cfg->l2tcm_size) { - memory_region_init_ram(&vms->tcm, NULL, "tcm.ram", m_cfg->l2tcm_si= ze, - &error_fatal); - memory_region_add_subregion(vms->sys, m_cfg->cfgtable.l2tcm_base <= < 16, - &vms->tcm); - } - - fdt_add_hvx(vms, m_cfg); - - l2vic_phandle =3D fdt_add_l2vic(vms, m_cfg); - create_virtio_devices(vms, l2vic_phandle); - - g_autofree HexagonCPU **cpus =3D g_new(HexagonCPU *, ms->smp.cpus); - - for (int i =3D 0; i < ms->smp.cpus; i++) { - HexagonCPU *cpu =3D HEXAGON_CPU(object_new(ms->cpu_type)); - qemu_register_reset(do_cpu_reset, cpu); - - if (i =3D=3D 0) { - if (ms->kernel_filename) { - uint64_t entry =3D load_kernel(vms); - qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", entry= ); - } else if (ms->firmware) { - uint64_t entry =3D load_bios(vms); - qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", entry= ); - } - } - qdev_prop_set_uint32(DEVICE(cpu), "htid", i); - qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i !=3D 0)); - hex_subsys_add_cpu(&vms->parent_obj, DEVICE(cpu)); - cpus[i] =3D cpu; - } - - hex_subsys_realize_cluster(&vms->parent_obj); - - for (int i =3D 0; i < ms->smp.cpus; i++) { - hex_subsys_realize_cpu(&vms->parent_obj, DEVICE(cpus[i]), (i =3D= =3D 0)); + hex_board_create_tcm(m_cfg, &vms->tcm); + hex_board_fdt_add_hvx(ms, m_cfg); + + l2vic_phandle =3D hex_board_fdt_add_l2vic(ms, m_cfg); + hex_board_create_virtio(ms, base_memmap[VIRT_MMIO].base, + base_memmap[VIRT_MMIO].size, VIRTIO_IRQ_BASE, + VIRTIO_DEV_COUNT, l2vic_phandle); + + if (ms->kernel_filename) { + start =3D load_kernel(vms); + have_start =3D true; + } else if (ms->firmware) { + start =3D load_bios(vms); + have_start =3D true; } + hex_board_create_cpus(ms, have_start, start); =20 - fdt_add_cpu_nodes(vms); - clk_phandle =3D fdt_add_clocks(vms); - fdt_add_uart(vms, VIRT_UART0, clk_phandle, l2vic_phandle); + hex_board_fdt_add_cpus(ms); + hex_board_create_uart(ms, base_memmap[VIRT_UART0].base, + base_memmap[VIRT_UART0].size, VIRT_UART0_IRQ, + l2vic_phandle); =20 - hexagon_load_fdt(vms); + hex_board_load_fdt(ms, vms->fdt_size, base_memmap[VIRT_FDT].base); } =20 =20 --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792543466; cv=none; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543467675158500 Firmware brings a Hexagon DSP's clocks up by programming a PLL and polling its lock-detect. Then it asks the RCG to switch to the new clock. Signed-off-by: Brian Cain --- MAINTAINERS | 2 + include/hw/misc/qcom-qdsp6ss-clk.h | 15 +++ hw/misc/qcom-qdsp6ss-clk.c | 208 +++++++++++++++++++++++++++++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 3 + 5 files changed, 231 insertions(+) create mode 100644 include/hw/misc/qcom-qdsp6ss-clk.h create mode 100644 hw/misc/qcom-qdsp6ss-clk.c diff --git a/MAINTAINERS b/MAINTAINERS index 7c14d006f64..794fd79d7d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1380,7 +1380,9 @@ M: Brian Cain R: Pierrick Bouvier S: Supported F: hw/hexagon/ +F: hw/misc/qcom-qdsp6ss-clk.c F: include/hw/hexagon/ +F: include/hw/misc/qcom-qdsp6ss-clk.h F: configs/devices/hexagon-softmmu/default.mak F: docs/system/hexagon/ F: tests/functional/hexagon/ diff --git a/include/hw/misc/qcom-qdsp6ss-clk.h b/include/hw/misc/qcom-qdsp= 6ss-clk.h new file mode 100644 index 00000000000..9e3c58b5726 --- /dev/null +++ b/include/hw/misc/qcom-qdsp6ss-clk.h @@ -0,0 +1,15 @@ +/* + * Qualcomm QDSP6SS clock blocks: the Lucid alpha PLL and the root clock + * generator that firmware programs while bringing a Hexagon DSP up. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_QCOM_QDSP6SS_CLK_H +#define HW_MISC_QCOM_QDSP6SS_CLK_H + +#define TYPE_QCOM_LUCID_PLL "qcom-lucid-pll" +#define TYPE_QCOM_RCG "qcom-rcg" + +#endif /* HW_MISC_QCOM_QDSP6SS_CLK_H */ diff --git a/hw/misc/qcom-qdsp6ss-clk.c b/hw/misc/qcom-qdsp6ss-clk.c new file mode 100644 index 00000000000..5c9b55e0568 --- /dev/null +++ b/hw/misc/qcom-qdsp6ss-clk.c @@ -0,0 +1,208 @@ +/* + * Qualcomm QDSP6SS clock blocks + * + * Firmware brings the DSP's PLLs up by programming them, releasing reset, + * selecting the RUN mode and then polling for lock; it then asks the root + * clock generator to switch over to the new clock by setting UPDATE and + * waiting for the hardware to clear it. Neither the frequencies nor the + * clock tree matter to the model: these devices only complete those + * handshakes, and otherwise hold whatever is written to them. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/resettable.h" +#include "hw/core/sysbus.h" +#include "hw/misc/qcom-qdsp6ss-clk.h" +#include "migration/vmstate.h" +#include "qom/object.h" + +#define QCOM_CLK_REGS_SIZE 0x1000 +#define QCOM_CLK_NUM_REGS (QCOM_CLK_REGS_SIZE / 4) + +/* Lucid PLL registers */ +#define PLL_MODE 0x00 +#define PLL_OPMODE 0x38 + +#define PLL_MODE_OUTCTRL BIT(0) +#define PLL_MODE_BYPASSNL BIT(1) +#define PLL_MODE_RESET_N BIT(2) +#define PLL_MODE_ACTIVE BIT(30) +#define PLL_MODE_LOCK_DET BIT(31) + +#define PLL_OPMODE_MASK 0x7 +#define PLL_OPMODE_RUN 0x1 + +/* RCG registers */ +#define RCG_CMD 0x20 + +#define RCG_CMD_UPDATE BIT(0) +#define RCG_CMD_ROOT_EN BIT(1) +#define RCG_CMD_ROOT_OFF BIT(31) + +typedef struct QcomClkRegsState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t regs[QCOM_CLK_NUM_REGS]; +} QcomClkRegsState; + +#define TYPE_QCOM_CLK_REGS "qcom-clk-regs" +OBJECT_DECLARE_SIMPLE_TYPE(QcomClkRegsState, QCOM_CLK_REGS) + +static uint64_t qcom_clk_read(void *opaque, hwaddr offset, unsigned size) +{ + QcomClkRegsState *s =3D opaque; + + return s->regs[offset / 4]; +} + +static void qcom_lucid_pll_write(void *opaque, hwaddr offset, uint64_t val= ue, + unsigned size) +{ + QcomClkRegsState *s =3D opaque; + + s->regs[offset / 4] =3D value; + if (offset =3D=3D PLL_MODE || offset =3D=3D PLL_OPMODE) { + uint32_t mode =3D s->regs[PLL_MODE / 4]; + uint32_t opmode =3D s->regs[PLL_OPMODE / 4]; + + /* The PLL locks once it is out of reset and running */ + if ((mode & PLL_MODE_RESET_N) && + (opmode & PLL_OPMODE_MASK) =3D=3D PLL_OPMODE_RUN) { + mode |=3D PLL_MODE_LOCK_DET | PLL_MODE_ACTIVE; + } else { + mode &=3D ~(PLL_MODE_LOCK_DET | PLL_MODE_ACTIVE); + } + s->regs[PLL_MODE / 4] =3D mode; + } +} + +static void qcom_rcg_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + QcomClkRegsState *s =3D opaque; + + s->regs[offset / 4] =3D value; + if (offset =3D=3D RCG_CMD) { + /* The update completes at once; the root is on if it was enabled = */ + value &=3D ~(RCG_CMD_UPDATE | RCG_CMD_ROOT_OFF); + if (!(value & RCG_CMD_ROOT_EN)) { + value |=3D RCG_CMD_ROOT_OFF; + } + s->regs[RCG_CMD / 4] =3D value; + } +} + +static const MemoryRegionOps qcom_lucid_pll_ops =3D { + .read =3D qcom_clk_read, + .write =3D qcom_lucid_pll_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static const MemoryRegionOps qcom_rcg_ops =3D { + .read =3D qcom_clk_read, + .write =3D qcom_rcg_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void qcom_clk_realize(DeviceState *dev, const MemoryRegionOps *ops, + const char *name) +{ + QcomClkRegsState *s =3D QCOM_CLK_REGS(dev); + + memory_region_init_io(&s->iomem, OBJECT(dev), ops, s, name, + QCOM_CLK_REGS_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); +} + +static void qcom_lucid_pll_realize(DeviceState *dev, Error **errp) +{ + qcom_clk_realize(dev, &qcom_lucid_pll_ops, TYPE_QCOM_LUCID_PLL); +} + +static void qcom_rcg_realize(DeviceState *dev, Error **errp) +{ + qcom_clk_realize(dev, &qcom_rcg_ops, TYPE_QCOM_RCG); +} + +static void qcom_clk_reset_hold(Object *obj, ResetType type) +{ + QcomClkRegsState *s =3D QCOM_CLK_REGS(obj); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static const VMStateDescription vmstate_qcom_clk =3D { + .name =3D "qcom-qdsp6ss-clk", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, QcomClkRegsState, QCOM_CLK_NUM_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void qcom_clk_regs_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->vmsd =3D &vmstate_qcom_clk; + RESETTABLE_CLASS(oc)->phases.hold =3D qcom_clk_reset_hold; +} + +static void qcom_lucid_pll_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D qcom_lucid_pll_realize; + dc->desc =3D "Qualcomm Lucid alpha PLL"; +} + +static void qcom_rcg_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D qcom_rcg_realize; + dc->desc =3D "Qualcomm root clock generator"; +} + +static const TypeInfo qcom_qdsp6ss_clk_types[] =3D { + { + .name =3D TYPE_QCOM_CLK_REGS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(QcomClkRegsState), + .class_init =3D qcom_clk_regs_class_init, + .abstract =3D true, + }, + { + .name =3D TYPE_QCOM_LUCID_PLL, + .parent =3D TYPE_QCOM_CLK_REGS, + .class_init =3D qcom_lucid_pll_class_init, + }, + { + .name =3D TYPE_QCOM_RCG, + .parent =3D TYPE_QCOM_CLK_REGS, + .class_init =3D qcom_rcg_class_init, + }, +}; + +DEFINE_TYPES(qcom_qdsp6ss_clk_types) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 7abd22869a4..363930230b4 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -267,3 +267,6 @@ config SOPHGO_CV1800B_CLK bool =20 source macio/Kconfig + +config QCOM_QDSP6SS_CLK + bool diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 8a94aba751d..2b437f53d6a 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -179,3 +179,6 @@ system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('= sbsa_ec.c')) system_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c')) =20 system_ss.add(when: 'CONFIG_AXIADO_CLK', if_true: files('axiado_clk.c')) + +# Qualcomm Hexagon DSP subsystems +system_ss.add(when: 'CONFIG_QCOM_QDSP6SS_CLK', if_true: files('qcom-qdsp6s= s-clk.c')) --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543376043158501 Signed-off-by: Brian Cain Reviewed-by: Anton Johansson --- MAINTAINERS | 1 + include/hw/hexagon/hexagon.h | 1 + include/hw/hexagon/qcom_dsp.h | 81 +++++ hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc | 65 ++++ hw/hexagon/qcom_dsp.c | 410 ++++++++++++++++++++++ hw/hexagon/qcs6490_cdsp.c | 64 ++++ tests/qtest/l2vic-test.c | 2 + tests/qtest/qcom-dsp-test.c | 93 +++++ tests/qtest/qct-qtimer-test.c | 2 + hw/hexagon/Kconfig | 15 + hw/hexagon/meson.build | 2 + tests/qtest/meson.build | 3 +- 12 files changed, 738 insertions(+), 1 deletion(-) create mode 100644 include/hw/hexagon/qcom_dsp.h create mode 100644 hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc create mode 100644 hw/hexagon/qcom_dsp.c create mode 100644 hw/hexagon/qcs6490_cdsp.c create mode 100644 tests/qtest/qcom-dsp-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 794fd79d7d9..9449e66d33b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1386,6 +1386,7 @@ F: include/hw/misc/qcom-qdsp6ss-clk.h F: configs/devices/hexagon-softmmu/default.mak F: docs/system/hexagon/ F: tests/functional/hexagon/ +F: tests/qtest/qcom-dsp-test.c F: docs/devel/hexagon-sys.rst =20 LoongArch Machines diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 6955e600aee..1d0d55ea938 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -23,6 +23,7 @@ typedef enum { v66_rev =3D 0xa666, v67_rev =3D 0x2667, v68_rev =3D 0x8d68, + v68_qcs6490_rev =3D 0x8a68, v69_rev =3D 0x8c69, v71_rev =3D 0x8c71, v73_rev =3D 0x8c73, diff --git a/include/hw/hexagon/qcom_dsp.h b/include/hw/hexagon/qcom_dsp.h new file mode 100644 index 00000000000..d127b0b0b10 --- /dev/null +++ b/include/hw/hexagon/qcom_dsp.h @@ -0,0 +1,81 @@ +/* + * Qualcomm DSP subsystem machines: the board layer shared by the SoC mode= ls. + * + * Each SoC provides a QcomDspMachineInfo describing its subsystem, and the + * layer supplies what every one of them has in common: the CPUs, a QEMU-o= nly + * PL011 console, virtio-mmio slots, a generated device tree, and the + * -bios/-kernel/-initrd boot flow. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_HEXAGON_QCOM_DSP_H +#define HW_HEXAGON_QCOM_DSP_H + +#include "hw/hexagon/hexagon.h" +#include "qom/object.h" + +#define TYPE_QCOM_DSP_MACHINE MACHINE_TYPE_NAME("qcom-dsp") +OBJECT_DECLARE_TYPE(QcomDspMachineState, QcomDspMachineClass, QCOM_DSP_MAC= HINE) + +/* Number of virtio-mmio transports every machine provides. */ +#define QCOM_DSP_VIRTIO_COUNT 8 + +typedef struct QcomDspMachineInfo { + const char *desc; + const char *cpu_type; + unsigned int cpus; + Rev_t rev; + const struct hexagon_machine_config *cfg; + /* Where the H2 loadlinux of this SoC expects to find the Linux kernel= . */ + hwaddr kernel_addr; + /* Add the devices that are specific to this SoC; may be NULL. */ + void (*init_devices)(MachineState *ms); +} QcomDspMachineInfo; + +struct QcomDspMachineState { + HexagonCommonMachineState parent_obj; + + MemoryRegion tcm; + MemoryRegion l2_ecc; + int fdt_size; + hwaddr fdt_addr; + char *firmware_path; +}; + +struct QcomDspMachineClass { + MachineClass parent_class; + + const QcomDspMachineInfo *info; +}; + +/* Describes a register window the machine stubs out as unimplemented. */ +typedef struct QcomDspRegion { + const char *name; + hwaddr base; + /* Zero means one 4 KiB page. */ + hwaddr size; +} QcomDspRegion; + +/* + * Stub out register windows the guest may probe, named + * ".@". + */ +void qcom_dsp_add_regions(MachineState *ms, const QcomDspRegion *regions, + unsigned int count); + +/* Create the sysbus device @type and map it at @base. */ +void qcom_dsp_add_device(const char *type, hwaddr base); + +/* + * Stub out @ports consecutive QUP GENI serial engines of @size bytes. Th= ey + * belong to the SoC @soc rather than to the DSP. + */ +void qcom_soc_add_qup_geni_ports(const char *soc, hwaddr base, + unsigned int ports, hwaddr size); + +/* Class init for a machine type whose class_data is a QcomDspMachineInfo.= */ +void qcom_dsp_class_init(ObjectClass *oc, const void *data); + +#endif /* HW_HEXAGON_QCOM_DSP_H */ diff --git a/hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc b/hw/hexagon/machine= _cfg_qcs6490_cdsp.h.inc new file mode 100644 index 00000000000..11302da2238 --- /dev/null +++ b/hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config qcs6490_cdsp =3D { + .ddr_base =3D 0x80000000, + .cfgbase =3D 0x09980000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0x0a390000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0x0a3a0000, + .qtmr_region =3D 0x0a3a1000, + .cfgtable =3D { + .l2tcm_base =3D 0x00000980, + .reserved0 =3D 0x00000000, + .subsystem_base =3D 0x00000a38, + .etm_base =3D 0x00000999, + .l2cfg_base =3D 0x0000099a, + .reserved1 =3D 0x0000099b, + .l1s0_base =3D 0x000009c0, + .axi2_lowaddr =3D 0x00000000, + .streamer_base =3D 0x0000099c, + .reserved2 =3D 0x0000099d, + .fastl2vic_base =3D 0x0000099e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x00000001, + .ext_contexts =3D 0x00000002, + .vtcm_base =3D 0x000009c0, + .vtcm_size_kb =3D 0x00000800, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x0000003f, + .eccreg_base =3D 0x0000099f, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x00000980, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000001, + .hvx_vec_log_length =3D 0x00000007, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000040, + .coproc2_reg1 =3D 0x00000020, + .v2x_mode =3D 0x00000001, + .coproc2_reg2 =3D 0x00000002, + .coproc2_reg3 =3D 0x00000000, + .coproc2_reg4 =3D 0x00000000, + .coproc2_reg5 =3D 0x00000000, + .coproc2_reg6 =3D 0x00000000, + .coproc2_reg7 =3D 0x00000000, + .acd_preset =3D 0x00000001, + .mnd_preset =3D 0x00000001, + .l1d_size_kb =3D 0x00000010, + .l1i_size_kb =3D 0x00000020, + .l1d_write_policy =3D 0x00000002, + .vtcm_bank_width =3D 0x00000040, + .reserved4 =3D 0x00000001, + .reserved5 =3D 0x00000000, + .reserved6 =3D 0x00000000, + .coproc2_cvt_mpy_size =3D 0x0000000a, + .consistency_domain =3D 0x00000000, + .capacity_domain =3D 0x00000000, + .axi3_lowaddr =3D 0x00000000, + }, +}; diff --git a/hw/hexagon/qcom_dsp.c b/hw/hexagon/qcom_dsp.c new file mode 100644 index 00000000000..a78445132a6 --- /dev/null +++ b/hw/hexagon/qcom_dsp.c @@ -0,0 +1,410 @@ +/* + * DSP subsystem machines: the board layer shared by the SoC models. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/core/boards.h" +#include "hw/core/loader.h" +#include "hw/core/sysbus.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hex-board.h" +#include "hw/hexagon/hex-subsys.h" +#include "hw/hexagon/qcom_dsp.h" +#include "hw/misc/unimp.h" +#include "qemu/datadir.h" +#include "qemu/error-report.h" +#include "qemu/units.h" +#include "system/address-spaces.h" +#include "system/device_tree.h" + +enum { + QCOM_DSP_UART0, + QCOM_DSP_VIRTIO, + QCOM_DSP_GPT, + QCOM_DSP_BOOT, +}; + +static const MemMapEntry qcom_dsp_memmap[] =3D { + [QCOM_DSP_UART0] =3D { 0x37000000, 0x00001000 }, + [QCOM_DSP_VIRTIO] =3D { 0x37010000, 0x00001000 }, + /* Not a device: the window the kernel's H2 timer driver binds to. */ + [QCOM_DSP_GPT] =3D { 0xab000000, 0x00001000 }, + [QCOM_DSP_BOOT] =3D { 0x99c00000, 0x00000200 }, +}; + +static const int QCOM_DSP_UART0_IRQ =3D 15; +/* Virtio IRQs run from QCOM_DSP_VIRTIO_IRQ to QCOM_DSP_VIRTIO_IRQ + 7 */ +static const int QCOM_DSP_VIRTIO_IRQ =3D 96; +static const int QCOM_DSP_GPT_IRQ =3D 12; + +#define QCOM_DSP_L2_ECC_SIZE 0x1000 + +#define QCOM_DSP_MAX_KERNEL_RAM (896 * MiB) + +static const uint32_t bootloader[] =3D { + /* Load fdt_base_low value into r0: */ + 0x099c4000, /* { immext(#0x99c00000) */ + 0x7800c606, /* r6 =3D ##-0x662fffd0 } */ + 0x9186c000, /* { r0 =3D memw(r6+#0x0) } */ + + /* Load fdt_base_high value into r1: */ + 0x099c4000, /* { immext(#0x99c00000) */ + 0x7800c586, /* r6 =3D ##-0x662fffd4 } */ + 0x9186c001, /* { r1 =3D memw(r6+#0x0) } */ + + /* Load next_stage_entry value into r7: */ + 0x099c4000, /* { immext(#0x99c00000) */ + 0x7800c687, /* r7 =3D ##-0x662fffcc } */ + 0x9187c007, /* { r7 =3D memw(r7+#0x0) } */ + + /* Jump to next_stage_entry, r1:0 now contains fdt_base: */ + 0x5287c000, /* { jumpr r7 } */ + 0x0, /* Invalid packet */ + 0x0, /* Pad for fdt_base_high */ + 0x0, /* Pad for fdt_base_low */ + 0x0, /* Pad for next_stage_entry */ +}; + +enum { + FDT_HI =3D 11, + FDT_LO, + ENTRY_ADDR, +}; + +static const QcomDspMachineInfo *qcom_dsp_info(MachineState *ms) +{ + return QCOM_DSP_MACHINE_GET_CLASS(ms)->info; +} + +void qcom_dsp_add_regions(MachineState *ms, const QcomDspRegion *regions, + unsigned int count) +{ + const char *machine =3D MACHINE_GET_CLASS(ms)->name; + + for (unsigned int i =3D 0; i < count; i++) { + g_autofree char *name =3D g_strdup_printf("%s.%s@%" HWADDR_PRIx, m= achine, + regions[i].name, + regions[i].base); + + create_unimplemented_device(name, regions[i].base, + regions[i].size ? regions[i].size : 0x= 1000); + } +} + +void qcom_dsp_add_device(const char *type, hwaddr base) +{ + DeviceState *dev =3D qdev_new(type); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); +} + +void qcom_soc_add_qup_geni_ports(const char *soc, hwaddr base, + unsigned int ports, hwaddr size) +{ + for (unsigned int i =3D 0; i < ports; i++) { + g_autofree char *name =3D g_strdup_printf("%s.qup-geni@%" HWADDR_P= RIx, + soc, base + i * size); + + create_unimplemented_device(name, base + i * size, size); + } +} + +/* + * The firmware programs the L2 ECC registers and polls them until what it + * wrote reads back, so they need to hold state. + */ +static void qcom_dsp_add_l2_ecc_regs(QcomDspMachineState *qms, + const QcomDspMachineInfo *info) +{ + hwaddr base =3D (hwaddr)info->cfg->cfgtable.eccreg_base << 16; + + if (!base) { + return; + } + memory_region_init_ram(&qms->l2_ecc, NULL, "l2-ecc-regs", + QCOM_DSP_L2_ECC_SIZE, &error_fatal); + memory_region_add_subregion(get_system_memory(), base, &qms->l2_ecc); +} + +static void qcom_dsp_create_fdt(QcomDspMachineState *qms) +{ + MachineState *ms =3D MACHINE(qms); + g_autofree char *compatible =3D g_strdup_printf("qcom,%s", + MACHINE_GET_CLASS(ms)->name); + + hex_board_create_fdt(ms, MACHINE_GET_CLASS(ms)->desc, compatible, + &qms->fdt_size); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); +} + +/* + * The H2 hypervisor provides the guest timer through hypercalls, so this + * node only tells the kernel's timer driver which interrupt to expect. + */ +static void qcom_dsp_fdt_add_gpt(MachineState *ms) +{ + static const char compat[] =3D "qcom,h2-timer\0hvm-timer"; + g_autofree char *name =3D g_strdup_printf("/soc/gpt@%" PRIx64, + qcom_dsp_memmap[QCOM_DSP_GPT].= base); + + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop(ms->fdt, name, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", QCOM_DSP_GPT_IRQ, = 0); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, + qcom_dsp_memmap[QCOM_DSP_GPT].base, + qcom_dsp_memmap[QCOM_DSP_GPT].size); +} + +static void qcom_dsp_fdt_add_memory(MachineState *ms) +{ + hwaddr kernel_addr =3D qcom_dsp_info(ms)->kernel_addr; + hwaddr ram_end =3D qcom_dsp_info(ms)->cfg->ddr_base + ms->ram_size; + hwaddr size =3D MIN(ram_end - kernel_addr, QCOM_DSP_MAX_KERNEL_RAM); + g_autofree char *nodename =3D g_strdup_printf("/memory@%" HWADDR_PRIx, + kernel_addr); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, kernel_addr, + size); +} + +static uint64_t qcom_dsp_kernel_translate(void *opaque, uint64_t addr) +{ + return addr + qcom_dsp_info(MACHINE(opaque))->kernel_addr; +} + +static uint64_t qcom_dsp_load_kernel(MachineState *ms, bool through_firmwa= re, + hwaddr *image_high) +{ + return hex_board_load_elf(ms->kernel_filename, + through_firmware ? qcom_dsp_kernel_translate + : NULL, + ms, image_high); +} + +static uint64_t qcom_dsp_load_firmware(QcomDspMachineState *qms) +{ + return hex_board_load_elf(qms->firmware_path, NULL, NULL, NULL); +} + +/* + * Place the FDT after the kernel image, inside the RAM window the kernel + * maps, and the initrd after that. + */ +static void qcom_dsp_load_initrd(QcomDspMachineState *qms) +{ + MachineState *ms =3D MACHINE(qms); + hwaddr start =3D qms->fdt_addr + 4 * MiB; + hwaddr ram_end =3D qcom_dsp_info(ms)->cfg->ddr_base + ms->ram_size; + hwaddr available; + ssize_t size; + + available =3D qms->fdt_addr < ram_end ? ram_end - qms->fdt_addr : 0; + if (qms->fdt_size > available) { + error_report("no room for the FDT (size 0x%x): only 0x%" HWADDR_PR= Ix + " bytes available at 0x%" HWADDR_PRIx, + qms->fdt_size, available, qms->fdt_addr); + exit(1); + } + + if (!ms->initrd_filename) { + return; + } + + if (start >=3D ram_end) { + error_report("no room for the initrd: RAM ends at 0x%" HWADDR_PRIx + " but the initrd would start at 0x%" HWADDR_PRIx, + ram_end, start); + exit(1); + } + + size =3D load_image_targphys_as(ms->initrd_filename, start, ram_end - = start, + &address_space_memory, &error_fatal); + + qemu_fdt_setprop_u64(ms->fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_u64(ms->fdt, "/chosen", "linux,initrd-end", start + s= ize); +} + +/* + * A boot stub that passes the FDT address to the firmware in r1:r0, then + * jumps to the firmware's entry point. + */ +static uint64_t qcom_dsp_setup_boot_stub(QcomDspMachineState *qms, + uint64_t firmware_entry) +{ + hwaddr bootl_base =3D qcom_dsp_memmap[QCOM_DSP_BOOT].base; + uint32_t stub[ARRAY_SIZE(bootloader)]; + + for (size_t i =3D 0; i < ARRAY_SIZE(stub); i++) { + stub[i] =3D cpu_to_le32(bootloader[i]); + } + stub[FDT_LO] =3D cpu_to_le32(extract64(qms->fdt_addr, 0, 32)); + stub[FDT_HI] =3D cpu_to_le32(extract64(qms->fdt_addr, 32, 32)); + stub[ENTRY_ADDR] =3D cpu_to_le32(extract64(firmware_entry, 0, 32)); + + g_assert(sizeof(stub) <=3D qcom_dsp_memmap[QCOM_DSP_BOOT].size); + rom_add_blob_fixed_as("bootloader", stub, sizeof(stub), bootl_base, + &address_space_memory); + + return bootl_base; +} + +/* Reject boot options that do not make sense together, and find -bios. */ +static void qcom_dsp_check_boot_options(QcomDspMachineState *qms) +{ + MachineState *ms =3D MACHINE(qms); + hwaddr ddr_base =3D qcom_dsp_info(ms)->cfg->ddr_base; + hwaddr kernel_addr =3D qcom_dsp_info(ms)->kernel_addr; + + if (ms->firmware) { + qms->firmware_path =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, ms->fir= mware); + if (!qms->firmware_path) { + error_report("Could not find firmware '%s'", ms->firmware); + exit(1); + } + } + + if (ms->initrd_filename && !(ms->kernel_filename && qms->firmware_path= )) { + error_report("-initrd needs both -kernel and the H2 loadlinux " + "firmware given with -bios"); + exit(1); + } + + if (ms->kernel_filename && qms->firmware_path && + (ddr_base > qcom_dsp_memmap[QCOM_DSP_BOOT].base || + ddr_base + ms->ram_size <=3D kernel_addr)) { + error_report("RAM (%" PRIu64 " MiB at 0x%" HWADDR_PRIx ") is too " + "small: the kernel is loaded at 0x%" HWADDR_PRIx, + ms->ram_size / MiB, ddr_base, kernel_addr); + exit(1); + } +} + +/* Load what -bios and -kernel name and return where CPU 0 starts, if know= n. */ +static bool qcom_dsp_load_images(QcomDspMachineState *qms, uint64_t *start) +{ + MachineState *ms =3D MACHINE(qms); + hwaddr image_high =3D 0; + + if (ms->kernel_filename && qms->firmware_path) { + uint64_t firmware_entry =3D qcom_dsp_load_firmware(qms); + + qcom_dsp_load_kernel(ms, true, &image_high); + qms->fdt_addr =3D QEMU_ALIGN_UP(image_high + 16 * MiB, 4 * MiB); + qcom_dsp_load_initrd(qms); + *start =3D qcom_dsp_setup_boot_stub(qms, firmware_entry); + return true; + } + if (ms->kernel_filename) { + *start =3D qcom_dsp_load_kernel(ms, false, &image_high); + return true; + } + if (qms->firmware_path) { + *start =3D qcom_dsp_load_firmware(qms); + return true; + } + return false; +} + +static void qcom_dsp_init(MachineState *ms) +{ + QcomDspMachineState *qms =3D QCOM_DSP_MACHINE(ms); + HexagonCommonMachineState *hms =3D HEXAGON_COMMON_MACHINE(ms); + const QcomDspMachineInfo *info =3D qcom_dsp_info(ms); + int32_t l2vic_phandle; + uint64_t start =3D 0; + bool have_start; + + qcom_dsp_check_boot_options(qms); + qcom_dsp_create_fdt(qms); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "bootargs", ms->kernel_cmd= line); + + hex_subsys_create(hms, info->cfg, info->rev); + hex_board_create_tcm(info->cfg, &qms->tcm); + + hex_board_fdt_add_hvx(ms, info->cfg); + l2vic_phandle =3D hex_board_fdt_add_l2vic(ms, info->cfg); + qcom_dsp_fdt_add_gpt(ms); + /* loadlinux gives the kernel a virtual CPU for every thread that runs= . */ + hex_board_fdt_add_cpus(ms); + if (ms->kernel_filename && qms->firmware_path) { + qcom_dsp_fdt_add_memory(ms); + } + hex_board_create_uart(ms, qcom_dsp_memmap[QCOM_DSP_UART0].base, + qcom_dsp_memmap[QCOM_DSP_UART0].size, + QCOM_DSP_UART0_IRQ, l2vic_phandle); + hex_board_create_virtio(ms, qcom_dsp_memmap[QCOM_DSP_VIRTIO].base, + qcom_dsp_memmap[QCOM_DSP_VIRTIO].size, + QCOM_DSP_VIRTIO_IRQ, QCOM_DSP_VIRTIO_COUNT, + l2vic_phandle); + qcom_dsp_add_l2_ecc_regs(qms, info); + if (info->init_devices) { + info->init_devices(ms); + } + + if (ms->dtb) { + g_free(ms->fdt); + ms->fdt =3D load_device_tree(ms->dtb, &qms->fdt_size); + if (!ms->fdt) { + error_report("could not load device tree '%s'", ms->dtb); + exit(1); + } + if (ms->kernel_cmdline && *ms->kernel_cmdline) { + qemu_fdt_setprop_string(ms->fdt, "/chosen", "bootargs", + ms->kernel_cmdline); + } + } + + have_start =3D qcom_dsp_load_images(qms, &start); + hex_board_create_cpus(ms, have_start, start); + + if (ms->kernel_filename && qms->firmware_path) { + hex_board_load_fdt(ms, qms->fdt_size, qms->fdt_addr); + } +} + +static void qcom_dsp_base_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D qcom_dsp_init; + mc->default_ram_size =3D 1 * GiB; + mc->is_default =3D false; + mc->block_default_type =3D IF_VIRTIO; + mc->no_cdrom =3D true; + mc->no_floppy =3D true; + mc->no_parallel =3D true; + mc->numa_mem_supported =3D false; +} + +void qcom_dsp_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + QcomDspMachineClass *qc =3D QCOM_DSP_MACHINE_CLASS(oc); + const QcomDspMachineInfo *info =3D data; + + qc->info =3D info; + mc->desc =3D info->desc; + mc->default_cpu_type =3D info->cpu_type; + mc->default_cpus =3D info->cpus; + mc->max_cpus =3D info->cpus; +} + +static const TypeInfo qcom_dsp_types[] =3D { + { + .name =3D TYPE_QCOM_DSP_MACHINE, + .parent =3D TYPE_HEXAGON_COMMON_MACHINE, + .instance_size =3D sizeof(QcomDspMachineState), + .class_size =3D sizeof(QcomDspMachineClass), + .class_init =3D qcom_dsp_base_class_init, + .abstract =3D true, + }, +}; + +DEFINE_TYPES(qcom_dsp_types) diff --git a/hw/hexagon/qcs6490_cdsp.c b/hw/hexagon/qcs6490_cdsp.c new file mode 100644 index 00000000000..fe255640c49 --- /dev/null +++ b/hw/hexagon/qcs6490_cdsp.c @@ -0,0 +1,64 @@ +/* + * QCS6490 CDSP machine. + * + * Models the Hexagon v68 CDSP subsystem of the QCS6490/SM7325. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/qcom_dsp.h" +#include "hw/misc/qcom-qdsp6ss-clk.h" +#include "hw/misc/unimp.h" +#include "qapi/error.h" +#include "system/address-spaces.h" +#include "target/hexagon/cpu.h" + +#include "machine_cfg_qcs6490_cdsp.h.inc" + +#define TYPE_QCS6490_CDSP_MACHINE MACHINE_TYPE_NAME("qcs6490-cdsp") + +#define QCS6490_CFGSPACE_BASE 0x09990000 +#define QCS6490_CFGSPACE_SIZE 0x00070000 + +static const QcomDspRegion qcs6490_regions[] =3D { + { "ss-csr", 0x0a380000, 0x10000 }, +}; + +static void qcs6490_cdsp_init_devices(MachineState *ms) +{ + MemoryRegion *cfgspace =3D g_new(MemoryRegion, 1); + + memory_region_init_ram(cfgspace, NULL, "cfgspace.ram", + QCS6490_CFGSPACE_SIZE, &error_fatal); + memory_region_add_subregion_overlap(get_system_memory(), + QCS6490_CFGSPACE_BASE, cfgspace, -= 1); + qcom_dsp_add_regions(ms, qcs6490_regions, ARRAY_SIZE(qcs6490_regions)); + qcom_dsp_add_device(TYPE_QCOM_LUCID_PLL, 0x0a001000); + qcom_dsp_add_device(TYPE_QCOM_LUCID_PLL, 0x0a340000); + qcom_dsp_add_device(TYPE_QCOM_RCG, 0x0a341000); +} + +static const QcomDspMachineInfo qcs6490_cdsp_info =3D { + .desc =3D "QCS6490 CDSP", + .cpu_type =3D HEXAGON_CPU_TYPE_NAME("v68"), + .cpus =3D 6, + .rev =3D v68_qcs6490_rev, + .cfg =3D &qcs6490_cdsp, + .kernel_addr =3D 0xa1000000, + .init_devices =3D qcs6490_cdsp_init_devices, +}; + +static const TypeInfo qcs6490_cdsp_types[] =3D { + { + .name =3D TYPE_QCS6490_CDSP_MACHINE, + .parent =3D TYPE_QCOM_DSP_MACHINE, + .class_init =3D qcom_dsp_class_init, + .class_data =3D &qcs6490_cdsp_info, + }, +}; + +DEFINE_TYPES(qcs6490_cdsp_types) diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c index adb4dc7281e..2e0d7dcb0f1 100644 --- a/tests/qtest/l2vic-test.c +++ b/tests/qtest/l2vic-test.c @@ -11,6 +11,7 @@ =20 #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" +#include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" =20 /* L2VIC register offsets exercised by this test */ #define L2VIC_INT_ENABLEn 0x100 /* Read/Write */ @@ -45,6 +46,7 @@ typedef struct { static const L2VICMachineCfg l2vic_machines[] =3D { { "virt", &v68n_1024 }, { "V66G_1024", &v66g_1024 }, + { "qcs6490-cdsp", &qcs6490_cdsp }, }; =20 static uint32_t l2vic_read32(uint64_t base, uint32_t offset) diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c new file mode 100644 index 00000000000..39d6e53bc4e --- /dev/null +++ b/tests/qtest/qcom-dsp-test.c @@ -0,0 +1,93 @@ +/* + * QTest for what the Qualcomm DSP machines have in common: the console and + * the virtio-mmio transports. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqtest-single.h" + +#define QCOM_DSP_UART_BASE 0x37000000 +#define QCOM_DSP_VIRTIO_BASE 0x37010000 +#define QCOM_DSP_VIRTIO_STRIDE 0x1000 +#define QCOM_DSP_VIRTIO_COUNT 8 + +#define PL011_UARTPERIPHID0 0xfe0 +#define PL011_PERIPHID0 0x11 + +#define VIRTIO_MMIO_MAGIC_VALUE 0x000 +#define VIRTIO_MMIO_DEVICE_ID 0x008 +#define VIRTIO_MAGIC 0x74726976 /* "virt" */ + +static const char *const qcom_dsp_machines[] =3D { + "qcs6490-cdsp", +}; + +static void test_console(const void *machine) +{ + g_autofree char *args =3D g_strdup_printf("-machine %s", + (const char *)machine); + + qtest_start(args); + g_assert_cmphex(readl(QCOM_DSP_UART_BASE + PL011_UARTPERIPHID0), =3D= =3D, + PL011_PERIPHID0); + qtest_end(); +} + +static void test_virtio_slots(const void *machine) +{ + g_autofree char *args =3D g_strdup_printf("-machine %s", + (const char *)machine); + + qtest_start(args); + for (int i =3D 0; i < QCOM_DSP_VIRTIO_COUNT; i++) { + uint64_t base =3D QCOM_DSP_VIRTIO_BASE + i * QCOM_DSP_VIRTIO_STRID= E; + + g_assert_cmphex(readl(base + VIRTIO_MMIO_MAGIC_VALUE), =3D=3D, + VIRTIO_MAGIC); + /* No backend is attached, so the transport is empty. */ + g_assert_cmpuint(readl(base + VIRTIO_MMIO_DEVICE_ID), =3D=3D, 0); + } + qtest_end(); +} + +/* A drive is attached to a virtio transport without any -device. */ +static void test_default_drive(const void *machine) +{ + g_autofree char *args =3D g_strdup_printf( + "-machine %s -drive if=3Dvirtio,file=3Dnull-co://,format=3Draw", + (const char *)machine); + int found =3D 0; + + qtest_start(args); + for (int i =3D 0; i < QCOM_DSP_VIRTIO_COUNT; i++) { + uint64_t base =3D QCOM_DSP_VIRTIO_BASE + i * QCOM_DSP_VIRTIO_STRID= E; + + /* virtio-blk is device ID 2 */ + found +=3D readl(base + VIRTIO_MMIO_DEVICE_ID) =3D=3D 2; + } + g_assert_cmpint(found, =3D=3D, 1); + qtest_end(); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + for (size_t i =3D 0; i < ARRAY_SIZE(qcom_dsp_machines); i++) { + const char *name =3D qcom_dsp_machines[i]; + g_autofree char *path =3D NULL; + + path =3D g_strdup_printf("/qcom-dsp/%s/console", name); + qtest_add_data_func(path, name, test_console); + path =3D g_strdup_printf("/qcom-dsp/%s/virtio-slots", name); + qtest_add_data_func(path, name, test_virtio_slots); + path =3D g_strdup_printf("/qcom-dsp/%s/default-drive", name); + qtest_add_data_func(path, name, test_default_drive); + } + + return g_test_run(); +} diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c index fd8bb0af776..263751b55bf 100644 --- a/tests/qtest/qct-qtimer-test.c +++ b/tests/qtest/qct-qtimer-test.c @@ -12,6 +12,7 @@ =20 #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" +#include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" =20 #define QTIMER_DEFAULT_FREQ_HZ 19200000ULL =20 @@ -342,6 +343,7 @@ typedef struct { static const QtimerMachineCfg qtimer_machines[] =3D { { "virt", &v68n_1024 }, { "V66G_1024", &v66g_1024 }, + { "qcs6490-cdsp", &qcs6490_cdsp }, }; =20 static void test_qtimer_on_machine(gconstpointer data) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index 63ee8836aca..ffc8623691c 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -21,3 +21,18 @@ config HEX_VIRT select HEX_BOARD select VIRTIO_BLK select VIRTIO_SCSI + +config HEX_QCOM_DSP + bool + depends on HEX_DSP && FDT + select HEX_BOARD + select UNIMP + select QCOM_QDSP6SS_CLK + select VIRTIO_BLK + select VIRTIO_SCSI + +config HEX_QCS6490_CDSP + bool + default y + depends on HEX_DSP && FDT + select HEX_QCOM_DSP diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index 57bff31ad00..7145e8a65df 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -6,5 +6,7 @@ hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hex-= subsys.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_BOARD', if_true: files('hex-board.c')) hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c')) +hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true: files('qcom_dsp.c')) +hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: files('qcs6490_cd= sp.c')) =20 hw_arch +=3D {'hexagon': hexagon_ss} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 019c63ca60b..0bbca236659 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -320,7 +320,8 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ ['k230-ddr-test', 'k230-wdt-test', 'k230-gsdma-test', 'k230-decomp-gzip= -test'] : []) + \ ['milkv-duo-test'] =20 -qtests_hexagon =3D ['boot-serial-test', 'l2vic-test', 'qct-qtimer-test'] +qtests_hexagon =3D ['boot-serial-test', 'l2vic-test', 'qcom-dsp-test', + 'qct-qtimer-test'] =20 qos_test_ss =3D ss.source_set() qos_test_ss.add( --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543496180158500 Signed-off-by: Brian Cain --- hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 6 ++- hw/hexagon/sa8775p_cdsp.c | 59 +++++++++++++++++++++++ tests/qtest/l2vic-test.c | 2 + tests/qtest/qcom-dsp-test.c | 1 + tests/qtest/qct-qtimer-test.c | 2 + hw/hexagon/Kconfig | 6 +++ hw/hexagon/meson.build | 1 + 7 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 hw/hexagon/sa8775p_cdsp.c diff --git a/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc b/hw/hexagon/machine= _cfg_sa8775_cdsp0.h.inc index 442cbe3be31..7e2ef42b9e2 100644 --- a/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc +++ b/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 static const struct hexagon_machine_config SA8775P_cdsp0 =3D { + .ddr_base =3D 0x80000000, .cfgbase =3D 0x24000000 + 0x180000, .l2tcm_size =3D 0x00000000, .l2vic_base =3D 0x26300000 + 0x90000, @@ -25,7 +26,7 @@ static const struct hexagon_machine_config SA8775P_cdsp0 = =3D { .vtcm_base =3D 0x00002500, .vtcm_size_kb =3D 0x00002000, .l2tag_size =3D 0x00000400, - .l2ecomem_size =3D 0x00000000, + .l2ecomem_size =3D 0x00000400, .thread_enable_mask =3D 0x0000003f, .eccreg_base =3D 0x0000241f, .l2line_size =3D 0x00000080, @@ -60,5 +61,8 @@ static const struct hexagon_machine_config SA8775P_cdsp0 = =3D { .consistency_domain =3D 0x000000e0, .capacity_domain =3D 0x00000080, .axi3_lowaddr =3D 0x00000000, + .coproc2_int8_subcolumns =3D 0x00000002, + .corecfg_present =3D 0x00000005, + .coproc2_fp16_acc_exp =3D 0x00000007, }, }; diff --git a/hw/hexagon/sa8775p_cdsp.c b/hw/hexagon/sa8775p_cdsp.c new file mode 100644 index 00000000000..de44f8f65cc --- /dev/null +++ b/hw/hexagon/sa8775p_cdsp.c @@ -0,0 +1,59 @@ +/* + * Models the v73 CDSP0 of the SA8775P. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/qcom_dsp.h" +#include "target/hexagon/cpu.h" + +#include "machine_cfg_sa8775_cdsp0.h.inc" + +#define TYPE_SA8775P_CDSP_MACHINE MACHINE_TYPE_NAME("sa8775p-cdsp") + +static const QcomDspRegion sa8775p_cdsp_regions[] =3D { + { "tcsr", 0x01fc0000 }, + { "hwkm-prng", 0x010da000 }, + { "gdscr", 0x00151000 }, + { "pll0", 0x26340000 }, + { "pll1", 0x26000000 }, + { "clkctl", 0x26348000 }, + { "ccswi", 0x26008000 }, + { "rsc", 0x260a4000 }, +}; + +static void sa8775p_cdsp_init_devices(MachineState *ms) +{ + qcom_dsp_add_regions(ms, sa8775p_cdsp_regions, + ARRAY_SIZE(sa8775p_cdsp_regions)); + + qcom_soc_add_qup_geni_ports("sa8775p", 0x00b80000, 1, 0x4000); + qcom_soc_add_qup_geni_ports("sa8775p", 0x00880000, 7, 0x4000); + qcom_soc_add_qup_geni_ports("sa8775p", 0x00980000, 7, 0x4000); + qcom_soc_add_qup_geni_ports("sa8775p", 0x00a80000, 7, 0x4000); +} + +static const QcomDspMachineInfo sa8775p_cdsp_info =3D { + .desc =3D "SA8775P CDSP0", + .cpu_type =3D HEXAGON_CPU_TYPE_NAME("v73"), + .cpus =3D 6, + .rev =3D v73_rev, + .cfg =3D &SA8775P_cdsp0, + .kernel_addr =3D 0xa0000000, + .init_devices =3D sa8775p_cdsp_init_devices, +}; + +static const TypeInfo sa8775p_cdsp_types[] =3D { + { + .name =3D TYPE_SA8775P_CDSP_MACHINE, + .parent =3D TYPE_QCOM_DSP_MACHINE, + .class_init =3D qcom_dsp_class_init, + .class_data =3D &sa8775p_cdsp_info, + }, +}; + +DEFINE_TYPES(sa8775p_cdsp_types) diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c index 2e0d7dcb0f1..5d30d18a9fd 100644 --- a/tests/qtest/l2vic-test.c +++ b/tests/qtest/l2vic-test.c @@ -12,6 +12,7 @@ #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" =20 /* L2VIC register offsets exercised by this test */ #define L2VIC_INT_ENABLEn 0x100 /* Read/Write */ @@ -47,6 +48,7 @@ static const L2VICMachineCfg l2vic_machines[] =3D { { "virt", &v68n_1024 }, { "V66G_1024", &v66g_1024 }, { "qcs6490-cdsp", &qcs6490_cdsp }, + { "sa8775p-cdsp", &SA8775P_cdsp0 }, }; =20 static uint32_t l2vic_read32(uint64_t base, uint32_t offset) diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c index 39d6e53bc4e..586e113c181 100644 --- a/tests/qtest/qcom-dsp-test.c +++ b/tests/qtest/qcom-dsp-test.c @@ -24,6 +24,7 @@ =20 static const char *const qcom_dsp_machines[] =3D { "qcs6490-cdsp", + "sa8775p-cdsp", }; =20 static void test_console(const void *machine) diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c index 263751b55bf..b20d4a2bced 100644 --- a/tests/qtest/qct-qtimer-test.c +++ b/tests/qtest/qct-qtimer-test.c @@ -13,6 +13,7 @@ #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" =20 #define QTIMER_DEFAULT_FREQ_HZ 19200000ULL =20 @@ -344,6 +345,7 @@ static const QtimerMachineCfg qtimer_machines[] =3D { { "virt", &v68n_1024 }, { "V66G_1024", &v66g_1024 }, { "qcs6490-cdsp", &qcs6490_cdsp }, + { "sa8775p-cdsp", &SA8775P_cdsp0 }, }; =20 static void test_qtimer_on_machine(gconstpointer data) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index ffc8623691c..bdda7872878 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -36,3 +36,9 @@ config HEX_QCS6490_CDSP default y depends on HEX_DSP && FDT select HEX_QCOM_DSP + +config HEX_SA8775P_CDSP + bool + default y + depends on HEX_DSP && FDT + select HEX_QCOM_DSP diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index 7145e8a65df..b7496426c9a 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -8,5 +8,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_BOARD', if_true: files('he= x-board.c')) hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c')) hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true: files('qcom_dsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: files('qcs6490_cd= sp.c')) +hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true: files('sa8775p_cd= sp.c')) =20 hw_arch +=3D {'hexagon': hexagon_ss} --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543359497158500 Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 1 + hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc | 52 +++++++++++++ hw/hexagon/sc8480xp_nsp0.c | 90 ++++++++++++++++++++++ tests/qtest/l2vic-test.c | 2 + tests/qtest/qcom-dsp-test.c | 1 + tests/qtest/qct-qtimer-test.c | 2 + hw/hexagon/Kconfig | 6 ++ hw/hexagon/meson.build | 1 + 8 files changed, 155 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc create mode 100644 hw/hexagon/sc8480xp_nsp0.c diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 1d0d55ea938..5f993214784 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -29,6 +29,7 @@ typedef enum { v73_rev =3D 0x8c73, v73m_rev =3D 0xcc73, v81_rev =3D 0x8781, + v81_sc8480xp_rev =3D 0x8081, v81dgb_1_rev =3D 0xcc81, } Rev_t; #define HEXAGON_LATEST_REV v73 diff --git a/hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc b/hw/hexagon/machin= e_cfg_sc8480xp_nsp0.h.inc new file mode 100644 index 00000000000..5a39e53d834 --- /dev/null +++ b/hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Config table of the SC8480XP NSP0. */ +static const struct hexagon_machine_config sc8480xp_nsp0 =3D { + .ddr_base =3D 0x80000000, + .cfgbase =3D 0x30180000, + .l2vic_base =3D 0x32390000, + .l2vic_size =3D 0x1000, + .csr_base =3D 0x323a0000, + .qtmr_region =3D 0x323a1000, + .cfgtable =3D { + .l2tcm_base =3D 0x3000, + .subsystem_base =3D 0x3238, + .etm_base =3D 0x3019, + .l2cfg_base =3D 0x301a, + .l1s0_base =3D 0x3100, + .fastl2vic_base =3D 0x301e, + .jtlb_size_entries =3D 0x80, + .coproc_present =3D 0xd, + .ext_contexts =3D 8, + .vtcm_base =3D 0x3100, + .vtcm_size_kb =3D 0x2000, + .l2tag_size =3D 0x400, + .l2ecomem_size =3D 0x400, + .thread_enable_mask =3D 0xfff, + .l2line_size =3D 0x80, + .l2itcm_base =3D 0xd800, + .dma_version =3D 8, + .hvx_vec_log_length =3D 7, + .coproc2_reg0 =3D 0x10, + .coproc2_reg1 =3D 8, + .acd_preset =3D 1, + .mnd_preset =3D 1, + .l1d_size_kb =3D 0x40, + .l1i_size_kb =3D 0x40, + .l1d_write_policy =3D 2, + .vtcm_bank_width =3D 0x80, + .reserved4 =3D 1, + .axi3_lowaddr =3D 0x4000, + .corecfg_present =3D 0xd, + .coproc2_fp16_acc_exp =3D 1, + .AXIM_data_width =3D 0x100, + .l1d_ways =3D 8, + .l1i_ways =3D 4, + .l2way_num =3D 8, + .dma_jtlb_entries =3D 0x40, + }, +}; diff --git a/hw/hexagon/sc8480xp_nsp0.c b/hw/hexagon/sc8480xp_nsp0.c new file mode 100644 index 00000000000..68003f88161 --- /dev/null +++ b/hw/hexagon/sc8480xp_nsp0.c @@ -0,0 +1,90 @@ +/* + * Models the Hexagon v81 NSP of the SC8480XP. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/qcom_dsp.h" +#include "target/hexagon/cpu.h" + +#include "machine_cfg_sc8480xp_nsp0.h.inc" + +#define TYPE_SC8480XP_NSP0_MACHINE MACHINE_TYPE_NAME("sc8480xp-nsp0") + +static const QcomDspRegion sc8480xp_nsp0_regions[] =3D { + { "tcsr", 0x01f40000, 0xc0000 }, + { "hwkm-prng", 0x010ca000 }, + { "pll", 0x32340000 }, + { "clkctl", 0x32344000, 0x4000 }, + { "turing-cc", 0x32008000, 0x14000 }, + { "rsc", 0x320a4000 }, + { "dsp-rsc", 0x323c0000 }, + { "ipcc", 0x03e00000 }, + { "ipcc-legacy", 0x32380000 }, + { "pinctrl", 0x0f100000, 0x0f00000 }, + { "gcc", 0x00100000, 0x200000 }, + { "turing-cc-pll", 0x32000000, 0x8000 }, + { "q6-acd", 0x32350000, 0x800 }, + { "hmx-pll", 0x32348000 }, + { "hmx-cc", 0x3234c000, 0x4000 }, + { "hmx-acd", 0x32350800, 0x800 }, + { "stmtrace", 0x16000000, 0x1000000 }, + { "stmcfg", 0x10002000 }, + { "etb", 0x11c05000 }, + { "tpdm", 0x11181000, 0x6000 }, + { "tpda", 0x11188000 }, + { "funnel", 0x10041000 }, + { "funnel", 0x11c04000 }, + { "llcc", 0x20400000, 0x100000 }, + { "llcc", 0x20600000, 0x100000 }, + { "llcc", 0x21800000, 0x100000 }, + { "llcc", 0x21a00000, 0x100000 }, + { "llcc", 0x21c00000, 0x100000 }, + { "llcc", 0x21e00000, 0x100000 }, + { "llcc", 0x22800000, 0x100000 }, + { "llcc", 0x22a00000, 0x100000 }, + { "llcc", 0x22c00000, 0x100000 }, + { "llcc", 0x22e00000, 0x100000 }, + { "llcc", 0x23800000, 0x100000 }, + { "llcc", 0x23a00000, 0x100000 }, + { "llcc", 0x23c00000, 0x100000 }, + { "llcc", 0x23e00000, 0x100000 }, + { "ddrss", 0x20280000, 0x400 }, +}; + +static void sc8480xp_nsp0_init_devices(MachineState *ms) +{ + qcom_dsp_add_regions(ms, sc8480xp_nsp0_regions, + ARRAY_SIZE(sc8480xp_nsp0_regions)); + + qcom_soc_add_qup_geni_ports("sc8480xp", 0x07980000, 15, 0x4000); + qcom_soc_add_qup_geni_ports("sc8480xp", 0x00b80000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sc8480xp", 0x00a80000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sc8480xp", 0x00980000, 2, 0x4000); + qcom_soc_add_qup_geni_ports("sc8480xp", 0x00880000, 8, 0x4000); +} + +static const QcomDspMachineInfo sc8480xp_nsp0_info =3D { + .desc =3D "SC8480XP NSP", + .cpu_type =3D HEXAGON_CPU_TYPE_NAME("v81"), + .cpus =3D 12, + .rev =3D v81_sc8480xp_rev, + .cfg =3D &sc8480xp_nsp0, + .kernel_addr =3D 0xa0000000, + .init_devices =3D sc8480xp_nsp0_init_devices, +}; + +static const TypeInfo sc8480xp_nsp0_types[] =3D { + { + .name =3D TYPE_SC8480XP_NSP0_MACHINE, + .parent =3D TYPE_QCOM_DSP_MACHINE, + .class_init =3D qcom_dsp_class_init, + .class_data =3D &sc8480xp_nsp0_info, + }, +}; + +DEFINE_TYPES(sc8480xp_nsp0_types) diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c index 5d30d18a9fd..7afeabdbed8 100644 --- a/tests/qtest/l2vic-test.c +++ b/tests/qtest/l2vic-test.c @@ -12,6 +12,7 @@ #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" =20 /* L2VIC register offsets exercised by this test */ @@ -49,6 +50,7 @@ static const L2VICMachineCfg l2vic_machines[] =3D { { "V66G_1024", &v66g_1024 }, { "qcs6490-cdsp", &qcs6490_cdsp }, { "sa8775p-cdsp", &SA8775P_cdsp0 }, + { "sc8480xp-nsp0", &sc8480xp_nsp0 }, }; =20 static uint32_t l2vic_read32(uint64_t base, uint32_t offset) diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c index 586e113c181..46bbae47881 100644 --- a/tests/qtest/qcom-dsp-test.c +++ b/tests/qtest/qcom-dsp-test.c @@ -25,6 +25,7 @@ static const char *const qcom_dsp_machines[] =3D { "qcs6490-cdsp", "sa8775p-cdsp", + "sc8480xp-nsp0", }; =20 static void test_console(const void *machine) diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c index b20d4a2bced..629a11802ef 100644 --- a/tests/qtest/qct-qtimer-test.c +++ b/tests/qtest/qct-qtimer-test.c @@ -13,6 +13,7 @@ #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" =20 #define QTIMER_DEFAULT_FREQ_HZ 19200000ULL @@ -346,6 +347,7 @@ static const QtimerMachineCfg qtimer_machines[] =3D { { "V66G_1024", &v66g_1024 }, { "qcs6490-cdsp", &qcs6490_cdsp }, { "sa8775p-cdsp", &SA8775P_cdsp0 }, + { "sc8480xp-nsp0", &sc8480xp_nsp0 }, }; =20 static void test_qtimer_on_machine(gconstpointer data) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index bdda7872878..8785129da0e 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -42,3 +42,9 @@ config HEX_SA8775P_CDSP default y depends on HEX_DSP && FDT select HEX_QCOM_DSP + +config HEX_SC8480XP_NSP0 + bool + default y + depends on HEX_DSP && FDT + select HEX_QCOM_DSP diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index b7496426c9a..b42a37b14de 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -9,5 +9,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('vir= t.c')) hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true: files('qcom_dsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: files('qcs6490_cd= sp.c')) hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true: files('sa8775p_cd= sp.c')) +hexagon_ss.add(when: 'CONFIG_HEX_SC8480XP_NSP0', if_true: files('sc8480xp_= nsp0.c')) =20 hw_arch +=3D {'hexagon': hexagon_ss} --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543488104158500 Signed-off-by: Brian Cain --- hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc | 56 +++++++++++++++++++ hw/hexagon/sa8797p_nsp0.c | 68 +++++++++++++++++++++++ tests/qtest/l2vic-test.c | 2 + tests/qtest/qcom-dsp-test.c | 1 + tests/qtest/qct-qtimer-test.c | 2 + hw/hexagon/Kconfig | 6 ++ hw/hexagon/meson.build | 1 + 7 files changed, 136 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc create mode 100644 hw/hexagon/sa8797p_nsp0.c diff --git a/hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc b/hw/hexagon/machine= _cfg_sa8797p_nsp0.h.inc new file mode 100644 index 00000000000..abc02a3e9ce --- /dev/null +++ b/hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +static const struct hexagon_machine_config sa8797p_nsp0 =3D { + .ddr_base =3D 0x80000000, + .cfgbase =3D 0x30180000, + .l2vic_base =3D 0x32390000, + .l2vic_size =3D 0x1000, + .l2tcm_size =3D 0x100000, + .csr_base =3D 0x323a0000, + .qtmr_region =3D 0x323a1000, + .cfgtable =3D { + .l2tcm_base =3D 0x3000, + .subsystem_base =3D 0x3238, + .etm_base =3D 0x3019, + .l2cfg_base =3D 0x301a, + .l1s0_base =3D 0x3100, + .fastl2vic_base =3D 0x301e, + .jtlb_size_entries =3D 0x80, + .coproc_present =3D 0xd, + .ext_contexts =3D 8, + .vtcm_base =3D 0x3100, + .vtcm_size_kb =3D 0x4000, + .l2tag_size =3D 0x400, + .l2ecomem_size =3D 0x400, + .thread_enable_mask =3D 0xfff, + .eccreg_base =3D 0x301f, + .l2line_size =3D 0x80, + .l2itcm_base =3D 0x3000, + .dma_version =3D 8, + .hvx_vec_log_length =3D 7, + .coproc2_reg0 =3D 0x10, + .coproc2_reg1 =3D 8, + .v2x_mode =3D 1, + .acd_preset =3D 1, + .mnd_preset =3D 1, + .l1d_size_kb =3D 0x40, + .l1i_size_kb =3D 0x40, + .l1d_write_policy =3D 2, + .vtcm_bank_width =3D 0x80, + .reserved4 =3D 1, + .reserved6 =3D 3, + .consistency_domain =3D 0xe0, + .capacity_domain =3D 0x80, + .corecfg_present =3D 0xd, + .coproc2_fp16_acc_exp =3D 1, + .AXIM_data_width =3D 0x100, + .l1d_ways =3D 8, + .l1i_ways =3D 4, + .l2way_num =3D 8, + .dma_jtlb_entries =3D 0x40, + }, +}; diff --git a/hw/hexagon/sa8797p_nsp0.c b/hw/hexagon/sa8797p_nsp0.c new file mode 100644 index 00000000000..20eebd5389f --- /dev/null +++ b/hw/hexagon/sa8797p_nsp0.c @@ -0,0 +1,68 @@ +/* + * Models the v81 NSP0 of the SA8797P. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/qcom_dsp.h" +#include "target/hexagon/cpu.h" + +#include "machine_cfg_sa8797p_nsp0.h.inc" + +#define TYPE_SA8797P_NSP0_MACHINE MACHINE_TYPE_NAME("sa8797p-nsp0") + +static const QcomDspRegion sa8797p_nsp0_regions[] =3D { + { "gcc", 0x00100000, 0x200000 }, + { "ne-gcc", 0x08900000, 0x100000 }, + { "se-gcc", 0x08a00000, 0x100000 }, + { "nw-gcc", 0x08b00000, 0x100000 }, + { "nsp-cc", 0x320c0000, 0x10000 }, + { "qfprom", 0x360c8000, 0x8000 }, + { "q6-cc", 0x32340000, 0x11000 }, + { "pinctrl", 0x0f100000, 0x0f00000 }, + { "ipcc", 0x09000000 }, + { "ipcc-legacy", 0x32380000 }, + { "stmtrace", 0x16000000, 0x1000000 }, + { "tpdm", 0x117c0000, 0x2000 }, + { "tpdm", 0x117c5000, 0x2000 }, + { "tpda", 0x117c8000 }, +}; + +static void sa8797p_nsp0_init_devices(MachineState *ms) +{ + qcom_dsp_add_regions(ms, sa8797p_nsp0_regions, + ARRAY_SIZE(sa8797p_nsp0_regions)); + + qcom_soc_add_qup_geni_ports("sa8797p", 0x09b86000, 5, 0x2000); + qcom_soc_add_qup_geni_ports("sa8797p", 0x09c06000, 5, 0x2000); + qcom_soc_add_qup_geni_ports("sa8797p", 0x00c80000, 1, 0x4000); + qcom_soc_add_qup_geni_ports("sa8797p", 0x00a80000, 7, 0x4000); + qcom_soc_add_qup_geni_ports("sa8797p", 0x00980000, 7, 0x4000); + qcom_soc_add_qup_geni_ports("sa8797p", 0x00880000, 7, 0x4000); + qcom_soc_add_qup_geni_ports("sa8797p", 0x198880000, 6, 0x4000); +} + +static const QcomDspMachineInfo sa8797p_nsp0_info =3D { + .desc =3D "SA8797P NSP", + .cpu_type =3D HEXAGON_CPU_TYPE_NAME("v81"), + .cpus =3D 12, + .rev =3D v81_rev, + .cfg =3D &sa8797p_nsp0, + .kernel_addr =3D 0xa0000000, + .init_devices =3D sa8797p_nsp0_init_devices, +}; + +static const TypeInfo sa8797p_nsp0_types[] =3D { + { + .name =3D TYPE_SA8797P_NSP0_MACHINE, + .parent =3D TYPE_QCOM_DSP_MACHINE, + .class_init =3D qcom_dsp_class_init, + .class_data =3D &sa8797p_nsp0_info, + }, +}; + +DEFINE_TYPES(sa8797p_nsp0_types) diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c index 7afeabdbed8..4cd0319e8b5 100644 --- a/tests/qtest/l2vic-test.c +++ b/tests/qtest/l2vic-test.c @@ -12,6 +12,7 @@ #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" =20 @@ -51,6 +52,7 @@ static const L2VICMachineCfg l2vic_machines[] =3D { { "qcs6490-cdsp", &qcs6490_cdsp }, { "sa8775p-cdsp", &SA8775P_cdsp0 }, { "sc8480xp-nsp0", &sc8480xp_nsp0 }, + { "sa8797p-nsp0", &sa8797p_nsp0 }, }; =20 static uint32_t l2vic_read32(uint64_t base, uint32_t offset) diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c index 46bbae47881..def389a0e9e 100644 --- a/tests/qtest/qcom-dsp-test.c +++ b/tests/qtest/qcom-dsp-test.c @@ -26,6 +26,7 @@ static const char *const qcom_dsp_machines[] =3D { "qcs6490-cdsp", "sa8775p-cdsp", "sc8480xp-nsp0", + "sa8797p-nsp0", }; =20 static void test_console(const void *machine) diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c index 629a11802ef..21870de5649 100644 --- a/tests/qtest/qct-qtimer-test.c +++ b/tests/qtest/qct-qtimer-test.c @@ -13,6 +13,7 @@ #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" =20 @@ -348,6 +349,7 @@ static const QtimerMachineCfg qtimer_machines[] =3D { { "qcs6490-cdsp", &qcs6490_cdsp }, { "sa8775p-cdsp", &SA8775P_cdsp0 }, { "sc8480xp-nsp0", &sc8480xp_nsp0 }, + { "sa8797p-nsp0", &sa8797p_nsp0 }, }; =20 static void test_qtimer_on_machine(gconstpointer data) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index 8785129da0e..bcf368cb8b7 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -48,3 +48,9 @@ config HEX_SC8480XP_NSP0 default y depends on HEX_DSP && FDT select HEX_QCOM_DSP + +config HEX_SA8797P_NSP0 + bool + default y + depends on HEX_DSP && FDT + select HEX_QCOM_DSP diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index b42a37b14de..5a10ae694fe 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -10,5 +10,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_QCOM_DSP', if_true: file= s('qcom_dsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: files('qcs6490_cd= sp.c')) hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true: files('sa8775p_cd= sp.c')) hexagon_ss.add(when: 'CONFIG_HEX_SC8480XP_NSP0', if_true: files('sc8480xp_= nsp0.c')) +hexagon_ss.add(when: 'CONFIG_HEX_SA8797P_NSP0', if_true: files('sa8797p_ns= p0.c')) =20 hw_arch +=3D {'hexagon': hexagon_ss} --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543453328158500 Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 1 + hw/hexagon/machine_cfg_sm8975_nsp.h.inc | 55 +++++++++++++ hw/hexagon/sm8975_nsp.c | 102 ++++++++++++++++++++++++ tests/qtest/l2vic-test.c | 2 + tests/qtest/qcom-dsp-test.c | 17 ++++ tests/qtest/qct-qtimer-test.c | 2 + hw/hexagon/Kconfig | 6 ++ hw/hexagon/meson.build | 1 + 8 files changed, 186 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sm8975_nsp.h.inc create mode 100644 hw/hexagon/sm8975_nsp.c diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 5f993214784..26b0a1b3757 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -31,6 +31,7 @@ typedef enum { v81_rev =3D 0x8781, v81_sc8480xp_rev =3D 0x8081, v81dgb_1_rev =3D 0xcc81, + v85_sm8975_rev =3D 0x8085, } Rev_t; #define HEXAGON_LATEST_REV v73 #define HEXAGON_LATEST_REV_UPPER V73 diff --git a/hw/hexagon/machine_cfg_sm8975_nsp.h.inc b/hw/hexagon/machine_c= fg_sm8975_nsp.h.inc new file mode 100644 index 00000000000..b97e7880938 --- /dev/null +++ b/hw/hexagon/machine_cfg_sm8975_nsp.h.inc @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Config table of the SM8975 NSP. */ +static const struct hexagon_machine_config sm8975_nsp =3D { + .ddr_base =3D 0x80000000, + .cfgbase =3D 0x24180000, + .l2tcm_size =3D 0x100000, + .l2vic_base =3D 0x26390000, + .l2vic_size =3D 0x1000, + .csr_base =3D 0x263a0000, + .qtmr_region =3D 0x263a1000, + .cfgtable =3D { + .l2tcm_base =3D 0x2400, + .subsystem_base =3D 0x2638, + .etm_base =3D 0x2419, + .l2cfg_base =3D 0x241a, + .l1s0_base =3D 0x2500, + .fastl2vic_base =3D 0x241e, + .jtlb_size_entries =3D 0x80, + .coproc_present =3D 0x1d, + .ext_contexts =3D 8, + .vtcm_base =3D 0x2500, + .vtcm_size_kb =3D 0x3000, + .l2tag_size =3D 0x400, + .l2ecomem_size =3D 0x400, + .thread_enable_mask =3D 0xfff, + .l2line_size =3D 0x80, + .l2itcm_base =3D 0x2400, + .dma_version =3D 0xc, + .hvx_vec_log_length =3D 7, + .coproc2_reg0 =3D 0x10, + .coproc2_reg1 =3D 8, + .coproc2_reg2 =3D 3, + .acd_preset =3D 1, + .mnd_preset =3D 1, + .l1d_size_kb =3D 0x40, + .l1i_size_kb =3D 0x40, + .l1d_write_policy =3D 2, + .vtcm_bank_width =3D 0x80, + .consistency_domain =3D 0xe0, + .capacity_domain =3D 0x80, + .axi3_lowaddr =3D 0x4000, + .corecfg_present =3D 0xd, + .coproc2_fp16_acc_exp =3D 3, + .AXIM_data_width =3D 0x100, + .l1d_ways =3D 8, + .l1i_ways =3D 4, + .l2way_num =3D 8, + .dma_jtlb_entries =3D 0x40, + }, +}; diff --git a/hw/hexagon/sm8975_nsp.c b/hw/hexagon/sm8975_nsp.c new file mode 100644 index 00000000000..91790c84230 --- /dev/null +++ b/hw/hexagon/sm8975_nsp.c @@ -0,0 +1,102 @@ +/* + * sm8975-nsp machine. + * + * Models the Hexagon v85 NSP of the SM8975. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/qcom_dsp.h" +#include "target/hexagon/cpu.h" + +#include "machine_cfg_sm8975_nsp.h.inc" + +#define TYPE_SM8975_NSP_MACHINE MACHINE_TYPE_NAME("sm8975-nsp") + +static const QcomDspRegion sm8975_nsp_regions[] =3D { + { "dspss-pub", 0x26300000, 0x10000 }, + { "wdog", 0x26384000 }, + { "turing-cc", 0x26008000, 0x14000 }, + { "pll", 0x26340000 }, + { "clkctl", 0x26344000, 0x4000 }, + { "compute-rsc", 0x260a4000 }, + { "qdsp6-rsc", 0x263c0000 }, + { "ipcc", 0x01100000 }, + { "tcsr", 0x26080000, 0x1f000 }, + { "turing-cc-pll", 0x26000000 }, + { "turing-cc-pll", 0x26001000 }, + { "turing-cc-pll", 0x26002000 }, + { "turing-cc-pll", 0x26003000 }, + { "turing-cc-pll", 0x26004000 }, + { "ahb2phy", 0x26006000, 0x2000 }, + { "ahbe-time", 0x260b7000 }, + { "nsp-noc", 0x260c0000, 0x21280 }, + { "ceng", 0x26260000, 0xc000 }, + { "ceng-irq", 0x2626c000 }, + { "ubwcd", 0x26280000, 0x10000 }, + { "vapss", 0x262c0000, 0x40000 }, + { "llm-isense", 0x26310000, 0x10000 }, + { "lpm-stats", 0x26320000, 0x10000 }, + { "mxu-pll", 0x26348000 }, + { "acd-mnd-dcc", 0x26350000, 0x800 }, + { "hmx-acd-mnd-dcc", 0x26350800, 0x800 }, + { "gcc", 0x00100000, 0x200000 }, + { "fuse", 0x221c8000 }, + { "hmx-swman", 0x2634a000, 0x400 }, + { "hmx-broadcast", 0x2634b000, 0x400 }, + { "hmx-cc", 0x2634c000, 0x4000 }, + { "ipcc-legacy", 0x26380000 }, + { "pinctrl", 0x0f100000, 0x0f00000 }, + { "llcc", 0x31800000, 0x200000 }, + { "llcc", 0x31c00000, 0x200000 }, + { "llcc", 0x32800000, 0x200000 }, + { "llcc", 0x32c00000, 0x200000 }, + { "llcc", 0x34800000, 0x200000 }, + { "llcc", 0x34c00000, 0x200000 }, + { "stmtrace", 0x16000000, 0x1000000 }, + { "stmcfg", 0x10002000 }, + { "etb", 0x11305000 }, + { "tpdm", 0x11181000, 0x2000 }, + { "tpdm", 0x11185000, 0x2000 }, + { "funnel", 0x10041000 }, + { "funnel", 0x11304000 }, + { "tpda", 0x11188000 }, +}; + +static void sm8975_nsp_init_devices(MachineState *ms) +{ + qcom_dsp_add_regions(ms, sm8975_nsp_regions, + ARRAY_SIZE(sm8975_nsp_regions)); + + qcom_soc_add_qup_geni_ports("sm8975", 0x08180000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x08280000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x01980000, 6, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x01a80000, 5, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x00a80000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x00880000, 5, 0x4000); +} + +static const QcomDspMachineInfo sm8975_nsp_info =3D { + .desc =3D "SM8975 NSP", + .cpu_type =3D HEXAGON_CPU_TYPE_NAME("v85"), + .cpus =3D 12, + .rev =3D v85_sm8975_rev, + .cfg =3D &sm8975_nsp, + .kernel_addr =3D 0xa0000000, + .init_devices =3D sm8975_nsp_init_devices, +}; + +static const TypeInfo sm8975_nsp_types[] =3D { + { + .name =3D TYPE_SM8975_NSP_MACHINE, + .parent =3D TYPE_QCOM_DSP_MACHINE, + .class_init =3D qcom_dsp_class_init, + .class_data =3D &sm8975_nsp_info, + }, +}; + +DEFINE_TYPES(sm8975_nsp_types) diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c index 4cd0319e8b5..82f93fd58f9 100644 --- a/tests/qtest/l2vic-test.c +++ b/tests/qtest/l2vic-test.c @@ -12,6 +12,7 @@ #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sm8975_nsp.h.inc" #include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" @@ -53,6 +54,7 @@ static const L2VICMachineCfg l2vic_machines[] =3D { { "sa8775p-cdsp", &SA8775P_cdsp0 }, { "sc8480xp-nsp0", &sc8480xp_nsp0 }, { "sa8797p-nsp0", &sa8797p_nsp0 }, + { "sm8975-nsp", &sm8975_nsp }, }; =20 static uint32_t l2vic_read32(uint64_t base, uint32_t offset) diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c index def389a0e9e..9cca6a835d0 100644 --- a/tests/qtest/qcom-dsp-test.c +++ b/tests/qtest/qcom-dsp-test.c @@ -9,6 +9,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "libqtest-single.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/machine_cfg_sm8975_nsp.h.inc" =20 #define QCOM_DSP_UART_BASE 0x37000000 #define QCOM_DSP_VIRTIO_BASE 0x37010000 @@ -27,6 +29,7 @@ static const char *const qcom_dsp_machines[] =3D { "sa8775p-cdsp", "sc8480xp-nsp0", "sa8797p-nsp0", + "sm8975-nsp", }; =20 static void test_console(const void *machine) @@ -76,6 +79,18 @@ static void test_default_drive(const void *machine) qtest_end(); } =20 +static void test_tcm(const void *unused) +{ + uint64_t base =3D (uint64_t)sm8975_nsp.cfgtable.l2tcm_base << 16; + + qtest_start("-machine sm8975-nsp"); + writel(base, 0xdeadbeef); + writel(base + sm8975_nsp.l2tcm_size - 4, 0xcafef00d); + g_assert_cmphex(readl(base), =3D=3D, 0xdeadbeef); + g_assert_cmphex(readl(base + sm8975_nsp.l2tcm_size - 4), =3D=3D, 0xcaf= ef00d); + qtest_end(); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); @@ -92,5 +107,7 @@ int main(int argc, char **argv) qtest_add_data_func(path, name, test_default_drive); } =20 + qtest_add_data_func("/qcom-dsp/sm8975-nsp/tcm", NULL, test_tcm); + return g_test_run(); } diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c index 21870de5649..b4c1b9e37f4 100644 --- a/tests/qtest/qct-qtimer-test.c +++ b/tests/qtest/qct-qtimer-test.c @@ -13,6 +13,7 @@ #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sm8975_nsp.h.inc" #include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" @@ -350,6 +351,7 @@ static const QtimerMachineCfg qtimer_machines[] =3D { { "sa8775p-cdsp", &SA8775P_cdsp0 }, { "sc8480xp-nsp0", &sc8480xp_nsp0 }, { "sa8797p-nsp0", &sa8797p_nsp0 }, + { "sm8975-nsp", &sm8975_nsp }, }; =20 static void test_qtimer_on_machine(gconstpointer data) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index bcf368cb8b7..177d87f7f94 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -54,3 +54,9 @@ config HEX_SA8797P_NSP0 default y depends on HEX_DSP && FDT select HEX_QCOM_DSP + +config HEX_SM8975_NSP + bool + default y + depends on HEX_DSP && FDT + select HEX_QCOM_DSP diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index 5a10ae694fe..fa5bc5eb9f1 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -11,5 +11,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: = files('qcs6490_cdsp.c') hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true: files('sa8775p_cd= sp.c')) hexagon_ss.add(when: 'CONFIG_HEX_SC8480XP_NSP0', if_true: files('sc8480xp_= nsp0.c')) hexagon_ss.add(when: 'CONFIG_HEX_SA8797P_NSP0', if_true: files('sa8797p_ns= p0.c')) +hexagon_ss.add(when: 'CONFIG_HEX_SM8975_NSP', if_true: files('sm8975_nsp.c= ')) =20 hw_arch +=3D {'hexagon': hexagon_ss} --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543355761158500 Add the Hexagon V79NA_1 simulator machine, with the config table of the v79 core and eight CPUs by default. Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 1 + hw/hexagon/machine_cfg_v79na_1.h.inc | 34 ++++++++++++++++++++++++++++ hw/hexagon/hexagon_dsp.c | 22 ++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 hw/hexagon/machine_cfg_v79na_1.h.inc diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 26b0a1b3757..7d15a9e1eb0 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -28,6 +28,7 @@ typedef enum { v71_rev =3D 0x8c71, v73_rev =3D 0x8c73, v73m_rev =3D 0xcc73, + v79_rev =3D 0x8c79, v81_rev =3D 0x8781, v81_sc8480xp_rev =3D 0x8081, v81dgb_1_rev =3D 0xcc81, diff --git a/hw/hexagon/machine_cfg_v79na_1.h.inc b/hw/hexagon/machine_cfg_= v79na_1.h.inc new file mode 100644 index 00000000000..70a7ae58bc5 --- /dev/null +++ b/hw/hexagon/machine_cfg_v79na_1.h.inc @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v79na_1 =3D { + .cfgbase =3D 0xd8180000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, .subsystem_base =3D 0x00002000, + .etm_base =3D 0x0000d819, .l2cfg_base =3D 0x0000d81a, + .l1s0_base =3D 0x0000d900, .axi2_lowaddr =3D 0x00003000, + .fastl2vic_base =3D 0x0000d81e, .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x0000000d, .ext_contexts =3D 0x00000006, + .vtcm_base =3D 0x0000d900, .vtcm_size_kb =3D 0x00002000, + .l2tag_size =3D 0x00000400, .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x000000ff, .l2line_size =3D 0x00000080, + .l2itcm_base =3D 0x0000d800, .dma_version =3D 0x00000006, + .hvx_vec_log_length =3D 0x00000007, .coproc2_reg0 =3D 0x00000040, + .coproc2_reg1 =3D 0x00000020, .v2x_mode =3D 0x00000001, + .coproc2_reg2 =3D 0x00000010, .coproc2_reg3 =3D 0x00000020, + .coproc2_reg4 =3D 0x00000020, .coproc2_reg5 =3D 0x00000008, + .coproc2_reg6 =3D 0x00000016, .coproc2_reg7 =3D 0x00000008, + .acd_preset =3D 0x00000001, .mnd_preset =3D 0x00000001, + .l1d_size_kb =3D 0x00000020, .l1i_size_kb =3D 0x00000020, + .l1d_write_policy =3D 0x00000002, .vtcm_bank_width =3D 0x00000080, + .reserved4 =3D 0x00000001, .coproc2_cvt_mpy_size =3D 0x0000000a, + .consistency_domain =3D 0x000000e0, .capacity_domain =3D 0x0000008= 0, + .axi3_lowaddr =3D 0x00004000, .coproc2_int8_subcolumns =3D 0x00000= 002, + .corecfg_present =3D 0x0000000d, .coproc2_fp16_acc_exp =3D 0x00000= 007, + .AXIM2_secondary_base =3D 0x00004000, .AXIM_data_width =3D 0x00000= 100, + }, +}; diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index 8824fe10a59..9f6f34ef9be 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -30,6 +30,7 @@ =20 #include "machine_cfg_v66g_1024.h.inc" #include "machine_cfg_v68n_1024.h.inc" +#include "machine_cfg_v79na_1.h.inc" #include "machine_cfg_v81dgb_1.h.inc" #include "machine_cfg_v81qa_1.h.inc" =20 @@ -205,6 +206,22 @@ static void v81dgb_1_config_init(MachineState *machine) hexagon_common_init(machine, v81dgb_1_rev, &v81dgb_1); } =20 +static void v79na_1_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v79_rev, &v79na_1); +} + +static void v79na_1_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V79NA_1"; + mc->init =3D v79na_1_config_init; + init_mc(mc); + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V79; + mc->default_cpus =3D 8; +} + static void v81dgb_1_init(ObjectClass *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -258,6 +275,11 @@ static const TypeInfo hexagon_machine_types[] =3D { .parent =3D TYPE_HEXAGON_DSP_MACHINE, .class_init =3D v68n_1024_init, }, + { + .name =3D MACHINE_TYPE_NAME("V79NA_1"), + .parent =3D TYPE_HEXAGON_DSP_MACHINE, + .class_init =3D v79na_1_init, + }, { .name =3D MACHINE_TYPE_NAME("V81DGB_1"), .parent =3D TYPE_HEXAGON_DSP_MACHINE, --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792543454; cv=none; d=zohomail.com; s=zohoarc; b=aCJHN8amySSTU8K90Xpphmana3XR2b3m7VgyWLmpaBZtBOKCiArxCdf3jQ7R4rTdybClVYvLVGt9/TcgxyVhrKTNruoLxUnWeBGTjFoKmpyDT5jZHhiMzFPt1z4iiBNgMC2S8gIAQjS4YZkEeo1PaFysmjUZMucNE+kHUwfUi/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543455417158500 Let the hexagon-sim-style machines their QDSP6 subsystem, and with it the l2vic and QTimer. The config table's subsystem base is updated to align with the chosen address. Signed-off-by: Brian Cain Reviewed-by: Anton Johansson --- MAINTAINERS | 1 + include/hw/hexagon/hexagon.h | 4 ++ hw/hexagon/hexagon_dsp.c | 71 +++++++++++++++++++++++++++- tests/qtest/hexagon-config-test.c | 78 +++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 5 files changed, 155 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/hexagon-config-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 9449e66d33b..8f327cf3371 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1386,6 +1386,7 @@ F: include/hw/misc/qcom-qdsp6ss-clk.h F: configs/devices/hexagon-softmmu/default.mak F: docs/system/hexagon/ F: tests/functional/hexagon/ +F: tests/qtest/hexagon-config-test.c F: tests/qtest/qcom-dsp-test.c F: docs/devel/hexagon-sys.rst =20 diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 7d15a9e1eb0..32acc2aa26b 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -44,6 +44,10 @@ typedef enum { =20 #define HEXAGON_CFGSPACE_ENTRIES (128) =20 +/* Offsets of q6ss cfg peripherals from the subsystem base. */ +#define HEXAGON_L2VIC_OFFSET 0x10000 +#define HEXAGON_QTIMER_OFFSET 0x21000 + union hexagon_config_table { struct { /* Base address of L2TCM space */ diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index 9f6f34ef9be..6c3de73dcc8 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -17,6 +17,7 @@ #include "hw/hexagon/hex-subsys.h" #include "hw/core/loader.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "qemu/log.h" #include "elf.h" @@ -35,6 +36,8 @@ #include "machine_cfg_v81qa_1.h.inc" =20 #define TYPE_HEXAGON_DSP_MACHINE "hexagon-dsp-machine" +#define HEXAGON_DSP_SUBSYSTEM_BASE 0xfc900000 +#define HEXAGON_DSP_SUBSYSTEM_SIZE (HEXAGON_QTIMER_OFFSET + 0x1000) OBJECT_DECLARE_SIMPLE_TYPE(HexagonDspMachineState, HEXAGON_DSP_MACHINE) =20 struct HexagonDspMachineState { @@ -42,6 +45,8 @@ struct HexagonDspMachineState { =20 hwaddr isdb_secure_flag; hwaddr isdb_trusted_flag; + uint32_t subsystem_base; + struct hexagon_machine_config config; }; =20 static HexagonDspMachineState *current_dms; @@ -107,6 +112,58 @@ static void do_cpu_reset(void *opaque) cpu_reset(cs); } =20 +static void hexagon_sim_get_subsystem_base(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + HexagonDspMachineState *dms =3D HEXAGON_DSP_MACHINE(obj); + uint32_t value =3D dms->subsystem_base; + + visit_type_uint32(v, name, &value, errp); +} + +static void hexagon_sim_set_subsystem_base(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + HexagonDspMachineState *dms =3D HEXAGON_DSP_MACHINE(obj); + uint64_t subsystem_end; + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + if (!value || !QEMU_IS_ALIGNED(value, 64 * KiB)) { + error_setg(errp, "subsystem-base must be nonzero and 64 KiB aligne= d"); + return; + } + subsystem_end =3D (uint64_t)value + HEXAGON_DSP_SUBSYSTEM_SIZE; + if (subsystem_end > (uint64_t)UINT32_MAX + 1) { + error_setg(errp, "subsystem-base 0x%x requires 0x%x bytes for the " + "subsystem, beyond the end of the address space", + value, HEXAGON_DSP_SUBSYSTEM_SIZE); + return; + } + + dms->subsystem_base =3D value; +} + +static void add_dsp_properties(ObjectClass *oc) +{ + object_class_property_add(oc, "subsystem-base", "uint32", + hexagon_sim_get_subsystem_base, + hexagon_sim_set_subsystem_base, NULL, NULL); + object_class_property_set_description(oc, "subsystem-base", + "Simulator subsystem base addres= s"); +} + +static void hexagon_dsp_init(Object *obj) +{ + HexagonDspMachineState *dms =3D HEXAGON_DSP_MACHINE(obj); + + dms->subsystem_base =3D HEXAGON_DSP_SUBSYSTEM_BASE; +} + static void hexagon_common_init(MachineState *machine, Rev_t rev, const struct hexagon_machine_config *m_cfg) { @@ -121,7 +178,13 @@ static void hexagon_common_init(MachineState *machine,= Rev_t rev, =20 machine->enable_graphics =3D 0; =20 - hex_subsys_create(hms, m_cfg, rev); + dms->config =3D *m_cfg; + dms->config.csr_base =3D dms->subsystem_base; + dms->config.l2vic_base =3D dms->subsystem_base + HEXAGON_L2VIC_OFFSET; + dms->config.qtmr_region =3D dms->subsystem_base + HEXAGON_QTIMER_OFFSE= T; + dms->config.cfgtable.subsystem_base =3D dms->subsystem_base >> 16; + + hex_subsys_create(hms, &dms->config, rev); =20 g_autofree HexagonCPU **cpus =3D g_new(HexagonCPU *, machine->smp.cpus= ); =20 @@ -183,6 +246,7 @@ static void v66g_1024_init(ObjectClass *oc, const void = *data) mc->is_default =3D true; mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V66; mc->default_cpus =3D 4; + add_dsp_properties(oc); } =20 static void v68n_1024_config_init(MachineState *machine) @@ -199,6 +263,7 @@ static void v68n_1024_init(ObjectClass *oc, const void = *data) init_mc(mc); mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V68; mc->default_cpus =3D 6; + add_dsp_properties(oc); } =20 static void v81dgb_1_config_init(MachineState *machine) @@ -220,6 +285,7 @@ static void v79na_1_init(ObjectClass *oc, const void *d= ata) init_mc(mc); mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V79; mc->default_cpus =3D 8; + add_dsp_properties(oc); } =20 static void v81dgb_1_init(ObjectClass *oc, const void *data) @@ -232,6 +298,7 @@ static void v81dgb_1_init(ObjectClass *oc, const void *= data) mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V81; mc->max_cpus =3D 12; mc->default_cpus =3D 12; + add_dsp_properties(oc); } =20 static void v81qa_1_config_init(MachineState *machine) @@ -250,6 +317,7 @@ static void v81qa_1_init(ObjectClass *oc, const void *d= ata) mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V81; mc->max_cpus =3D 12; mc->default_cpus =3D 12; + add_dsp_properties(oc); } =20 static const TypeInfo hexagon_machine_types[] =3D { @@ -263,6 +331,7 @@ static const TypeInfo hexagon_machine_types[] =3D { .name =3D TYPE_HEXAGON_DSP_MACHINE, .parent =3D TYPE_HEXAGON_COMMON_MACHINE, .instance_size =3D sizeof(HexagonDspMachineState), + .instance_init =3D hexagon_dsp_init, .abstract =3D true, }, { diff --git a/tests/qtest/hexagon-config-test.c b/tests/qtest/hexagon-config= -test.c new file mode 100644 index 00000000000..9554fce57ca --- /dev/null +++ b/tests/qtest/hexagon-config-test.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "hw/hexagon/hexagon.h" + +#include "hw/hexagon/machine_cfg_v66g_1024.h.inc" +#include "hw/hexagon/machine_cfg_v68n_1024.h.inc" +#include "hw/hexagon/machine_cfg_v79na_1.h.inc" +#include "hw/hexagon/machine_cfg_v81dgb_1.h.inc" +#include "hw/hexagon/machine_cfg_v81qa_1.h.inc" + +typedef struct { + const char *machine; + const struct hexagon_machine_config *cfg; + uint32_t subsystem_base; +} HexagonMachineCfg; + +static const HexagonMachineCfg hexagon_machines[] =3D { + { "V66G_1024", &v66g_1024, 0 }, + { "V68N_1024", &v68n_1024, 0 }, + { "V79NA_1", &v79na_1, 0 }, + { "V81DGB_1", &v81dgb_1, 0 }, + { "V81QA_1", &v81qa_1, 0 }, + { "V81QA_1", &v81qa_1, 0xfca00000 }, +}; + +static void test_config_table(gconstpointer data) +{ + const HexagonMachineCfg *mc =3D data; + uint64_t subsystem_base; + uint32_t subsystem_base_entry; + g_autofree char *args; + + if (mc->subsystem_base) { + args =3D g_strdup_printf("-machine %s,subsystem-base=3D0x%x", mc->= machine, + mc->subsystem_base); + } else { + args =3D g_strdup_printf("-machine %s", mc->machine); + } + + qtest_start(args); + + subsystem_base_entry =3D readl(mc->cfg->cfgbase + + offsetof(union hexagon_config_table, + subsystem_base)); + subsystem_base =3D (uint64_t)subsystem_base_entry << 16; + g_assert_cmphex(subsystem_base, =3D=3D, + mc->subsystem_base ?: mc->cfg->csr_base); + writel(subsystem_base + HEXAGON_L2VIC_OFFSET + 0x200, 1); + g_assert_cmphex(readl(subsystem_base + HEXAGON_L2VIC_OFFSET + 0x100), + =3D=3D, 1); + g_assert_cmphex(readl(subsystem_base + HEXAGON_QTIMER_OFFSET + 0x10), + =3D=3D, 19200000); + + qtest_end(); +} + +int main(int argc, char **argv) +{ + size_t i; + + g_test_init(&argc, &argv, NULL); + + for (i =3D 0; i < ARRAY_SIZE(hexagon_machines); i++) { + const HexagonMachineCfg *mc =3D &hexagon_machines[i]; + g_autofree char *path =3D g_strdup_printf("/config/%s/%x", mc->mac= hine, + mc->subsystem_base); + + qtest_add_data_func(path, mc, test_config_table); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 0bbca236659..1cbf8cd391a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -320,7 +320,8 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ ['k230-ddr-test', 'k230-wdt-test', 'k230-gsdma-test', 'k230-decomp-gzip= -test'] : []) + \ ['milkv-duo-test'] =20 -qtests_hexagon =3D ['boot-serial-test', 'l2vic-test', 'qcom-dsp-test', +qtests_hexagon =3D ['boot-serial-test', 'hexagon-config-test', 'l2vic-test= ', + 'qcom-dsp-test', 'qct-qtimer-test'] =20 qos_test_ss =3D ss.source_set() --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543394261158500 The frame that allocframe pushes is {LR, FP}, and what is scrambled is the LR word: FRAMEKEY is XOR'd into the upper 32 bits. The generated code for fFRAME_SCRAMBLE built the key from FRAMEKEY in both halves of a 64-bit value, so it scrambled FP as well. deallocframe and dealloc_return only undo the upper word, so a FP restored from a frame pushed with a non-zero FRAMEKEY was corrupt. Uncovered by testing some boot images using QuRT. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/idef-parser/parser-helpers.c | 2 +- tests/tcg/hexagon/framekey.c | 67 +++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 3 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/hexagon/framekey.c diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 49cc11fddd8..14840d98737 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1989,7 +1989,7 @@ HexValue gen_rvalue_fscr(Context *c, YYLTYPE *locp, H= exValue *value) *value =3D gen_rvalue_extend(c, locp, value); OUT(c, locp, "gen_read_reg(", &frame_key, ", HEX_REG_FRAMEKEY);\n"); OUT(c, locp, "tcg_gen_concat_i32_i64(", - &key, ", ", &frame_key, ", ", &frame_key, ");\n"); + &key, ", tcg_constant_tl(0), ", &frame_key, ");\n"); OUT(c, locp, "tcg_gen_xor_i64(", &res, ", ", value, ", ", &key, ");\n"= ); return res; } diff --git a/tests/tcg/hexagon/framekey.c b/tests/tcg/hexagon/framekey.c new file mode 100644 index 00000000000..5d579293477 --- /dev/null +++ b/tests/tcg/hexagon/framekey.c @@ -0,0 +1,67 @@ +/* + * Copyright(c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +int err; + +#include "hex_test.h" + +/* + * allocframe pushes {LR, FP}, scrambling LR with FRAMEKEY, and deallocfra= me + * restores them. Push a frame and return the words that were stored, FP + * through the return value and LR through @lr_stored, and the FP and LR + * that deallocframe restores. + */ +static inline uint32_t frame_roundtrip(uint32_t key, uint32_t fp, + uint32_t lr, uint32_t *lr_stored, + uint32_t *fp_back, uint32_t *lr_bac= k) +{ + uint32_t fp_stored, saved_fp, saved_lr; + + asm volatile("%[saved_fp] =3D r30\n\t" + "%[saved_lr] =3D r31\n\t" + "framekey =3D %[key]\n\t" + "r30 =3D %[fp]\n\t" + "r31 =3D %[lr]\n\t" + "allocframe(#0)\n\t" + "%[fp_stored] =3D memw(r30)\n\t" + "%[lr_stored] =3D memw(r30 + #4)\n\t" + "r31 =3D #0\n\t" + "deallocframe\n\t" + "%[fp_back] =3D r30\n\t" + "%[lr_back] =3D r31\n\t" + "framekey =3D %[zero]\n\t" + "r30 =3D %[saved_fp]\n\t" + "r31 =3D %[saved_lr]\n" + : [fp_stored] "=3D&r"(fp_stored), [lr_stored] "=3D&r"(*lr= _stored), + [fp_back] "=3D&r"(*fp_back), [lr_back] "=3D&r"(*lr_back= ), + [saved_fp] "=3D&r"(saved_fp), [saved_lr] "=3D&r"(saved_= lr) + : [key] "r"(key), [fp] "r"(fp), [lr] "r"(lr), [zero] "r"(= 0) + : "memory", "framekey"); + return fp_stored; +} + +static void check_frame(uint32_t key, uint32_t fp, uint32_t lr) +{ + uint32_t lr_stored, fp_back, lr_back; + + /* Only LR is scrambled, FP is stored as is */ + check32(frame_roundtrip(key, fp, lr, &lr_stored, &fp_back, &lr_back), = fp); + check32(lr_stored, lr ^ key); + check32(fp_back, fp); + check32(lr_back, lr); +} + +int main() +{ + check_frame(0, 0x1234fff0, 0x5678abcc); + check_frame(0xf21f20a0, 0x1234fff0, 0x5678abcc); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index a6ace4c77c2..0fd62ce7e4c 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -68,6 +68,7 @@ tests +=3D { 'overflow.c': {'cflags': cflags, 'exe_name': 'hex-overflow'}, 'preg_alias.c': {'cflags': cflags}, 'dual_stores.c': {'cflags': cflags}, + 'framekey.c': {'cflags': cflags}, 'multi_result.c': {'cflags': cflags}, 'mem_noshuf.c': {'cflags': cflags}, 'mem_noshuf_exception.c': {'cflags': cflags}, --=20 2.34.1 From nobody Fri Oct 23 21:06:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792543407; cv=none; d=zohomail.com; s=zohoarc; b=Czh9Qci30gNDYzoYOZSZztn3FkQSDbprS0nAwE9Ul3lzWxQuct7VwFe9ytu/FIwI5ny6HM88uHL1LA1IlCtOqa9/2p7JujcsXnBUr+nKWp7xNZNibTFES+XX2R2kbzVdjw54cNZDL5PTfyun6ub5nFo12DcMJfu4qowoq7gZOJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792543407; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=48XaNEhdi2CXpZ2OiYRzTDErtu1d4rVLSi/9r3SFsnw=; b=G+FAygZdTiJl4cHzyvKVrueprh5RJRmVZ3mTqAvnem2OYTJ0ybaAEWeGjHfDvKrzpaazHSKKxG6rUsjUPZVh6zYmv4dFEEqHSFZd/LSHozm1V8kVartpOg5o3PC5nRVke+4x6p9MHkMC10ASuFRIkbKRnKGPLXhOJyd2LDI0WXU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792543406948940.7830550743488; Tue, 20 Oct 2026 17:43:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJKPZ-0002OQ-Rj; Tue, 20 Oct 2026 20:42:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJKPM-0002HK-0u for qemu-devel@nongnu.org; Tue, 20 Oct 2026 20:42:20 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJKPJ-00071r-Ud for qemu-devel@nongnu.org; Tue, 20 Oct 2026 20:42:19 -0400 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69KKtiN23818756 for ; Wed, 21 Oct 2026 00:42:15 GMT Received: from mail-dl1-f69.google.com (mail-dl1-f69.google.com [74.125.82.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4heda4s674-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 00:42:14 +0000 (GMT) Received: by mail-dl1-f69.google.com with SMTP id a92af1059eb24-1665200f4c2so270186c88.0 for ; Tue, 20 Oct 2026 17:42:14 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792543408471158500 Download the firmware and run it on the corresponding DSP machine. The images are third-party binaries, so the tests run only when untrusted code is allowed. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- tests/functional/hexagon/meson.build | 2 + .../hexagon/test_qcom_dsp_firmware.py | 92 +++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100755 tests/functional/hexagon/test_qcom_dsp_firmware.py diff --git a/tests/functional/hexagon/meson.build b/tests/functional/hexago= n/meson.build index e182bc98a06..0fd90e491a2 100644 --- a/tests/functional/hexagon/meson.build +++ b/tests/functional/hexagon/meson.build @@ -2,10 +2,12 @@ =20 tests_hexagon_system_thorough =3D [ 'arch_tests', + 'qcom_dsp_firmware', 'systests', 'minivm', ] =20 test_hexagon_timeouts =3D { + 'qcom_dsp_firmware': 240, 'systests': 180, } diff --git a/tests/functional/hexagon/test_qcom_dsp_firmware.py b/tests/fun= ctional/hexagon/test_qcom_dsp_firmware.py new file mode 100755 index 00000000000..31beabc2374 --- /dev/null +++ b/tests/functional/hexagon/test_qcom_dsp_firmware.py @@ -0,0 +1,92 @@ +#!/usr/bin/env python3 +# +# Boot the production DSP firmware on the Qualcomm DSP machines +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset, skipUntrustedTest +from qemu_test import wait_for_console_pattern + + +class QcomDspFirmwareTest(QemuSystemTest): + """Base class: the firmware is the ELF that -kernel starts running.""" + + MACHINE =3D None + ASSET =3D None + MILESTONE =3D 'Entering main() ...' + + def boot_firmware(self): + self.set_machine(self.MACHINE) + firmware =3D self.ASSET.fetch() + + self.vm.set_console(semihosting=3DTrue) + self.vm.add_args('-kernel', firmware) + self.vm.launch() + wait_for_console_pattern(self, 'QURT kernel started', + failure_message=3D'Fatal Error') + wait_for_console_pattern(self, self.MILESTONE, + failure_message=3D'Fatal Error') + self.vm.kill() + + +@skipUntrustedTest() +class Qcs6490CdspFirmwareTest(QcomDspFirmwareTest): + MACHINE =3D 'qcs6490-cdsp' + + ASSET =3D Asset('https://gitlab.com/kernel-firmware/linux-firmware/-/r= aw/' + '20261019/qcom/qcm6490/cdsp.mbn', + '43e9c89e15ee82daf83214cae34006a8515fddf9db7f645f5eff4b8= e3c4ebb64') + + def test_qcs6490_cdsp_firmware(self): + self.boot_firmware() + + +@skipUntrustedTest() +class Sa8775pCdspFirmwareTest(QcomDspFirmwareTest): + MACHINE =3D 'sa8775p-cdsp' + ASSET =3D Asset('https://gitlab.com/kernel-firmware/linux-firmware/-/r= aw/' + '20261019/qcom/sa8775p/cdsp0.mbn', + '1d9d8cd1e913b0d3b49a77b4e962564ab481193e6a5697c8f06406b= 3fd85a8fc') + + def test_sa8775p_cdsp_firmware(self): + self.boot_firmware() + + +@skipUntrustedTest() +class Sc8480xpNsp0FirmwareTest(QcomDspFirmwareTest): + MACHINE =3D 'sc8480xp-nsp0' + ASSET =3D Asset('https://gitlab.com/kernel-firmware/linux-firmware/-/r= aw/' + '20261019/qcom/glymur/cdsp.mbn', + '7b22f33ae273d3dfc5f741a967831e7d4fd79ad141e6a1ecee17509= eac207109') + + def test_sc8480xp_nsp0_firmware(self): + self.boot_firmware() + + +@skipUntrustedTest() +class Sa8797pNsp0FirmwareTest(QcomDspFirmwareTest): + MACHINE =3D 'sa8797p-nsp0' + ASSET =3D Asset('https://gitlab.com/kernel-firmware/linux-firmware/-/r= aw/' + '20261019/qcom/nord/cdsp.mbn', + '410e7ca3b340e80835e464545a218d9376310a09f24bc87de40bc25= f7f5e3240') + + def test_sa8797p_nsp0_firmware(self): + self.boot_firmware() + + +@skipUntrustedTest() +class Sm8975NspFirmwareTest(QcomDspFirmwareTest): + MACHINE =3D 'sm8975-nsp' + MILESTONE =3D 'QURT root task started' + ASSET =3D Asset('https://gitlab.com/kernel-firmware/linux-firmware/-/r= aw/' + '20261019/qcom/hawi/cdsp.mbn', + '7373952413c141fc636aa933ab0c71e7be1d10f5f7dd36be5374827= b253c3db5') + + def test_sm8975_nsp_firmware(self): + self.boot_firmware() + + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.34.1