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X-purgate-type: clean X-purgate-size: 6643 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411562503158500 Content-Type: text/plain; charset="utf-8" This is to emphasise that child types of PIC_COMMON are all instances of an an 8259 PIC. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/i8259_internal.h | 4 ++-- hw/i386/kvm/i8259.c | 8 ++++---- hw/intc/i8259.c | 10 +++++----- hw/intc/i8259_common.c | 14 +++++++------- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index f9dcc4163e..54dc9036cf 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -31,8 +31,8 @@ #include "qom/object.h" =20 =20 -#define TYPE_PIC_COMMON "pic-common" -OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, PIC_COMMON) +#define TYPE_I8259_COMMON "pic-common" +OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, I8259_COMMON) =20 struct PICCommonClass { DeviceClass parent_class; diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 66f37e1303..14029783e5 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -103,7 +103,7 @@ static void kvm_pic_put(PICCommonState *s) =20 static void kvm_pic_reset(DeviceState *dev) { - PICCommonState *s =3D PIC_COMMON(dev); + PICCommonState *s =3D I8259_COMMON(dev); =20 s->elcr =3D 0; pic_reset_common(s); @@ -122,7 +122,7 @@ static void kvm_pic_set_irq(void *opaque, int irq, int = level) =20 static void kvm_pic_realize(DeviceState *dev, Error **errp) { - PICCommonState *s =3D PIC_COMMON(dev); + PICCommonState *s =3D I8259_COMMON(dev); KVMPICClass *kpc =3D KVM_PIC_GET_CLASS(dev); =20 memory_region_init_io(&s->base_io, OBJECT(dev), NULL, NULL, "kvm-pic",= 2); @@ -142,7 +142,7 @@ qemu_irq *kvm_i8259_init(ISABus *bus) static void kvm_i8259_class_init(ObjectClass *klass, const void *data) { KVMPICClass *kpc =3D KVM_PIC_CLASS(klass); - PICCommonClass *k =3D PIC_COMMON_CLASS(klass); + PICCommonClass *k =3D I8259_COMMON_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 device_class_set_legacy_reset(dc, kvm_pic_reset); @@ -153,7 +153,7 @@ static void kvm_i8259_class_init(ObjectClass *klass, co= nst void *data) =20 static const TypeInfo kvm_i8259_info =3D { .name =3D TYPE_KVM_I8259, - .parent =3D TYPE_PIC_COMMON, + .parent =3D TYPE_I8259_COMMON, .instance_size =3D sizeof(PICCommonState), .class_init =3D kvm_i8259_class_init, .class_size =3D sizeof(KVMPICClass), diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 8f2aa1f0fb..52e24d333e 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -218,7 +218,7 @@ static void pic_init_reset(PICCommonState *s) =20 static void pic_reset(DeviceState *dev) { - PICCommonState *s =3D PIC_COMMON(dev); + PICCommonState *s =3D I8259_COMMON(dev); =20 s->elcr =3D 0; s->ltim =3D 0; @@ -387,7 +387,7 @@ static const MemoryRegionOps pic_elcr_ioport_ops =3D { =20 static void pic_realize(DeviceState *dev, Error **errp) { - PICCommonState *s =3D PIC_COMMON(dev); + PICCommonState *s =3D I8259_COMMON(dev); PICClass *pc =3D PIC_GET_CLASS(dev); =20 memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, @@ -418,7 +418,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_i= n) irq_set[i] =3D qdev_get_gpio_in(dev, i); } =20 - isa_pic =3D PIC_COMMON(dev); + isa_pic =3D I8259_COMMON(dev); =20 isadev =3D i8259_init_chip(TYPE_I8259, bus, false); dev =3D DEVICE(isadev); @@ -428,7 +428,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_i= n) irq_set[i + 8] =3D qdev_get_gpio_in(dev, i); } =20 - slave_pic =3D PIC_COMMON(dev); + slave_pic =3D I8259_COMMON(dev); =20 return irq_set; } @@ -445,7 +445,7 @@ static void i8259_class_init(ObjectClass *klass, const = void *data) static const TypeInfo i8259_info =3D { .name =3D TYPE_I8259, .instance_size =3D sizeof(PICCommonState), - .parent =3D TYPE_PIC_COMMON, + .parent =3D TYPE_I8259_COMMON, .class_init =3D i8259_class_init, .class_size =3D sizeof(PICClass), }; diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 8ceb5841b9..e2f997e161 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -56,7 +56,7 @@ void pic_reset_common(PICCommonState *s) static int pic_dispatch_pre_save(void *opaque) { PICCommonState *s =3D opaque; - PICCommonClass *info =3D PIC_COMMON_GET_CLASS(s); + PICCommonClass *info =3D I8259_COMMON_GET_CLASS(s); =20 if (info->pre_save) { info->pre_save(s); @@ -68,7 +68,7 @@ static int pic_dispatch_pre_save(void *opaque) static int pic_dispatch_post_load(void *opaque, int version_id) { PICCommonState *s =3D opaque; - PICCommonClass *info =3D PIC_COMMON_GET_CLASS(s); + PICCommonClass *info =3D I8259_COMMON_GET_CLASS(s); =20 if (info->post_load) { info->post_load(s); @@ -78,7 +78,7 @@ static int pic_dispatch_post_load(void *opaque, int versi= on_id) =20 static void pic_common_realize(DeviceState *dev, Error **errp) { - PICCommonState *s =3D PIC_COMMON(dev); + PICCommonState *s =3D I8259_COMMON(dev); ISADevice *isa =3D ISA_DEVICE(dev); =20 isa_register_ioport(isa, &s->base_io, s->iobase); @@ -118,7 +118,7 @@ void pic_stat_update_irq(int irq, int level) static bool pic_get_statistics(InterruptStatsProvider *obj, uint64_t **irq_counts, unsigned int *nb_irq= s) { - PICCommonState *s =3D PIC_COMMON(obj); + PICCommonState *s =3D I8259_COMMON(obj); =20 if (s->master) { *irq_counts =3D irq_count; @@ -133,7 +133,7 @@ static bool pic_get_statistics(InterruptStatsProvider *= obj, =20 static void pic_print_info(InterruptStatsProvider *obj, GString *buf) { - PICCommonState *s =3D PIC_COMMON(obj); + PICCommonState *s =3D I8259_COMMON(obj); =20 pic_dispatch_pre_save(s); g_string_append_printf(buf, "pic%d: irr=3D%02x imr=3D%02x isr=3D%02x h= prio=3D%d " @@ -146,7 +146,7 @@ static void pic_print_info(InterruptStatsProvider *obj,= GString *buf) =20 static bool ltim_state_needed(void *opaque) { - PICCommonState *s =3D PIC_COMMON(opaque); + PICCommonState *s =3D I8259_COMMON(opaque); =20 return !!s->ltim; } @@ -220,7 +220,7 @@ static void pic_common_class_init(ObjectClass *klass, c= onst void *data) } =20 static const TypeInfo pic_common_type =3D { - .name =3D TYPE_PIC_COMMON, + .name =3D TYPE_I8259_COMMON, .parent =3D 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X-purgate-type: clean X-purgate-size: 749 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411556086158500 Content-Type: text/plain; charset="utf-8" This is to emphasise that child types of PIC_COMMON are all instances of an an 8259 PIC. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/i8259_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 54dc9036cf..289d08b7d7 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -31,7 +31,7 @@ #include "qom/object.h" =20 =20 -#define TYPE_I8259_COMMON "pic-common" +#define TYPE_I8259_COMMON "i8259-common" OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, I8259_COMMON) =20 struct PICCommonClass { --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 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X-purgate-type: clean X-purgate-size: 14398 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411566452158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/intc/i8259.h | 8 ++--- include/hw/isa/i8259_internal.h | 10 +++--- hw/i386/kvm/i8259.c | 10 +++--- hw/intc/i8259.c | 34 +++++++++---------- hw/intc/i8259_common.c | 58 ++++++++++++++++----------------- 5 files changed, 60 insertions(+), 60 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index 1f2420231f..1921a30371 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -3,9 +3,9 @@ =20 /* i8259.c */ =20 -typedef struct PICCommonState PICCommonState; +typedef struct I8259CommonState I8259CommonState; =20 -extern PICCommonState *isa_pic; +extern I8259CommonState *isa_pic; =20 /* * i8259_init() @@ -16,7 +16,7 @@ extern PICCommonState *isa_pic; */ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in); qemu_irq *kvm_i8259_init(ISABus *bus); -int pic_get_output(PICCommonState *s); -int pic_read_irq(PICCommonState *s); +int pic_get_output(I8259CommonState *s); +int pic_read_irq(I8259CommonState *s); =20 #endif diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 289d08b7d7..7a2f9addaf 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -32,16 +32,16 @@ =20 =20 #define TYPE_I8259_COMMON "i8259-common" -OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, I8259_COMMON) +OBJECT_DECLARE_TYPE(I8259CommonState, PICCommonClass, I8259_COMMON) =20 struct PICCommonClass { DeviceClass parent_class; =20 - void (*pre_save)(PICCommonState *s); - void (*post_load)(PICCommonState *s); + void (*pre_save)(I8259CommonState *s); + void (*post_load)(I8259CommonState *s); }; =20 -struct PICCommonState { +struct I8259CommonState { ISADevice parent_obj; =20 uint8_t last_irr; /* edge detection */ @@ -70,7 +70,7 @@ struct PICCommonState { MemoryRegion elcr_io; }; =20 -void pic_reset_common(PICCommonState *s); +void pic_reset_common(I8259CommonState *s); ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); void pic_stat_update_irq(int irq, int level); =20 diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 14029783e5..f10643a120 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -34,7 +34,7 @@ struct KVMPICClass { DeviceRealize parent_realize; }; =20 -static void kvm_pic_get(PICCommonState *s) +static void kvm_pic_get(I8259CommonState *s) { struct kvm_irqchip chip; struct kvm_pic_state *kpic; @@ -67,7 +67,7 @@ static void kvm_pic_get(PICCommonState *s) s->elcr_mask =3D kpic->elcr_mask; } =20 -static void kvm_pic_put(PICCommonState *s) +static void kvm_pic_put(I8259CommonState *s) { struct kvm_irqchip chip; struct kvm_pic_state *kpic; @@ -103,7 +103,7 @@ static void kvm_pic_put(PICCommonState *s) =20 static void kvm_pic_reset(DeviceState *dev) { - PICCommonState *s =3D I8259_COMMON(dev); + I8259CommonState *s =3D I8259_COMMON(dev); =20 s->elcr =3D 0; pic_reset_common(s); @@ -122,7 +122,7 @@ static void kvm_pic_set_irq(void *opaque, int irq, int = level) =20 static void kvm_pic_realize(DeviceState *dev, Error **errp) { - PICCommonState *s =3D I8259_COMMON(dev); + I8259CommonState *s =3D I8259_COMMON(dev); KVMPICClass *kpc =3D KVM_PIC_GET_CLASS(dev); =20 memory_region_init_io(&s->base_io, OBJECT(dev), NULL, NULL, "kvm-pic",= 2); @@ -154,7 +154,7 @@ static void kvm_i8259_class_init(ObjectClass *klass, co= nst void *data) static const TypeInfo kvm_i8259_info =3D { .name =3D TYPE_KVM_I8259, .parent =3D TYPE_I8259_COMMON, - .instance_size =3D sizeof(PICCommonState), + .instance_size =3D sizeof(I8259CommonState), .class_init =3D kvm_i8259_class_init, .class_size =3D sizeof(KVMPICClass), }; diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 52e24d333e..45db87a2ad 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -52,12 +52,12 @@ struct PICClass { #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif -PICCommonState *isa_pic; -static PICCommonState *slave_pic; +I8259CommonState *isa_pic; +static I8259CommonState *slave_pic; =20 /* return the highest priority found in mask (highest =3D smallest number). Return 8 if no irq */ -static int get_priority(PICCommonState *s, int mask) +static int get_priority(I8259CommonState *s, int mask) { int priority; =20 @@ -72,7 +72,7 @@ static int get_priority(PICCommonState *s, int mask) } =20 /* return the pic wanted interrupt. return -1 if none */ -static int pic_get_irq(PICCommonState *s) +static int pic_get_irq(I8259CommonState *s) { int mask, cur_priority, priority; =20 @@ -101,7 +101,7 @@ static int pic_get_irq(PICCommonState *s) } =20 /* Update INT output. Must be called every time the output may have change= d. */ -static void pic_update_irq(PICCommonState *s) +static void pic_update_irq(I8259CommonState *s) { int irq; =20 @@ -117,7 +117,7 @@ static void pic_update_irq(PICCommonState *s) /* set irq level. If an edge is detected, then the IRR is set to 1 */ static void pic_set_irq(void *opaque, int irq, int level) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; int mask =3D 1 << irq; int irq_index =3D s->master ? irq : irq + 8; =20 @@ -154,7 +154,7 @@ static void pic_set_irq(void *opaque, int irq, int leve= l) } =20 /* acknowledge interrupt 'irq' */ -static void pic_intack(PICCommonState *s, int irq) +static void pic_intack(I8259CommonState *s, int irq) { if (s->auto_eoi) { if (s->rotate_on_auto_eoi) { @@ -170,7 +170,7 @@ static void pic_intack(PICCommonState *s, int irq) pic_update_irq(s); } =20 -int pic_read_irq(PICCommonState *s) +int pic_read_irq(I8259CommonState *s) { int irq, intno; =20 @@ -210,7 +210,7 @@ int pic_read_irq(PICCommonState *s) return intno; } =20 -static void pic_init_reset(PICCommonState *s) +static void pic_init_reset(I8259CommonState *s) { pic_reset_common(s); pic_update_irq(s); @@ -218,7 +218,7 @@ static void pic_init_reset(PICCommonState *s) =20 static void pic_reset(DeviceState *dev) { - PICCommonState *s =3D I8259_COMMON(dev); + I8259CommonState *s =3D I8259_COMMON(dev); =20 s->elcr =3D 0; s->ltim =3D 0; @@ -228,7 +228,7 @@ static void pic_reset(DeviceState *dev) static void pic_ioport_write(void *opaque, hwaddr addr64, uint64_t val64, unsigned size) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; uint32_t addr =3D addr64; uint32_t val =3D val64; int priority, cmd, irq; @@ -321,7 +321,7 @@ static void pic_ioport_write(void *opaque, hwaddr addr6= 4, static uint64_t pic_ioport_read(void *opaque, hwaddr addr, unsigned size) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; int ret; =20 if (s->poll) { @@ -348,7 +348,7 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr ad= dr, return ret; } =20 -int pic_get_output(PICCommonState *s) +int pic_get_output(I8259CommonState *s) { return (pic_get_irq(s) >=3D 0); } @@ -356,14 +356,14 @@ int pic_get_output(PICCommonState *s) static void elcr_ioport_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; s->elcr =3D val & s->elcr_mask; } =20 static uint64_t elcr_ioport_read(void *opaque, hwaddr addr, unsigned size) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; return s->elcr; } =20 @@ -387,7 +387,7 @@ static const MemoryRegionOps pic_elcr_ioport_ops =3D { =20 static void pic_realize(DeviceState *dev, Error **errp) { - PICCommonState *s =3D I8259_COMMON(dev); + I8259CommonState *s =3D I8259_COMMON(dev); PICClass *pc =3D PIC_GET_CLASS(dev); =20 memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, @@ -444,7 +444,7 @@ static void i8259_class_init(ObjectClass *klass, const = void *data) =20 static const TypeInfo i8259_info =3D { .name =3D TYPE_I8259, - .instance_size =3D sizeof(PICCommonState), + .instance_size =3D sizeof(I8259CommonState), .parent =3D TYPE_I8259_COMMON, .class_init =3D i8259_class_init, .class_size =3D sizeof(PICClass), diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index e2f997e161..17040bdb1e 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -33,7 +33,7 @@ static int irq_level[16]; static uint64_t irq_count[16]; =20 -void pic_reset_common(PICCommonState *s) +void pic_reset_common(I8259CommonState *s) { s->last_irr =3D 0; s->irr &=3D s->elcr; @@ -55,7 +55,7 @@ void pic_reset_common(PICCommonState *s) =20 static int pic_dispatch_pre_save(void *opaque) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; PICCommonClass *info =3D I8259_COMMON_GET_CLASS(s); =20 if (info->pre_save) { @@ -67,7 +67,7 @@ static int pic_dispatch_pre_save(void *opaque) =20 static int pic_dispatch_post_load(void *opaque, int version_id) { - PICCommonState *s =3D opaque; + I8259CommonState *s =3D opaque; PICCommonClass *info =3D I8259_COMMON_GET_CLASS(s); =20 if (info->post_load) { @@ -78,7 +78,7 @@ static int pic_dispatch_post_load(void *opaque, int versi= on_id) =20 static void pic_common_realize(DeviceState *dev, Error **errp) { - PICCommonState *s =3D I8259_COMMON(dev); + I8259CommonState *s =3D I8259_COMMON(dev); ISADevice *isa =3D ISA_DEVICE(dev); =20 isa_register_ioport(isa, &s->base_io, s->iobase); @@ -118,7 +118,7 @@ void pic_stat_update_irq(int irq, int level) static bool pic_get_statistics(InterruptStatsProvider *obj, uint64_t **irq_counts, unsigned int *nb_irq= s) { - PICCommonState *s =3D I8259_COMMON(obj); + I8259CommonState *s =3D I8259_COMMON(obj); =20 if (s->master) { *irq_counts =3D irq_count; @@ -133,7 +133,7 @@ static bool pic_get_statistics(InterruptStatsProvider *= obj, =20 static void pic_print_info(InterruptStatsProvider *obj, GString *buf) { - PICCommonState *s =3D I8259_COMMON(obj); + I8259CommonState *s =3D I8259_COMMON(obj); =20 pic_dispatch_pre_save(s); g_string_append_printf(buf, "pic%d: irr=3D%02x imr=3D%02x isr=3D%02x h= prio=3D%d " @@ -146,7 +146,7 @@ static void pic_print_info(InterruptStatsProvider *obj,= GString *buf) =20 static bool ltim_state_needed(void *opaque) { - PICCommonState *s =3D I8259_COMMON(opaque); + I8259CommonState *s =3D I8259_COMMON(opaque); =20 return !!s->ltim; } @@ -157,7 +157,7 @@ static const VMStateDescription vmstate_pic_ltim =3D { .minimum_version_id =3D 1, .needed =3D ltim_state_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINT8(ltim, PICCommonState), + VMSTATE_UINT8(ltim, I8259CommonState), VMSTATE_END_OF_LIST() } }; @@ -169,22 +169,22 @@ static const VMStateDescription vmstate_pic_common = =3D { .pre_save =3D pic_dispatch_pre_save, .post_load =3D pic_dispatch_post_load, .fields =3D (const VMStateField[]) { - VMSTATE_UINT8(last_irr, PICCommonState), - VMSTATE_UINT8(irr, PICCommonState), - VMSTATE_UINT8(imr, PICCommonState), - VMSTATE_UINT8(isr, PICCommonState), - VMSTATE_UINT8(priority_add, PICCommonState), - VMSTATE_UINT8(irq_base, PICCommonState), - VMSTATE_UINT8(read_reg_select, PICCommonState), - VMSTATE_UINT8(poll, PICCommonState), - VMSTATE_UINT8(special_mask, PICCommonState), - VMSTATE_UINT8(init_state, PICCommonState), - VMSTATE_UINT8(auto_eoi, PICCommonState), - VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState), - VMSTATE_UINT8(special_fully_nested_mode, PICCommonState), - VMSTATE_UINT8(init4, PICCommonState), - VMSTATE_UINT8(single_mode, PICCommonState), - VMSTATE_UINT8(elcr, PICCommonState), + VMSTATE_UINT8(last_irr, I8259CommonState), + VMSTATE_UINT8(irr, I8259CommonState), + VMSTATE_UINT8(imr, I8259CommonState), + VMSTATE_UINT8(isr, I8259CommonState), + VMSTATE_UINT8(priority_add, I8259CommonState), + VMSTATE_UINT8(irq_base, I8259CommonState), + VMSTATE_UINT8(read_reg_select, I8259CommonState), + VMSTATE_UINT8(poll, I8259CommonState), + VMSTATE_UINT8(special_mask, I8259CommonState), + VMSTATE_UINT8(init_state, I8259CommonState), + VMSTATE_UINT8(auto_eoi, I8259CommonState), + VMSTATE_UINT8(rotate_on_auto_eoi, I8259CommonState), + VMSTATE_UINT8(special_fully_nested_mode, I8259CommonState), + VMSTATE_UINT8(init4, I8259CommonState), + VMSTATE_UINT8(single_mode, I8259CommonState), + VMSTATE_UINT8(elcr, I8259CommonState), VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription * const []) { @@ -194,10 +194,10 @@ static const VMStateDescription vmstate_pic_common = =3D { }; =20 static const Property pic_properties_common[] =3D { - DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1), - DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1), - DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1), - DEFINE_PROP_BIT("master", PICCommonState, master, 0, false), + DEFINE_PROP_UINT32("iobase", I8259CommonState, iobase, -1), + DEFINE_PROP_UINT32("elcr_addr", I8259CommonState, elcr_addr, -1), + DEFINE_PROP_UINT8("elcr_mask", I8259CommonState, elcr_mask, -1), + DEFINE_PROP_BIT("master", I8259CommonState, master, 0, false), }; =20 static void pic_common_class_init(ObjectClass *klass, const void *data) @@ -222,7 +222,7 @@ static void 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X-purgate-type: clean X-purgate-size: 3291 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411566386158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/i8259_internal.h | 4 ++-- hw/i386/kvm/i8259.c | 4 ++-- hw/intc/i8259.c | 2 +- hw/intc/i8259_common.c | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 7a2f9addaf..e039d6f067 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -32,9 +32,9 @@ =20 =20 #define TYPE_I8259_COMMON "i8259-common" -OBJECT_DECLARE_TYPE(I8259CommonState, PICCommonClass, I8259_COMMON) +OBJECT_DECLARE_TYPE(I8259CommonState, I8259CommonClass, I8259_COMMON) =20 -struct PICCommonClass { +struct I8259CommonClass { DeviceClass parent_class; =20 void (*pre_save)(I8259CommonState *s); diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index f10643a120..68607d721d 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -29,7 +29,7 @@ DECLARE_CLASS_CHECKERS(KVMPICClass, KVM_PIC, * @parent_realize: The parent's realizefn. */ struct KVMPICClass { - PICCommonClass parent_class; + I8259CommonClass parent_class; =20 DeviceRealize parent_realize; }; @@ -142,7 +142,7 @@ qemu_irq *kvm_i8259_init(ISABus *bus) static void kvm_i8259_class_init(ObjectClass *klass, const void *data) { KVMPICClass *kpc =3D KVM_PIC_CLASS(klass); - PICCommonClass *k =3D I8259_COMMON_CLASS(klass); + I8259CommonClass *k =3D I8259_COMMON_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 device_class_set_legacy_reset(dc, kvm_pic_reset); diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 45db87a2ad..547e86c5f4 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -44,7 +44,7 @@ DECLARE_CLASS_CHECKERS(PICClass, PIC, * @parent_realize: The parent's realizefn. */ struct PICClass { - PICCommonClass parent_class; + I8259CommonClass parent_class; =20 DeviceRealize parent_realize; }; diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 17040bdb1e..ac8dc7cf00 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -56,7 +56,7 @@ void pic_reset_common(I8259CommonState *s) static int pic_dispatch_pre_save(void *opaque) { I8259CommonState *s =3D opaque; - PICCommonClass *info =3D I8259_COMMON_GET_CLASS(s); + I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(s); =20 if (info->pre_save) { info->pre_save(s); @@ -68,7 +68,7 @@ static int pic_dispatch_pre_save(void *opaque) static int pic_dispatch_post_load(void *opaque, int version_id) { I8259CommonState *s =3D opaque; - PICCommonClass *info =3D I8259_COMMON_GET_CLASS(s); + I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(s); =20 if (info->post_load) { info->post_load(s); @@ -223,7 +223,7 @@ static const TypeInfo pic_common_type =3D { .name =3D TYPE_I8259_COMMON, .parent =3D TYPE_ISA_DEVICE, .instance_size =3D sizeof(I8259CommonState), - .class_size =3D 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tlsNG-ebf023/1792411543-C0CDFB50-5A15A95A/0/0 X-purgate-type: clean X-purgate-size: 2342 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411573319158500 Content-Type: text/plain; charset="utf-8" This is in preparation for its use within a QOM type presenting a single emulated 8259 PIC. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 547e86c5f4..856075a754 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -35,15 +35,15 @@ /*#define DEBUG_IRQ_LATENCY*/ =20 #define TYPE_I8259 "isa-i8259" -typedef struct PICClass PICClass; -DECLARE_CLASS_CHECKERS(PICClass, PIC, +typedef struct I8259Class I8259Class; +DECLARE_CLASS_CHECKERS(I8259Class, I8259, TYPE_I8259) =20 /** - * PICClass: + * I8259Class: * @parent_realize: The parent's realizefn. */ -struct PICClass { +struct I8259Class { I8259CommonClass parent_class; =20 DeviceRealize parent_realize; @@ -388,7 +388,7 @@ static const MemoryRegionOps pic_elcr_ioport_ops =3D { static void pic_realize(DeviceState *dev, Error **errp) { I8259CommonState *s =3D I8259_COMMON(dev); - PICClass *pc =3D PIC_GET_CLASS(dev); + I8259Class *k =3D I8259_GET_CLASS(dev); =20 memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, "pic", 2); @@ -398,7 +398,7 @@ static void pic_realize(DeviceState *dev, Error **errp) qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out)); qdev_init_gpio_in(dev, pic_set_irq, 8); =20 - pc->parent_realize(dev, errp); + k->parent_realize(dev, errp); } =20 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in) @@ -435,7 +435,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_i= n) =20 static void i8259_class_init(ObjectClass *klass, const void *data) { - PICClass *k =3D PIC_CLASS(klass); + I8259Class *k =3D I8259_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); @@ -447,7 +447,7 @@ static const TypeInfo i8259_info =3D { .instance_size =3D sizeof(I8259CommonState), .parent =3D TYPE_I8259_COMMON, .class_init =3D i8259_class_init, - .class_size =3D sizeof(PICClass), + .class_size =3D sizeof(I8259Class), }; =20 static void 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tlsNG-d62444/1792411546-C475B757-A06D7E48/0/0 X-purgate-type: clean X-purgate-size: 3947 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411571563158500 Content-Type: text/plain; charset="utf-8" This device represents a single emulated 8259 PIC and its associated class = and ensures that we can safely embed the device within a container device. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/intc/i8259.h | 8 ++++---- hw/intc/i8259.c | 33 +++++++++++++++++++-------------- 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index 1921a30371..87ccd55a4d 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -3,9 +3,9 @@ =20 /* i8259.c */ =20 -typedef struct I8259CommonState I8259CommonState; +typedef struct I8259State I8259State; =20 -extern I8259CommonState *isa_pic; +extern I8259State *isa_pic; =20 /* * i8259_init() @@ -16,7 +16,7 @@ extern I8259CommonState *isa_pic; */ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in); qemu_irq *kvm_i8259_init(ISABus *bus); -int pic_get_output(I8259CommonState *s); -int pic_read_irq(I8259CommonState *s); +int pic_get_output(I8259State *s); +int pic_read_irq(I8259State *s); =20 #endif diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 856075a754..81827f2734 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -35,9 +35,11 @@ /*#define DEBUG_IRQ_LATENCY*/ =20 #define TYPE_I8259 "isa-i8259" -typedef struct I8259Class I8259Class; -DECLARE_CLASS_CHECKERS(I8259Class, I8259, - TYPE_I8259) +OBJECT_DECLARE_TYPE(I8259State, I8259Class, I8259) + +struct I8259State { + I8259CommonState parent_obj; +}; =20 /** * I8259Class: @@ -52,7 +54,7 @@ struct I8259Class { #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif -I8259CommonState *isa_pic; +I8259State *isa_pic; static I8259CommonState *slave_pic; =20 /* return the highest priority found in mask (highest =3D smallest @@ -170,11 +172,12 @@ static void pic_intack(I8259CommonState *s, int irq) pic_update_irq(s); } =20 -int pic_read_irq(I8259CommonState *s) +int pic_read_irq(I8259State *s) { + I8259CommonState *cs =3D I8259_COMMON(s); int irq, intno; =20 - irq =3D pic_get_irq(s); + irq =3D pic_get_irq(cs); if (irq >=3D 0) { int irq2; =20 @@ -187,16 +190,16 @@ int pic_read_irq(I8259CommonState *s) irq2 =3D 7; } intno =3D slave_pic->irq_base + irq2; - pic_intack(s, irq); + pic_intack(cs, irq); irq =3D irq2 + 8; } else { - intno =3D s->irq_base + irq; - pic_intack(s, irq); + intno =3D cs->irq_base + irq; + pic_intack(cs, irq); } } else { /* spurious IRQ on host controller */ irq =3D 7; - intno =3D s->irq_base + irq; + intno =3D cs->irq_base + irq; } =20 #ifdef DEBUG_IRQ_LATENCY @@ -348,9 +351,11 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr a= ddr, return ret; } =20 -int pic_get_output(I8259CommonState *s) +int pic_get_output(I8259State *s) { - return (pic_get_irq(s) >=3D 0); + I8259CommonState *cs =3D I8259_COMMON(s); + + return (pic_get_irq(cs) >=3D 0); } =20 static void elcr_ioport_write(void *opaque, hwaddr addr, @@ -418,7 +423,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_i= n) irq_set[i] =3D qdev_get_gpio_in(dev, i); } =20 - isa_pic =3D I8259_COMMON(dev); + isa_pic =3D I8259(dev); =20 isadev =3D i8259_init_chip(TYPE_I8259, bus, false); dev =3D DEVICE(isadev); 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b=pn9n4g/181E1gURFv2pfkYvawkYbATKfhsNiN4nAeM6fzUZ5YpNtUQCmWCjx7djbUMEQ433R4AFC6Ecy2lrEnEPb2PM8srxkUSO6uLlnn+hHafHBYqonScmIUZ+acnYngREerINlo57HsCwpCTvEuVvtPBbk2txLwG9h8+uu44H/UX4P7JskRznSYJncoT0FV3qx9ibLIuDDMefORrMYCyhl+8GYNXRiXS9jJ6ngqYzHNFxOXTYmvjDwBsH7XIXKLyQcbDo3S5beBHYBMk4l3HIThdoSPwRXuJVODCc9/Z7ORKwVBuu36JYQksXxPjk/YBGGyYj6ok0rIQ6ItAEAng== Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nutanix.com; From: Mark Cave-Ayland To: pbonzini@redhat.com, richard.henderson@linaro.org, mst@redhat.com, sstabellini@kernel.org, anthony@xenproject.org, edgar.iglesias@gmail.com, qemu-devel@nongnu.org, xen-devel@lists.xenproject.org Subject: [PATCH v3 07/28] i8259.c: always use cs for I8259CommonState variables Date: Mon, 19 Oct 2026 13:04:39 +0100 Message-ID: <20261019120517.1448687-8-mark.caveayland@nutanix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261019120517.1448687-1-mark.caveayland@nutanix.com> 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Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259.c | 192 ++++++++++++++++++++++++------------------------ 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 81827f2734..700412df74 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -59,7 +59,7 @@ static I8259CommonState *slave_pic; =20 /* return the highest priority found in mask (highest =3D smallest number). Return 8 if no irq */ -static int get_priority(I8259CommonState *s, int mask) +static int get_priority(I8259CommonState *cs, int mask) { int priority; =20 @@ -67,63 +67,63 @@ static int get_priority(I8259CommonState *s, int mask) return 8; } priority =3D 0; - while ((mask & (1 << ((priority + s->priority_add) & 7))) =3D=3D 0) { + while ((mask & (1 << ((priority + cs->priority_add) & 7))) =3D=3D 0) { priority++; } return priority; } =20 /* return the pic wanted interrupt. return -1 if none */ -static int pic_get_irq(I8259CommonState *s) +static int pic_get_irq(I8259CommonState *cs) { int mask, cur_priority, priority; =20 - mask =3D s->irr & ~s->imr; - priority =3D get_priority(s, mask); + mask =3D cs->irr & ~cs->imr; + priority =3D get_priority(cs, mask); if (priority =3D=3D 8) { return -1; } /* compute current priority. If special fully nested mode on the master, the IRQ coming from the slave is not taken into account for the priority computation. */ - mask =3D s->isr; - if (s->special_mask) { - mask &=3D ~s->imr; + mask =3D cs->isr; + if (cs->special_mask) { + mask &=3D ~cs->imr; } - if (s->special_fully_nested_mode && s->master) { + if (cs->special_fully_nested_mode && cs->master) { mask &=3D ~(1 << 2); } - cur_priority =3D get_priority(s, mask); + cur_priority =3D get_priority(cs, mask); if (priority < cur_priority) { /* higher priority found: an irq should be generated */ - return (priority + s->priority_add) & 7; + return (priority + cs->priority_add) & 7; } else { return -1; } } =20 /* Update INT output. Must be called every time the output may have change= d. */ -static void pic_update_irq(I8259CommonState *s) +static void pic_update_irq(I8259CommonState *cs) { int irq; =20 - irq =3D pic_get_irq(s); + irq =3D pic_get_irq(cs); if (irq >=3D 0) { - trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); - qemu_irq_raise(s->int_out[0]); + trace_pic_update_irq(cs->master, cs->imr, cs->irr, cs->priority_ad= d); + qemu_irq_raise(cs->int_out[0]); } else { - qemu_irq_lower(s->int_out[0]); + qemu_irq_lower(cs->int_out[0]); } } =20 /* set irq level. If an edge is detected, then the IRR is set to 1 */ static void pic_set_irq(void *opaque, int irq, int level) { - I8259CommonState *s =3D opaque; + I8259CommonState *cs =3D opaque; int mask =3D 1 << irq; - int irq_index =3D s->master ? irq : irq + 8; + int irq_index =3D cs->master ? irq : irq + 8; =20 - trace_pic_set_irq(s->master, irq, level); + trace_pic_set_irq(cs->master, irq, level); pic_stat_update_irq(irq_index, level); =20 #ifdef DEBUG_IRQ_LATENCY @@ -132,44 +132,44 @@ static void pic_set_irq(void *opaque, int irq, int le= vel) } #endif =20 - if (s->ltim || (s->elcr & mask)) { + if (cs->ltim || (cs->elcr & mask)) { /* level triggered */ if (level) { - s->irr |=3D mask; - s->last_irr |=3D mask; + cs->irr |=3D mask; + cs->last_irr |=3D mask; } else { - s->irr &=3D ~mask; - s->last_irr &=3D ~mask; + cs->irr &=3D ~mask; + cs->last_irr &=3D ~mask; } } else { /* edge triggered */ if (level) { - if ((s->last_irr & mask) =3D=3D 0) { - s->irr |=3D mask; + if ((cs->last_irr & mask) =3D=3D 0) { + cs->irr |=3D mask; } - s->last_irr |=3D mask; + cs->last_irr |=3D mask; } else { - s->last_irr &=3D ~mask; + cs->last_irr &=3D ~mask; } } - pic_update_irq(s); + pic_update_irq(cs); } =20 /* acknowledge interrupt 'irq' */ -static void pic_intack(I8259CommonState *s, int irq) +static void pic_intack(I8259CommonState *cs, int irq) { - if (s->auto_eoi) { - if (s->rotate_on_auto_eoi) { - s->priority_add =3D (irq + 1) & 7; + if (cs->auto_eoi) { + if (cs->rotate_on_auto_eoi) { + cs->priority_add =3D (irq + 1) & 7; } } else { - s->isr |=3D (1 << irq); + cs->isr |=3D (1 << irq); } /* We don't clear a level sensitive interrupt here */ - if (!s->ltim && !(s->elcr & (1 << irq))) { - s->irr &=3D ~(1 << irq); + if (!cs->ltim && !(cs->elcr & (1 << irq))) { + cs->irr &=3D ~(1 << irq); } - pic_update_irq(s); + pic_update_irq(cs); } =20 int pic_read_irq(I8259State *s) @@ -213,81 +213,81 @@ int pic_read_irq(I8259State *s) return intno; } =20 -static void pic_init_reset(I8259CommonState *s) +static void pic_init_reset(I8259CommonState *cs) { - pic_reset_common(s); - pic_update_irq(s); + pic_reset_common(cs); + pic_update_irq(cs); } =20 static void pic_reset(DeviceState *dev) { - I8259CommonState *s =3D I8259_COMMON(dev); + I8259CommonState *cs =3D I8259_COMMON(dev); =20 - s->elcr =3D 0; - s->ltim =3D 0; - pic_init_reset(s); + cs->elcr =3D 0; + cs->ltim =3D 0; + pic_init_reset(cs); } =20 static void pic_ioport_write(void *opaque, hwaddr addr64, uint64_t val64, unsigned size) { - I8259CommonState *s =3D opaque; + I8259CommonState *cs =3D opaque; uint32_t addr =3D addr64; uint32_t val =3D val64; int priority, cmd, irq; =20 - trace_pic_ioport_write(s->master, addr, val); + trace_pic_ioport_write(cs->master, addr, val); =20 if (addr =3D=3D 0) { if (val & 0x10) { - pic_init_reset(s); - s->init_state =3D 1; - s->init4 =3D val & 1; - s->single_mode =3D val & 2; - s->ltim =3D val & 8; + pic_init_reset(cs); + cs->init_state =3D 1; + cs->init4 =3D val & 1; + cs->single_mode =3D val & 2; + cs->ltim =3D val & 8; } else if (val & 0x08) { if (val & 0x04) { - s->poll =3D 1; + cs->poll =3D 1; } if (val & 0x02) { - s->read_reg_select =3D val & 1; + cs->read_reg_select =3D val & 1; } if (val & 0x40) { - s->special_mask =3D (val >> 5) & 1; + cs->special_mask =3D (val >> 5) & 1; } } else { cmd =3D val >> 5; switch (cmd) { case 0: case 4: - s->rotate_on_auto_eoi =3D cmd >> 2; + cs->rotate_on_auto_eoi =3D cmd >> 2; break; case 1: /* end of interrupt */ case 5: - priority =3D get_priority(s, s->isr); + priority =3D get_priority(cs, cs->isr); if (priority !=3D 8) { - irq =3D (priority + s->priority_add) & 7; - s->isr &=3D ~(1 << irq); + irq =3D (priority + cs->priority_add) & 7; + cs->isr &=3D ~(1 << irq); if (cmd =3D=3D 5) { - s->priority_add =3D (irq + 1) & 7; + cs->priority_add =3D (irq + 1) & 7; } - pic_update_irq(s); + pic_update_irq(cs); } break; case 3: irq =3D val & 7; - s->isr &=3D ~(1 << irq); - pic_update_irq(s); + cs->isr &=3D ~(1 << irq); + pic_update_irq(cs); break; case 6: - s->priority_add =3D (val + 1) & 7; - pic_update_irq(s); + cs->priority_add =3D (val + 1) & 7; + pic_update_irq(cs); break; case 7: irq =3D val & 7; - s->isr &=3D ~(1 << irq); - s->priority_add =3D (irq + 1) & 7; - pic_update_irq(s); + cs->isr &=3D ~(1 << irq); + cs->priority_add =3D (irq + 1) & 7; + pic_update_irq(cs); break; default: /* no operation */ @@ -295,27 +295,27 @@ static void pic_ioport_write(void *opaque, hwaddr add= r64, } } } else { - switch (s->init_state) { + switch (cs->init_state) { case 0: /* normal mode */ - s->imr =3D val; - pic_update_irq(s); + cs->imr =3D val; + pic_update_irq(cs); break; case 1: - s->irq_base =3D val & 0xf8; - s->init_state =3D s->single_mode ? (s->init4 ? 3 : 0) : 2; + cs->irq_base =3D val & 0xf8; + cs->init_state =3D cs->single_mode ? (cs->init4 ? 3 : 0) : 2; break; case 2: - if (s->init4) { - s->init_state =3D 3; + if (cs->init4) { + cs->init_state =3D 3; } else { - s->init_state =3D 0; + cs->init_state =3D 0; } break; case 3: - s->special_fully_nested_mode =3D (val >> 4) & 1; - s->auto_eoi =3D (val >> 1) & 1; - s->init_state =3D 0; + cs->special_fully_nested_mode =3D (val >> 4) & 1; + cs->auto_eoi =3D (val >> 1) & 1; + cs->init_state =3D 0; break; } } @@ -324,30 +324,30 @@ static void pic_ioport_write(void *opaque, hwaddr add= r64, static uint64_t pic_ioport_read(void *opaque, hwaddr addr, unsigned size) { - I8259CommonState *s =3D opaque; + I8259CommonState *cs =3D opaque; int ret; =20 - if (s->poll) { - ret =3D pic_get_irq(s); + if (cs->poll) { + ret =3D pic_get_irq(cs); if (ret >=3D 0) { - pic_intack(s, ret); + pic_intack(cs, ret); ret |=3D 0x80; } else { ret =3D 0; } - s->poll =3D 0; + cs->poll =3D 0; } else { if (addr =3D=3D 0) { - if (s->read_reg_select) { - ret =3D s->isr; + if (cs->read_reg_select) { + ret =3D cs->isr; } else { - ret =3D s->irr; + ret =3D cs->irr; } } else { - ret =3D s->imr; + ret =3D cs->imr; } } - trace_pic_ioport_read(s->master, addr, ret); + trace_pic_ioport_read(cs->master, addr, ret); return ret; } =20 @@ -361,15 +361,15 @@ int pic_get_output(I8259State *s) static void elcr_ioport_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - I8259CommonState *s =3D opaque; - s->elcr =3D val & s->elcr_mask; + I8259CommonState *cs =3D opaque; + cs->elcr =3D val & cs->elcr_mask; } =20 static uint64_t elcr_ioport_read(void *opaque, hwaddr addr, unsigned size) { - I8259CommonState *s =3D opaque; - return s->elcr; + I8259CommonState *cs =3D opaque; + return cs->elcr; } =20 static const MemoryRegionOps pic_base_ioport_ops =3D { @@ -392,15 +392,15 @@ static const MemoryRegionOps pic_elcr_ioport_ops =3D { =20 static void pic_realize(DeviceState *dev, Error **errp) { - I8259CommonState *s =3D I8259_COMMON(dev); + I8259CommonState *cs =3D I8259_COMMON(dev); I8259Class *k =3D I8259_GET_CLASS(dev); =20 - memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s, + memory_region_init_io(&cs->base_io, OBJECT(cs), &pic_base_ioport_ops, = cs, "pic", 2); - memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s, + memory_region_init_io(&cs->elcr_io, OBJECT(cs), &pic_elcr_ioport_ops, = cs, "elcr", 1); =20 - qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out)); + qdev_init_gpio_out(dev, cs->int_out, ARRAY_SIZE(cs->int_out)); qdev_init_gpio_in(dev, pic_set_irq, 8); =20 k->parent_realize(dev, errp); --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 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tlsNG-c1860d/1792411551-D497287B-78D5DAF2/0/0 X-purgate-type: clean X-purgate-size: 2134 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411573314158500 Content-Type: text/plain; charset="utf-8" This is in preparation for its use within a QOM type presenting a single KVM 8259 PIC. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/i386/kvm/i8259.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 68607d721d..85176dcf80 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -20,15 +20,15 @@ #include "qom/object.h" =20 #define TYPE_KVM_I8259 "kvm-i8259" -typedef struct KVMPICClass KVMPICClass; -DECLARE_CLASS_CHECKERS(KVMPICClass, KVM_PIC, +typedef struct KVMI8259Class KVMI8259Class; +DECLARE_CLASS_CHECKERS(KVMI8259Class, KVM_I8259, TYPE_KVM_I8259) =20 /** - * KVMPICClass: + * KVMI8259Class: * @parent_realize: The parent's realizefn. */ -struct KVMPICClass { +struct KVMI8259Class { I8259CommonClass parent_class; =20 DeviceRealize parent_realize; @@ -123,7 +123,7 @@ static void kvm_pic_set_irq(void *opaque, int irq, int = level) static void kvm_pic_realize(DeviceState *dev, Error **errp) { I8259CommonState *s =3D I8259_COMMON(dev); - KVMPICClass *kpc =3D KVM_PIC_GET_CLASS(dev); + KVMI8259Class *kpc =3D KVM_I8259_GET_CLASS(dev); =20 memory_region_init_io(&s->base_io, OBJECT(dev), NULL, NULL, "kvm-pic",= 2); memory_region_init_io(&s->elcr_io, OBJECT(dev), NULL, NULL, "kvm-elcr"= , 1); @@ -141,7 +141,7 @@ qemu_irq *kvm_i8259_init(ISABus *bus) =20 static void kvm_i8259_class_init(ObjectClass *klass, const void *data) { - KVMPICClass *kpc =3D KVM_PIC_CLASS(klass); + KVMI8259Class *kpc =3D KVM_I8259_CLASS(klass); I8259CommonClass *k =3D I8259_COMMON_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 @@ -156,7 +156,7 @@ static const TypeInfo kvm_i8259_info =3D { .parent =3D TYPE_I8259_COMMON, .instance_size =3D sizeof(I8259CommonState), .class_init =3D kvm_i8259_class_init, - .class_size =3D sizeof(KVMPICClass), + .class_size =3D sizeof(KVMI8259Class), }; =20 static void kvm_pic_register_types(void) --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of 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AW1haW4tMjYxMDE5MDA0OCBTYWx0ZWRfX7oO6HjnoAiz3 opHmYR6ScrbajuVTfrdFJx+tbAX/z+8l3Nh0pVp8xmZMpFNKExp0N7nctPp/Oli+oReXwiqngT4 +1E54BFkOf281CtGgXnFi0y/tah7MC8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDA0OCBTYWx0ZWRfXx/AMR5cWogcj wYnY1ypxVQ0LgxHYhNqeUPcn/IknShRF+bPAgwsqPvfcY8zfomTXvh7RcOTPy+vYsOhmBDvUTz9 BDP9/ty6jgWD6EXdpP1MHy73Hvg2b1e8SMwbbXh1YSt3lx3rUxDUKoMnu0dqS0sABRclMolzg0Z lJcRbTBrXjb25RWSi/a+aO/QkWQm2Z4lwFb+gkhKrDPGUZI6LZsIzPVb//eV+9mj921ErdeizI3 kRfSuND1CR0BzG0DLufX56CSaJInuVG9F/yZZp48RuJHX0xDk0XP247ZKT8nGypgALnrjYQiOKk p6o1KsZIxpx5kdKh4SDa+rgd0GYstm+WarGTHJl4LE5r8ILsi/MsorCipi6au74eZJf3P0zGYKp pIHJImWw/bnh9Ywenyze4E934/iBJV+GSuHkBxWExQyqNyndbkpXCpO2LIi+eJV+gQgrzdeZR7+ LTnMYR1pG4UrwLxytxA== X-Proofpoint-GUID: iRUqzQHItJ1qDvR5G3MT4hV9Pw78pJhf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_03,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Reason: safe X-purgate-ID: tlsNG-42698a/1792411556-1B4D39EA-703576D8/0/0 X-purgate-type: clean X-purgate-size: 1293 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411581861158500 Content-Type: text/plain; charset="utf-8" This device represents a single KVM 8259 PIC and its associated class and ensures that we can safely embed the device within a container device. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/i386/kvm/i8259.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 85176dcf80..8ae5dd39b5 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -20,9 +20,11 @@ #include "qom/object.h" =20 #define TYPE_KVM_I8259 "kvm-i8259" -typedef struct KVMI8259Class KVMI8259Class; -DECLARE_CLASS_CHECKERS(KVMI8259Class, KVM_I8259, - TYPE_KVM_I8259) +OBJECT_DECLARE_TYPE(KVMI8259State, KVMI8259Class, KVM_I8259) + +struct KVMI8259State { + I8259CommonState parent_obj; +}; =20 /** * KVMI8259Class: @@ -154,7 +156,7 @@ static void kvm_i8259_class_init(ObjectClass *klass, co= nst void *data) static const TypeInfo kvm_i8259_info =3D { .name =3D TYPE_KVM_I8259, .parent =3D TYPE_I8259_COMMON, - .instance_size =3D sizeof(I8259CommonState), + .instance_size =3D sizeof(KVMI8259State), .class_init =3D kvm_i8259_class_init, .class_size =3D sizeof(KVMI8259Class), }; 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X-purgate-type: clean X-purgate-size: 5300 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411577528158500 Content-Type: text/plain; charset="utf-8" The use of consistent variable names makes it much easier to follow which fields are being accessed from I8259CommonState. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/i386/kvm/i8259.c | 86 ++++++++++++++++++++++----------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 8ae5dd39b5..86b1ffea4e 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -36,13 +36,13 @@ struct KVMI8259Class { DeviceRealize parent_realize; }; =20 -static void kvm_pic_get(I8259CommonState *s) +static void kvm_pic_get(I8259CommonState *cs) { struct kvm_irqchip chip; struct kvm_pic_state *kpic; int ret; =20 - chip.chip_id =3D s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_= SLAVE; + chip.chip_id =3D cs->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC= _SLAVE; ret =3D kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip); if (ret < 0) { fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(-ret)); @@ -51,50 +51,50 @@ static void kvm_pic_get(I8259CommonState *s) =20 kpic =3D &chip.chip.pic; =20 - s->last_irr =3D kpic->last_irr; - s->irr =3D kpic->irr; - s->imr =3D kpic->imr; - s->isr =3D kpic->isr; - s->priority_add =3D kpic->priority_add; - s->irq_base =3D kpic->irq_base; - s->read_reg_select =3D kpic->read_reg_select; - s->poll =3D kpic->poll; - s->special_mask =3D kpic->special_mask; - s->init_state =3D kpic->init_state; - s->auto_eoi =3D kpic->auto_eoi; - s->rotate_on_auto_eoi =3D kpic->rotate_on_auto_eoi; - s->special_fully_nested_mode =3D kpic->special_fully_nested_mode; - s->init4 =3D kpic->init4; - s->elcr =3D kpic->elcr; - s->elcr_mask =3D kpic->elcr_mask; + cs->last_irr =3D kpic->last_irr; + cs->irr =3D kpic->irr; + cs->imr =3D kpic->imr; + cs->isr =3D kpic->isr; + cs->priority_add =3D kpic->priority_add; + cs->irq_base =3D kpic->irq_base; + cs->read_reg_select =3D kpic->read_reg_select; + cs->poll =3D kpic->poll; + cs->special_mask =3D kpic->special_mask; + cs->init_state =3D kpic->init_state; + cs->auto_eoi =3D kpic->auto_eoi; + cs->rotate_on_auto_eoi =3D kpic->rotate_on_auto_eoi; + cs->special_fully_nested_mode =3D kpic->special_fully_nested_mode; + cs->init4 =3D kpic->init4; + cs->elcr =3D kpic->elcr; + cs->elcr_mask =3D kpic->elcr_mask; } =20 -static void kvm_pic_put(I8259CommonState *s) +static void kvm_pic_put(I8259CommonState *cs) { struct kvm_irqchip chip; struct kvm_pic_state *kpic; int ret; =20 - chip.chip_id =3D s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_= SLAVE; + chip.chip_id =3D cs->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC= _SLAVE; =20 kpic =3D &chip.chip.pic; =20 - kpic->last_irr =3D s->last_irr; - kpic->irr =3D s->irr; - kpic->imr =3D s->imr; - kpic->isr =3D s->isr; - kpic->priority_add =3D s->priority_add; - kpic->irq_base =3D s->irq_base; - kpic->read_reg_select =3D s->read_reg_select; - kpic->poll =3D s->poll; - kpic->special_mask =3D s->special_mask; - kpic->init_state =3D s->init_state; - kpic->auto_eoi =3D s->auto_eoi; - kpic->rotate_on_auto_eoi =3D s->rotate_on_auto_eoi; - kpic->special_fully_nested_mode =3D s->special_fully_nested_mode; - kpic->init4 =3D s->init4; - kpic->elcr =3D s->elcr; - kpic->elcr_mask =3D s->elcr_mask; + kpic->last_irr =3D cs->last_irr; + kpic->irr =3D cs->irr; + kpic->imr =3D cs->imr; + kpic->isr =3D cs->isr; + kpic->priority_add =3D cs->priority_add; + kpic->irq_base =3D cs->irq_base; + kpic->read_reg_select =3D cs->read_reg_select; + kpic->poll =3D cs->poll; + kpic->special_mask =3D cs->special_mask; + kpic->init_state =3D cs->init_state; + kpic->auto_eoi =3D cs->auto_eoi; + kpic->rotate_on_auto_eoi =3D cs->rotate_on_auto_eoi; + kpic->special_fully_nested_mode =3D cs->special_fully_nested_mode; + kpic->init4 =3D cs->init4; + kpic->elcr =3D cs->elcr; + kpic->elcr_mask =3D cs->elcr_mask; =20 ret =3D kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip); if (ret < 0) { @@ -105,12 +105,12 @@ static void kvm_pic_put(I8259CommonState *s) =20 static void kvm_pic_reset(DeviceState *dev) { - I8259CommonState *s =3D I8259_COMMON(dev); + I8259CommonState *cs =3D I8259_COMMON(dev); =20 - s->elcr =3D 0; - pic_reset_common(s); + cs->elcr =3D 0; + pic_reset_common(cs); =20 - kvm_pic_put(s); + kvm_pic_put(cs); } =20 static void kvm_pic_set_irq(void *opaque, int irq, int level) @@ -124,11 +124,11 @@ static void kvm_pic_set_irq(void *opaque, int irq, in= t level) =20 static void kvm_pic_realize(DeviceState *dev, Error **errp) { - I8259CommonState *s =3D I8259_COMMON(dev); + I8259CommonState *cs =3D I8259_COMMON(dev); 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tlsNG-42698a/1792411562-184CB9EA-F3662C0F/0/0 X-purgate-type: clean X-purgate-size: 5702 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411595817158500 Content-Type: text/plain; charset="utf-8" The use of consistent variable names makes it much easier to follow which fields are being accessed from I8259CommonState. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/i8259_internal.h | 6 +-- hw/intc/i8259_common.c | 74 ++++++++++++++++----------------- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index e039d6f067..71fdd74266 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -37,8 +37,8 @@ OBJECT_DECLARE_TYPE(I8259CommonState, I8259CommonClass, I= 8259_COMMON) struct I8259CommonClass { DeviceClass parent_class; =20 - void (*pre_save)(I8259CommonState *s); - void (*post_load)(I8259CommonState *s); + void (*pre_save)(I8259CommonState *cs); + void (*post_load)(I8259CommonState *cs); }; =20 struct I8259CommonState { @@ -70,7 +70,7 @@ struct I8259CommonState { MemoryRegion elcr_io; }; =20 -void pic_reset_common(I8259CommonState *s); +void pic_reset_common(I8259CommonState *cs); ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); void pic_stat_update_irq(int irq, int level); =20 diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index ac8dc7cf00..705a28ecbf 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -33,33 +33,33 @@ static int irq_level[16]; static uint64_t irq_count[16]; =20 -void pic_reset_common(I8259CommonState *s) +void pic_reset_common(I8259CommonState *cs) { - s->last_irr =3D 0; - s->irr &=3D s->elcr; - s->imr =3D 0; - s->isr =3D 0; - s->priority_add =3D 0; - s->irq_base =3D 0; - s->read_reg_select =3D 0; - s->poll =3D 0; - s->special_mask =3D 0; - s->init_state =3D 0; - s->auto_eoi =3D 0; - s->rotate_on_auto_eoi =3D 0; - s->special_fully_nested_mode =3D 0; - s->init4 =3D 0; - s->single_mode =3D 0; + cs->last_irr =3D 0; + cs->irr &=3D cs->elcr; + cs->imr =3D 0; + cs->isr =3D 0; + cs->priority_add =3D 0; + cs->irq_base =3D 0; + cs->read_reg_select =3D 0; + cs->poll =3D 0; + cs->special_mask =3D 0; + cs->init_state =3D 0; + cs->auto_eoi =3D 0; + cs->rotate_on_auto_eoi =3D 0; + cs->special_fully_nested_mode =3D 0; + cs->init4 =3D 0; + cs->single_mode =3D 0; /* Note: ELCR and LTIM are not reset */ } =20 static int pic_dispatch_pre_save(void *opaque) { - I8259CommonState *s =3D opaque; - I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(s); + I8259CommonState *cs =3D opaque; + I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(cs); =20 if (info->pre_save) { - info->pre_save(s); + info->pre_save(cs); } =20 return 0; @@ -67,26 +67,26 @@ static int pic_dispatch_pre_save(void *opaque) =20 static int pic_dispatch_post_load(void *opaque, int version_id) { - I8259CommonState *s =3D opaque; - I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(s); + I8259CommonState *cs =3D opaque; + I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(cs); =20 if (info->post_load) { - info->post_load(s); + info->post_load(cs); } return 0; } =20 static void pic_common_realize(DeviceState *dev, Error **errp) { - I8259CommonState *s =3D I8259_COMMON(dev); + I8259CommonState *cs =3D I8259_COMMON(dev); ISADevice *isa =3D ISA_DEVICE(dev); =20 - isa_register_ioport(isa, &s->base_io, s->iobase); - if (s->elcr_addr !=3D -1) { - isa_register_ioport(isa, &s->elcr_io, s->elcr_addr); + isa_register_ioport(isa, &cs->base_io, cs->iobase); + if (cs->elcr_addr !=3D -1) { + isa_register_ioport(isa, &cs->elcr_io, cs->elcr_addr); } =20 - qdev_set_legacy_instance_id(dev, s->iobase, 1); + qdev_set_legacy_instance_id(dev, cs->iobase, 1); } =20 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) @@ -118,9 +118,9 @@ void pic_stat_update_irq(int irq, int level) static bool pic_get_statistics(InterruptStatsProvider *obj, uint64_t **irq_counts, unsigned int *nb_irq= s) { - I8259CommonState *s =3D I8259_COMMON(obj); + I8259CommonState *cs =3D I8259_COMMON(obj); =20 - if (s->master) { + if (cs->master) { *irq_counts =3D irq_count; *nb_irqs =3D ARRAY_SIZE(irq_count); } else { @@ -133,22 +133,22 @@ static bool pic_get_statistics(InterruptStatsProvider= *obj, =20 static void pic_print_info(InterruptStatsProvider *obj, GString *buf) { - I8259CommonState *s =3D I8259_COMMON(obj); + I8259CommonState *cs =3D I8259_COMMON(obj); =20 - pic_dispatch_pre_save(s); + pic_dispatch_pre_save(cs); g_string_append_printf(buf, "pic%d: irr=3D%02x imr=3D%02x isr=3D%02x h= prio=3D%d " "irq_base=3D%02x rr_sel=3D%d elcr=3D%02x fnm=3D= %d\n", - s->master ? 0 : 1, s->irr, s->imr, s->isr, - s->priority_add, - s->irq_base, s->read_reg_select, s->elcr, - s->special_fully_nested_mode); + cs->master ? 0 : 1, cs->irr, cs->imr, cs->isr, + cs->priority_add, + cs->irq_base, cs->read_reg_select, cs->elcr, + cs->special_fully_nested_mode); } =20 static bool ltim_state_needed(void *opaque) { - I8259CommonState *s =3D I8259_COMMON(opaque); + I8259CommonState *cs =3D I8259_COMMON(opaque); =20 - return !!s->ltim; + return !!cs->ltim; } =20 static const VMStateDescription vmstate_pic_ltim =3D { --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org 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Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/i8259_internal.h | 4 +-- hw/i386/kvm/i8259.c | 4 +-- hw/intc/i8259.c | 4 +-- hw/intc/i8259_common.c | 49 +++++++++++++++++---------------- 4 files changed, 31 insertions(+), 30 deletions(-) diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 71fdd74266..644508a44e 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -70,8 +70,8 @@ struct I8259CommonState { MemoryRegion elcr_io; }; =20 -void pic_reset_common(I8259CommonState *cs); +void i8259_common_reset(I8259CommonState *cs); ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); -void pic_stat_update_irq(int irq, int level); +void i8259_stat_update_irq(int irq, int level); =20 #endif /* QEMU_I8259_INTERNAL_H */ diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 86b1ffea4e..3a960e48e6 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -108,7 +108,7 @@ static void kvm_pic_reset(DeviceState *dev) I8259CommonState *cs =3D I8259_COMMON(dev); =20 cs->elcr =3D 0; - pic_reset_common(cs); + i8259_common_reset(cs); =20 kvm_pic_put(cs); } @@ -117,7 +117,7 @@ static void kvm_pic_set_irq(void *opaque, int irq, int = level) { int delivered; =20 - pic_stat_update_irq(irq, level); + i8259_stat_update_irq(irq, level); delivered =3D kvm_set_irq(kvm_state, irq, level); kvm_report_irq_delivered(delivered); } diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 700412df74..97ecb77407 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -124,7 +124,7 @@ static void pic_set_irq(void *opaque, int irq, int leve= l) int irq_index =3D cs->master ? irq : irq + 8; =20 trace_pic_set_irq(cs->master, irq, level); - pic_stat_update_irq(irq_index, level); + i8259_stat_update_irq(irq_index, level); =20 #ifdef DEBUG_IRQ_LATENCY if (level) { @@ -215,7 +215,7 @@ int pic_read_irq(I8259State *s) =20 static void pic_init_reset(I8259CommonState *cs) { - pic_reset_common(cs); + i8259_common_reset(cs); pic_update_irq(cs); } =20 diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 705a28ecbf..31bd663439 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -33,7 +33,7 @@ static int irq_level[16]; static uint64_t irq_count[16]; =20 -void pic_reset_common(I8259CommonState *cs) +void i8259_common_reset(I8259CommonState *cs) { cs->last_irr =3D 0; cs->irr &=3D cs->elcr; @@ -53,7 +53,7 @@ void pic_reset_common(I8259CommonState *cs) /* Note: ELCR and LTIM are not reset */ } =20 -static int pic_dispatch_pre_save(void *opaque) +static int i8259_common_dispatch_pre_save(void *opaque) { I8259CommonState *cs =3D opaque; I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(cs); @@ -65,7 +65,7 @@ static int pic_dispatch_pre_save(void *opaque) return 0; } =20 -static int pic_dispatch_post_load(void *opaque, int version_id) +static int i8259_common_dispatch_post_load(void *opaque, int version_id) { I8259CommonState *cs =3D opaque; I8259CommonClass *info =3D I8259_COMMON_GET_CLASS(cs); @@ -76,7 +76,7 @@ static int pic_dispatch_post_load(void *opaque, int versi= on_id) return 0; } =20 -static void pic_common_realize(DeviceState *dev, Error **errp) +static void i8259_common_realize(DeviceState *dev, Error **errp) { I8259CommonState *cs =3D I8259_COMMON(dev); ISADevice *isa =3D ISA_DEVICE(dev); @@ -105,7 +105,7 @@ ISADevice *i8259_init_chip(const char *name, ISABus *bu= s, bool master) return isadev; } =20 -void pic_stat_update_irq(int irq, int level) +void i8259_stat_update_irq(int irq, int level) { if (level !=3D irq_level[irq]) { irq_level[irq] =3D level; @@ -115,8 +115,9 @@ void pic_stat_update_irq(int irq, int level) } } =20 -static bool pic_get_statistics(InterruptStatsProvider *obj, - uint64_t **irq_counts, unsigned int *nb_irq= s) +static bool i8259_common_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, + unsigned int *nb_irqs) { I8259CommonState *cs =3D I8259_COMMON(obj); =20 @@ -131,11 +132,11 @@ static bool pic_get_statistics(InterruptStatsProvider= *obj, return true; } =20 -static void pic_print_info(InterruptStatsProvider *obj, GString *buf) +static void i8259_common_print_info(InterruptStatsProvider *obj, GString *= buf) { I8259CommonState *cs =3D I8259_COMMON(obj); =20 - pic_dispatch_pre_save(cs); + i8259_common_dispatch_pre_save(cs); g_string_append_printf(buf, "pic%d: irr=3D%02x imr=3D%02x isr=3D%02x h= prio=3D%d " "irq_base=3D%02x rr_sel=3D%d elcr=3D%02x fnm=3D= %d\n", cs->master ? 0 : 1, cs->irr, cs->imr, cs->isr, @@ -162,12 +163,12 @@ static const VMStateDescription vmstate_pic_ltim =3D { } }; =20 -static const VMStateDescription vmstate_pic_common =3D { +static const VMStateDescription vmstate_i8259_common =3D { .name =3D "i8259", .version_id =3D 1, .minimum_version_id =3D 1, - .pre_save =3D pic_dispatch_pre_save, - .post_load =3D pic_dispatch_post_load, + .pre_save =3D i8259_common_dispatch_pre_save, + .post_load =3D i8259_common_dispatch_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT8(last_irr, I8259CommonState), VMSTATE_UINT8(irr, I8259CommonState), @@ -193,21 +194,21 @@ static const VMStateDescription vmstate_pic_common = =3D { } }; =20 -static const Property pic_properties_common[] =3D { +static const Property i8259_common_properties[] =3D { DEFINE_PROP_UINT32("iobase", I8259CommonState, iobase, -1), DEFINE_PROP_UINT32("elcr_addr", I8259CommonState, elcr_addr, -1), DEFINE_PROP_UINT8("elcr_mask", I8259CommonState, elcr_mask, -1), DEFINE_PROP_BIT("master", I8259CommonState, master, 0, false), }; =20 -static void pic_common_class_init(ObjectClass *klass, const void *data) +static void i8259_common_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); =20 - dc->vmsd =3D &vmstate_pic_common; - device_class_set_props(dc, pic_properties_common); - dc->realize =3D pic_common_realize; + dc->vmsd =3D &vmstate_i8259_common; + device_class_set_props(dc, i8259_common_properties); + dc->realize =3D i8259_common_realize; /* * Reason: unlike ordinary ISA devices, the PICs need additional * wiring: its IRQ input lines are set up by board code, and the @@ -215,16 +216,16 @@ static void pic_common_class_init(ObjectClass *klass,= const void *data) * code. */ dc->user_creatable =3D false; - ic->get_statistics =3D pic_get_statistics; - ic->print_info =3D pic_print_info; + ic->get_statistics =3D i8259_common_get_statistics; + ic->print_info =3D i8259_common_print_info; } =20 -static const TypeInfo pic_common_type =3D { +static const TypeInfo i8259_common_type =3D { .name =3D TYPE_I8259_COMMON, .parent =3D TYPE_ISA_DEVICE, .instance_size =3D sizeof(I8259CommonState), .class_size =3D sizeof(I8259CommonClass), - .class_init =3D pic_common_class_init, + .class_init =3D i8259_common_class_init, .abstract =3D true, .interfaces =3D (const InterfaceInfo[]) { { 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X-purgate-type: clean X-purgate-size: 11620 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411614505158500 Content-Type: text/plain; charset="utf-8" This ensures consistency with our normal QOM-based naming convention. Also update the trace event names for those trace events that originate from a single i8259 chip. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259.c | 104 +++++++++++++++++++++---------------------- hw/intc/trace-events | 8 ++-- 2 files changed, 56 insertions(+), 56 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 97ecb77407..4b34e5a649 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -73,8 +73,8 @@ static int get_priority(I8259CommonState *cs, int mask) return priority; } =20 -/* return the pic wanted interrupt. return -1 if none */ -static int pic_get_irq(I8259CommonState *cs) +/* return the i8259 wanted interrupt. return -1 if none */ +static int i8259_get_irq(I8259CommonState *cs) { int mask, cur_priority, priority; =20 @@ -103,13 +103,13 @@ static int pic_get_irq(I8259CommonState *cs) } =20 /* Update INT output. Must be called every time the output may have change= d. */ -static void pic_update_irq(I8259CommonState *cs) +static void i8259_update_irq(I8259CommonState *cs) { int irq; =20 - irq =3D pic_get_irq(cs); + irq =3D i8259_get_irq(cs); if (irq >=3D 0) { - trace_pic_update_irq(cs->master, cs->imr, cs->irr, cs->priority_ad= d); + trace_i8259_update_irq(cs->master, cs->imr, cs->irr, cs->priority_= add); qemu_irq_raise(cs->int_out[0]); } else { qemu_irq_lower(cs->int_out[0]); @@ -117,13 +117,13 @@ static void pic_update_irq(I8259CommonState *cs) } =20 /* set irq level. If an edge is detected, then the IRR is set to 1 */ -static void pic_set_irq(void *opaque, int irq, int level) +static void i8259_set_irq(void *opaque, int irq, int level) { I8259CommonState *cs =3D opaque; int mask =3D 1 << irq; int irq_index =3D cs->master ? irq : irq + 8; =20 - trace_pic_set_irq(cs->master, irq, level); + trace_i8259_set_irq(cs->master, irq, level); i8259_stat_update_irq(irq_index, level); =20 #ifdef DEBUG_IRQ_LATENCY @@ -152,11 +152,11 @@ static void pic_set_irq(void *opaque, int irq, int le= vel) cs->last_irr &=3D ~mask; } } - pic_update_irq(cs); + i8259_update_irq(cs); } =20 /* acknowledge interrupt 'irq' */ -static void pic_intack(I8259CommonState *cs, int irq) +static void i8259_intack(I8259CommonState *cs, int irq) { if (cs->auto_eoi) { if (cs->rotate_on_auto_eoi) { @@ -169,7 +169,7 @@ static void pic_intack(I8259CommonState *cs, int irq) if (!cs->ltim && !(cs->elcr & (1 << irq))) { cs->irr &=3D ~(1 << irq); } - pic_update_irq(cs); + i8259_update_irq(cs); } =20 int pic_read_irq(I8259State *s) @@ -177,24 +177,24 @@ int pic_read_irq(I8259State *s) I8259CommonState *cs =3D I8259_COMMON(s); int irq, intno; =20 - irq =3D pic_get_irq(cs); + irq =3D i8259_get_irq(cs); if (irq >=3D 0) { int irq2; =20 if (irq =3D=3D 2) { - irq2 =3D pic_get_irq(slave_pic); + irq2 =3D i8259_get_irq(slave_pic); if (irq2 >=3D 0) { - pic_intack(slave_pic, irq2); + i8259_intack(slave_pic, irq2); } else { /* spurious IRQ on slave controller */ irq2 =3D 7; } intno =3D slave_pic->irq_base + irq2; - pic_intack(cs, irq); + i8259_intack(cs, irq); irq =3D irq2 + 8; } else { intno =3D cs->irq_base + irq; - pic_intack(cs, irq); + i8259_intack(cs, irq); } } else { /* spurious IRQ on host controller */ @@ -213,34 +213,34 @@ int pic_read_irq(I8259State *s) return intno; } =20 -static void pic_init_reset(I8259CommonState *cs) +static void i8259_init_reset(I8259CommonState *cs) { i8259_common_reset(cs); - pic_update_irq(cs); + i8259_update_irq(cs); } =20 -static void pic_reset(DeviceState *dev) +static void i8259_reset(DeviceState *dev) { I8259CommonState *cs =3D I8259_COMMON(dev); =20 cs->elcr =3D 0; cs->ltim =3D 0; - pic_init_reset(cs); + i8259_init_reset(cs); } =20 -static void pic_ioport_write(void *opaque, hwaddr addr64, - uint64_t val64, unsigned size) +static void i8259_base_ioport_write(void *opaque, hwaddr addr64, + uint64_t val64, unsigned size) { I8259CommonState *cs =3D opaque; uint32_t addr =3D addr64; uint32_t val =3D val64; int priority, cmd, irq; =20 - trace_pic_ioport_write(cs->master, addr, val); + trace_i8259_ioport_write(cs->master, addr, val); =20 if (addr =3D=3D 0) { if (val & 0x10) { - pic_init_reset(cs); + i8259_init_reset(cs); cs->init_state =3D 1; cs->init4 =3D val & 1; cs->single_mode =3D val & 2; @@ -271,23 +271,23 @@ static void pic_ioport_write(void *opaque, hwaddr add= r64, if (cmd =3D=3D 5) { cs->priority_add =3D (irq + 1) & 7; } - pic_update_irq(cs); + i8259_update_irq(cs); } break; case 3: irq =3D val & 7; cs->isr &=3D ~(1 << irq); - pic_update_irq(cs); + i8259_update_irq(cs); break; case 6: cs->priority_add =3D (val + 1) & 7; - pic_update_irq(cs); + i8259_update_irq(cs); break; case 7: irq =3D val & 7; cs->isr &=3D ~(1 << irq); cs->priority_add =3D (irq + 1) & 7; - pic_update_irq(cs); + i8259_update_irq(cs); break; default: /* no operation */ @@ -299,7 +299,7 @@ static void pic_ioport_write(void *opaque, hwaddr addr6= 4, case 0: /* normal mode */ cs->imr =3D val; - pic_update_irq(cs); + i8259_update_irq(cs); break; case 1: cs->irq_base =3D val & 0xf8; @@ -321,16 +321,16 @@ static void pic_ioport_write(void *opaque, hwaddr add= r64, } } =20 -static uint64_t pic_ioport_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t i8259_base_ioport_read(void *opaque, hwaddr addr, + unsigned size) { I8259CommonState *cs =3D opaque; int ret; =20 if (cs->poll) { - ret =3D pic_get_irq(cs); + ret =3D i8259_get_irq(cs); if (ret >=3D 0) { - pic_intack(cs, ret); + i8259_intack(cs, ret); ret |=3D 0x80; } else { ret =3D 0; @@ -347,7 +347,7 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr ad= dr, ret =3D cs->imr; } } - trace_pic_ioport_read(cs->master, addr, ret); + trace_i8259_ioport_read(cs->master, addr, ret); return ret; } =20 @@ -355,53 +355,53 @@ int pic_get_output(I8259State *s) { I8259CommonState *cs =3D I8259_COMMON(s); =20 - return (pic_get_irq(cs) >=3D 0); + return (i8259_get_irq(cs) >=3D 0); } =20 -static void elcr_ioport_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void i8259_elcr_ioport_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { I8259CommonState *cs =3D opaque; cs->elcr =3D val & cs->elcr_mask; } =20 -static uint64_t elcr_ioport_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t i8259_elcr_ioport_read(void *opaque, hwaddr addr, + unsigned size) { I8259CommonState *cs =3D opaque; return cs->elcr; } =20 -static const MemoryRegionOps pic_base_ioport_ops =3D { - .read =3D pic_ioport_read, - .write =3D pic_ioport_write, +static const MemoryRegionOps i8259_base_ioport_ops =3D { + .read =3D i8259_base_ioport_read, + .write =3D i8259_base_ioport_write, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, }; =20 -static const MemoryRegionOps pic_elcr_ioport_ops =3D { - .read =3D elcr_ioport_read, - .write =3D elcr_ioport_write, +static const MemoryRegionOps i8259_elcr_ioport_ops =3D { + .read =3D i8259_elcr_ioport_read, + .write =3D i8259_elcr_ioport_write, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, }; =20 -static void pic_realize(DeviceState *dev, Error **errp) +static void i8259_realize(DeviceState *dev, Error **errp) { I8259CommonState *cs =3D I8259_COMMON(dev); I8259Class *k =3D I8259_GET_CLASS(dev); =20 - memory_region_init_io(&cs->base_io, OBJECT(cs), &pic_base_ioport_ops, = cs, + memory_region_init_io(&cs->base_io, OBJECT(cs), &i8259_base_ioport_ops= , cs, "pic", 2); - memory_region_init_io(&cs->elcr_io, OBJECT(cs), &pic_elcr_ioport_ops, = cs, + memory_region_init_io(&cs->elcr_io, OBJECT(cs), &i8259_elcr_ioport_ops= , cs, "elcr", 1); =20 qdev_init_gpio_out(dev, cs->int_out, ARRAY_SIZE(cs->int_out)); - qdev_init_gpio_in(dev, pic_set_irq, 8); + qdev_init_gpio_in(dev, i8259_set_irq, 8); =20 k->parent_realize(dev, errp); } @@ -443,8 +443,8 @@ static void i8259_class_init(ObjectClass *klass, const = void *data) I8259Class *k =3D I8259_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - device_class_set_parent_realize(dc, pic_realize, &k->parent_realize); - device_class_set_legacy_reset(dc, pic_reset); + device_class_set_parent_realize(dc, i8259_realize, &k->parent_realize); + device_class_set_legacy_reset(dc, i8259_reset); } =20 static const TypeInfo i8259_info =3D { @@ -455,9 +455,9 @@ static const TypeInfo i8259_info =3D { .class_size =3D sizeof(I8259Class), }; =20 -static void pic_register_types(void) +static void i8259_register_types(void) { type_register_static(&i8259_info); } =20 -type_init(pic_register_types) +type_init(i8259_register_types) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 7512c6e600..003924ddb4 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -1,11 +1,11 @@ # See docs/devel/tracing.rst for syntax documentation. =20 # i8259.c -pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) "maste= r %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 -pic_set_irq(bool master, int irq, int level) "master %d irq %d level %d" +i8259_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) "mas= ter %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 +i8259_set_irq(bool master, int irq, int level) "master %d irq %d level %d" +i8259_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d ad= dr 0x%"PRIx64" val 0x%"PRIx64 +i8259_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%= "PRIx64" val 0x%x" pic_interrupt(int irq, int intno) "irq %d intno %d" -pic_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d addr= 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X-purgate-type: clean X-purgate-size: 2803 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411591896158500 Content-Type: text/plain; charset="utf-8" This ensures consistency with our normal QOM-based naming convention. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/i386/kvm/i8259.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 3a960e48e6..952f58be11 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -36,7 +36,7 @@ struct KVMI8259Class { DeviceRealize parent_realize; }; =20 -static void kvm_pic_get(I8259CommonState *cs) +static void kvm_i8259_get(I8259CommonState *cs) { struct kvm_irqchip chip; struct kvm_pic_state *kpic; @@ -69,7 +69,7 @@ static void kvm_pic_get(I8259CommonState *cs) cs->elcr_mask =3D kpic->elcr_mask; } =20 -static void kvm_pic_put(I8259CommonState *cs) +static void kvm_i8259_put(I8259CommonState *cs) { struct kvm_irqchip chip; struct kvm_pic_state *kpic; @@ -103,14 +103,14 @@ static void kvm_pic_put(I8259CommonState *cs) } } =20 -static void kvm_pic_reset(DeviceState *dev) +static void kvm_i8259_reset(DeviceState *dev) { I8259CommonState *cs =3D I8259_COMMON(dev); =20 cs->elcr =3D 0; i8259_common_reset(cs); =20 - kvm_pic_put(cs); + kvm_i8259_put(cs); } =20 static void kvm_pic_set_irq(void *opaque, int irq, int level) @@ -122,7 +122,7 @@ static void kvm_pic_set_irq(void *opaque, int irq, int = level) kvm_report_irq_delivered(delivered); } =20 -static void kvm_pic_realize(DeviceState *dev, Error **errp) +static void kvm_i8259_realize(DeviceState *dev, Error **errp) { I8259CommonState *cs =3D I8259_COMMON(dev); KVMI8259Class *kpc =3D KVM_I8259_GET_CLASS(dev); @@ -147,10 +147,11 @@ static void kvm_i8259_class_init(ObjectClass *klass, = const void *data) I8259CommonClass *k =3D I8259_COMMON_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - device_class_set_legacy_reset(dc, kvm_pic_reset); - device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_real= ize); - k->pre_save =3D kvm_pic_get; - k->post_load =3D kvm_pic_put; + device_class_set_legacy_reset(dc, kvm_i8259_reset); + device_class_set_parent_realize(dc, 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tlsNG-720697/1792411577-F3ABD2AC-6E3D95A9/0/0 X-purgate-type: clean X-purgate-size: 1595 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411603862158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259_common.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 31bd663439..09b761321a 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -220,22 +220,19 @@ static void i8259_common_class_init(ObjectClass *klas= s, const void *data) ic->print_info =3D i8259_common_print_info; } =20 -static const TypeInfo i8259_common_type =3D { - .name =3D TYPE_I8259_COMMON, - .parent =3D TYPE_ISA_DEVICE, - .instance_size =3D sizeof(I8259CommonState), - .class_size =3D sizeof(I8259CommonClass), - .class_init =3D i8259_common_class_init, - .abstract =3D true, - .interfaces =3D (const InterfaceInfo[]) { - { TYPE_INTERRUPT_STATS_PROVIDER }, - { } +static const TypeInfo i8259_common_type_infos[] =3D { + { + .name =3D TYPE_I8259_COMMON, + .parent =3D TYPE_ISA_DEVICE, + .instance_size =3D sizeof(I8259CommonState), + .class_size =3D sizeof(I8259CommonClass), + .class_init =3D i8259_common_class_init, + .abstract =3D true, + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, }, }; =20 -static void i8259_common_register_types(void) -{ - type_register_static(&i8259_common_type); -} - -type_init(i8259_common_register_types) +DEFINE_TYPES(i8259_common_type_infos) --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nutanix.com); dmarc=pass(p=none dis=none) header.from=nutanix.com ARC-Seal: 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X-ZM-MESSAGEID: 1792411671337158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 4b34e5a649..e5fa0f2e5e 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -447,17 +447,14 @@ static void i8259_class_init(ObjectClass *klass, cons= t void *data) device_class_set_legacy_reset(dc, i8259_reset); } =20 -static const TypeInfo i8259_info =3D { - .name =3D TYPE_I8259, - .instance_size =3D sizeof(I8259State), - .parent =3D TYPE_I8259_COMMON, - .class_init =3D i8259_class_init, - .class_size =3D sizeof(I8259Class), +static const TypeInfo i8259_type_infos[] =3D { + { + .name =3D TYPE_I8259, + .instance_size =3D sizeof(I8259State), + .parent =3D TYPE_I8259_COMMON, + .class_init =3D i8259_class_init, + .class_size =3D sizeof(I8259Class), + }, }; =20 -static void i8259_register_types(void) -{ - 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X-purgate-size: 1426 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411606004158500 Content-Type: text/plain; charset="utf-8" This is required for implementing a container device containing one or more= ISA devices to ensure that the refcount is handled correctly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/isa.h | 1 + hw/isa/isa-bus.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index 94bff33fcc..a3d54110fd 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -82,6 +82,7 @@ IsaDma *isa_bus_get_dma(ISABus *bus, int nchan); qemu_irq isa_bus_get_irq(ISABus *bus, unsigned irqnum); ISADevice *isa_new(const char *name); ISADevice *isa_try_new(const char *name); +bool isa_realize(ISADevice *dev, ISABus *bus, Error **errp); bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp); ISADevice *isa_create_simple(ISABus *bus, const char *name); =20 diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c index 7e6d2ce5a9..102f4a0e0d 100644 --- a/hw/isa/isa-bus.c +++ b/hw/isa/isa-bus.c @@ -172,6 +172,11 @@ ISADevice *isa_create_simple(ISABus *bus, const char *= name) return dev; } =20 +bool isa_realize(ISADevice *dev, ISABus *bus, Error **errp) +{ + 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X-purgate-size: 5658 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411644757158500 Content-Type: text/plain; charset="utf-8" This device represents a PIC for an x86 machine consisting of 2 cascaded i8= 259 devices wired accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259.c | 133 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 118 insertions(+), 15 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index e5fa0f2e5e..fe524efbce 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -25,7 +25,9 @@ #include "qemu/osdep.h" #include "hw/intc/i8259.h" #include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" #include "hw/isa/isa.h" +#include "qapi/error.h" #include "qemu/timer.h" #include "qemu/log.h" #include "hw/isa/i8259_internal.h" @@ -51,6 +53,22 @@ struct I8259Class { DeviceRealize parent_realize; }; =20 +#define TYPE_I8259_PIC "isa-i8259-pic" + +struct I8259PICState { + DeviceState parent_obj; + + qemu_irq pic_out_irq; + qemu_irq pass_irqs[ISA_NUM_IRQS]; + + ISABus *isabus; + IRQState i8259_primary_out_irq; + I8259State i8259[2]; +}; + +OBJECT_DECLARE_SIMPLE_TYPE(I8259PICState, I8259_PIC) + + #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif @@ -410,30 +428,24 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq= _in) { qemu_irq *irq_set; DeviceState *dev; - ISADevice *isadev; + Object *pic_obj; int i; =20 irq_set =3D g_new0(qemu_irq, ISA_NUM_IRQS); =20 - isadev =3D i8259_init_chip(TYPE_I8259, bus, true); - dev =3D DEVICE(isadev); + dev =3D qdev_new(TYPE_I8259_PIC); + object_property_set_link(OBJECT(dev), "bus", OBJECT(bus), &error_fatal= ); + qdev_realize_and_unref(dev, NULL, &error_fatal); =20 qdev_connect_gpio_out(dev, 0, parent_irq_in); - for (i =3D 0 ; i < 8; i++) { + for (i =3D 0 ; i < ISA_NUM_IRQS; i++) { irq_set[i] =3D qdev_get_gpio_in(dev, i); } =20 - isa_pic =3D I8259(dev); - - isadev =3D i8259_init_chip(TYPE_I8259, bus, false); - dev =3D DEVICE(isadev); - - qdev_connect_gpio_out(dev, 0, irq_set[2]); - for (i =3D 0 ; i < 8; i++) { - irq_set[i + 8] =3D qdev_get_gpio_in(dev, i); - } - - slave_pic =3D I8259_COMMON(dev); + pic_obj =3D object_resolve_path_component(OBJECT(dev), "primary"); + isa_pic =3D I8259(pic_obj); + pic_obj =3D object_resolve_path_component(OBJECT(dev), "secondary"); + slave_pic =3D I8259_COMMON(pic_obj); =20 return irq_set; } @@ -447,6 +459,90 @@ static void i8259_class_init(ObjectClass *klass, const= void *data) device_class_set_legacy_reset(dc, i8259_reset); } =20 + +static void i8259_pic_set_irq(void *opaque, int n, int level) +{ + I8259PICState *s =3D opaque; + + qemu_set_irq(s->pass_irqs[n], level); +} + +static void i8259_primary_out_irq(void *opaque, int n, int level) +{ + I8259PICState *s =3D opaque; + + qemu_set_irq(s->pic_out_irq, level); +} + +static void i8259_pic_init(Object *obj) +{ + I8259PICState *s =3D I8259_PIC(obj); + + object_initialize_child(obj, "primary", &s->i8259[0], TYPE_I8259); + object_initialize_child(obj, "secondary", &s->i8259[1], TYPE_I8259); + + qemu_init_irq(&s->i8259_primary_out_irq, i8259_primary_out_irq, s, 1); + + qdev_init_gpio_in(DEVICE(obj), i8259_pic_set_irq, ISA_NUM_IRQS); + qdev_init_gpio_out(DEVICE(obj), &s->pic_out_irq, 1); +} + +static void i8259_pic_realize(DeviceState *dev, Error **errp) +{ + I8259PICState *s =3D I8259_PIC(dev); + DeviceState *pri_dev, *sec_dev; + int i; + + /* Primary */ + pri_dev =3D DEVICE(&s->i8259[0]); + qdev_prop_set_uint32(pri_dev, "iobase", 0x20); + qdev_prop_set_uint32(pri_dev, "elcr_addr", 0x4d0); + qdev_prop_set_uint8(pri_dev, "elcr_mask", 0xf8); + qdev_prop_set_bit(pri_dev, "master", 1); + if (!isa_realize(ISA_DEVICE(pri_dev), s->isabus, errp)) { + return; + } + + for (i =3D 0; i < 8; i++) { + s->pass_irqs[i] =3D qdev_get_gpio_in(pri_dev, i); + } + + qdev_connect_gpio_out(pri_dev, 0, &s->i8259_primary_out_irq); + + /* Secondary */ + sec_dev =3D DEVICE(&s->i8259[1]); + qdev_prop_set_uint32(sec_dev, "iobase", 0xa0); + qdev_prop_set_uint32(sec_dev, "elcr_addr", 0x4d1); + qdev_prop_set_uint8(sec_dev, "elcr_mask", 0xde); + if (!isa_realize(ISA_DEVICE(sec_dev), s->isabus, errp)) { + return; + } + + /* Wire up secondary cascade */ + qdev_connect_gpio_out(sec_dev, 0, s->pass_irqs[2]); + + for (i =3D 8; i < ISA_NUM_IRQS; i++) { + s->pass_irqs[i] =3D qdev_get_gpio_in(sec_dev, i - 8); + } +} + +static const Property i8259_pic_properties[] =3D { + DEFINE_PROP_LINK("bus", I8259PICState, isabus, TYPE_ISA_BUS, + ISABus *), +}; + +static void i8259_pic_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D i8259_pic_realize; + device_class_set_props(dc, i8259_pic_properties); + /* + * Reason: must be wired to the ISA bus via the "bus" property + */ + dc->user_creatable =3D false; +} + static const TypeInfo i8259_type_infos[] =3D { { .name =3D TYPE_I8259, @@ -455,6 +551,13 @@ static const TypeInfo i8259_type_infos[] =3D { .class_init =3D i8259_class_init, .class_size =3D sizeof(I8259Class), }, + { + .name =3D TYPE_I8259_PIC, + .parent =3D TYPE_DEVICE, + .class_init =3D i8259_pic_class_init, + .instance_init =3D i8259_pic_init, + .instance_size =3D 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b=A6anItIMk5HDevlYxhvuiZ3TXb0RZbA/QdB7cq+gRGlxymUElbJGD9R8mG282+gT3C5CdnL1GDemK6oVVSKQfR/iMgGOhTsb5Q3PYKEs9Pn0m/A1sPU+ZgW3MXF7I0mUKZApc9yyq+ZjwB7FlcgMB2b7jSXCMtFs+B9GQf69r595a+Tph+Kj3UKUgH4pxshYfo8eN+NTRgOI+A+RGgpSVZFUmRWmRPhkd6eBitdz5Zt3tL1HZR22OaohmAVxi5lfFN2NXzyxq3nxycul85n97yXfOzv2F5JRqCWkidKwOjQqixujJSU3YNQBa3uYx3Ti/55M2mWOOakzR8h+iG8TDA== Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nutanix.com; From: Mark Cave-Ayland To: pbonzini@redhat.com, richard.henderson@linaro.org, mst@redhat.com, sstabellini@kernel.org, anthony@xenproject.org, edgar.iglesias@gmail.com, qemu-devel@nongnu.org, xen-devel@lists.xenproject.org Subject: [PATCH v3 20/28] i8259.c: properly cascade secondary i8259 from primary i8259 Date: Mon, 19 Oct 2026 13:04:52 +0100 Message-ID: <20261019120517.1448687-21-mark.caveayland@nutanix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261019120517.1448687-1-mark.caveayland@nutanix.com> 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X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411616306158500 Content-Type: text/plain; charset="utf-8" Currently the cascaded output from the secondary i8259 is returned directly= in the pass_irqs[] array, instead of being connected to the relevant input of = the primary i8259. This is a bug fix since in a cascaded configuration on real hardware it is possible (although unlikely) that the cascaded input from the secondary i82= 59 can be masked on the primary i8259. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index fe524efbce..d713795ae0 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -504,6 +504,11 @@ static void i8259_pic_realize(DeviceState *dev, Error = **errp) } =20 for (i =3D 0; i < 8; i++) { + /* Cascaded input is not usable */ + if (i =3D=3D 2) { + continue; + } + s->pass_irqs[i] =3D qdev_get_gpio_in(pri_dev, i); } =20 @@ -519,7 +524,8 @@ static void i8259_pic_realize(DeviceState *dev, Error *= *errp) } =20 /* Wire up secondary cascade */ - qdev_connect_gpio_out(sec_dev, 0, s->pass_irqs[2]); + qdev_connect_gpio_out(sec_dev, 0, + qdev_get_gpio_in(pri_dev, 2)); =20 for (i =3D 8; i < ISA_NUM_IRQS; i++) { s->pass_irqs[i] =3D qdev_get_gpio_in(sec_dev, i - 8); --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of 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X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411638640158500 Content-Type: text/plain; charset="utf-8" This device represents the KVM in-kernel PIC for an x86 machine. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/i386/kvm/i8259.c | 91 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 3 deletions(-) diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 9ee23b5695..48282db58e 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -16,7 +16,9 @@ #include "qemu/module.h" #include "hw/intc/kvm_irqcount.h" #include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" #include "system/kvm.h" +#include "qapi/error.h" #include "qom/object.h" =20 #define TYPE_KVM_I8259 "kvm-i8259" @@ -36,6 +38,18 @@ struct KVMI8259Class { DeviceRealize parent_realize; }; =20 +#define TYPE_KVM_I8259_PIC "kvm-i8259-pic" + +struct KVMI8259PICState { + DeviceState parent_obj; + + ISABus *isabus; + KVMI8259State i8259[2]; +}; + +OBJECT_DECLARE_SIMPLE_TYPE(KVMI8259PICState, KVM_I8259_PIC) + + static void kvm_i8259_get(I8259CommonState *cs) { struct kvm_irqchip chip; @@ -135,10 +149,21 @@ static void kvm_i8259_realize(DeviceState *dev, Error= **errp) =20 qemu_irq *kvm_i8259_init(ISABus *bus) { - i8259_init_chip(TYPE_KVM_I8259, bus, true); - i8259_init_chip(TYPE_KVM_I8259, bus, false); + qemu_irq *irq_set; + DeviceState *dev; + int i; + + irq_set =3D g_new0(qemu_irq, ISA_NUM_IRQS); + + dev =3D qdev_new(TYPE_KVM_I8259_PIC); + object_property_set_link(OBJECT(dev), "bus", OBJECT(bus), &error_fatal= ); + qdev_realize_and_unref(dev, NULL, &error_fatal); =20 - return qemu_allocate_irqs(kvm_pic_set_irq, NULL, ISA_NUM_IRQS); + for (i =3D 0 ; i < ISA_NUM_IRQS; i++) { + irq_set[i] =3D qdev_get_gpio_in(dev, i); + } + + return irq_set; } =20 static void kvm_i8259_class_init(ObjectClass *klass, const void *data) @@ -154,6 +179,59 @@ static void kvm_i8259_class_init(ObjectClass *klass, c= onst void *data) k->post_load =3D kvm_i8259_put; } =20 + +static void kvm_i8259_pic_init(Object *obj) +{ + KVMI8259PICState *s =3D KVM_I8259_PIC(obj); + + object_initialize_child(obj, "primary", &s->i8259[0], TYPE_KVM_I8259); + object_initialize_child(obj, "secondary", &s->i8259[1], TYPE_KVM_I8259= ); + + qdev_init_gpio_in(DEVICE(obj), kvm_pic_set_irq, ISA_NUM_IRQS); +} + +static void kvm_i8259_pic_realize(DeviceState *dev, Error **errp) +{ + KVMI8259PICState *s =3D KVM_I8259_PIC(dev); + DeviceState *pri_dev, *sec_dev; + + /* Primary */ + pri_dev =3D DEVICE(&s->i8259[0]); + qdev_prop_set_uint32(pri_dev, "iobase", 0x20); + qdev_prop_set_uint32(pri_dev, "elcr_addr", 0x4d0); + qdev_prop_set_uint8(pri_dev, "elcr_mask", 0xf8); + qdev_prop_set_bit(pri_dev, "master", 1); + if (!isa_realize(ISA_DEVICE(pri_dev), s->isabus, errp)) { + return; + } + + /* Secondary */ + sec_dev =3D DEVICE(&s->i8259[1]); + qdev_prop_set_uint32(sec_dev, "iobase", 0xa0); + qdev_prop_set_uint32(sec_dev, "elcr_addr", 0x4d1); + qdev_prop_set_uint8(sec_dev, "elcr_mask", 0xde); + if (!isa_realize(ISA_DEVICE(sec_dev), s->isabus, errp)) { + return; + } +} + +static const Property kvm_i8259_pic_properties[] =3D { + DEFINE_PROP_LINK("bus", KVMI8259PICState, isabus, TYPE_ISA_BUS, + ISABus *), +}; + +static void kvm_i8259_pic_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D kvm_i8259_pic_realize; + device_class_set_props(dc, kvm_i8259_pic_properties); + /* + * Reason: must be wired to the ISA bus via the "bus" property + */ + dc->user_creatable =3D false; +} + static const TypeInfo kvm_i8259_type_infos[] =3D { { .name =3D TYPE_KVM_I8259, @@ -162,6 +240,13 @@ static const TypeInfo kvm_i8259_type_infos[] =3D { .class_init =3D kvm_i8259_class_init, .class_size =3D sizeof(KVMI8259Class), }, + { + .name =3D TYPE_KVM_I8259_PIC, + .parent =3D TYPE_DEVICE, + .class_init =3D kvm_i8259_pic_class_init, + .instance_init =3D kvm_i8259_pic_init, + .instance_size =3D sizeof(KVMI8259PICState), + }, }; =20 DEFINE_TYPES(kvm_i8259_type_infos) --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass 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X-purgate-type: clean X-purgate-size: 2252 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411618351158500 Content-Type: text/plain; charset="utf-8" This clarifies that the interrupt controller being modelled is an emulated i8259 implementation, and brings the naming convention in line with the in-built i8259 and KVM i8259 implementations. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/xen/xen.h | 2 +- hw/i386/pc.c | 2 +- hw/i386/xen/xen-hvm.c | 2 +- stubs/xen-hw-stub.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h index e94c6e5a31..ee4ed4f11b 100644 --- a/include/hw/xen/xen.h +++ b/include/hw/xen/xen.h @@ -42,7 +42,7 @@ void xen_intx_set_irq(void *opaque, int irq_num, int leve= l); void xen_hvm_inject_msi(uint64_t addr, uint32_t data); int xen_is_pirq_msi(uint32_t msi_data); =20 -qemu_irq *xen_interrupt_controller_init(void); +qemu_irq *xen_i8259_init(void); =20 void xen_register_framebuffer(struct MemoryRegion *mr); =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2d8c87b0e3..dbfd55de30 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1167,7 +1167,7 @@ void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259= _irqs) if (kvm_pic_in_kernel()) { i8259 =3D kvm_i8259_init(isa_bus); } else if (xen_enabled()) { - i8259 =3D xen_interrupt_controller_init(); + i8259 =3D xen_i8259_init(); } else { i8259 =3D i8259_init(isa_bus, x86_allocate_cpu_irq()); } diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index d3ce082e07..af3a90987c 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -112,7 +112,7 @@ static void xen_set_irq(void *opaque, int irq, int leve= l) xen_set_isa_irq_level(xen_domid, irq, level); } =20 -qemu_irq *xen_interrupt_controller_init(void) +qemu_irq *xen_i8259_init(void) { return qemu_allocate_irqs(xen_set_irq, NULL, 16); } diff --git a/stubs/xen-hw-stub.c b/stubs/xen-hw-stub.c index 6cf0e9a4c1..b3e27f0292 100644 --- a/stubs/xen-hw-stub.c +++ b/stubs/xen-hw-stub.c @@ -29,7 +29,7 @@ int xen_is_pirq_msi(uint32_t msi_data) return 0; } =20 -qemu_irq *xen_interrupt_controller_init(void) +qemu_irq *xen_i8259_init(void) { return NULL; } --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of 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X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411646917158500 Content-Type: text/plain; charset="utf-8" This device represents the Xen PIC for an x86 machine. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/i386/xen/xen-hvm.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index af3a90987c..b2378fe3f0 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -13,6 +13,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/qapi-commands-migration.h" +#include "qom/object.h" #include "trace.h" =20 #include "hw/core/hw-error.h" @@ -69,6 +70,12 @@ static unsigned long *dirty_bitmap; static Notifier suspend; static Notifier wakeup; =20 +#define TYPE_XEN_I8259_PIC "xen-i8259-pic" + +DECLARE_OBJ_CHECKERS(DeviceState, DeviceClass, XEN_I8259_PIC, + TYPE_XEN_I8259_PIC) + + /* Xen specific function for piix pci */ =20 int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) @@ -114,9 +121,28 @@ static void xen_set_irq(void *opaque, int irq, int lev= el) =20 qemu_irq *xen_i8259_init(void) { - return qemu_allocate_irqs(xen_set_irq, NULL, 16); + qemu_irq *irq_set; + DeviceState *dev; + int i; + + irq_set =3D g_new0(qemu_irq, 16); + + dev =3D qdev_new(TYPE_XEN_I8259_PIC); + qdev_realize_and_unref(dev, NULL, &error_fatal); + + for (i =3D 0 ; i < 16; i++) { + irq_set[i] =3D qdev_get_gpio_in(dev, i); + } + + return irq_set; } =20 +static void xen_i8259_pic_init(Object *obj) +{ + qdev_init_gpio_in(DEVICE(obj), xen_set_irq, 16); +} + + /* Memory Ops */ =20 static void xen_ram_init(PCMachineState *pcms, @@ -760,3 +786,13 @@ void arch_handle_ioreq(XenIOState *state, ioreq_t *req) hw_error("Invalid ioreq type 0x%x\n", req->type); } } + +static const TypeInfo xen_i8259_type_infos[] =3D { + { + .name =3D TYPE_XEN_I8259_PIC, + .parent =3D TYPE_DEVICE, + .instance_init =3D xen_i8259_pic_init, + }, +}; + +DEFINE_TYPES(xen_i8259_type_infos) --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org 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Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/isa/i8259_internal.h | 1 - hw/intc/i8259_common.c | 16 ---------------- 2 files changed, 17 deletions(-) diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 644508a44e..dd255fac24 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -71,7 +71,6 @@ struct I8259CommonState { }; =20 void i8259_common_reset(I8259CommonState *cs); -ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); void i8259_stat_update_irq(int irq, int level); =20 #endif /* QEMU_I8259_INTERNAL_H */ diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 09b761321a..5fa38fbc5f 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -89,22 +89,6 @@ static void i8259_common_realize(DeviceState *dev, Error= **errp) qdev_set_legacy_instance_id(dev, cs->iobase, 1); } =20 -ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) -{ 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X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDA0OCBTYWx0ZWRfX5EGJous4Wetm X4ZUdoqS1fOtRbiM/Z5N5lxcZl8ijC1H7DFuraSLmkg2yYly9gRrmKHj5B9sfXnlR0tNBn9KH2u uU57zDVXOIl9HizGfPZ+h+7vm7VWjYk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDA0OCBTYWx0ZWRfX4Ba4PBjsU9/y sWJctk3i1gK84ofezgL/MSlBDXgKlfsTbqUVrk7vC4t1FktYhYuHCXjX+/ryEZPvsLF464kdfbA HNcfF4VxW0uaUmllfTvejhJLI8X+oKv4hBEWtAlMOST7ez46pxPeb9n6pGXXHhXrK7nw9J/rA1Q TOp7Wmig4m0pZeqWVI1qju+b6nlzfXym4YPoha5BPC9UHk577wPwFC1p+gf1XKUzG6JTtt6B0Cj 515Q4+hEQuTsnpJWH56ZSOquipYSG2QF4Z1buWySNlTfqGHrRaTtUAa3btCysTDeW3StI3KS94j o1fglNii3ST8aDOJz6041w2lITZ9bvZPYsw16Pm4Kz3KvF3ROcGARCq4ll26qUc/WscZwYSlqJm Iap5MYcPW+HsrUfvWfK6LvDueX57PErBgKlV9qgpeUP+ItK1PeP5NOmWrABQvKroNrSvCcxR8UN IT99GMg++DKeBfxYNpQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_03,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Reason: safe X-purgate-ID: tlsNG-c1860d/1792411607-CD14E87B-94C3D63C/0/0 X-purgate-type: clean X-purgate-size: 5964 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411636566158500 Content-Type: text/plain; charset="utf-8" The internal i8259 implementation has workaround logic for storing interrupt statistics since these are currently recorded at the PIC level (i.e. for all 16 interrupt lines) whilst being stored in the master i8259 device which on= ly has 8 physical interrupt lines. Move the get_statistics() implementation from the individual i8259 device to the containing PIC device in preparation for removing this hack. Note that this has a visible change to the "info pic" HMP monitor output since the na= med device displayed by "info irq" is now the PIC and not the individual i8259: Before (TCG): (qemu) info irq IRQ statistics for ioapic: 0: 68 4: 1 IRQ statistics for isa-i8259: 0: 68 4: 1 After (TCG): (qemu) info irq IRQ statistics for ioapic: 0: 47 4: 1 IRQ statistics for isa-i8259-pic: 0: 47 4: 1 Before (KVM): (qemu) info irq IRQ statistics for kvm-ioapic: 4: 1 IRQ statistics for kvm-i8259: 4: 1 After (KVM): (qemu) info irq IRQ statistics for kvm-ioapic: 1: 3 4: 1 IRQ statistics for kvm-i8259-pic: 1: 3 4: 1 Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/intc/i8259.h | 6 ++++++ include/hw/isa/i8259_internal.h | 1 - hw/i386/kvm/i8259.c | 7 +++++++ hw/intc/i8259.c | 7 +++++++ hw/intc/i8259_common.c | 27 ++++++++++++++++++--------- 5 files changed, 38 insertions(+), 10 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index 87ccd55a4d..d51a7fde32 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -1,6 +1,8 @@ #ifndef HW_I8259_H #define HW_I8259_H =20 +#include "hw/intc/intc.h" + /* i8259.c */ =20 typedef struct I8259State I8259State; @@ -18,5 +20,9 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in); qemu_irq *kvm_i8259_init(ISABus *bus); int pic_get_output(I8259State *s); int pic_read_irq(I8259State *s); +bool i8259_pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, + unsigned int *nb_irqs); +void i8259_pic_print_info(InterruptStatsProvider *obj, GString *buf); =20 #endif diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index dd255fac24..2807409eff 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -26,7 +26,6 @@ #define QEMU_I8259_INTERNAL_H =20 #include "hw/isa/isa.h" -#include "hw/intc/intc.h" #include "hw/intc/i8259.h" #include "qom/object.h" =20 diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 48282db58e..8cea5fb12b 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -223,9 +223,12 @@ static const Property kvm_i8259_pic_properties[] =3D { static void kvm_i8259_pic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); =20 dc->realize =3D kvm_i8259_pic_realize; device_class_set_props(dc, kvm_i8259_pic_properties); + ic->get_statistics =3D i8259_pic_get_statistics; + ic->print_info =3D i8259_pic_print_info; /* * Reason: must be wired to the ISA bus via the "bus" property */ @@ -246,6 +249,10 @@ static const TypeInfo kvm_i8259_type_infos[] =3D { .class_init =3D kvm_i8259_pic_class_init, .instance_init =3D kvm_i8259_pic_init, .instance_size =3D sizeof(KVMI8259PICState), + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, }, }; =20 diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index d713795ae0..c3a3199b8e 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -540,9 +540,12 @@ static const Property i8259_pic_properties[] =3D { static void i8259_pic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + InterruptStatsProviderClass *ic =3D INTERRUPT_STATS_PROVIDER_CLASS(kla= ss); =20 dc->realize =3D i8259_pic_realize; device_class_set_props(dc, i8259_pic_properties); + ic->get_statistics =3D i8259_pic_get_statistics; + ic->print_info =3D i8259_pic_print_info; /* * Reason: must be wired to the ISA bus via the "bus" property */ @@ -563,6 +566,10 @@ static const TypeInfo i8259_type_infos[] =3D { .class_init =3D i8259_pic_class_init, .instance_init =3D i8259_pic_init, .instance_size =3D sizeof(I8259PICState), + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, }, }; =20 diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 5fa38fbc5f..684290fb2d 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -99,19 +99,28 @@ void i8259_stat_update_irq(int irq, int level) } } =20 +bool i8259_pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, + unsigned int *nb_irqs) +{ + *irq_counts =3D irq_count; + *nb_irqs =3D ARRAY_SIZE(irq_count); + + return true; +} + +void i8259_pic_print_info(InterruptStatsProvider *obj, GString *buf) +{ + /* No information for i8259-based PICs */ + return; +} + static bool i8259_common_get_statistics(InterruptStatsProvider *obj, uint64_t **irq_counts, unsigned int *nb_irqs) { - I8259CommonState *cs =3D I8259_COMMON(obj); - - if (cs->master) { - *irq_counts =3D irq_count; - *nb_irqs =3D ARRAY_SIZE(irq_count); - } else { - *irq_counts =3D NULL; - *nb_irqs =3D 0; - } + /* No statistics for individual i8259s */ + *nb_irqs =3D 0; =20 return true; } --=20 2.43.0 From nobody Fri Oct 23 15:09:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) 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tlsNG-ef75cf/1792411610-344CBAE4-2B3F9E28/0/0 X-purgate-type: clean X-purgate-size: 4546 X-ZohoMail-DKIM: pass (identity @nutanix.com) X-ZM-MESSAGEID: 1792411632511158500 Content-Type: text/plain; charset="utf-8" The isa_pic variable exists to allow the output to be fetched or read (fetc= hed and acknowledged) from the x86 PIC. Since this can also contain a cascaded interrupt from a slave i8259, switch isa_pic from I8259State to I8259PICSta= te and update both pic_get_output() and pic_read_irq() accordingly. This has the advantage that a i8259-based PIC device contains its own inter= nal reference to both the primary and secondary i8259s, and therefore it becomes possible to completely remove the slave_pic variable. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/intc/i8259.h | 8 ++++---- hw/intc/i8259.c | 34 +++++++++++++++------------------- 2 files changed, 19 insertions(+), 23 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index d51a7fde32..4922f88d5b 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -5,9 +5,9 @@ =20 /* i8259.c */ =20 -typedef struct I8259State I8259State; +typedef struct I8259PICState I8259PICState; =20 -extern I8259State *isa_pic; +extern I8259PICState *isa_pic; =20 /* * i8259_init() @@ -18,8 +18,8 @@ extern I8259State *isa_pic; */ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in); qemu_irq *kvm_i8259_init(ISABus *bus); -int pic_get_output(I8259State *s); -int pic_read_irq(I8259State *s); +int pic_get_output(I8259PICState *s); +int pic_read_irq(I8259PICState *s); bool i8259_pic_get_statistics(InterruptStatsProvider *obj, uint64_t **irq_counts, unsigned int *nb_irqs); diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index c3a3199b8e..b59e26cbc6 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -72,8 +72,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(I8259PICState, I8259_PIC) #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif -I8259State *isa_pic; -static I8259CommonState *slave_pic; +I8259PICState *isa_pic; =20 /* return the highest priority found in mask (highest =3D smallest number). Return 8 if no irq */ @@ -190,34 +189,35 @@ static void i8259_intack(I8259CommonState *cs, int ir= q) i8259_update_irq(cs); } =20 -int pic_read_irq(I8259State *s) +int pic_read_irq(I8259PICState *s) { - I8259CommonState *cs =3D I8259_COMMON(s); + I8259CommonState *pcs =3D I8259_COMMON(&s->i8259[0]); + I8259CommonState *scs =3D I8259_COMMON(&s->i8259[1]); int irq, intno; =20 - irq =3D i8259_get_irq(cs); + irq =3D i8259_get_irq(pcs); if (irq >=3D 0) { int irq2; =20 if (irq =3D=3D 2) { - irq2 =3D i8259_get_irq(slave_pic); + irq2 =3D i8259_get_irq(scs); if (irq2 >=3D 0) { - i8259_intack(slave_pic, irq2); + i8259_intack(scs, irq2); } else { /* spurious IRQ on slave controller */ irq2 =3D 7; } - intno =3D slave_pic->irq_base + irq2; - i8259_intack(cs, irq); + intno =3D scs->irq_base + irq2; + i8259_intack(pcs, irq); irq =3D irq2 + 8; } else { - intno =3D cs->irq_base + irq; - i8259_intack(cs, irq); + intno =3D pcs->irq_base + irq; + i8259_intack(pcs, irq); } } else { /* spurious IRQ on host controller */ irq =3D 7; - intno =3D cs->irq_base + irq; + intno =3D pcs->irq_base + irq; } =20 #ifdef DEBUG_IRQ_LATENCY @@ -369,9 +369,9 @@ static uint64_t i8259_base_ioport_read(void *opaque, hw= addr addr, return ret; } =20 -int pic_get_output(I8259State *s) +int pic_get_output(I8259PICState *s) { - I8259CommonState *cs =3D I8259_COMMON(s); + I8259CommonState *cs =3D I8259_COMMON(&s->i8259[0]); =20 return (i8259_get_irq(cs) >=3D 0); } @@ -428,7 +428,6 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_i= n) { qemu_irq *irq_set; DeviceState *dev; - Object *pic_obj; int i; =20 irq_set =3D g_new0(qemu_irq, ISA_NUM_IRQS); @@ -442,10 +441,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_= in) irq_set[i] =3D qdev_get_gpio_in(dev, i); } =20 - pic_obj =3D object_resolve_path_component(OBJECT(dev), "primary"); - isa_pic =3D I8259(pic_obj); - pic_obj =3D object_resolve_path_component(OBJECT(dev), "secondary"); - slave_pic =3D I8259_COMMON(pic_obj); + isa_pic =3D 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i8259 PIC and KVM PIC devices. Doing this allows the statistics capture logic in i8259_set_irq() that hand= les incoming cascading interrupts to be removed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/hw/intc/i8259.h | 3 --- include/hw/isa/i8259_internal.h | 3 ++- hw/i386/kvm/i8259.c | 20 +++++++++++++++-- hw/intc/i8259.c | 40 ++++++++++++++++++++++----------- hw/intc/i8259_common.c | 21 +++++------------ 5 files changed, 52 insertions(+), 35 deletions(-) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index 4922f88d5b..42d6f992ac 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -20,9 +20,6 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in); qemu_irq *kvm_i8259_init(ISABus *bus); int pic_get_output(I8259PICState *s); int pic_read_irq(I8259PICState *s); -bool i8259_pic_get_statistics(InterruptStatsProvider *obj, - uint64_t **irq_counts, - unsigned int *nb_irqs); void i8259_pic_print_info(InterruptStatsProvider *obj, GString *buf); =20 #endif diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 2807409eff..e0002843a1 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -70,6 +70,7 @@ struct I8259CommonState { }; =20 void i8259_common_reset(I8259CommonState *cs); -void i8259_stat_update_irq(int irq, int level); +void i8259_stat_update_irq(uint64_t *irq_levels, int *irq_counts, + int irq, int level); =20 #endif /* QEMU_I8259_INTERNAL_H */ diff --git a/hw/i386/kvm/i8259.c b/hw/i386/kvm/i8259.c index 8cea5fb12b..bf5ae334b9 100644 --- a/hw/i386/kvm/i8259.c +++ b/hw/i386/kvm/i8259.c @@ -45,6 +45,9 @@ struct KVMI8259PICState { =20 ISABus *isabus; KVMI8259State i8259[2]; + + int irq_level[ISA_NUM_IRQS]; + uint64_t irq_count[ISA_NUM_IRQS]; }; =20 OBJECT_DECLARE_SIMPLE_TYPE(KVMI8259PICState, KVM_I8259_PIC) @@ -117,6 +120,18 @@ static void kvm_i8259_put(I8259CommonState *cs) } } =20 +static bool kvm_i8259_pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, + unsigned int *nb_irqs) +{ + KVMI8259PICState *s =3D KVM_I8259_PIC(obj); + + *irq_counts =3D s->irq_count; + *nb_irqs =3D ARRAY_SIZE(s->irq_count); + + return true; +} + static void kvm_i8259_reset(DeviceState *dev) { I8259CommonState *cs =3D I8259_COMMON(dev); @@ -129,9 +144,10 @@ static void kvm_i8259_reset(DeviceState *dev) =20 static void kvm_pic_set_irq(void *opaque, int irq, int level) { + KVMI8259PICState *s =3D opaque; int delivered; =20 - i8259_stat_update_irq(irq, level); + i8259_stat_update_irq(s->irq_count, s->irq_level, irq, level); delivered =3D kvm_set_irq(kvm_state, irq, level); kvm_report_irq_delivered(delivered); } @@ -227,7 +243,7 @@ static void kvm_i8259_pic_class_init(ObjectClass *klass= , const void *data) =20 dc->realize =3D kvm_i8259_pic_realize; device_class_set_props(dc, kvm_i8259_pic_properties); - ic->get_statistics =3D i8259_pic_get_statistics; + ic->get_statistics =3D kvm_i8259_pic_get_statistics; ic->print_info =3D i8259_pic_print_info; /* * Reason: must be wired to the ISA bus via the "bus" property diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index b59e26cbc6..79b5e603bc 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -64,14 +64,16 @@ struct I8259PICState { ISABus *isabus; IRQState i8259_primary_out_irq; I8259State i8259[2]; + + int irq_level[ISA_NUM_IRQS]; + uint64_t irq_count[ISA_NUM_IRQS]; +#ifdef DEBUG_IRQ_LATENCY + int64_t irq_time[ISA_NUM_IRQS]; +#endif }; =20 OBJECT_DECLARE_SIMPLE_TYPE(I8259PICState, I8259_PIC) =20 - -#ifdef DEBUG_IRQ_LATENCY -static int64_t irq_time[16]; -#endif I8259PICState *isa_pic; =20 /* return the highest priority found in mask (highest =3D smallest @@ -138,16 +140,8 @@ static void i8259_set_irq(void *opaque, int irq, int l= evel) { I8259CommonState *cs =3D opaque; int mask =3D 1 << irq; - int irq_index =3D cs->master ? irq : irq + 8; =20 trace_i8259_set_irq(cs->master, irq, level); - i8259_stat_update_irq(irq_index, level); - -#ifdef DEBUG_IRQ_LATENCY - if (level) { - irq_time[irq_index] =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - } -#endif =20 if (cs->ltim || (cs->elcr & mask)) { /* level triggered */ @@ -224,7 +218,7 @@ int pic_read_irq(I8259PICState *s) printf("IRQ%d latency=3D%0.3fus\n", irq, (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - - irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND); + s->irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND= ); #endif =20 trace_pic_interrupt(irq, intno); @@ -456,10 +450,30 @@ static void i8259_class_init(ObjectClass *klass, cons= t void *data) } =20 =20 +static bool i8259_pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, + unsigned int *nb_irqs) +{ + I8259PICState *s =3D I8259_PIC(obj); + + *irq_counts =3D s->irq_count; + *nb_irqs =3D ARRAY_SIZE(s->irq_count); + + return true; +} + static void i8259_pic_set_irq(void *opaque, int n, int level) { I8259PICState *s =3D opaque; =20 + i8259_stat_update_irq(s->irq_count, s->irq_level, n, level); + +#ifdef DEBUG_IRQ_LATENCY + if (level) { + s->irq_time[n] =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } +#endif + qemu_set_irq(s->pass_irqs[n], level); } =20 diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 684290fb2d..3bafd81ea7 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -30,8 +30,6 @@ #include "migration/vmstate.h" #include "qapi/error.h" =20 -static int irq_level[16]; -static uint64_t irq_count[16]; =20 void i8259_common_reset(I8259CommonState *cs) { @@ -89,26 +87,17 @@ static void i8259_common_realize(DeviceState *dev, Erro= r **errp) qdev_set_legacy_instance_id(dev, cs->iobase, 1); } =20 -void i8259_stat_update_irq(int irq, int level) +void i8259_stat_update_irq(uint64_t *irq_counts, int *irq_levels, + int irq, int level) { - if (level !=3D irq_level[irq]) { - irq_level[irq] =3D level; + if (level !=3D irq_levels[irq]) { + irq_levels[irq] =3D level; if (level =3D=3D 1) { - irq_count[irq]++; + irq_counts[irq]++; } } } =20 -bool i8259_pic_get_statistics(InterruptStatsProvider *obj, - uint64_t **irq_counts, - unsigned int *nb_irqs) -{ - *irq_counts =3D irq_count; - *nb_irqs =3D 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Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/intc/i8259_common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 3bafd81ea7..ee325a659a 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -119,8 +119,9 @@ static void i8259_common_print_info(InterruptStatsProvi= der *obj, GString *buf) I8259CommonState *cs =3D I8259_COMMON(obj); =20 i8259_common_dispatch_pre_save(cs); - g_string_append_printf(buf, "pic%d: irr=3D%02x imr=3D%02x isr=3D%02x h= prio=3D%d " - "irq_base=3D%02x rr_sel=3D%d elcr=3D%02x fnm=3D= %d\n", + g_string_append_printf(buf, + "pic%d: irr=3D0x%02x imr=3D0x%02x isr=3D0x%02x = hprio=3D%d " + "irq_base=3D0x%02x rr_sel=3D%d elcr=3D0x%02x fn= m=3D%d\n", cs->master ? 0 : 1, cs->irr, cs->imr, cs->isr, cs->priority_add, cs->irq_base, cs->read_reg_select, cs->elcr, --=20 2.43.0