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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193048891158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Daniel Henrique Barboza Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- include/qemu/target-info.h | 7 +++++++ target-info.c | 11 +++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 862097c6c63..b0f3b4cfb8b 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -112,6 +112,13 @@ bool target_ppc64(void); */ bool target_s390x(void); =20 +/** + * target_base_riscv: + * + * Returns whether the target architecture is RISC-V 32-bit or 64-bit. + */ +bool target_base_riscv(void); + /** * target_riscv64: * diff --git a/target-info.c b/target-info.c index 254530d8ea5..e827026bd23 100644 --- a/target-info.c +++ b/target-info.c @@ -104,6 +104,17 @@ bool target_s390x(void) return target_arch() =3D=3D SYS_EMU_TARGET_S390X; } =20 +bool target_base_riscv(void) +{ + switch (target_arch()) { + case SYS_EMU_TARGET_RISCV32: + case SYS_EMU_TARGET_RISCV64: + return true; + default: + return false; + } +} + bool target_riscv64(void) { return target_arch() =3D=3D SYS_EMU_TARGET_RISCV64; --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193036948158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- hw/riscv/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d4b501802f6..894cdd97976 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -22,6 +22,7 @@ #include "qemu/units.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "qapi/error.h" #include "hw/core/boards.h" #include "hw/core/loader.h" @@ -1203,6 +1204,7 @@ static const TypeInfo virt_machine_typeinfo =3D { .instance_init =3D virt_machine_instance_init, .instance_finalize =3D virt_machine_instance_finalize, .instance_size =3D sizeof(RISCVVirtState), + .is_available =3D target_base_riscv, .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, { } --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193085558158500 Content-Type: text/plain; charset="utf-8" Currently, we are initializing QOM type after having set target to the first one available. That's not enough to catch conflicts among types within targets. Indeed, we'll miss some conflicts since some types are registered conditionnally through .is_available. To ensure full coverage, we detect all targets available, and generate a sub test for each of them. Then, using g_test_trap_subprocess(), we can recursively call only this test in a children process. Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- tests/unit/test-multi-target.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/tests/unit/test-multi-target.c b/tests/unit/test-multi-target.c index 89b55bb1632..c7559827a08 100644 --- a/tests/unit/test-multi-target.c +++ b/tests/unit/test-multi-target.c @@ -30,13 +30,20 @@ /* stub for system/main.c */ int (*qemu_main)(void); =20 -static void test_qom_types_are_unique(void) +static void test_qom_types_are_unique(const void *data) { - module_call_init(MODULE_INIT_TARGET_INFO); - g_autoptr(GSList) targets =3D object_class_get_list(TYPE_TARGET_INFO, = false); - g_assert(targets); - const TargetInfo *first_ti =3D TARGET_INFO_CLASS(targets->data)->targe= t_info; - target_info_qom_set_target_info(first_ti); + const TargetInfo *ti =3D data; + + /* QOM types can be initialized only once, so do it in a subprocess. */ + if (!g_test_subprocess()) { + /* parent process path - respawn this exact test path */ + g_test_trap_subprocess(NULL, 0, G_TEST_SUBPROCESS_INHERIT_STDERR); + g_test_trap_assert_passed(); + return; + } + /* child process path */ + + target_info_qom_set_target_info(ti); =20 /* register all types */ module_call_init(MODULE_INIT_QOM); @@ -47,7 +54,18 @@ static void test_qom_types_are_unique(void) int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); - g_test_add_func("/multi-targets/qom-types-are-unique", - test_qom_types_are_unique); + + module_call_init(MODULE_INIT_TARGET_INFO); + g_autoptr(GSList) targets =3D object_class_get_list_sorted(TYPE_TARGET= _INFO, + false); + g_assert(targets); + for (GSList *elem =3D targets; elem; elem =3D elem->next) { + const TargetInfo *ti =3D TARGET_INFO_CLASS(elem->data)->target_inf= o; + g_autofree char *path =3D + g_strdup_printf("/multi-targets/qom-types-are-unique/%s", + ti->target_name); + g_test_add_data_func(path, ti, test_qom_types_are_unique); + } + return g_test_run(); } --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792193033; cv=none; d=zohomail.com; s=zohoarc; b=Wk21zyT+iCDPaIBS0RSKacpRoBEIwGoLG5QPmBg6ez8/akAgPXr6RsW0HP3/P5/f2G6+EFaJEQEhHDhQ36A2/mmYDdQARlUbyCAPQHUmzb+/ASqi+ppIaLKv+DWxu6/OfrkG2OkvzFMO17qv6bU2Jvc78Vrb9V7ie2b7TeP/21Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792193033; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gxzfhBQPTlpQD1gauaZQgadOvZwnlYfgG+GUSV0P/rE=; b=O9QcvnQ2c6mcQss8AqWNPhyDEAE0zmuEw5bD611b0muutun5RV7hZqMIKWfDA6kvOq4nzKp6QCw+72U5vAY9xX7JuOOAGT+krK4dIvCKRIkn1RKakHK6bEGQdZ6XN5z8/RQfPEu5AcFePGNB2xF/EFA0k7ipoOKcA9wnQ4BrFxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179219303381391.46726874620413; Fri, 16 Oct 2026 16:23:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHrGk-0002st-E8; Fri, 16 Oct 2026 19:23:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGi-0002sB-T3 for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:21 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGh-0001Rs-78 for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:20 -0400 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GNF9us482410 for ; Fri, 16 Oct 2026 23:23:18 GMT Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbrvwgxpd-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 23:23:17 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-3aaee1fc104so603409a91.1 for ; Fri, 16 Oct 2026 16:23:17 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193036958158500 Content-Type: text/plain; charset="utf-8" This removes conflict with the same function from target/arm. To the opposite of arm target, there is no external caller for this function. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- hw/riscv/virt.c | 10 +++++----- include/hw/riscv/virt.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 894cdd97976..2c6f983f83f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -72,6 +72,11 @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIATyp= e aia_type) return riscv_is_kvm_aia_aplic_imsic(msimode); } =20 +static bool virt_is_acpi_enabled(RISCVVirtState *s) +{ + return s->acpi !=3D ON_OFF_AUTO_OFF; +} + static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) { bool msimode =3D aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC; @@ -1067,11 +1072,6 @@ static void virt_set_iommu_sys(Object *obj, Visitor = *v, const char *name, visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); } =20 -bool virt_is_acpi_enabled(RISCVVirtState *s) -{ - return s->acpi !=3D ON_OFF_AUTO_OFF; -} - static void virt_get_acpi(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e516898f9ad..16d86edfcfc 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -121,7 +121,6 @@ enum { #define VIRT_PLIC_SIZE(__num_context) \ (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 -bool virt_is_acpi_enabled(RISCVVirtState *s); bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); =20 --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792193103; cv=none; d=zohomail.com; s=zohoarc; b=k87+KuIcn9MBuqrI1U5vnu5qTRz0wQ/th09ayFv1BPVyiRMntXjiazncdcTKyISJ02HlCzkOROINj3BzUfyZoCYtqMWSS93VP0QRWxrORuNPUcN8Spw8c6k6j3K3xJcr7uuBVEjq2cGjKx2nCTWsuacplqLeKOVXUWkINlywvS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792193103; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vkhIYyllJe4IgoATCTRxOXy8TRvNQr72Y0KFcr4Bq2M=; b=FoR6jNI9heSZfB0R0irA+NJrsoE4dNr2emwok9Prhw+E1v/n7WgwjzgLDRQmJYHbgPU+3qxLWCo4AI+P9NcJQcPYfS2sstXKLCEDhAOI8yuHe+JbTQd+sPPMJ6jr7+JaRSWAfGAhrii8RdMM77d3T1QDg6WTpONetBzlnSV0I1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792193103285205.34158543206354; Fri, 16 Oct 2026 16:25:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHrGn-0002u3-8e; Fri, 16 Oct 2026 19:23:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGk-0002so-5X for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:22 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGi-0001Ry-7L for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:21 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GNF68k2164588 for ; Fri, 16 Oct 2026 23:23:19 GMT Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbcjtc3gh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 23:23:18 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-3aca98f01c1so407722a91.2 for ; Fri, 16 Oct 2026 16:23:18 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193103809158500 Content-Type: text/plain; charset="utf-8" This removes conflict with same function from target/arm. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- hw/riscv/virt-acpi-build.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/virt.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 0475dcb5c60..4565359e908 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -1021,7 +1021,7 @@ static const VMStateDescription vmstate_virt_acpi_bui= ld =3D { }, }; =20 -void virt_acpi_setup(RISCVVirtState *s) +void riscv_virt_acpi_setup(RISCVVirtState *s) { AcpiBuildTables tables; AcpiBuildState *build_state; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2c6f983f83f..de1c92463ad 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -712,7 +712,7 @@ static void virt_machine_done(Notifier *notifier, void = *data) virt_build_smbios(s); =20 if (virt_is_acpi_enabled(s)) { - virt_acpi_setup(s); + riscv_virt_acpi_setup(s); } } =20 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 16d86edfcfc..6e4fbf4b647 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -122,7 +122,7 @@ enum { (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 bool virt_is_iommu_sys_enabled(RISCVVirtState *s); -void virt_acpi_setup(RISCVVirtState *vms); +void riscv_virt_acpi_setup(RISCVVirtState *vms); =20 /* * The virt machine physical address space used by some of the devices --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792193047; cv=none; d=zohomail.com; s=zohoarc; b=hiC3oFoj1q+TQ1CK5Kesl/NROKdSwcpx74Dqz/sedbyOY+IJGUMZuB7aYyJDK9FzRLDiWPj6ZHJV52B7CfsdansmNK/B7uyAS0tBqmBGu+7YchPqb9VhxOD8YEM7Z0C9RIkIHHdV8S65j+cksSzI/pu+e7Nmca+wkYQgxYkbxJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792193047; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YPgk74j0VerDi8vyc+2Qq309omIYhnrRYn8VjK48BiA=; b=hOuOKTctVG3h5bq8d38z5gR7FQ6yUC6mkgAsbyE8RobF8aOGUWmaqU4JSXvh8Lpeg52PeuoNHpOkw2ajq5Fji4Zp36ZFli4ADYZPXBOTf4kniTyyIWCvzCelrzIg+4ZS8vckTBJjcnPmBTtzLHAt7iJcg0IU5HaDRK3qBi7RPh8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792193047230985.4307625968003; Fri, 16 Oct 2026 16:24:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHrGp-0002v3-Mb; Fri, 16 Oct 2026 19:23:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGn-0002uJ-So for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:25 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGk-0001SO-B4 for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:25 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GNFGlW552038 for ; Fri, 16 Oct 2026 23:23:21 GMT Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbrw70wqu-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 23:23:20 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-3ab1e771632so1391654a91.1 for ; Fri, 16 Oct 2026 16:23:20 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193049014158500 Content-Type: text/plain; charset="utf-8" List of helpers: - fadd_s - fsub_s - fdiv_s - fsqrt_s - fadd_d - fsub_d - fdiv_d - fsqrt_d - crc32 - crc32c - raise_exception - wfi Reviewed-by: Daniel Henrique Barboza Signed-off-by: Pierrick Bouvier --- target/riscv/helper.h | 24 +++++++++---------- target/riscv/tcg/bitmanip_helper.c | 4 ++-- target/riscv/tcg/fpu_helper.c | 16 ++++++------- .../tcg/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/tcg/insn_trans/trans_rvd.c.inc | 8 +++---- target/riscv/tcg/insn_trans/trans_rvf.c.inc | 8 +++---- target/riscv/tcg/insn_trans/trans_rvi.c.inc | 4 ++-- .../tcg/insn_trans/trans_rvzicfiss.c.inc | 2 +- target/riscv/tcg/insn_trans/trans_xlrbr.c.inc | 4 ++-- target/riscv/tcg/op_helper.c | 4 ++-- target/riscv/tcg/translate.c | 4 ++-- 11 files changed, 40 insertions(+), 40 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 372f1049726..6aae192112a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1,5 +1,5 @@ /* Exceptions */ -DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_2(riscv_raise_exception, noreturn, env, i32) =20 /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) @@ -20,15 +20,15 @@ DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env,= i64, i64, i64) DEF_HELPER_FLAGS_4(fnmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 /* Floating Point - Single Precision */ -DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmin_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fminm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmax_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmaxm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_2(fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(riscv_fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(fleq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64) @@ -47,17 +47,17 @@ DEF_HELPER_FLAGS_2(fround_s, TCG_CALL_NO_RWG_SE, i64, e= nv, i64) DEF_HELPER_FLAGS_2(froundnx_s, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 /* Floating Point - Double Precision */ -DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmul_d, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmin_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fminm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmax_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmaxm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(riscv_fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(fleq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64) @@ -83,8 +83,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 /* Floating Point - Half Precision */ DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -135,7 +135,7 @@ DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(dret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) -DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(riscv_wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) diff --git a/target/riscv/tcg/bitmanip_helper.c b/target/riscv/tcg/bitmanip= _helper.c index d8d94bca7ba..5af3efe194d 100644 --- a/target/riscv/tcg/bitmanip_helper.c +++ b/target/riscv/tcg/bitmanip_helper.c @@ -117,7 +117,7 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ul= ong rs2) return do_xperm(rs1, rs2, 3); } =20 -target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32)(target_ulong rs1, target_ulong sz) { for (target_ulong i =3D 0; i < sz; i++) { rs1 =3D crc32_table[rs1 & 0xFF] ^ (rs1 >> 8); @@ -126,7 +126,7 @@ target_ulong HELPER(crc32)(target_ulong rs1, target_ulo= ng sz) return rs1; } =20 -target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32c)(target_ulong rs1, target_ulong sz) { for (target_ulong i =3D 0; i < sz; i++) { rs1 =3D crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8); diff --git a/target/riscv/tcg/fpu_helper.c b/target/riscv/tcg/fpu_helper.c index db1475271b6..85fc419eb95 100644 --- a/target/riscv/tcg/fpu_helper.c +++ b/target/riscv/tcg/fpu_helper.c @@ -230,14 +230,14 @@ uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t= frs1, uint64_t frs2, float_muladd_negate_c | float_muladd_negate_product); } =20 -uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +uint64_t helper_riscv_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs= 2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); } =20 -uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +uint64_t helper_riscv_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs= 2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); @@ -251,7 +251,7 @@ uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); } =20 -uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +uint64_t helper_riscv_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs= 2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); @@ -292,7 +292,7 @@ uint64_t helper_fmaxm_s(CPURISCVState *env, uint64_t rs= 1, uint64_t rs2) return nanbox_s(env, ret); } =20 -uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) +uint64_t helper_riscv_fsqrt_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); @@ -434,12 +434,12 @@ uint64_t helper_froundnx_s(CPURISCVState *env, uint64= _t rs1) return nanbox_s(env, frs1); } =20 -uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_riscv_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t f= rs2) { return float64_add(frs1, frs2, &env->fp_status); } =20 -uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_riscv_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t f= rs2) { return float64_sub(frs1, frs2, &env->fp_status); } @@ -449,7 +449,7 @@ uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs= 1, uint64_t frs2) return float64_mul(frs1, frs2, &env->fp_status); } =20 -uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_riscv_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t f= rs2) { return float64_div(frs1, frs2, &env->fp_status); } @@ -489,7 +489,7 @@ uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t r= s1) return float32_to_float64(frs1, &env->fp_status); } =20 -uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) +uint64_t helper_riscv_fsqrt_d(CPURISCVState *env, uint64_t frs1) { return float64_sqrt(frs1, &env->fp_status); } diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index e22df6fbe71..4f18b6c3fa4 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -168,7 +168,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) #ifndef CONFIG_USER_ONLY decode_save_opc(ctx, 0); gen_update_pc(ctx, ctx->cur_insn_len); - gen_helper_wfi(tcg_env); + gen_helper_riscv_wfi(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return true; #else diff --git a/target/riscv/tcg/insn_trans/trans_rvd.c.inc b/target/riscv/tcg= /insn_trans/trans_rvd.c.inc index 1be2bee9465..596a4ad888e 100644 --- a/target/riscv/tcg/insn_trans/trans_rvd.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvd.c.inc @@ -194,7 +194,7 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_d(dest, tcg_env, src1, src2); + gen_helper_riscv_fadd_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -211,7 +211,7 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_d(dest, tcg_env, src1, src2); + gen_helper_riscv_fsub_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -245,7 +245,7 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_d(dest, tcg_env, src1, src2); + gen_helper_riscv_fdiv_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -261,7 +261,7 @@ static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_= d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_d(dest, tcg_env, src1); + gen_helper_riscv_fsqrt_d(dest, tcg_env, src1); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc b/target/riscv/tcg= /insn_trans/trans_rvf.c.inc index 636dec1664d..551c9b39861 100644 --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc @@ -178,7 +178,7 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_s(dest, tcg_env, src1, src2); + gen_helper_riscv_fadd_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -194,7 +194,7 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_s(dest, tcg_env, src1, src2); + gen_helper_riscv_fsub_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -226,7 +226,7 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_s(dest, tcg_env, src1, src2); + gen_helper_riscv_fdiv_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -241,7 +241,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_= s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_s(dest, tcg_env, src1); + gen_helper_riscv_fsqrt_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index cc1b5dbbadc..8d63efe09b5 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -55,7 +55,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) */ tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); - gen_helper_raise_exception(tcg_env, + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); return true; } @@ -68,7 +68,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); - gen_helper_raise_exception(tcg_env, + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); gen_set_label(skip); } diff --git a/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc b/target/ris= cv/tcg/insn_trans/trans_rvzicfiss.c.inc index d47a9f9c7d2..0556f37805a 100644 --- a/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc @@ -43,7 +43,7 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopch= k *a) tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_BCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); - gen_helper_raise_exception(tcg_env, + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); gen_set_label(skip); tcg_gen_addi_tl(addr, addr, tmp); diff --git a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc b/target/riscv/t= cg/insn_trans/trans_xlrbr.c.inc index 01da2b6ce1d..795231f0839 100644 --- a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc @@ -29,11 +29,11 @@ static bool gen_crc(DisasContext *ctx, arg_r2 *a, #define TRANS_CRC32(NAME, SIZE) \ static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE =3D=3D 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32, tcg_constant_tl(SIZE)= ); } #define TRANS_CRC32C(NAME, SIZE) \ static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE =3D=3D 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32c, tcg_constant_tl(SIZE= )); } =20 TRANS_CRC32(b, 1); TRANS_CRC32(h, 2); diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b8b3e43ccd5..3df01016dfa 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -48,7 +48,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, cpu_loop_exit_restore(cs, pc); } =20 -void helper_raise_exception(CPURISCVState *env, uint32_t exception) +void helper_riscv_raise_exception(CPURISCVState *env, uint32_t exception) { #ifndef CONFIG_USER_ONLY riscv_pmu_decr_instret(env); @@ -625,7 +625,7 @@ void helper_ctr_clear(CPURISCVState *env) riscv_ctr_clear(env); } =20 -void helper_wfi(CPURISCVState *env) +void helper_riscv_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); bool rvs =3D riscv_has_ext(env, RVS); diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index ede9c2563f7..2ffbf26bb19 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -259,7 +259,7 @@ static void gen_update_pc(DisasContext *ctx, target_lon= g diff) static void generate_exception(DisasContext *ctx, RISCVException excp) { gen_update_pc(ctx, 0); - gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1407,7 +1407,7 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) tcg_ctx->emit_before_op =3D QTAILQ_NEXT(ctx->base.insn_start, link= ); tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193105854158500 Content-Type: text/plain; charset="utf-8" $ ./build/tests/unit/test-multi-target Type 'tcg-accel-riscv-cpu' is missing its parent 'accel-riscv-cpu' Aborted Parent type is conditionally registered from current target: register_accel_target_type uses '"accel-" + target_cpu_type()' as type name. Multi-target test takes the first target available, which is not riscv in current state. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e07ca95e49b..be913602489 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1749,6 +1749,7 @@ static const TypeInfo riscv_tcg_cpu_accel_type_info = =3D { =20 .parent =3D TYPE_ACCEL_CPU, .class_init =3D riscv_tcg_cpu_accel_class_init, + .is_available =3D target_base_riscv, .abstract =3D true, }; =20 --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792193105; cv=none; d=zohomail.com; s=zohoarc; b=OLL76Kf0tugJrhMf1ciqhvgX3EEx595WYTTUzrO4X1XaWLswfbnyZyNoiLq4ObqCY6wIQE9DzaBv5z6Ys94GpaexJWkuHkc85FFSI9aUD/XMu/h0RriK0wAJDrQH8qE1+okD0WcI56LF3RAzKFwESFG8gs04F1JestaSG0JLHGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792193105; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mVQ89yGa+x6PkYvQ7Aeo5IezZzb3plczjNJmXEs9y0A=; b=AOlpOAaS6Kc7/oGGS2r3L3C7Lzgc/3A0rPkYiuV1nHYO+7KVmsWMB4nUCMP/QbgLP9OkmIm6qBtx5bfta/Uy4OLfT1LOojcimr/xm0pfjpOyaR+aRjD+NrHhNISbbc2KnTfqWRf4ONsq7DYJP5DOisZ3xkkdPOpaZ32qhfPULfA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792193105600470.08930207781395; Fri, 16 Oct 2026 16:25:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHrGn-0002uE-HK; Fri, 16 Oct 2026 19:23:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGl-0002tL-Ok for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:23 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHrGk-0001SM-8o for qemu-devel@nongnu.org; Fri, 16 Oct 2026 19:23:23 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GNFJB4552057 for ; Fri, 16 Oct 2026 23:23:21 GMT Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbrw70wqv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 23:23:20 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-3823dcc1647so321013a91.3 for ; Fri, 16 Oct 2026 16:23:20 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193105846158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index b67a97ab458..ce3eb00f2da 100644 --- a/meson.build +++ b/meson.build @@ -4279,6 +4279,7 @@ multi_target_supported_targets =3D [ 'm68k-softmmu', 'microblaze-softmmu', 'or1k-softmmu', + 'riscv64-softmmu', 'rx-softmmu', 'tricore-softmmu', ] --=20 2.47.3 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792193091734158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Acked-by: Alistair Francis --- meson.build | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/meson.build b/meson.build index ce3eb00f2da..a025cebc6d5 100644 --- a/meson.build +++ b/meson.build @@ -4276,12 +4276,29 @@ multi_target_supported_targets =3D [ 'avr-softmmu', 'hexagon-softmmu', 'hppa-softmmu', + # 'i386-softmmu', + # 'loongarch64-softmmu', 'm68k-softmmu', 'microblaze-softmmu', + # 'mips-softmmu', + # 'mips64-softmmu', + # 'mips64el-softmmu', + # 'mipsel-softmmu', 'or1k-softmmu', + # 'ppc-softmmu', + # 'ppc64-softmmu', + # 'riscv32-softmmu', 'riscv64-softmmu', 'rx-softmmu', + # 's390x-softmmu', + # 'sh4-softmmu', + # 'sh4eb-softmmu', + # 'sparc-softmmu', + # 'sparc64-softmmu', 'tricore-softmmu', + # 'x86_64-softmmu', + # 'xtensa-softmmu', + # 'xtensaeb-softmmu', ] =20 emulators =3D {} --=20 2.47.3