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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792175326453158500 Content-Type: text/plain; charset="utf-8" This removes conflict with the same function from target/arm. To the opposite of arm target, there is no external caller for this function. Signed-off-by: Pierrick Bouvier Reviewed-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 10 +++++----- include/hw/riscv/virt.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d4b501802f6..b53ae07f9b9 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -71,6 +71,11 @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIATyp= e aia_type) return riscv_is_kvm_aia_aplic_imsic(msimode); } =20 +static bool virt_is_acpi_enabled(RISCVVirtState *s) +{ + return s->acpi !=3D ON_OFF_AUTO_OFF; +} + static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) { bool msimode =3D aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC; @@ -1066,11 +1071,6 @@ static void virt_set_iommu_sys(Object *obj, Visitor = *v, const char *name, visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); } =20 -bool virt_is_acpi_enabled(RISCVVirtState *s) -{ - return s->acpi !=3D ON_OFF_AUTO_OFF; -} - static void virt_get_acpi(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e516898f9ad..16d86edfcfc 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -121,7 +121,6 @@ enum { #define VIRT_PLIC_SIZE(__num_context) \ (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 -bool virt_is_acpi_enabled(RISCVVirtState *s); bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); =20 --=20 2.47.3 From nobody Sat Oct 24 15:41:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792175352; cv=none; d=zohomail.com; s=zohoarc; b=Emw6rJDfkuBFomUWGuzV8lZidEgH4lgypiUQ9y8nGD6HdSPqJLXDmhaXNrX6/fq8dZAtcyR4wHYkA9zHs3+8SXXPVp5ecednp+fXpo0VYdqiBvOKJepnPAqYpBlu3HMlK9oDuc2/iQ27c7lYIrl+OY57CtFbNagTnawu+KkN0DA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792175352; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EkjBTuuNx1t3GDjOBqoqRzdYNtKWZGyVRWPYYW/o6iI=; b=h6AL3wFlKDj7LIkerzRMIAaRqzpMItIfI5dlbKNZULZbLrUV3iX0PlzSLlgKigH9TyXIrgsoDF8L8A0gO9lyUi1SikuJKGBdLCXQsvHQlk8ooAquI6yFknYUHyrjYaVSPliej4c6H608OAwpKJ+H8f8VXMYEU2Zf6/xo/7extaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792175352525887.754614996854; Fri, 16 Oct 2026 11:29:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHmf0-0007dG-Tl; Fri, 16 Oct 2026 14:28:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHmeu-0007ce-GT for qemu-devel@nongnu.org; Fri, 16 Oct 2026 14:28:00 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHmes-0002wf-MT for qemu-devel@nongnu.org; Fri, 16 Oct 2026 14:28:00 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GE654Q2154151 for ; Fri, 16 Oct 2026 18:27:57 GMT Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbhumsue3-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 18:27:57 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-3ab868fe362so339856a91.2 for ; Fri, 16 Oct 2026 11:27:57 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792175352934158500 Content-Type: text/plain; charset="utf-8" This removes conflict with same function from target/arm. Signed-off-by: Pierrick Bouvier Reviewed-by: Daniel Henrique Barboza --- hw/riscv/virt-acpi-build.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/virt.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 0475dcb5c60..4565359e908 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -1021,7 +1021,7 @@ static const VMStateDescription vmstate_virt_acpi_bui= ld =3D { }, }; =20 -void virt_acpi_setup(RISCVVirtState *s) +void riscv_virt_acpi_setup(RISCVVirtState *s) { AcpiBuildTables tables; AcpiBuildState *build_state; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b53ae07f9b9..220f125d56b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -711,7 +711,7 @@ static void virt_machine_done(Notifier *notifier, void = *data) virt_build_smbios(s); =20 if (virt_is_acpi_enabled(s)) { - virt_acpi_setup(s); + riscv_virt_acpi_setup(s); } } =20 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 16d86edfcfc..6e4fbf4b647 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -122,7 +122,7 @@ enum { (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 bool virt_is_iommu_sys_enabled(RISCVVirtState *s); -void virt_acpi_setup(RISCVVirtState *vms); +void riscv_virt_acpi_setup(RISCVVirtState *vms); =20 /* * The virt machine physical address space used by some of the devices --=20 2.47.3 From nobody Sat Oct 24 15:41:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792175352; cv=none; d=zohomail.com; s=zohoarc; b=a47FIQ37ixwTs+NlyrYQtff8Kmn9tAAmTCYpU7IWsN2KnbaJ3r394IYFgx31gkK0bXeoT184B6ZgOcOsTbkFPz4KUIVPR6YYbi9uP9FIrSkBmcZho4Az7o18xKwiw1ABOf9STzcOfVQst98l12wklah4hNbjzxWRetrfHcOobII= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792175352; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Xn5yLlAal5EdekAgD06heSprBaA9iowyGv1vatdfD5o=; b=eB6ul+CkXz7uvAJCMwMcQNqJYFCgtx6viR0TkUpfreTKetbIAdRIJ84FCGaCL6fZRjBarMNF+4SkkhrDG2qnD3HJjKBaCx734bn96VvyaV7hsLQsmAGjasZtWOJeclgLKBB5xP4I233/5CnL5hxsG2Ic9lyuzaEE/N76etYtL/w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792175352805474.9239043190677; Fri, 16 Oct 2026 11:29:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHmfU-0007iy-JC; Fri, 16 Oct 2026 14:28:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHmey-0007dD-5f for qemu-devel@nongnu.org; Fri, 16 Oct 2026 14:28:05 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHmeu-0002x0-So for qemu-devel@nongnu.org; Fri, 16 Oct 2026 14:28:03 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GE65VW1451773 for ; Fri, 16 Oct 2026 18:27:59 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbhur1uxf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 18:27:59 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cd1e45a268cso135307a12.1 for ; Fri, 16 Oct 2026 11:27:59 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792175355018158500 Content-Type: text/plain; charset="utf-8" List of helpers: - fadd_s - fsub_s - fdiv_s - fsqrt_s - fadd_d - fsub_d - fdiv_d - fsqrt_d - crc32 - crc32c - raise_exception - wfi Signed-off-by: Pierrick Bouvier Reviewed-by: Daniel Henrique Barboza --- target/riscv/helper.h | 24 +++++++++---------- target/riscv/tcg/bitmanip_helper.c | 4 ++-- target/riscv/tcg/fpu_helper.c | 16 ++++++------- .../tcg/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/tcg/insn_trans/trans_rvd.c.inc | 8 +++---- target/riscv/tcg/insn_trans/trans_rvf.c.inc | 8 +++---- target/riscv/tcg/insn_trans/trans_rvi.c.inc | 4 ++-- .../tcg/insn_trans/trans_rvzicfiss.c.inc | 2 +- target/riscv/tcg/insn_trans/trans_xlrbr.c.inc | 4 ++-- target/riscv/tcg/op_helper.c | 4 ++-- target/riscv/tcg/translate.c | 4 ++-- 11 files changed, 40 insertions(+), 40 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 372f1049726..6aae192112a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1,5 +1,5 @@ /* Exceptions */ -DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_2(riscv_raise_exception, noreturn, env, i32) =20 /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) @@ -20,15 +20,15 @@ DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env,= i64, i64, i64) DEF_HELPER_FLAGS_4(fnmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 /* Floating Point - Single Precision */ -DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmin_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fminm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmax_s, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmaxm_s, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_2(fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(riscv_fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(fleq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64) @@ -47,17 +47,17 @@ DEF_HELPER_FLAGS_2(fround_s, TCG_CALL_NO_RWG_SE, i64, e= nv, i64) DEF_HELPER_FLAGS_2(froundnx_s, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 /* Floating Point - Double Precision */ -DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmul_d, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(riscv_fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmin_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fminm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmax_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmaxm_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(riscv_fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(fleq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64) @@ -83,8 +83,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(riscv_crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl) =20 /* Floating Point - Half Precision */ DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -135,7 +135,7 @@ DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(dret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) -DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(riscv_wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) diff --git a/target/riscv/tcg/bitmanip_helper.c b/target/riscv/tcg/bitmanip= _helper.c index d8d94bca7ba..5af3efe194d 100644 --- a/target/riscv/tcg/bitmanip_helper.c +++ b/target/riscv/tcg/bitmanip_helper.c @@ -117,7 +117,7 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ul= ong rs2) return do_xperm(rs1, rs2, 3); } =20 -target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32)(target_ulong rs1, target_ulong sz) { for (target_ulong i =3D 0; i < sz; i++) { rs1 =3D crc32_table[rs1 & 0xFF] ^ (rs1 >> 8); @@ -126,7 +126,7 @@ target_ulong HELPER(crc32)(target_ulong rs1, target_ulo= ng sz) return rs1; } =20 -target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz) +target_ulong HELPER(riscv_crc32c)(target_ulong rs1, target_ulong sz) { for (target_ulong i =3D 0; i < sz; i++) { rs1 =3D crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8); diff --git a/target/riscv/tcg/fpu_helper.c b/target/riscv/tcg/fpu_helper.c index db1475271b6..85fc419eb95 100644 --- a/target/riscv/tcg/fpu_helper.c +++ b/target/riscv/tcg/fpu_helper.c @@ -230,14 +230,14 @@ uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t= frs1, uint64_t frs2, float_muladd_negate_c | float_muladd_negate_product); } =20 -uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +uint64_t helper_riscv_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs= 2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); } =20 -uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +uint64_t helper_riscv_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs= 2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); @@ -251,7 +251,7 @@ uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); } =20 -uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +uint64_t helper_riscv_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs= 2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); @@ -292,7 +292,7 @@ uint64_t helper_fmaxm_s(CPURISCVState *env, uint64_t rs= 1, uint64_t rs2) return nanbox_s(env, ret); } =20 -uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) +uint64_t helper_riscv_fsqrt_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); @@ -434,12 +434,12 @@ uint64_t helper_froundnx_s(CPURISCVState *env, uint64= _t rs1) return nanbox_s(env, frs1); } =20 -uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_riscv_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t f= rs2) { return float64_add(frs1, frs2, &env->fp_status); } =20 -uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_riscv_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t f= rs2) { return float64_sub(frs1, frs2, &env->fp_status); } @@ -449,7 +449,7 @@ uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs= 1, uint64_t frs2) return float64_mul(frs1, frs2, &env->fp_status); } =20 -uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_riscv_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t f= rs2) { return float64_div(frs1, frs2, &env->fp_status); } @@ -489,7 +489,7 @@ uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t r= s1) return float32_to_float64(frs1, &env->fp_status); } =20 -uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) +uint64_t helper_riscv_fsqrt_d(CPURISCVState *env, uint64_t frs1) { return float64_sqrt(frs1, &env->fp_status); } diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index e22df6fbe71..4f18b6c3fa4 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -168,7 +168,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) #ifndef CONFIG_USER_ONLY decode_save_opc(ctx, 0); gen_update_pc(ctx, ctx->cur_insn_len); - gen_helper_wfi(tcg_env); + gen_helper_riscv_wfi(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return true; #else diff --git a/target/riscv/tcg/insn_trans/trans_rvd.c.inc b/target/riscv/tcg= /insn_trans/trans_rvd.c.inc index 1be2bee9465..596a4ad888e 100644 --- a/target/riscv/tcg/insn_trans/trans_rvd.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvd.c.inc @@ -194,7 +194,7 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_d(dest, tcg_env, src1, src2); + gen_helper_riscv_fadd_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -211,7 +211,7 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_d(dest, tcg_env, src1, src2); + gen_helper_riscv_fsub_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -245,7 +245,7 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_d(dest, tcg_env, src1, src2); + gen_helper_riscv_fdiv_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -261,7 +261,7 @@ static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_= d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_d(dest, tcg_env, src1); + gen_helper_riscv_fsqrt_d(dest, tcg_env, src1); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc b/target/riscv/tcg= /insn_trans/trans_rvf.c.inc index 636dec1664d..551c9b39861 100644 --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc @@ -178,7 +178,7 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_s(dest, tcg_env, src1, src2); + gen_helper_riscv_fadd_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -194,7 +194,7 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_s(dest, tcg_env, src1, src2); + gen_helper_riscv_fsub_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -226,7 +226,7 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_s(dest, tcg_env, src1, src2); + gen_helper_riscv_fdiv_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -241,7 +241,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_= s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_s(dest, tcg_env, src1); + gen_helper_riscv_fsqrt_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index cc1b5dbbadc..8d63efe09b5 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -55,7 +55,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) */ tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); - gen_helper_raise_exception(tcg_env, + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); return true; } @@ -68,7 +68,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); - gen_helper_raise_exception(tcg_env, + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); gen_set_label(skip); } diff --git a/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc b/target/ris= cv/tcg/insn_trans/trans_rvzicfiss.c.inc index d47a9f9c7d2..0556f37805a 100644 --- a/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc @@ -43,7 +43,7 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopch= k *a) tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_BCFI_TVAL), tcg_env, offsetof(CPURISCVState, sw_check_code)); - gen_helper_raise_exception(tcg_env, + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); gen_set_label(skip); tcg_gen_addi_tl(addr, addr, tmp); diff --git a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc b/target/riscv/t= cg/insn_trans/trans_xlrbr.c.inc index 01da2b6ce1d..795231f0839 100644 --- a/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xlrbr.c.inc @@ -29,11 +29,11 @@ static bool gen_crc(DisasContext *ctx, arg_r2 *a, #define TRANS_CRC32(NAME, SIZE) \ static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE =3D=3D 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32, tcg_constant_tl(SIZE)= ); } #define TRANS_CRC32C(NAME, SIZE) \ static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \ { if (SIZE =3D=3D 8) { REQUIRE_64BIT(ctx); }; \ - return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); } + return gen_crc(ctx, a, gen_helper_riscv_crc32c, tcg_constant_tl(SIZE= )); } =20 TRANS_CRC32(b, 1); TRANS_CRC32(h, 2); diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b8b3e43ccd5..3df01016dfa 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -48,7 +48,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, cpu_loop_exit_restore(cs, pc); } =20 -void helper_raise_exception(CPURISCVState *env, uint32_t exception) +void helper_riscv_raise_exception(CPURISCVState *env, uint32_t exception) { #ifndef CONFIG_USER_ONLY riscv_pmu_decr_instret(env); @@ -625,7 +625,7 @@ void helper_ctr_clear(CPURISCVState *env) riscv_ctr_clear(env); } =20 -void helper_wfi(CPURISCVState *env) +void helper_riscv_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); bool rvs =3D riscv_has_ext(env, RVS); diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index ede9c2563f7..2ffbf26bb19 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -259,7 +259,7 @@ static void gen_update_pc(DisasContext *ctx, target_lon= g diff) static void generate_exception(DisasContext *ctx, RISCVException excp) { gen_update_pc(ctx, 0); - gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); + gen_helper_riscv_raise_exception(tcg_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1407,7 +1407,7 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) tcg_ctx->emit_before_op =3D QTAILQ_NEXT(ctx->base.insn_start, link= ); tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), tcg_env, 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792175359050158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Reviewed-by: Daniel Henrique Barboza --- include/qemu/target-info.h | 7 +++++++ target-info.c | 11 +++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 862097c6c63..b0f3b4cfb8b 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -112,6 +112,13 @@ bool target_ppc64(void); */ bool target_s390x(void); =20 +/** + * target_base_riscv: + * + * Returns whether the target architecture is RISC-V 32-bit or 64-bit. + */ +bool target_base_riscv(void); + /** * target_riscv64: * diff --git a/target-info.c b/target-info.c index 254530d8ea5..e827026bd23 100644 --- a/target-info.c +++ b/target-info.c @@ -104,6 +104,17 @@ bool target_s390x(void) return target_arch() =3D=3D SYS_EMU_TARGET_S390X; } =20 +bool target_base_riscv(void) +{ + switch (target_arch()) { + case SYS_EMU_TARGET_RISCV32: + case SYS_EMU_TARGET_RISCV64: + return true; + default: + return false; + } +} + bool target_riscv64(void) { return target_arch() =3D=3D SYS_EMU_TARGET_RISCV64; --=20 2.47.3 From nobody Sat Oct 24 15:41:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792175359046158500 Content-Type: text/plain; charset="utf-8" $ ./build/tests/unit/test-multi-target Type 'tcg-accel-riscv-cpu' is missing its parent 'accel-riscv-cpu' Aborted Parent type is conditionally registered from current target: register_accel_target_type uses '"accel-" + target_cpu_type()' as type name. Multi-target test takes the first target available, which is not riscv in current state. Signed-off-by: Pierrick Bouvier Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e07ca95e49b..be913602489 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1749,6 +1749,7 @@ static const TypeInfo riscv_tcg_cpu_accel_type_info = =3D { =20 .parent =3D TYPE_ACCEL_CPU, .class_init =3D riscv_tcg_cpu_accel_class_init, + .is_available =3D target_base_riscv, .abstract =3D true, }; =20 --=20 2.47.3 From nobody Sat Oct 24 15:41:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792175333; cv=none; d=zohomail.com; s=zohoarc; b=TZkcF7PH5QEjITrnsB2XppqmXIzJrRyQ7gKrglCQsAYZ5x/DZ/seLAr3dWlbk1uMuqOQ/qQGAAyIXC4xrqaBcxhtacqtVBcPeaRejgvOw1oDLFr9d/YYANuba/ibbif884bxqNDDI8GMdx2SAb1td6WRkvTfvNbEl/o12EH2jnA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792175333; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KNdJSxw6lnIw8GulV/ST8A6A+dKhkfuEhtyi8Ir9t1U=; b=j1pcFEZI6g8y7b/x6YSFcg+2jqTBdfFvWDtK76uQMmIpMkHhUwJQI2mUcp7isk++2yRXRhSlytLoLfJfCCX6LtVUw+fI+ZRyO23W6NVbTGzSr2MFP4iTv3Z0scNsElpxDtUkutGe5OmyUgOWD8uSPsRVy3dlquS7E82wZ6uypZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792175333063368.2383652716338; Fri, 16 Oct 2026 11:28:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHmfC-0007eO-5O; Fri, 16 Oct 2026 14:28:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHmey-0007dE-6P for qemu-devel@nongnu.org; Fri, 16 Oct 2026 14:28:05 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHmew-0002xZ-BG for qemu-devel@nongnu.org; Fri, 16 Oct 2026 14:28:03 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69GE5xCE1450921 for ; Fri, 16 Oct 2026 18:28:01 GMT Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hbhur1uxm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 16 Oct 2026 18:28:01 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-868db1b2c64so139604b3a.3 for ; Fri, 16 Oct 2026 11:28:01 -0700 (PDT) Received: from pc.taild8403c.ts.net (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792175334740158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Reviewed-by: Daniel Henrique Barboza --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index b67a97ab458..c76d1bba5b2 100644 --- a/meson.build +++ b/meson.build @@ -4280,6 +4280,7 @@ multi_target_supported_targets =3D [ 'microblaze-softmmu', 'or1k-softmmu', 'rx-softmmu', + 'riscv64-softmmu', 'tricore-softmmu', ] =20 --=20 2.47.3