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Thu, 15 Oct 2026 18:02:48 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: imaginos , qemu-stable@nongnu.org, Alistair Francis Subject: [PULL v2 01/50] target/riscv: check G-stage write permission for VS-stage A/D updates Date: Fri, 16 Oct 2026 11:01:48 +1000 Message-ID: <20261016010237.1102834-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112619313158500 Content-Type: text/plain; charset="utf-8" From: imaginos During a two-stage (VS-stage + G-stage) page-table walk with hardware A/D updating enabled (Svadu / menvcfg.ADUE), a store that reaches a VS-stage leaf PTE whose accessed or dirty bit is clear triggers a hardware write-back of those bits into the PTE. That write-back is an implicit store to the PTE's guest-physical address, so it must be permitted by G-stage. Fix this by re-running the G-stage translation of the guest PTE's address with store semantics. get_physical_address() then also checks that G-stage permits the guest PTE to be written, and raises a guest-page store fault when it does not. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3426 Signed-off-by: imaginos Reviewed-by: Alistair Francis Message-ID: <20260705140508.17692-1-imaginos32@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/cpu_helper.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 07d9222652..6115f65adb 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -1133,6 +1133,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, int ptshift; target_ulong pte; hwaddr pte_addr; + hwaddr pte_gpa =3D 0; const hwaddr base_root =3D base; const bool be =3D mo_endian_env(env) =3D=3D MO_BE; int i; @@ -1170,6 +1171,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, } =20 pte_addr =3D vbase + idx * ptesize; + pte_gpa =3D base + idx * ptesize; } else { pte_addr =3D base + idx * ptesize; } @@ -1424,6 +1426,28 @@ static int get_physical_address(CPURISCVState *env, = hwaddr *physical, return TRANSLATE_FAIL; } =20 + /* + * The implicit store that writes updated A/D bits back to a VS-st= age + * (first-stage) PTE must itself be permitted by G-stage. Re-run t= he + * second-stage translation of the PTE's guest-physical address wi= th + * store semantics. If G-stage denies write, raise G-stage store f= ault + * against the PTE address. + */ + if (two_stage && first_stage) { + int gpa_prot; + hwaddr gpa_paddr; + int gpa_ret =3D get_physical_address(env, &gpa_paddr, &gpa_pro= t, + pte_gpa, NULL, MMU_DATA_STO= RE, + MMUIdx_U, false, true, + is_debug, false); + if (gpa_ret !=3D TRANSLATE_SUCCESS) { + if (fault_pte_addr) { + *fault_pte_addr =3D pte_gpa >> 2; + } + return TRANSLATE_G_STAGE_FAIL; + } + } + pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, sxlen_bytes, MMU_DATA_STORE, PR= V_S); if (pmp_ret !=3D TRANSLATE_SUCCESS) { @@ -2114,6 +2138,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) * doing VS-stage page table walk. */ tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + + if (cause =3D=3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT) { + tinst |=3D 0x20; + } } else { /* * The "Addr. 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Thu, 15 Oct 2026 18:02:51 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Mayuresh Chitale , qemu-stable@nongnu.org, Daniel Henrique Barboza , Gong Shuai , TianCheng TANG , Alistair Francis Subject: [PULL v2 02/50] target/riscv: Restore LCOFI handling in interrupt CSRs Date: Fri, 16 Oct 2026 11:01:49 +1000 Message-ID: <20261016010237.1102834-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112614178158500 Content-Type: text/plain; charset="utf-8" From: Mayuresh Chitale Commit 27f9566dcd98 dropped bits 13-15 from the LOCAL_INTERRUPTS macro and hence also from individual masks such as all_ints, sip_writable_mask etc. As a result, even with sscofpmf and ssaia enabled, the LCOFI never got delivered to the host OS and guest OS respectively. Add back bit 13 in all the affected masks, but gate it on Sscofpmf being implemented. For the virtual interrupt paths, i.e., mvip/mvien, hvip/hvien/vsip/vsie registers, bit 13 is additionally gated on Smaia and Ssaia respectively. Bits 14, 15 can be added when those interrupt sources get defined. Cc: qemu-stable@nongnu.org Fixes: 27f9566dcd98 ("target/riscv: Update the local interrupt mask") Reviewed-by: Daniel Henrique Barboza Suggested-by: Gong Shuai Suggested-by: TianCheng TANG Signed-off-by: Mayuresh Chitale Message-ID: <20260921145334.419651-1-mayuresh.chitale@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/csr.c | 88 +++++++++++++++++++++++++++++++++++------- 1 file changed, 73 insertions(+), 15 deletions(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 061bc9db77..a3351428cb 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -1815,7 +1815,7 @@ static RISCVException write_stimecmph(CPURISCVState *= env, int csrno, #define LOCAL_INTERRUPTS (~0xFFFFULL) =20 static const uint64_t delegable_ints =3D - S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; + S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const uint64_t vs_delegable_ints =3D (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; static const uint64_t all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | @@ -1877,6 +1877,42 @@ static const uint64_t hvien_writable_mask =3D LOCAL_= INTERRUPTS; =20 static const uint64_t vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRUPTS; =20 +/* + * Selects the extensions that need to be checked when accessing various + * interrupt registers. + */ +typedef enum { + /* Accessing mideleg, mie, mip, and alias paths */ + AIA_NONE, + /* Accessing mvien, mvip non-alias path */ + AIA_SMAIA, + /* Accessing hvien, hvip, vsie, vsip paths */ + AIA_SSAIA, +} AIAExt; + +/* + * This function can be extended later to configure mask for standard local + * interrupt bits 14 and 15, once those get defined in the Priv Spec. + */ +static uint64_t std_impl_intr_mask(CPURISCVState *env, AIAExt ext) +{ + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); + + if (ext =3D=3D AIA_SMAIA && !cfg->ext_smaia) { + return 0; + } + + if (ext =3D=3D AIA_SSAIA && !cfg->ext_ssaia) { + return 0; + } + + if (!cfg->ext_sscofpmf) { + return 0; + } + + return MIP_LCOFIP; +} + /* Machine Information Registers */ static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulong *val) @@ -2249,8 +2285,10 @@ static RISCVException rmw_mideleg64(CPURISCVState *e= nv, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_NONE); uint64_t mask =3D wr_mask & delegable_ints; =20 + mask |=3D wr_mask & std_mask; if (ret_val) { *ret_val =3D env->mideleg; } @@ -2300,8 +2338,10 @@ static RISCVException rmw_mie64(CPURISCVState *env, = int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_NONE); uint64_t mask =3D wr_mask & all_ints; =20 + mask |=3D wr_mask & std_mask; if (ret_val) { *ret_val =3D env->mie; } @@ -2350,8 +2390,10 @@ static RISCVException rmw_mvien64(CPURISCVState *env= , int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_SMAIA); uint64_t mask =3D wr_mask & mvien_writable_mask; =20 + mask |=3D wr_mask & std_mask; if (ret_val) { *ret_val =3D env->mvien; } @@ -3784,9 +3826,12 @@ static RISCVException rmw_mip64(CPURISCVState *env, = int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_NONE); uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 + mask |=3D wr_mask & std_mask; + /* * When mvien[9]=3D1, mip.SEIP is read-only and reflects only * the external interrupt signal from the interrupt controller. @@ -3900,9 +3945,12 @@ static RISCVException rmw_mvip64(CPURISCVState *env,= int csrno, * alias_mask denotes the bits that come from mip nalias_mask denotes= bits * that come from hvip. */ - uint64_t alias_mask =3D ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + AIAExt intr_virt =3D ((csrno =3D=3D CSR_MVIP) || (csrno =3D=3D CSR_MVI= PH)) ? + AIA_SMAIA : AIA_NONE; + uint64_t std_mask =3D std_impl_intr_mask(env, intr_virt); + uint64_t alias_mask =3D ((S_MODE_INTERRUPTS | std_mask | LOCAL_INTERRU= PTS) & (env->mideleg | ~env->mvien)) | MIP_STIP; - uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | std_mask | LOCAL_INTERRU= PTS) & (~env->mideleg & env->mvien); uint64_t wr_mask_mvip; uint64_t wr_mask_mip; @@ -3931,8 +3979,8 @@ static RISCVException rmw_mvip64(CPURISCVState *env, = int csrno, alias_mask &=3D ~MIP_STIP; } =20 - wr_mask_mip =3D wr_mask & alias_mask & mvip_writable_mask; - wr_mask_mvip =3D wr_mask & nalias_mask & mvip_writable_mask; + wr_mask_mip =3D wr_mask & alias_mask & (mvip_writable_mask | std_mask); + wr_mask_mvip =3D wr_mask & nalias_mask & (mvip_writable_mask | std_mas= k); =20 /* * For bits set in alias_mask, mvip needs to be alias of mip, so forwa= rd @@ -4065,9 +4113,11 @@ static RISCVException rmw_vsie64(CPURISCVState *env,= int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { - uint64_t alias_mask =3D (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) & - env->hideleg; - uint64_t nalias_mask =3D LOCAL_INTERRUPTS & (~env->hideleg & env->hvie= n); + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_SSAIA); + uint64_t alias_mask =3D (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS | + std_mask) & env->hideleg; + uint64_t nalias_mask =3D (LOCAL_INTERRUPTS | std_mask) & + (~env->hideleg & env->hvien); uint64_t rval, rval_vs, vsbits; uint64_t wr_mask_vsie; uint64_t wr_mask_mie; @@ -4135,9 +4185,11 @@ static RISCVException rmw_sie64(CPURISCVState *env, = int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { - uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_NONE); + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | std_mask | LOCAL_INTERRU= PTS) & (~env->mideleg & env->mvien); - uint64_t alias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->= mideleg; + uint64_t alias_mask =3D (S_MODE_INTERRUPTS | std_mask | LOCAL_INTERRUP= TS) & + env->mideleg; uint64_t sie_mask =3D wr_mask & nalias_mask; RISCVException ret; =20 @@ -4320,6 +4372,7 @@ static RISCVException rmw_vsip64(CPURISCVState *env, = int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_SSAIA); uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; uint64_t vsbits; =20 @@ -4335,7 +4388,7 @@ static RISCVException rmw_vsip64(CPURISCVState *env, = int csrno, wr_mask |=3D vsbits << 1; =20 ret =3D rmw_hvip64(env, csrno, &rval, new_val, - wr_mask & mask & vsip_writable_mask); + wr_mask & mask & (vsip_writable_mask | std_mask)); if (ret_val) { rval &=3D mask; vsbits =3D rval & VS_MODE_INTERRUPTS; @@ -4382,7 +4435,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t mask =3D (env->mideleg | env->mvien) & sip_writable_mask; + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_NONE); + uint64_t mask =3D (env->mideleg | env->mvien) & + (sip_writable_mask | std_mask); =20 if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { @@ -4395,7 +4450,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, =20 if (ret_val) { *ret_val &=3D (env->mideleg | env->mvien) & - (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); + (S_MODE_INTERRUPTS | std_mask | LOCAL_INTERRUPTS); } =20 return ret; @@ -4737,7 +4792,9 @@ static RISCVException rmw_hvien64(CPURISCVState *env,= int csrno, uint64_t new_val, uint64_t wr_mask) { uint64_t mask =3D wr_mask & hvien_writable_mask; + uint64_t std_mask =3D std_impl_intr_mask(env, AIA_SSAIA); =20 + mask |=3D wr_mask & std_mask; if (ret_val) { *ret_val =3D env->hvien; } @@ -4861,6 +4918,7 @@ static RISCVException rmw_hvip64(CPURISCVState *env, = int csrno, */ uint64_t alias_mask =3D (env->hideleg | ~env->hvien) | VS_MODE_INTERRU= PTS; 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charset="utf-8" From: Richard Henderson Resolves: Coverity CID 1685513 Fixes: 4fec981f18fd ("disas/riscv: Split rvi_opcode_data") Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20260914015316.792751-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- disas/riscv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index e85dbac035..ef8b7ff20f 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2560,7 +2560,6 @@ static const rv_opcode_data *decode_inst_opcode(rv_de= code *dec, rv_isa isa) } break; case 2: - return &op_csrrs; if (operand_rs1(inst) =3D=3D 0) { switch (operand_csr12(inst)) { case 0x001: return &op_frflags; @@ -2574,7 +2573,7 @@ static const rv_opcode_data *decode_inst_opcode(rv_de= code *dec, rv_isa isa) case 0xc82: return &op_rdinstreth; } } - break; + return &op_csrrs; case 3: return &op_csrrc; case 4: if (dec->cfg && dec->cfg->ext_zimop) { --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:02:58 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Zephyr Li , qemu-stable@nongnu.org, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 04/50] target/riscv: stop translating after WFI Date: Fri, 16 Oct 2026 11:01:51 +1000 Message-ID: <20261016010237.1102834-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=alistair23@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112664605158500 Content-Type: text/plain; charset="utf-8" From: Zephyr Li helper_wfi() never returns to translated code: it either raises an exception or exits the CPU loop after marking the CPU as halted. However, trans_wfi() leaves the translation state as DISAS_NEXT, so instructions following WFI can be included in the same TB. With icount enabled, this makes the following instruction part of the TB's instruction count when WFI exits, causing minstret to be incremented once too many. Set DISAS_NORETURN after emitting the helper. Add a TCG test for both reported cases: WFI waking for a locally enabled pending interrupt with mstatus.MIE clear, and WFI taking a timer interrupt. Cc: qemu-stable@nongnu.org Fixes: 55c2a12cbcd3 ("RISC-V TCG Code Generation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4230 Signed-off-by: Zephyr Li Reviewed-by: Daniel Henrique Barboza Message-ID: <20260910025324.54990-1-fritchleybohrer@gmail.com> Signed-off-by: Alistair Francis --- .../tcg/insn_trans/trans_privileged.c.inc | 1 + tests/tcg/riscv64/system/meson.build | 1 + tests/tcg/riscv64/test-minstret-wfi.S | 100 ++++++++++++++++++ 3 files changed, 102 insertions(+) create mode 100644 tests/tcg/riscv64/test-minstret-wfi.S diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index a8eaccef67..ebbbb01179 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -145,6 +145,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) decode_save_opc(ctx, 0); gen_update_pc(ctx, ctx->cur_insn_len); gen_helper_wfi(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; return true; #else return false; diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/syste= m/meson.build index c2d7d09887..a632674832 100644 --- a/tests/tcg/riscv64/system/meson.build +++ b/tests/tcg/riscv64/system/meson.build @@ -23,6 +23,7 @@ tests +=3D { 'test-mepc-masking.S': setup, 'test-crc32.S': setup + {'qemu_args': ['-cpu', 'rv64,xlrbr=3Dtrue', qemu= _args]}, 'test-minstret-ecall.S': setup + {'qemu_args': ['-icount', 'shift=3D1', = qemu_args]}, + 'test-minstret-wfi.S': setup + {'qemu_args': ['-icount', 'shift=3D1', qe= mu_args]}, 'test-misa-w.S': setup + {'qemu_args': ['-cpu', 'rv64,x-misa-w=3Dtrue,c= =3Dtrue,v=3Dtrue', qemu_args]}, } =20 diff --git a/tests/tcg/riscv64/test-minstret-wfi.S b/tests/tcg/riscv64/test= -minstret-wfi.S new file mode 100644 index 0000000000..0fd0158d5b --- /dev/null +++ b/tests/tcg/riscv64/test-minstret-wfi.S @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + .option norvc + + .text + .global _start +_start: + lla t0, trap + csrw mtvec, t0 + li s3, 0 + + /* + * A pending, locally enabled interrupt wakes WFI even with MIE + * clear. + */ + li t0, 0x8 /* MIE_MSIE */ + csrw mie, t0 + csrci mstatus, 0x8 /* MSTATUS_MIE */ + li t0, 0x2000000 /* MSIP0 */ + li t1, 1 + sw t1, 0(t0) + + /* + * The first CSR read and WFI retire before the second read obtains s1, + * so the expected difference is two. + */ + csrr s0, minstret + wfi + csrr s1, minstret + sub s1, s1, s0 + li t1, 2 + beq s1, t1, 1f + ori s3, s3, 1 +1: + + /* Clear the software interrupt before testing the trap path. */ + sw zero, 0(t0) + csrw mie, zero + + /* Schedule a timer interrupt far enough ahead to reach WFI first. */ + li t0, 0x200bff8 /* MTIME */ + ld t1, 0(t0) + addi t1, t1, 100 + li t0, 0x2004000 /* MTIMECMP0 */ + sd t1, 0(t0) + li t0, 0x80 /* MIE_MTIE */ + csrw mie, t0 + csrsi mstatus, 0x8 /* MSTATUS_MIE */ + + /* + * The first CSR read and WFI retire before the trap handler obtains s1, + * so the expected difference is again two. + */ + li s2, 1 + csrr s0, minstret + wfi + beqz s2, 1f + ori s3, s3, 2 +1: + bnez s3, fail + li a0, 0 + j _exit + +fail: + mv a0, s3 + +_exit: + lla a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + + /* Semihosting call sequence */ + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .balign 4 +trap: + /* Read minstret before retiring an instruction in the handler. */ + csrr s1, minstret + sub s1, s1, s0 + addi s1, s1, -2 + snez s2, s1 + + /* Disable the timer interrupt before returning past WFI. */ + li t0, 0x2004000 /* MTIMECMP0 */ + li t1, -1 + sd t1, 0(t0) + li t0, 0x80 /* MIE_MTIE */ + csrc mie, t0 + mret + + .data + .balign 16 +semiargs: + .space 16 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:01 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: "Christian S. Lima" , qemu-stable@nongnu.org, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 05/50] targetriscv: svinval instructions raise virtual instruction exception Date: Fri, 16 Oct 2026 11:01:52 +1000 Message-ID: <20261016010237.1102834-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112692686158500 Content-Type: text/plain; charset="utf-8" From: "Christian S. Lima" The risc v privileged specification requires hinval.vvma, hinval.gvma, sfence.w.inval and sfence.inval.ir should raise a virtual instruction exception when executed in the vu-mode. This patch add the check to raise the virtual instruction exception when is in the vu-mode. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3621 Signed-off-by: Christian S. Lima Reviewed-by: Daniel Henrique Barboza Message-ID: <20260911201323.37757-1-christianslima@proton.me> Signed-off-by: Alistair Francis --- target/riscv/tcg/insn_trans/trans_svinval.c.inc | 3 +++ target/riscv/tcg/insn_trans/trans_xthead.c.inc | 12 +++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_svinval.c.inc b/target/riscv= /tcg/insn_trans/trans_svinval.c.inc index 4614c1489c..1341beba2f 100644 --- a/target/riscv/tcg/insn_trans/trans_svinval.c.inc +++ b/target/riscv/tcg/insn_trans/trans_svinval.c.inc @@ -25,6 +25,9 @@ /* Test if priv level is M or S. */ #define REQUIRE_PRIV_MS(ctx) do { \ if (ctx->priv =3D=3D PRV_U) { \ + if (ctx->virt_enabled) { \ + ctx->virt_inst_excp =3D true; \ + } \ return false; \ } \ } while (0) diff --git a/target/riscv/tcg/insn_trans/trans_xthead.c.inc b/target/riscv/= tcg/insn_trans/trans_xthead.c.inc index f4e3051000..ea4b169422 100644 --- a/target/riscv/tcg/insn_trans/trans_xthead.c.inc +++ b/target/riscv/tcg/insn_trans/trans_xthead.c.inc @@ -267,11 +267,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_ts= t *a) #define REQUIRE_PRIV_MSU(ctx) =20 /* Test if priv level is M or S. */ -#define REQUIRE_PRIV_MS(ctx) \ -do { \ - if (ctx->priv =3D=3D PRV_U) { \ - return false; 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charset="utf-8" From: Xie Bo kvm_riscv_get_regs_fp() and kvm_riscv_put_regs_fp() handle f0-f31 but not FCSR. KVM exposes FCSR as a separate 32-bit register in both the F and D register groups, so frm and fflags are lost after migration. Read and write FCSR together with the FP registers and save it in a KVM-only subsection. Older streams do not contain the subsection; in that case the destination keeps its reset value. Fixes: 937f0b45120b ("target/riscv: Implement kvm_arch_get_registers") Fixes: 9997cc1e19d1 ("target/riscv: Implement kvm_arch_put_registers") Signed-off-by: Xie Bo Cc: qemu-stable@nongnu.org Reviewed-by: Daniel Henrique Barboza Message-ID: <20260831074106.1798671-2-xb@ultrarisc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/kvm/kvm-cpu.c | 20 ++++++++++++++++---- target/riscv/machine.c | 27 +++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c8ffe94cd..25f8ec00a9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -535,6 +535,9 @@ struct CPUArchState { hwaddr fdt_addr; =20 #ifdef CONFIG_KVM + /* KVM floating-point state */ + uint32_t kvm_fcsr; + /* kvm timer */ bool kvm_timer_dirty; uint64_t kvm_timer_time; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 68e1501b21..c8ccd9124e 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -111,6 +111,14 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 +#define RISCV_FP_F_FCSR_REG \ + KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, \ + KVM_REG_RISCV_FP_F_REG(fcsr)) + +#define RISCV_FP_D_FCSR_REG \ + KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_D, \ + KVM_REG_RISCV_FP_D_REG(fcsr)) + #define RISCV_VECTOR_CSR_REG(name) \ KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) @@ -743,7 +751,8 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) } env->fpr[i] =3D reg; } - return ret; + return kvm_get_one_reg(cs, RISCV_FP_D_FCSR_REG, + &env->kvm_fcsr); } =20 if (riscv_has_ext(env, RVF)) { @@ -755,7 +764,8 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) } env->fpr[i] =3D reg; } - return ret; + return kvm_get_one_reg(cs, RISCV_FP_F_FCSR_REG, + &env->kvm_fcsr); } =20 return ret; @@ -776,7 +786,8 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) return ret; } } - return ret; + return kvm_set_one_reg(cs, RISCV_FP_D_FCSR_REG, + &env->kvm_fcsr); } =20 if (riscv_has_ext(env, RVF)) { @@ -788,7 +799,8 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) return ret; } } - return ret; + return kvm_set_one_reg(cs, RISCV_FP_F_FCSR_REG, + &env->kvm_fcsr); } =20 return ret; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index bf203bffce..3238912b63 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -197,6 +197,32 @@ static const VMStateDescription vmstate_rv128 =3D { }; =20 #ifdef CONFIG_KVM +static bool kvm_fcsr_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; 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Thu, 15 Oct 2026 18:03:07 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Xie Bo , qemu-stable@nongnu.org, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 07/50] target/riscv/kvm: Reject migration with a different timer frequency Date: Fri, 16 Oct 2026 11:01:54 +1000 Message-ID: <20261016010237.1102834-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112662281158500 Content-Type: text/plain; charset="utf-8" From: Xie Bo The timer frequency check is currently in kvm_riscv_put_regs_timer() and guarded by migration_is_running(). That condition is false on the incoming side, and the source frequency is not part of the migration stream, so migration between hosts with different frequencies completes. Add the source frequency to a KVM-only subsection. Its post_load checks the destination frequency before the timer registers are restored and rejects a mismatch. When loading an older stream without the subsection, skip the check and retain the old behavior. Fixes: 27abe66f31ef ("target/riscv: Add kvm_riscv_get/put_regs_timer") Signed-off-by: Xie Bo Cc: qemu-stable@nongnu.org Reviewed-by: Daniel Henrique Barboza Message-ID: <20260831074106.1798671-3-xb@ultrarisc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm_riscv.h | 1 + target/riscv/kvm/kvm-cpu.c | 40 +++++++++++++++++++++++------------- target/riscv/machine.c | 31 ++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 25f8ec00a9..5489c564ae 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -544,6 +544,7 @@ struct CPUArchState { uint64_t kvm_timer_compare; uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; + bool kvm_timer_frequency_loaded; =20 /* KVM multiprocessor state */ uint32_t kvm_mp_state; diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 61eaa12443..0e27ce8bf3 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -29,6 +29,7 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); bool kvm_riscv_has_mp_state(void); +int kvm_riscv_check_timer_frequency(RISCVCPU *cpu); void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu); =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c8ccd9124e..1993bd446b 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -45,7 +45,6 @@ #include "kvm_riscv.h" #include "sbi_ecall_interface.h" #include "chardev/char-fe.h" -#include "migration/misc.h" #include "system/runstate.h" #include "hw/riscv/numa.h" =20 @@ -822,9 +821,34 @@ static void kvm_riscv_get_regs_timer(CPUState *cs) env->kvm_timer_dirty =3D true; } =20 +int kvm_riscv_check_timer_frequency(RISCVCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + CPURISCVState *env =3D &cpu->env; + int ret; + uint64_t frequency; + + if (!env->kvm_timer_frequency_loaded) { + return 0; + } + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(frequency), &frequency); + if (ret) { + return ret; + } + + if (frequency !=3D env->kvm_timer_frequency) { + error_report("KVM timer frequency mismatch: source %" PRIu64 + " Hz, destination %" PRIu64 " Hz", + env->kvm_timer_frequency, frequency); + return -EINVAL; + } + + return 0; +} + static void kvm_riscv_put_regs_timer(CPUState *cs) { - uint64_t reg; CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 if (!env->kvm_timer_dirty) { @@ -844,18 +868,6 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); } =20 - /* - * For now, migration will not work between Hosts with different timer - * frequency. Therefore, we should check whether they are the same here - * during the migration. - */ - if (migration_is_running()) { - KVM_RISCV_GET_TIMER(cs, frequency, reg); - if (reg !=3D env->kvm_timer_frequency) { - error_report("Dst Hosts timer frequency !=3D Src Hosts"); - } - } - env->kvm_timer_dirty =3D false; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 3238912b63..ed10e65259 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -197,6 +197,35 @@ static const VMStateDescription vmstate_rv128 =3D { }; =20 #ifdef CONFIG_KVM +static bool kvm_timer_frequency_needed(void *opaque) +{ + return kvm_enabled(); +} + +static int kvm_timer_frequency_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + + if (!kvm_enabled()) { + return -ENOTSUP; + } + + cpu->env.kvm_timer_frequency_loaded =3D true; + return kvm_riscv_check_timer_frequency(cpu); +} + +static const VMStateDescription vmstate_kvm_timer_frequency =3D { + .name =3D "cpu/kvm-timer-frequency", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D kvm_timer_frequency_needed, + .post_load =3D kvm_timer_frequency_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(env.kvm_timer_frequency, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + static bool kvm_fcsr_needed(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -255,6 +284,7 @@ static int riscv_cpu_kvm_pre_load(void *opaque) { RISCVCPU *cpu =3D opaque; =20 + cpu->env.kvm_timer_frequency_loaded =3D false; cpu->env.kvm_mp_state_loaded =3D false; return 0; } @@ -591,6 +621,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_rv128, #ifdef CONFIG_KVM &vmstate_kvm_fcsr, + &vmstate_kvm_timer_frequency, &vmstate_kvmtimer, &vmstate_kvm_mp_state, #endif --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1792112818; cv=none; d=zohomail.com; s=zohoarc; b=JvwEpi1QjwU7kW/X45QS0jdKLeTLLUtRL8zQQ9WMZBAYbkLEjTiuBe0uhBSk1PKrCPu5iSw1uKfSNOqVglDT8OLtuB3uKoz6yT2zhivqCsRjTiBN6OlZz13AIVDPAUivaYIgiRMxZ+ZcOYYPLNOWN2l6NZierUrAOBi0C27i9lg= ARC-Message-Signature: i=1; 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charset="utf-8" From: Xie Bo The vector state sync handles vstart, vl and vtype, but leaves vcsr behind. vxrm and vxsat in the migration stream are therefore stale, and the destination does not restore the values held by KVM. Read vcsr when collecting vector state and split it into vxrm and vxsat. Rebuild it from those fields when writing vector state back. Fixes: 3ca78c0689d5 ("target/riscv/kvm: add RVV and Vector CSR regs") Cc: qemu-stable@nongnu.org Signed-off-by: Xie Bo Reviewed-by: Daniel Henrique Barboza Message-ID: <20260831074106.1798671-4-xb@ultrarisc.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 1993bd446b..45ad5e1525 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -910,6 +910,13 @@ static int kvm_riscv_get_regs_vector(CPUState *cs) } env->vtype =3D reg; =20 + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vcsr), ®); + if (ret) { + return ret; + } + env->vxrm =3D (reg & VCSR_VXRM) >> VCSR_VXRM_SHIFT; + env->vxsat =3D (reg & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; + if (kvm_v_vlenb.supported) { ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); if (ret) { @@ -966,6 +973,13 @@ static int kvm_riscv_put_regs_vector(CPUState *cs) return ret; } =20 + reg =3D (env->vxrm << VCSR_VXRM_SHIFT) | + (env->vxsat << VCSR_VXSAT_SHIFT); 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Thu, 15 Oct 2026 18:03:14 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Kuan-Wei Chiu , Chao Liu , Alistair Francis , Portia Stephens Subject: [PULL v2 09/50] hw/char: Add dw8250 UART Date: Fri, 16 Oct 2026 11:01:56 +1000 Message-ID: <20261016010237.1102834-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112660180158501 Content-Type: text/plain; charset="utf-8" From: Kuan-Wei Chiu Add the dw8250 uart support. This hardware is a widely used 16550A derivative that includes additional registers. Without this specific device support, the Linux 8250_dw driver fails to probe the extended registers (UCV, CPR, etc.), which are essential for correct feature detection. Signed-off-by: Kuan-Wei Chiu Reviewed-by: Chao Liu Reviewed-by: Alistair Francis Message-ID: <20260927201326.650943-2-visitorckw@gmail.com> [ Changes by Portia Stephens : - hw/char/dw8250: Fix leak when creating child device ] Signed-off-by: Portia Stephens Signed-off-by: Alistair Francis --- MAINTAINERS | 6 ++ include/hw/char/dw8250.h | 28 +++++++++ hw/char/dw8250.c | 130 +++++++++++++++++++++++++++++++++++++++ hw/char/Kconfig | 4 ++ hw/char/meson.build | 1 + 5 files changed, 169 insertions(+) create mode 100644 include/hw/char/dw8250.h create mode 100644 hw/char/dw8250.c diff --git a/MAINTAINERS b/MAINTAINERS index 1ee661cc23..3a3c3701a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2848,6 +2848,12 @@ S: Maintained F: hw/i2c/designware_i2c.c F: include/hw/i2c/designware_i2c.h =20 +DesignWare 8250 UART +M: Kuan-Wei Chiu +S: Maintained +F: hw/char/dw8250.c +F: include/hw/char/dw8250.h + Generic Loader M: Alistair Francis S: Maintained diff --git a/include/hw/char/dw8250.h b/include/hw/char/dw8250.h new file mode 100644 index 0000000000..ce0b97715b --- /dev/null +++ b/include/hw/char/dw8250.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Synopsys DesignWare APB UART (DW 8250) + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#ifndef HW_CHAR_DW8250_H +#define HW_CHAR_DW8250_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "hw/char/serial-mm.h" + +#define TYPE_DW8250 "dw8250" +OBJECT_DECLARE_SIMPLE_TYPE(DW8250State, DW8250) + +struct DW8250State { + SysBusDevice parent_obj; + + MemoryRegion container; + MemoryRegion ext_iomem; + SerialMM serial_mm; + + uint8_t regshift; +}; + +#endif diff --git a/hw/char/dw8250.c b/hw/char/dw8250.c new file mode 100644 index 0000000000..50baeae62c --- /dev/null +++ b/hw/char/dw8250.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Synopsys DesignWare APB UART (DW 8250) + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/char/dw8250.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/qdev-properties-system.h" + +#define DW_UART_REGION_SIZE 0x100 + +#define DW_UART_RE_EN (0xB4 >> 2) /* Receiver Output Enable Register */ +#define DW_UART_DLF (0xC0 >> 2) /* Divisor Latch Fraction Register */ +#define DW_UART_CPR (0xF4 >> 2) /* Component Parameter Register */ +#define DW_UART_UCV (0xF8 >> 2) /* UART Component Version */ +#define DW_UART_CTR (0xFC >> 2) /* Component Type Register */ + +#define DW_UART_UCV_VALUE 0x3332332A /* "323*" -> v3.23a */ +#define DW_UART_CTR_VALUE 0x44570110 /* "DW" */ + +static uint64_t dw8250_ext_read(void *opaque, hwaddr addr, unsigned int si= ze) +{ + DW8250State *s =3D opaque; + + switch (addr >> s->regshift) { + case DW_UART_UCV: + return DW_UART_UCV_VALUE; + case DW_UART_CPR: + return 0x00000000; /* No advanced features (DMA, extra FIFOs) */ + case DW_UART_CTR: + return DW_UART_CTR_VALUE; + + case DW_UART_RE_EN: + case DW_UART_DLF: + /* + * Return 0 to indicate these optional features + * (RS485 and Fractional Divisor) are not implemented. + */ + return 0x00000000; + + default: + return 0; + } +} + +static void dw8250_ext_write(void *opaque, hwaddr addr, uint64_t val, unsi= gned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented write to address 0x%" HWAD= DR_PRIx "\n", + __func__, addr); +} + +static const MemoryRegionOps dw8250_ext_ops =3D { + .read =3D dw8250_ext_read, + .write =3D dw8250_ext_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void dw8250_instance_init(Object *obj) +{ + DW8250State *s =3D DW8250(obj); + + object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_M= M); + object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "char= dev"); +} + +static void dw8250_realize(DeviceState *dev, Error **errp) +{ + DW8250State *s =3D DW8250(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + SysBusDevice *serial_sbd =3D SYS_BUS_DEVICE(&s->serial_mm); + + memory_region_init(&s->container, OBJECT(dev), "dw8250-container", + DW_UART_REGION_SIZE); + sysbus_init_mmio(sbd, &s->container); + + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", s->regshift); + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness", DEVICE_LITTLE= _ENDIAN); + if (!sysbus_realize(serial_sbd, errp)) { + return; + } + + memory_region_init_io(&s->ext_iomem, OBJECT(dev), &dw8250_ext_ops, s, + "dw8250-ext", DW_UART_REGION_SIZE); + memory_region_add_subregion(&s->container, 0, &s->ext_iomem); + + memory_region_add_subregion_overlap(&s->container, 0, + sysbus_mmio_get_region(serial_sbd,= 0), 1); + + sysbus_pass_irq(sbd, serial_sbd); +} + +static const Property dw8250_properties[] =3D { + DEFINE_PROP_UINT8("regshift", DW8250State, regshift, 2), +}; + +static void dw8250_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D dw8250_realize; + device_class_set_props(dc, dw8250_properties); +} + +static const TypeInfo dw8250_info =3D { + .name =3D TYPE_DW8250, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DW8250State), + .instance_init =3D dw8250_instance_init, + .class_init =3D dw8250_class_init, +}; + +static void dw8250_register_types(void) +{ + type_register_static(&dw8250_info); +} + +type_init(dw8250_register_types) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 020c0a84bb..7040040641 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -95,3 +95,7 @@ config IP_OCTAL_232 bool default y depends on IPACK + +config DW8250 + bool + select SERIAL_MM diff --git a/hw/char/meson.build b/hw/char/meson.build index fc3d7ee506..b2250ee6ae 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -38,6 +38,7 @@ system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: fi= les('stm32l4x5_usart.c' system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc= _mmuart.c')) system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) system_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c'= )) +system_ss.add(when: 'CONFIG_DW8250', if_true: files('dw8250.c')) =20 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.= c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:16 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Kuan-Wei Chiu , Alistair Francis Subject: [PULL v2 10/50] hw/misc: Add Sophgo CV1800B clock controller Date: Fri, 16 Oct 2026 11:01:57 +1000 Message-ID: <20261016010237.1102834-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112792982158500 Content-Type: text/plain; charset="utf-8" From: Kuan-Wei Chiu Add a stub for the CV1800B clock controller. This is specifically required for the SDHCI controller to function correctly under Linux. The Linux 'sophgo,cv1800-clk' driver probes this device to determine the clock tree configuration. This implementation sets the bypass registers (CLK_BYP_0 and CLK_BYP_1) to 0xFFFFFFFF during reset, matching the POR default state. This bypasses the PLLs and allows the SDHCI and other peripherals to operate using the 25MHz reference clock. Without this device, the SD card driver fails to initialize, preventing the system from mounting the root filesystem from the SD card. Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis Message-ID: <20260927201326.650943-3-visitorckw@gmail.com> Signed-off-by: Alistair Francis --- include/hw/misc/cv1800b_clk.h | 26 ++++++++++ hw/misc/cv1800b_clk.c | 98 +++++++++++++++++++++++++++++++++++ hw/misc/Kconfig | 3 ++ hw/misc/meson.build | 1 + 4 files changed, 128 insertions(+) create mode 100644 include/hw/misc/cv1800b_clk.h create mode 100644 hw/misc/cv1800b_clk.c diff --git a/include/hw/misc/cv1800b_clk.h b/include/hw/misc/cv1800b_clk.h new file mode 100644 index 0000000000..4d03d887c6 --- /dev/null +++ b/include/hw/misc/cv1800b_clk.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B Clock Controller + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#ifndef HW_MISC_CV1800B_CLK_H +#define HW_MISC_CV1800B_CLK_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_CV1800B_CLK "cv1800b-clk" +OBJECT_DECLARE_SIMPLE_TYPE(CV1800BClkState, CV1800B_CLK) + +#define CV1800B_CLK_IOSIZE 0x1000 + +struct CV1800BClkState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t regs[CV1800B_CLK_IOSIZE / sizeof(uint32_t)]; +}; + +#endif diff --git a/hw/misc/cv1800b_clk.c b/hw/misc/cv1800b_clk.c new file mode 100644 index 0000000000..38807995ac --- /dev/null +++ b/hw/misc/cv1800b_clk.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B Clock Controller + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/cv1800b_clk.h" + +#define REG_BYTE_WIDTH (sizeof(uint32_t)) +#define REG_CLK_BYP_0 (0x030 / REG_BYTE_WIDTH) +#define REG_CLK_BYP_1 (0x034 / REG_BYTE_WIDTH) + +static uint64_t cv1800b_clk_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + CV1800BClkState *s =3D opaque; + uint32_t val =3D 0; + + if (addr < CV1800B_CLK_IOSIZE) { + val =3D s->regs[addr / REG_BYTE_WIDTH]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, addr); + } + + return val; +} + +static void cv1800b_clk_write(void *opaque, hwaddr addr, uint64_t val, uns= igned int size) +{ + CV1800BClkState *s =3D opaque; + + if (addr < CV1800B_CLK_IOSIZE) { + s->regs[addr / REG_BYTE_WIDTH] =3D val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, addr); + } +} + +static const MemoryRegionOps cv1800b_clk_ops =3D { + .read =3D cv1800b_clk_read, + .write =3D cv1800b_clk_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void cv1800b_clk_reset_hold(Object *obj, ResetType type) +{ + CV1800BClkState *s =3D CV1800B_CLK(obj); + + memset(s->regs, 0, sizeof(s->regs)); + + /* + * TODO: Implement proper PLL state machines. + * For now, use POR default to bypass PLLs and boot via 25MHz XTAL. + */ + s->regs[REG_CLK_BYP_0] =3D 0xFFFFFFFF; + s->regs[REG_CLK_BYP_1] =3D 0xFFFFFFFF; +} + +static void cv1800b_clk_init(Object *obj) +{ + CV1800BClkState *s =3D CV1800B_CLK(obj); + + memory_region_init_io(&s->iomem, obj, &cv1800b_clk_ops, s, + TYPE_CV1800B_CLK, CV1800B_CLK_IOSIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static void cv1800b_clk_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D cv1800b_clk_reset_hold; +} + +static const TypeInfo cv1800b_clk_info =3D { + .name =3D TYPE_CV1800B_CLK, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CV1800BClkState), + .instance_init =3D cv1800b_clk_init, + .class_init =3D cv1800b_clk_class_init, +}; + +static void cv1800b_clk_register_types(void) +{ + type_register_static(&cv1800b_clk_info); +} + +type_init(cv1800b_clk_register_types) diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 46e3c03cc8..7abd22869a 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -263,4 +263,7 @@ config AXIADO_CLK config K230_DECOMP_GZIP bool =20 +config SOPHGO_CV1800B_CLK + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 9790afa104..244bf278a9 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -39,6 +39,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files= ('sifive_e_aon.c')) system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.= c')) system_ss.add(when: 'CONFIG_K230_DECOMP_GZIP', if_true: files('k230_decomp= _gzip.c')) +system_ss.add(when: 'CONFIG_SOPHGO_CV1800B_CLK', if_true: files('cv1800b_c= lk.c')) =20 subdir('macio') =20 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:19 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Kuan-Wei Chiu , Alistair Francis Subject: [PULL v2 11/50] hw/riscv: Add Sophgo CV1800B SoC support Date: Fri, 16 Oct 2026 11:01:58 +1000 Message-ID: <20261016010237.1102834-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112895011158500 Content-Type: text/plain; charset="utf-8" From: Kuan-Wei Chiu Add the Sophgo CV1800B SoC, which is the heart of the Milk-V Duo board. The SoC features a T-Head C906 CPU along with integrated PLIC, CLINT, and dw8250 UART. The memory map and interrupts are configured according to the CV1800B datasheet. [1] Several peripheral blocks are included as unimplemented devices to ensure that drivers can probe successfully without causing errors during boot. Link: https://github.com/milkv-duo/duo-files/tree/main/duo/datasheet [1] Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis Message-ID: <20260927201326.650943-4-visitorckw@gmail.com> Signed-off-by: Alistair Francis --- include/hw/riscv/cv1800b.h | 56 ++++++++++++ hw/riscv/cv1800b.c | 177 +++++++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 8 ++ hw/riscv/meson.build | 2 + 4 files changed, 243 insertions(+) create mode 100644 include/hw/riscv/cv1800b.h create mode 100644 hw/riscv/cv1800b.c diff --git a/include/hw/riscv/cv1800b.h b/include/hw/riscv/cv1800b.h new file mode 100644 index 0000000000..bde5eff96b --- /dev/null +++ b/include/hw/riscv/cv1800b.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B SoC + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#ifndef HW_RISCV_CV1800B_H +#define HW_RISCV_CV1800B_H + +#include "hw/core/boards.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/misc/cv1800b_clk.h" +#include "hw/char/dw8250.h" +#include "hw/sd/sdhci.h" + +#define TYPE_CV1800B_SOC "cv1800b-soc" +OBJECT_DECLARE_SIMPLE_TYPE(CV1800BSoCState, CV1800B_SOC) + +struct CV1800BSoCState { + DeviceState parent_obj; + + RISCVHartArrayState cpus; + MemoryRegion rom; + DeviceState *plic; + CV1800BClkState clk; + DW8250State uart; + SDHCIState sdhci; +}; + +#define CV1800B_PLIC_NUM_SOURCES 136 +#define CV1800B_PLIC_NUM_PRIORITIES 31 + +#define CV1800B_UART0_IRQ 44 +#define CV1800B_SD0_IRQ 36 + +enum { + CV1800B_DEV_TOP_MISC, + CV1800B_DEV_PINMUX, + CV1800B_DEV_CLK, + CV1800B_DEV_RST, + CV1800B_DEV_WDT, + CV1800B_DEV_GPIO, + CV1800B_DEV_UART0, + CV1800B_DEV_SD0, + CV1800B_DEV_ROM, + CV1800B_DEV_RTC_GPIO, + CV1800B_DEV_RTC_IO, + CV1800B_DEV_PLIC, + CV1800B_DEV_CLINT, + CV1800B_DEV_DRAM, +}; + +extern const MemMapEntry cv1800b_memmap[]; + +#endif diff --git a/hw/riscv/cv1800b.c b/hw/riscv/cv1800b.c new file mode 100644 index 0000000000..9386c40de8 --- /dev/null +++ b/hw/riscv/cv1800b.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Sophgo CV1800B SoC + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/riscv/cv1800b.h" +#include "hw/core/qdev-properties.h" +#include "target/riscv/cpu-qom.h" +#include "system/system.h" +#include "hw/intc/riscv_aclint.h" +#include "system/address-spaces.h" +#include "hw/intc/sifive_plic.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/boot.h" +#include "hw/sd/sdhci.h" +#include "hw/misc/unimp.h" + +const MemMapEntry cv1800b_memmap[] =3D { + [CV1800B_DEV_TOP_MISC] =3D { 0x03000000, 0x1000 }, + [CV1800B_DEV_PINMUX] =3D { 0x03001000, 0x1000 }, + [CV1800B_DEV_CLK] =3D { 0x03002000, 0x1000 }, + [CV1800B_DEV_RST] =3D { 0x03003000, 0x1000 }, + [CV1800B_DEV_WDT] =3D { 0x03010000, 0x1000 }, + [CV1800B_DEV_GPIO] =3D { 0x03020000, 0x4000 }, + [CV1800B_DEV_UART0] =3D { 0x04140000, 0x10000 }, + [CV1800B_DEV_SD0] =3D { 0x04310000, 0x10000 }, + [CV1800B_DEV_ROM] =3D { 0x04400000, 0x10000 }, + [CV1800B_DEV_RTC_GPIO] =3D { 0x05021000, 0x1000 }, + [CV1800B_DEV_RTC_IO] =3D { 0x05027000, 0x1000 }, + [CV1800B_DEV_PLIC] =3D { 0x70000000, 0x4000000 }, + [CV1800B_DEV_CLINT] =3D { 0x74000000, 0x10000 }, + [CV1800B_DEV_DRAM] =3D { 0x80000000, 0x0 }, +}; + +static void cv1800b_soc_instance_init(Object *obj) +{ + CV1800BSoCState *s =3D CV1800B_SOC(obj); + + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); + qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0); + qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type", TYPE_RISCV_CPU_THEA= D_C906); + qdev_prop_set_uint64(DEVICE(&s->cpus), "resetvec", + cv1800b_memmap[CV1800B_DEV_ROM].base); + + object_initialize_child(obj, "clk", &s->clk, TYPE_CV1800B_CLK); + object_initialize_child(obj, "uart", &s->uart, TYPE_DW8250); + object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI); +} + +static void cv1800b_soc_realize(DeviceState *dev, Error **errp) +{ + CV1800BSoCState *s =3D CV1800B_SOC(dev); + MachineState *ms =3D MACHINE(qdev_get_machine()); + uint32_t num_harts =3D ms->smp.cpus; + MemoryRegion *system_memory =3D get_system_memory(); + char *plic_hart_config; + + qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { + return; + } + + memory_region_init_rom(&s->rom, OBJECT(dev), "cv1800b.rom", + cv1800b_memmap[CV1800B_DEV_ROM].size, &error_fa= tal); + memory_region_add_subregion(system_memory, + cv1800b_memmap[CV1800B_DEV_ROM].base, &s->= rom); + + riscv_aclint_swi_create(system_memory, + cv1800b_memmap[CV1800B_DEV_CLINT].base, + 0, num_harts, false); + riscv_aclint_mtimer_create(system_memory, + cv1800b_memmap[CV1800B_DEV_CLINT].base + + RISCV_ACLINT_SWI_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + + plic_hart_config =3D riscv_plic_hart_config_string(num_harts); + s->plic =3D sifive_plic_create( + system_memory, + cv1800b_memmap[CV1800B_DEV_PLIC].base, + plic_hart_config, + num_harts, + 0, + CV1800B_PLIC_NUM_SOURCES, + CV1800B_PLIC_NUM_PRIORITIES, + 0x0, + 0x1000, + 0x2000, + 0x80, + 0x200000, + 0x1000, + cv1800b_memmap[CV1800B_DEV_PLIC].size); + + g_free(plic_hart_config); + + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); + qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, cv1800b_memmap[CV1800B_DE= V_UART0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, + qdev_get_gpio_in(DEVICE(s->plic), CV1800B_UART0_IRQ)); + + qdev_prop_set_uint8(DEVICE(&s->sdhci), "sd-spec-version", 3); + qdev_prop_set_uint64(DEVICE(&s->sdhci), "capareg", 0x056900b9); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, cv1800b_memmap[CV1800B_D= EV_SD0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, + qdev_get_gpio_in(DEVICE(s->plic), CV1800B_SD0_IRQ)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->clk), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, + cv1800b_memmap[CV1800B_DEV_CLK].base); + + create_unimplemented_device("cv1800b.top_misc", + cv1800b_memmap[CV1800B_DEV_TOP_MISC].base, + cv1800b_memmap[CV1800B_DEV_TOP_MISC].size); + + create_unimplemented_device("cv1800b.pinmux", + cv1800b_memmap[CV1800B_DEV_PINMUX].base, + cv1800b_memmap[CV1800B_DEV_PINMUX].size); + + create_unimplemented_device("cv1800b.rst", + cv1800b_memmap[CV1800B_DEV_RST].base, + cv1800b_memmap[CV1800B_DEV_RST].size); + + create_unimplemented_device("cv1800b.wdt", + cv1800b_memmap[CV1800B_DEV_WDT].base, + cv1800b_memmap[CV1800B_DEV_WDT].size); + + create_unimplemented_device("cv1800b.gpio0_3", + cv1800b_memmap[CV1800B_DEV_GPIO].base, + cv1800b_memmap[CV1800B_DEV_GPIO].size); + + create_unimplemented_device("cv1800b.rtc_gpio", + cv1800b_memmap[CV1800B_DEV_RTC_GPIO].base, + cv1800b_memmap[CV1800B_DEV_RTC_GPIO].size); + + create_unimplemented_device("cv1800b.rtc_io", + cv1800b_memmap[CV1800B_DEV_RTC_IO].base, + cv1800b_memmap[CV1800B_DEV_RTC_IO].size); +} + +static void cv1800b_soc_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D cv1800b_soc_realize; + dc->user_creatable =3D false; +} + +static const TypeInfo cv1800b_soc_type_info =3D { + .name =3D TYPE_CV1800B_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CV1800BSoCState), + .instance_init =3D cv1800b_soc_instance_init, + .class_init =3D cv1800b_soc_class_init, +}; + +static void cv1800b_soc_register_types(void) +{ + type_register_static(&cv1800b_soc_type_info); +} + +type_init(cv1800b_soc_register_types) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d06ac26648..b7c0871c67 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -164,3 +164,11 @@ config K230 select K230_WDT select K230_GSDMA select K230_DECOMP_GZIP + +config SOPHGO_CV1800B + bool + depends on RISCV64 + select RISCV_ACLINT + select SIFIVE_PLIC + select SOPHGO_CV1800B_CLK + select DW8250 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 7aa3c1578d..45895486d4 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -22,4 +22,6 @@ riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: file= s('cps.c')) riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) =20 +riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) + hw_arch +=3D {'riscv': riscv_ss} --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:21 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Kuan-Wei Chiu , Alistair Francis , Chao Liu Subject: [PULL v2 12/50] hw/riscv: Add Milk-V Duo board support Date: Fri, 16 Oct 2026 11:01:59 +1000 Message-ID: <20261016010237.1102834-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113050138158500 Content-Type: text/plain; charset="utf-8" From: Kuan-Wei Chiu Add support for the Milk-V Duo development board, which is powered by the Sophgo CV1800B SoC. The implementation includes: - Board-level machine initialization with 64mb of default ram. - Integration of the CV1800B SoC. - Support for loading external FDT, kernel, and initrd images. - Proper setup of the reset vector to match the CV1800B's boot flow. Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260927201326.650943-5-visitorckw@gmail.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 9 ++ configs/devices/riscv64-softmmu/default.mak | 1 + hw/riscv/milkv_duo.c | 118 ++++++++++++++++++++ hw/riscv/Kconfig | 6 + hw/riscv/meson.build | 1 + 5 files changed, 135 insertions(+) create mode 100644 hw/riscv/milkv_duo.c diff --git a/MAINTAINERS b/MAINTAINERS index 3a3c3701a5..5a615ecf95 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1871,6 +1871,15 @@ F: tests/qtest/k230-wdt-test.c F: tests/qtest/k230-gsdma-test.c F: tests/qtest/k230-decomp-gzip-test.c =20 +Milk-V Duo +M: Kuan-Wei Chiu +S: Maintained +F: hw/misc/cv1800b_clk.c +F: hw/riscv/cv1800b.c +F: hw/riscv/milkv_duo.c +F: include/hw/misc/cv1800b_clk.h +F: include/hw/riscv/cv1800b.h + RX Machines ----------- rx-gdbsim diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/= riscv64-softmmu/default.mak index a8e4d0ab33..2ba91b14d4 100644 --- a/configs/devices/riscv64-softmmu/default.mak +++ b/configs/devices/riscv64-softmmu/default.mak @@ -13,3 +13,4 @@ # CONFIG_SHAKTI_C=3Dn # CONFIG_XIANGSHAN_KUNMINGHU=3Dn # CONFIG_MIPS_BOSTON_AIA=3Dn +# CONFIG_MILKV_DUO=3Dn diff --git a/hw/riscv/milkv_duo.c b/hw/riscv/milkv_duo.c new file mode 100644 index 0000000000..1285c8d34f --- /dev/null +++ b/hw/riscv/milkv_duo.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Milk-V Duo board + * + * Copyright (c) 2026 Kuan-Wei Chiu + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/core/boards.h" +#include "hw/riscv/cv1800b.h" +#include "hw/riscv/boot.h" +#include "target/riscv/cpu-qom.h" +#include "system/system.h" +#include "system/device_tree.h" +#include "qemu/error-report.h" +#include "hw/core/loader.h" +#include + +struct MilkVDuoState { + MachineState parent_obj; + CV1800BSoCState soc; +}; + +#define TYPE_MILK_V_DUO MACHINE_TYPE_NAME("milkv-duo") +OBJECT_DECLARE_SIMPLE_TYPE(MilkVDuoState, MILK_V_DUO) + +static void milkv_duo_init(MachineState *machine) +{ + MilkVDuoState *s =3D MILK_V_DUO(machine); + MemoryRegion *system_memory =3D get_system_memory(); + RISCVBootInfo boot_info; + const char *firmware_name; + hwaddr firmware_load_addr, firmware_end_addr; + hwaddr fdt_load_addr =3D 0; + int fdt_size =3D 0; + uint64_t kernel_entry =3D 0; + + object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_CV1800B_= SOC); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); + + memory_region_add_subregion(system_memory, + cv1800b_memmap[CV1800B_DEV_DRAM].base, + machine->ram); + + riscv_boot_info_init(&boot_info, &s->soc.cpus); + + firmware_name =3D riscv_default_firmware_name(&s->soc.cpus); + firmware_load_addr =3D cv1800b_memmap[CV1800B_DEV_DRAM].base; + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, + &firmware_load_addr, = NULL); + + if (machine->dtb) { + machine->fdt =3D load_device_tree(machine->dtb, &fdt_size); + if (!machine->fdt) { + error_report("Failed to load device tree"); + exit(1); + } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + if (fdt_path_offset(machine->fdt, "/chosen") < 0) { + qemu_fdt_add_subnode(machine->fdt, "/chosen"); + } + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + } + + if (machine->kernel_filename) { + hwaddr kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_in= fo, + firmware_e= nd_addr); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NU= LL); + kernel_entry =3D boot_info.image_low_addr; + } + + if (machine->dtb) { + fdt_load_addr =3D riscv_compute_fdt_addr(cv1800b_memmap[CV1800B_DE= V_DRAM].base, + machine->ram_size, machine,= &boot_info); + riscv_load_fdt(fdt_load_addr, machine->fdt); + } + + riscv_setup_rom_reset_vec(machine, &s->soc.cpus, + firmware_load_addr, + cv1800b_memmap[CV1800B_DEV_ROM].base, + cv1800b_memmap[CV1800B_DEV_ROM].size, + kernel_entry, + fdt_load_addr); +} + +static void milkv_duo_machine_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + static const char *const valid_cpu_types[] =3D { + TYPE_RISCV_CPU_THEAD_C906, + NULL + }; + + mc->desc =3D "Milk-V Duo Board (CV1800B)"; + mc->init =3D milkv_duo_init; + mc->max_cpus =3D 2; + mc->default_cpu_type =3D TYPE_RISCV_CPU_THEAD_C906; + mc->valid_cpu_types =3D valid_cpu_types; + mc->default_ram_size =3D 64 * MiB; + mc->default_ram_id =3D "riscv.milkv_duo.ram"; +} + +static const TypeInfo milkv_duo_machine_type_infos[] =3D { + { + .name =3D TYPE_MILK_V_DUO, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(MilkVDuoState), + .class_init =3D milkv_duo_machine_class_init, + }, +}; + +DEFINE_TYPES(milkv_duo_machine_type_infos) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index b7c0871c67..70a331f7ae 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -172,3 +172,9 @@ config SOPHGO_CV1800B select SIFIVE_PLIC select SOPHGO_CV1800B_CLK select DW8250 + +config MILKV_DUO + bool + depends on RISCV64 + default y + select SOPHGO_CV1800B diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 45895486d4..a40e80645b 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -23,5 +23,6 @@ riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: fil= es('boston-aia.c')) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) =20 riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) +riscv_ss.add(when: 'CONFIG_MILKV_DUO', if_true: files('milkv_duo.c')) =20 hw_arch +=3D {'riscv': riscv_ss} --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:24 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Kuan-Wei Chiu , Alistair Francis Subject: [PULL v2 13/50] tests/qtest: Add qtest for Milk-V Duo board Date: Fri, 16 Oct 2026 11:02:00 +1000 Message-ID: <20261016010237.1102834-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113050132158500 Content-Type: text/plain; charset="utf-8" From: Kuan-Wei Chiu Add minimal qtest coverage for the Milk-V Duo machine to validate basic MMIO mapping and register access. Currently tested: - Verify DW8250 UART component version and type signatures. - Test read/write access to CV1800B clock bypass register. Tested with: $ meson test -C build -v qemu:qtest-riscv64/milkv-duo-test [...] Ok: 1 Fail: 0 Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis Message-ID: <20260927201326.650943-6-visitorckw@gmail.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + tests/qtest/milkv-duo-test.c | 70 ++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 3 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/milkv-duo-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 5a615ecf95..8de16c1959 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1879,6 +1879,7 @@ F: hw/riscv/cv1800b.c F: hw/riscv/milkv_duo.c F: include/hw/misc/cv1800b_clk.h F: include/hw/riscv/cv1800b.h +F: tests/qtest/milkv-duo-test.c =20 RX Machines ----------- diff --git a/tests/qtest/milkv-duo-test.c b/tests/qtest/milkv-duo-test.c new file mode 100644 index 0000000000..06064b8733 --- /dev/null +++ b/tests/qtest/milkv-duo-test.c @@ -0,0 +1,70 @@ +/* + * QTest for Milk-V Duo Board + * + * Copyright (c) 2026 Kuan-Wei Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define CV1800B_CLK_BASE 0x03002000 +#define CV1800B_CLK_BYPASS 0x030 +#define CV1800B_CLK_BYPASS_RESET 0xFFFFFFFF +#define TEST_PATTERN_5A 0x5A5A5A5A +#define TEST_PATTERN_A5 0xA5A5A5A5 + +#define CV1800B_UART0_BASE 0x04140000 +#define DW_UART_UCV 0xF8 +#define DW_UART_CTR 0xFC +#define DW_UART_VERSION_3_23A 0x3332332A +#define DW_UART_TYPE_SIGNATURE 0x44570110 + +static void test_milkv_duo_uart(void) +{ + QTestState *qts; + uint32_t component_version; + uint32_t component_type; + + qts =3D qtest_init("-M milkv-duo"); + + component_version =3D qtest_readl(qts, CV1800B_UART0_BASE + DW_UART_UC= V); + g_assert_cmphex(component_version, =3D=3D, DW_UART_VERSION_3_23A); + + component_type =3D qtest_readl(qts, CV1800B_UART0_BASE + DW_UART_CTR); + g_assert_cmphex(component_type, =3D=3D, DW_UART_TYPE_SIGNATURE); + + qtest_quit(qts); +} + +static void test_milkv_duo_clk(void) +{ + QTestState *qts; + uint32_t clk_bypass_val; + + qts =3D qtest_init("-M milkv-duo"); + + clk_bypass_val =3D qtest_readl(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYP= ASS); + g_assert_cmphex(clk_bypass_val, =3D=3D, CV1800B_CLK_BYPASS_RESET); + + qtest_writel(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYPASS, TEST_PATTERN_= 5A); + clk_bypass_val =3D qtest_readl(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYP= ASS); + g_assert_cmphex(clk_bypass_val, =3D=3D, TEST_PATTERN_5A); + + qtest_writel(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYPASS, TEST_PATTERN_= A5); + clk_bypass_val =3D qtest_readl(qts, CV1800B_CLK_BASE + CV1800B_CLK_BYP= ASS); + g_assert_cmphex(clk_bypass_val, =3D=3D, TEST_PATTERN_A5); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/riscv/milkv-duo/uart", test_milkv_duo_uart); + qtest_add_func("/riscv/milkv-duo/clk", test_milkv_duo_clk); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 200abf6f36..18fceca421 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -315,7 +315,8 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? ['iommu-riscv-test'] : []) + \ (config_all_devices.has_key('CONFIG_K230') ? - ['k230-ddr-test', 'k230-wdt-test', 'k230-gsdma-test', 'k230-decomp-gzip= -test'] : []) + ['k230-ddr-test', 'k230-wdt-test', 'k230-gsdma-test', 'k230-decomp-gzip= -test'] : []) + \ + ['milkv-duo-test'] =20 qtests_hexagon =3D ['boot-serial-test', 'l2vic-test', 'qct-qtimer-test'] =20 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1792112688; cv=none; d=zohomail.com; s=zohoarc; b=br/MXV/P7gzfd6ynrhdX4BLXfStL19ZSsilrFRuOjKcQUmv3uMKIQ8H0DBmcCfmzlrTcYuT7EtWGZqGsYoYXNX1ng1kmmoAsPkRZMJ9kMsljZnav4TuL4Bh1792pHMQfoGGubQWYtolov1EN5wR+PCk1DYSIgNtSOyjpehqk/kM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 15 Oct 2026 18:03:26 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Kuan-Wei Chiu , Alistair Francis Subject: [PULL v2 14/50] tests/functional/riscv64: Add boot test for Milk-V Duo board Date: Fri, 16 Oct 2026 11:02:01 +1000 Message-ID: <20261016010237.1102834-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112690631158500 Content-Type: text/plain; charset="utf-8" From: Kuan-Wei Chiu Add a functional boot test for the Milk-V Duo board to validate the end-to-end boot flow. $ ./build/run ./tests/functional/riscv64/test_milkv_duo.py TAP version 13 ok 1 test_milkv_duo.MilkvDuoMachine.test_riscv64_milkv_duo 1..1 Signed-off-by: Kuan-Wei Chiu Message-ID: <20260927201326.650943-7-visitorckw@gmail.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_milkv_duo.py | 53 ++++++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100755 tests/functional/riscv64/test_milkv_duo.py diff --git a/MAINTAINERS b/MAINTAINERS index 8de16c1959..a8751210ac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1879,6 +1879,7 @@ F: hw/riscv/cv1800b.c F: hw/riscv/milkv_duo.c F: include/hw/misc/cv1800b_clk.h F: include/hw/riscv/cv1800b.h +F: tests/functional/riscv64/test_milkv_duo.py F: tests/qtest/milkv-duo-test.c =20 RX Machines diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index d1a3e6c2bf..8a4f1d00f9 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -18,4 +18,5 @@ tests_riscv64_system_thorough =3D [ 'sifive_u', 'tt_atlantis', 'tuxrun', + 'milkv_duo', ] diff --git a/tests/functional/riscv64/test_milkv_duo.py b/tests/functional/= riscv64/test_milkv_duo.py new file mode 100755 index 0000000000..6a7e2a5d19 --- /dev/null +++ b/tests/functional/riscv64/test_milkv_duo.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a Linux kernel on a Milk-V Duo machine +# +# Copyright (c) 2026 Kuan-Wei Chiu +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset +from qemu_test import skipIfMissingCommands, wait_for_console_pattern + +class MilkvDuoMachine(LinuxKernelTest): + + timeout =3D 120 + + ASSET_KERNEL =3D Asset( + 'https://storage.tuxboot.com/kernels/6.11.9/riscv64/Image', + '174f8bb87f08961e54fa3fcd954a8e31f4645f6d6af4dd43983d5e9841490fb0' + ) + ASSET_DTBS =3D Asset( + 'https://storage.tuxboot.com/kernels/6.11.9/riscv64/dtbs.tar.xz', + '97e5e65a7e6c68303e53486af120c0846ee8df572e9c15f0c4dccb831d0cef4b' + ) + ASSET_ROOTFS =3D Asset( + 'https://storage.tuxboot.com/buildroot/20241119/riscv64/rootfs.ext= 4.zst', + 'aa4736a9872651dfc0d95e709465eedf1134fd19d42b8cb305bfd776f9801004' + ) + + @skipIfMissingCommands('zstd') + def test_riscv64_milkv_duo(self): + self.set_machine('milkv-duo') + + kernel_path =3D self.ASSET_KERNEL.fetch() + dtb_path =3D self.archive_extract( + self.ASSET_DTBS, member=3D'dtbs/sophgo/cv1800b-milkv-duo.dtb') + rootfs_path =3D self.uncompress(self.ASSET_ROOTFS) + + self.vm.set_console() + self.vm.add_args('-bios', 'default', + '-kernel', kernel_path, + '-dtb', dtb_path, + '-drive', f'file=3D{rootfs_path},format=3Draw,id= =3Dsd-card,snapshot=3Don', + '-device', 'sd-card,drive=3Dsd-card', + '-append', 'console=3DttyS0,115200 root=3D/dev/mm= cblk0 rootwait earlycon') + + self.vm.launch() + + wait_for_console_pattern(self, 'Machine model: Milk-V Duo') + wait_for_console_pattern(self, 'Welcome to TuxTest') + wait_for_console_pattern(self, 'tuxtest login:') + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Kuan-Wei Chiu Add documentation for the Milk-V Duo board. This includes a brief overview of the hardware, a list of supported devices, and practical instructions on how to boot the machine using OpenSBI and a Linux kernel with an emulated SD card. Signed-off-by: Kuan-Wei Chiu Acked-by: Alistair Francis Message-ID: <20260927201326.650943-8-visitorckw@gmail.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + docs/system/riscv/milkv-duo.rst | 49 +++++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 3 files changed, 51 insertions(+) create mode 100644 docs/system/riscv/milkv-duo.rst diff --git a/MAINTAINERS b/MAINTAINERS index a8751210ac..b912e4b8d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1874,6 +1874,7 @@ F: tests/qtest/k230-decomp-gzip-test.c Milk-V Duo M: Kuan-Wei Chiu S: Maintained +F: docs/system/riscv/milkv-duo.rst F: hw/misc/cv1800b_clk.c F: hw/riscv/cv1800b.c F: hw/riscv/milkv_duo.c diff --git a/docs/system/riscv/milkv-duo.rst b/docs/system/riscv/milkv-duo.= rst new file mode 100644 index 0000000000..1758db2c1e --- /dev/null +++ b/docs/system/riscv/milkv-duo.rst @@ -0,0 +1,49 @@ +Milk-V Duo board (``milkv-duo``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +The ``milkv-duo`` machine is compatible with the Milk-V Duo development bo= ard. + +The Milk-V Duo is an ultra-compact embedded development platform based on = the +Sophgo CV1800B SoC. The CV1800B features T-Head C906 RISC-V processing cor= es +along with integrated peripherals. + +For more information, see + +Supported devices +----------------- +The ``milkv-duo`` machine supports the following devices: + +* T-Head C906 cores +* Core Local Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* DesignWare APB UART (dw8250) +* SDHCI controller +* CV1800B clock controller + +Boot options +------------ +The ``milkv-duo`` machine supports direct boot using a generic RISC-V Open= SBI +firmware and a Linux kernel. The root filesystem can be provided via the +emulated SD card. + +Running +------- +To boot the machine, you need a Linux kernel (built with CV1800B support),= a +device tree blob (DTB), and a root filesystem image (e.g., built via BusyB= ox +or Buildroot). + +Use the following command to boot the system directly to the Linux shell: + +.. code-block:: bash + + $ qemu-system-riscv64 -M milkv-duo -nographic \ + -bios pc-bios/opensbi-riscv64-generic-fw_dynamic.bin \ + -dtb /path/to/linux/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtb= \ + -kernel /path/to/linux/arch/riscv/boot/Image \ + -drive file=3D/path/to/rootfs.ext4,format=3Draw,id=3Dsd-card \ + -device sd-card,drive=3Dsd-card \ + -append "console=3DttyS0,115200 root=3D/dev/mmcblk0 rootwait earlyco= n" + +This command boots the generic OpenSBI firmware, loads the Linux Image and= the +specified DTB, and mounts the ext4 root filesystem from the emulated SD ca= rd. +The console output is routed to the ``ttyS0`` serial port. diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 2639866a3e..1e49055e29 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -69,6 +69,7 @@ undocumented; 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Thu, 15 Oct 2026 18:03:31 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 16/50] target/riscv: Document riscv_cpu_update_mip() Date: Fri, 16 Oct 2026 11:02:03 +1000 Message-ID: <20261016010237.1102834-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113098979158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260930174508.81497-2-philmd@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5489c564ae..24b22032e1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -688,6 +688,20 @@ bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr= addr, bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); +/** + * riscv_cpu_update_mip: + * @env: CPURISCVState + * @mask: Mask of the MIP bits to update + * @value: New values for the bits set in @mask. + * Use BOOL_TO_MASK() for boolean values. + * + * Set or clear the Machine Interrupt Pending register (MIP) + * bits selected by @mask. + * + * Note: VSTIP is not maintained in MIP, so it is ignored here. + * + * Returns: the value of mip before the update. + */ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Thu, 15 Oct 2026 18:03:35 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 17/50] target/riscv: Document kvm_riscv_set_irq() Date: Fri, 16 Oct 2026 11:02:04 +1000 Message-ID: <20261016010237.1102834-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112876574158500 From: Philippe Mathieu-Daud=C3=A9 Describe the supported interrupt and the effect of @level. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260930174508.81497-3-philmd@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm_riscv.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 0e27ce8bf3..aef681f0a2 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -22,6 +22,12 @@ #include "target/riscv/cpu-qom.h" =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu); +/** + * kvm_riscv_set_irq: + * @cpu: RISC-V CPU + * @irq: Interrupt to set or clear (only %IRQ_S_EXT is supported). + * @level: %0 to clear the interrupt, non-zero to set it. + */ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, uint64_t aia_irq_num, uint64_t aia_msi_num, --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:38 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 18/50] target/riscv: Clarify riscv_accel_set_irq() arguments Date: Fri, 16 Oct 2026 11:02:05 +1000 Message-ID: <20261016010237.1102834-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113103064158500 From: Philippe Mathieu-Daud=C3=A9 Use per-accelerator locals to make the differing conventions explicit: TCG takes a MIP bitmask and value, KVM takes an IRQ number and a level. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260930174508.81497-4-philmd@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/time_helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index ede1a4c2a3..29bbebb96f 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -25,18 +25,24 @@ #include "system/kvm.h" #include "system/tcg.h" =20 -static void riscv_accel_set_irq(RISCVCPU *cpu, int irq, int level) +static void riscv_accel_set_irq(RISCVCPU *cpu, + int irq_or_mask, int level_or_value) { if (kvm_enabled()) { + int irq =3D irq_or_mask; + int level =3D level_or_value; + kvm_riscv_set_irq(cpu, irq, level); } =20 if (tcg_enabled()) { - riscv_cpu_update_mip(&cpu->env, irq, level); + uint64_t mask =3D irq_or_mask; + uint64_t value =3D level_or_value; + + riscv_cpu_update_mip(&cpu->env, mask, value); } } =20 - static void riscv_vstimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; 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Thu, 15 Oct 2026 18:03:41 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis Subject: [PULL v2 19/50] target/riscv: Have riscv_cpu_set_mode() call riscv_cpu_interrupt() Date: Fri, 16 Oct 2026 11:02:06 +1000 Message-ID: <20261016010237.1102834-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113013279158500 From: Philippe Mathieu-Daud=C3=A9 riscv_cpu_set_mode() only want the interrupt re-poll: the mip update with a zero mask is a no-op. Call riscv_cpu_interrupt() directly. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260930174508.81497-5-philmd@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 6115f65adb..6a8533ee31 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -886,7 +886,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, privilege_m= ode_t newpriv, * * To solve this, we check and inject interrupt after setting = V=3D1. */ - riscv_cpu_update_mip(env, 0, 0); + riscv_cpu_interrupt(env); } } } --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Thu, 15 Oct 2026 18:03:43 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 20/50] target/riscv: Add riscv_cpu_get_mip() Date: Fri, 16 Oct 2026 11:02:07 +1000 Message-ID: <20261016010237.1102834-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112835805158500 From: Philippe Mathieu-Daud=C3=A9 Route MIP reads in the interrupt, CSR, ACLINT and pending-IRQ code through a single riscv_cpu_get_mip() accessor, so the implementation can change in one place. riscv_cpu_update_mip() now reads the old value under the BQL, so the returned value matches the one written. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260930174508.81497-6-philmd@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 +++++++ hw/intc/riscv_aclint.c | 2 +- target/riscv/cpu.c | 8 +++++++- target/riscv/tcg/cpu_helper.c | 12 +++++++----- target/riscv/tcg/csr.c | 6 ++++-- 5 files changed, 26 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 24b22032e1..f9f0146f56 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -688,6 +688,13 @@ bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr= addr, bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); +/** + * riscv_cpu_get_mip: + * @env: CPURISCVState + * + * Returns: the current value of the Machine Interrupt Pending (MIP) regis= ter. + */ +uint64_t riscv_cpu_get_mip(const CPURISCVState *env); /** * riscv_cpu_update_mip: * @env: CPURISCVState diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 2d133d0dcf..4bd359c338 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -438,7 +438,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwa= ddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-swi: invalid hartid: %zu", hartid); } else if ((addr & 0x3) =3D=3D 0) { - return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); + return (swi->sswi) ? 0 : ((riscv_cpu_get_mip(env) & MIP_MSIP) = > 0); } } =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b..b8d6f992ba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -916,8 +916,9 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; + uint64_t mip =3D riscv_cpu_get_mip(env); =20 - return (env->mip | vsgein | vstip) & env->mie; + return (mip | vsgein | vstip) & env->mie; } =20 int riscv_cpu_mirq_pending(CPURISCVState *env) @@ -953,6 +954,11 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } =20 +uint64_t riscv_cpu_get_mip(const CPURISCVState *env) +{ + return env->mip; +} + bool riscv_cpu_has_work(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 6a8533ee31..f03f149a66 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -567,7 +567,7 @@ void riscv_cpu_interrupt(CPURISCVState *env) =20 vstip =3D env->vstime_irq ? MIP_VSTIP : 0; =20 - if (env->mip | vsgein | vstip | irqf) { + if (riscv_cpu_get_mip(env) | vsgein | vstip | irqf) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -576,14 +576,15 @@ void riscv_cpu_interrupt(CPURISCVState *env) =20 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t = value) { - uint64_t old =3D env->mip; + uint64_t old; =20 /* No need to update mip for VSTIP */ mask =3D ((mask =3D=3D MIP_VSTIP) && env->vstime_irq) ? 0 : mask; =20 BQL_LOCK_GUARD(); =20 - env->mip =3D (env->mip & ~mask) | (value & mask); + old =3D riscv_cpu_get_mip(env); + env->mip =3D (old & ~mask) | (value & mask); =20 riscv_cpu_interrupt(env); =20 @@ -2085,10 +2086,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; + uint64_t mip =3D riscv_cpu_get_mip(env); bool s_injected =3D env->mvip & (1ULL << cause) & env->mvien && - !(env->mip & (1ULL << cause)); + !(mip & (1ULL << cause)); bool vs_injected =3D env->hvip & (1ULL << cause) & env->hvien && - !(env->mip & (1ULL << cause)); + !(mip & (1ULL << cause)); bool smode_double_trap =3D false; uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; const bool prev_virt =3D env->virt_enabled; diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index a3351428cb..a030614434 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3861,7 +3861,7 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, if (mask) { old_mip =3D riscv_cpu_update_mip(env, mask, (new_val & mask)); } else { - old_mip =3D env->mip; + old_mip =3D riscv_cpu_get_mip(env); } =20 if (csrno !=3D CSR_HVIP) { @@ -4604,8 +4604,10 @@ static RISCVException read_vstopi(CPURISCVState *env= , int csrno, hviprio =3D get_field(env->hvictl, HVICTL_IPRIO); =20 if (gein) { + uint64_t mip =3D riscv_cpu_get_mip(env); + vsgein =3D (env->hgeip & (1ULL << gein)) ? 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Thu, 15 Oct 2026 18:03:46 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Alistair Francis Subject: [PULL v2 21/50] target/riscv: Access MIP atomically Date: Fri, 16 Oct 2026 11:02:08 +1000 Message-ID: <20261016010237.1102834-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112901234158500 From: Philippe Mathieu-Daud=C3=A9 Make riscv_cpu_get_mip() read env->mip with qatomic_read() and riscv_cpu_update_mip() store it with qatomic_set(). This makes MIP reads and writes safe for riscv_cpu_has_work(), which may run without the BQL. Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20260930174508.81497-7-philmd@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/tcg/cpu_helper.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8d6f992ba..45e82fc30c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "qemu/guest-random.h" +#include "qemu/atomic.h" #include "cpu.h" #include "cpu_vendorid.h" #include "target/riscv/tcg/csr.h" @@ -956,7 +957,7 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) =20 uint64_t riscv_cpu_get_mip(const CPURISCVState *env) { - return env->mip; + return qatomic_read(&env->mip); } =20 bool riscv_cpu_has_work(CPUState *cs) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index f03f149a66..58901bc3d8 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "qemu/atomic.h" #include "cpu.h" #include "internals.h" #include "pmu.h" @@ -584,7 +585,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, uint64_t value) BQL_LOCK_GUARD(); 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Thu, 15 Oct 2026 18:03:49 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Chao Liu , Daniel Henrique Barboza , Tao Tang , Nutty Liu , Alistair Francis Subject: [PULL v2 22/50] target/riscv: add sdext debug CSRs state Date: Fri, 16 Oct 2026 11:02:09 +1000 Message-ID: <20261016010237.1102834-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112856620158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add architectural state for Sdext Debug Mode: debug_mode, dcsr, dpc and dscratch0/1. Wire up CSR access for dcsr/dpc/dscratch and gate them to Debug Mode (or host debugger access). The Sdext is not fully implemented, so it is disabled by default. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Acked-by: Alistair Francis Message-ID: <20260928195902.2045235-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 33 ++++++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/cpu.c | 7 ++ target/riscv/machine.c | 22 ++++++ target/riscv/tcg/csr.c | 126 ++++++++++++++++++++++++++++++ 6 files changed, 193 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f9f0146f56..3b0d5e8aad 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -510,6 +510,10 @@ struct CPUArchState { =20 /* True if in debugger mode. */ bool debugger; + bool debug_mode; + uint32_t dcsr; + target_ulong dpc; + target_ulong dscratch[2]; =20 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c01050ce2b..3579789a1f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -467,6 +467,39 @@ #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 +#define CSR_DSCRATCH1 0x7b3 + +/* DCSR fields */ +#define DCSR_XDEBUGVER_SHIFT 28 +#define DCSR_XDEBUGVER_MASK (0xfu << DCSR_XDEBUGVER_SHIFT) +#define DCSR_DEBUGVER(val) ((val) << DCSR_XDEBUGVER_SHIFT) +#define DCSR_EXTCAUSE_SHIFT 24 +#define DCSR_EXTCAUSE_MASK (0x7u << DCSR_EXTCAUSE_SHIFT) +#define DCSR_CETRIG BIT(19) +#define DCSR_PELP BIT(18) +#define DCSR_EBREAKVS BIT(17) +#define DCSR_EBREAKVU BIT(16) +#define DCSR_EBREAKM BIT(15) +#define DCSR_EBREAKS BIT(13) +#define DCSR_EBREAKU BIT(12) +#define DCSR_STEPIE BIT(11) +#define DCSR_STOPCOUNT BIT(10) +#define DCSR_STOPTIME BIT(9) +#define DCSR_CAUSE_SHIFT 6 +#define DCSR_CAUSE_MASK (0x7u << DCSR_CAUSE_SHIFT) +#define DCSR_V BIT(5) +#define DCSR_MPRVEN BIT(4) +#define DCSR_NMIP BIT(3) +#define DCSR_STEP BIT(2) +#define DCSR_PRV_MASK 0x3u + +#define DCSR_CAUSE_EBREAK 1 +#define DCSR_CAUSE_TRIGGER 2 +#define DCSR_CAUSE_HALTREQ 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_RESET 5 +#define DCSR_CAUSE_GROUP 6 +#define DCSR_CAUSE_OTHER 7 =20 /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index f91c780299..24f3606f94 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -105,6 +105,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_sdext) BOOL_FIELD(ext_sdtrig) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 45e82fc30c..c0837c6c55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -249,6 +249,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext), ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_INTERNAL_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1101,6 +1102,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) =20 #ifndef CONFIG_USER_ONLY #ifdef CONFIG_TCG + env->debug_mode =3D false; + env->dcsr =3D DCSR_DEBUGVER(4); + env->dpc =3D 0; + env->dscratch[0] =3D 0; + env->dscratch[1] =3D 0; + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ed10e65259..0de06e9588 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -327,6 +327,13 @@ static bool debug_needed(void *opaque) return cpu->cfg.debug || cpu->cfg.ext_sdtrig; } =20 +static bool sdext_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_sdext; +} + static int debug_post_load(void *opaque, int version_id) { RISCVCPU *cpu =3D opaque; @@ -361,6 +368,20 @@ static const VMStateDescription vmstate_debug =3D { } }; =20 +static const VMStateDescription vmstate_sdext =3D { + .name =3D "cpu/sdext", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sdext_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_BOOL(env.debug_mode, RISCVCPU), + VMSTATE_UINT32(env.dcsr, RISCVCPU), + VMSTATE_UINTTL(env.dpc, RISCVCPU), + VMSTATE_UINTTL_ARRAY(env.dscratch, RISCVCPU, 2), + VMSTATE_END_OF_LIST() + } +}; + static int riscv_cpu_post_load(void *opaque, int version_id) { RISCVCPU *cpu =3D opaque; @@ -634,6 +655,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_ctr, &vmstate_sstc, &vmstate_mseccfg, + &vmstate_sdext, NULL } }; diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index a030614434..2ad66239ae 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3252,6 +3252,126 @@ static RISCVException write_mtval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +#if !defined(CONFIG_USER_ONLY) +static RISCVException sdext(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_sdext) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (!env->debug_mode && !env->debugger) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + +static target_ulong dcsr_visible_mask(CPURISCVState *env) +{ + target_ulong mask =3D (target_ulong)-1; + RISCVCPU *cpu =3D env_archcpu(env); + + if (!riscv_has_ext(env, RVH)) { + mask &=3D ~(DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V); + } + if (!riscv_has_ext(env, RVS)) { + mask &=3D ~DCSR_EBREAKS; + } + if (!riscv_has_ext(env, RVU)) { + mask &=3D ~DCSR_EBREAKU; + } + if (!cpu->cfg.ext_zicfilp) { + mask &=3D ~DCSR_PELP; + } + if (!cpu->cfg.ext_smdbltrp) { + mask &=3D ~DCSR_CETRIG; + } + + return mask; +} + +static RISCVException read_dcsr(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->dcsr & dcsr_visible_mask(env); + return RISCV_EXCP_NONE; +} + +static target_ulong dcsr_writable_mask(CPURISCVState *env) +{ + target_ulong mask =3D DCSR_EBREAKM | DCSR_EBREAKS | DCSR_EBREAKU | + DCSR_STEPIE | DCSR_STOPCOUNT | DCSR_STOPTIME | + DCSR_STEP | DCSR_PRV_MASK; + RISCVCPU *cpu =3D env_archcpu(env); + + mask |=3D DCSR_MPRVEN; + + if (riscv_has_ext(env, RVH)) { + mask |=3D DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V; + } + if (riscv_has_ext(env, RVS)) { + mask |=3D DCSR_EBREAKS; + } + if (riscv_has_ext(env, RVU)) { + mask |=3D DCSR_EBREAKU; + } + if (cpu->cfg.ext_zicfilp) { + mask |=3D DCSR_PELP; + } + if (cpu->cfg.ext_smdbltrp) { + mask |=3D DCSR_CETRIG; + } + + return mask; +} + +static RISCVException write_dcsr(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + target_ulong mask =3D dcsr_writable_mask(env); + target_ulong new_val =3D env->dcsr; + + new_val &=3D ~mask; + new_val |=3D val & mask; + new_val &=3D ~DCSR_XDEBUGVER_MASK; + new_val |=3D DCSR_DEBUGVER(4); + env->dcsr =3D new_val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_dpc(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->dpc & get_xepc_mask(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_dpc(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->dpc =3D val & get_xepc_mask(env); + return RISCV_EXCP_NONE; +} + +static RISCVException read_dscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D (csrno =3D=3D CSR_DSCRATCH1) ? 1 : 0; + + *val =3D env->dscratch[index]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_dscratch(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + int index =3D (csrno =3D=3D CSR_DSCRATCH1) ? 1 : 0; + + env->dscratch[index] =3D val; + return RISCV_EXCP_NONE; +} +#endif /* !CONFIG_USER_ONLY */ + /* Execution environment configuration setup */ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, target_ulong *val) @@ -6498,6 +6618,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata = }, [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore = }, [CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex= t }, +#if !defined(CONFIG_USER_ONLY) + [CSR_DCSR] =3D { "dcsr", sdext, read_dcsr, write_dcsr }, + [CSR_DPC] =3D { "dpc", sdext, read_dpc, write_dpc }, + [CSR_DSCRATCH] =3D { "dscratch0", sdext, read_dscratch, write_dscrat= ch }, + [CSR_DSCRATCH1] =3D { "dscratch1", sdext, read_dscratch, write_dscrat= ch }, +#endif =20 [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:52 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Chao Liu , Daniel Henrique Barboza , Tao Tang , Alistair Francis Subject: [PULL v2 23/50] target/riscv: add sdext Debug Mode helpers Date: Fri, 16 Oct 2026 11:02:10 +1000 Message-ID: <20261016010237.1102834-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112899020158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add helpers to enter/leave Debug Mode and to update dpc/dcsr. Model resume without a Debug Module by leaving Debug Mode at cpu_exec_enter and continuing from dpc. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260928195902.2045235-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++ target/riscv/tcg/cpu_helper.c | 85 +++++++++++++++++++++++++++++++++++ target/riscv/tcg/debug.c | 5 +++ target/riscv/tcg/tcg-cpu.c | 15 +++++++ 4 files changed, 108 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3b0d5e8aad..b0a0e5d51a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -678,6 +678,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, char *riscv_isa_string(RISCVCPU *cpu); int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, + uint32_t cause); +void riscv_cpu_leave_debug_mode(CPURISCVState *env); =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 58901bc3d8..a79efb2748 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -133,6 +133,91 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env= , bool virt) #endif } =20 +#ifndef CONFIG_USER_ONLY +static bool riscv_sdext_enabled(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_sdext; +} +#endif + +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, + uint32_t cause) +{ +#ifndef CONFIG_USER_ONLY + if (!riscv_sdext_enabled(env)) { + return; + } + + env->debug_mode =3D true; + env->dpc =3D pc & get_xepc_mask(env); + env->dcsr &=3D ~(DCSR_CAUSE_MASK | DCSR_PRV_MASK | DCSR_V); + env->dcsr |=3D (cause & 0x7) << DCSR_CAUSE_SHIFT; + env->dcsr |=3D env->priv & DCSR_PRV_MASK; + if (env->virt_enabled && riscv_has_ext(env, RVH)) { + env->dcsr |=3D DCSR_V; + } + + if (env_archcpu(env)->cfg.ext_zicfilp) { + if (env->elp) { + env->dcsr |=3D DCSR_PELP; + } else { + env->dcsr &=3D ~DCSR_PELP; + } + env->elp =3D false; + } +#endif +} + +void riscv_cpu_leave_debug_mode(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + uint32_t new_priv; + bool new_virt; + + if (!riscv_sdext_enabled(env)) { + return; + } + + new_priv =3D env->dcsr & DCSR_PRV_MASK; + new_virt =3D riscv_has_ext(env, RVH) && (env->dcsr & DCSR_V); + + if (new_priv =3D=3D PRV_M) { + new_virt =3D false; + } + + if (new_priv =3D=3D PRV_S && !riscv_has_ext(env, RVS)) { + new_priv =3D PRV_M; + new_virt =3D false; + } else if (new_priv =3D=3D PRV_U && !riscv_has_ext(env, RVU)) { + new_priv =3D riscv_has_ext(env, RVS) ? PRV_S : PRV_M; + new_virt =3D false; + } + + env->debug_mode =3D false; + riscv_cpu_set_mode(env, new_priv, new_virt); + + if (env_archcpu(env)->cfg.ext_zicfilp) { + env->elp =3D cpu_get_fcfien(env) && (env->dcsr & DCSR_PELP); + env->dcsr &=3D ~DCSR_PELP; + } + + if (new_priv !=3D PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, 0); + } + + if (env_archcpu(env)->cfg.ext_smdbltrp && new_priv !=3D PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 0); + } + if (env_archcpu(env)->cfg.ext_ssdbltrp && (new_priv =3D=3D PRV_U || ne= w_virt)) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_SDT, 0); + if (new_virt && new_priv =3D=3D PRV_U) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } +#endif +} + + /* * Returns the effective PMM field. * diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index e4d719a1da..2537515f54 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -973,6 +973,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 + /* Triggers must not match or fire while in Debug Mode. */ + if (env->debug_mode) { + return; + } + if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { do_trigger_action(env, DBG_ACTION_BP); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b68160af83..5729112201 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -269,6 +269,20 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_= idx, } return extract64(result, 0, 64 - pm_len); } + +static void riscv_cpu_exec_enter(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong pc =3D env->dpc; + + if (!cpu->cfg.ext_sdext || !env->debug_mode) { + return; + } + + riscv_cpu_leave_debug_mode(env); + env->pc =3D pc; +} #endif =20 const TCGCPUOps riscv_tcg_ops =3D { @@ -285,6 +299,7 @@ const TCGCPUOps riscv_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D riscv_cpu_tlb_fill, .pointer_wrap =3D riscv_pointer_wrap, + .cpu_exec_enter =3D riscv_cpu_exec_enter, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .cpu_exec_halt =3D riscv_cpu_has_work, .cpu_exec_reset =3D cpu_reset, --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:03:55 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Chao Liu , Daniel Henrique Barboza , Tao Tang , Alistair Francis , Nutty Liu Subject: [PULL v2 24/50] target/riscv: add dret instruction Date: Fri, 16 Oct 2026 11:02:11 +1000 Message-ID: <20261016010237.1102834-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=alistair23@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112866665158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add DRET decode/translate and a helper to leave Debug Mode and return to dpc. Executing DRET outside Debug Mode raises illegal instruction. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu Message-ID: <20260928195902.2045235-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/tcg/op_helper.c | 18 ++++++++++++++++++ .../tcg/insn_trans/trans_privileged.c.inc | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index aab92bf132..a790595b40 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -132,6 +132,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(dret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index aa02dae3c9..46b00411ff 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -118,6 +118,7 @@ sctrclr 000100000100 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 +dret 0111101 10010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma =20 diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b67c7718db..dbdaa64f5e 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -508,6 +508,24 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } =20 +target_ulong helper_dret(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +#else + target_ulong retpc; + + if (!riscv_cpu_cfg(env)->ext_sdext || !env->debug_mode) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + retpc =3D env->dpc & get_xepc_mask(env); + riscv_cpu_leave_debug_mode(env); + return retpc; +#endif +} + target_ulong helper_mnret(CPURISCVState *env) { target_ulong retpc =3D env->mnepc; diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index ebbbb01179..f1a042d57f 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -125,6 +125,24 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_dret(DisasContext *ctx, arg_dret *a) +{ +#ifndef CONFIG_USER_ONLY + if (!ctx->cfg_ptr->ext_sdext) { + return false; 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charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Route EBREAK via helper_sdext_ebreak. If Sdext is enabled and the matching dcsr.ebreak* bit is set, enter Debug Mode with cause=3Debreak and stop with EXCP_DEBUG. Otherwise keep the normal breakpoint trap. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu Message-ID: <20260928195902.2045235-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/tcg/op_helper.c | 34 +++++++++++++++++++ .../tcg/insn_trans/trans_privileged.c.inc | 6 ++++ 3 files changed, 41 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a790595b40..533dee1765 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -142,6 +142,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 /* Hypervisor functions */ diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index dbdaa64f5e..53e9eb445f 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -526,6 +526,40 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) +{ + CPUState *cs =3D env_cpu(env); + bool enter_debug =3D false; + + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode) { + if (env->virt_enabled) { + if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKVS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKVU; + } + } else { + if (env->priv =3D=3D PRV_M) { + enter_debug =3D env->dcsr & DCSR_EBREAKM; + } else if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKU; + } + } + } + + env->badaddr =3D pc; + + if (enter_debug) { + riscv_cpu_enter_debug_mode(env, pc, DCSR_CAUSE_EBREAK); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); + } + + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC()); +} + target_ulong helper_mnret(CPURISCVState *env) { target_ulong retpc =3D env->mnepc; diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index f1a042d57f..e22df6fbe7 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -68,9 +68,15 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *= a) if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D 0= x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); 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Thu, 15 Oct 2026 18:04:01 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Chao Liu , Daniel Henrique Barboza , Tao Tang , Alistair Francis , Nutty Liu Subject: [PULL v2 26/50] target/riscv: add sdext single-step support Date: Fri, 16 Oct 2026 11:02:13 +1000 Message-ID: <20261016010237.1102834-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113092982158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Use a TB flag when dcsr.step is set (and we are not in Debug Mode). When the flag is on, build 1-insn TBs and do not chain to the next TB. Add a TB-exit helper that enters Debug Mode with cause=3Dstep and sets dpc to the next pc, then stops with EXCP_DEBUG. If dcsr.stepie is 0, do not take interrupts while stepping. Treat WFI as a nop so the hart does not sleep during a step. PS: This patch references Max Chou's handling of ext_tb_flags. https://lore.kernel.org/qemu-devel/20260108132631.9429-6-max.chou@sifive.co= m/ Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu Message-ID: <20260928195902.2045235-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/exec/translation-block.h | 4 ++-- target/riscv/cpu.h | 2 ++ target/riscv/helper.h | 1 + target/riscv/tcg/cpu_helper.c | 6 ++++++ target/riscv/tcg/op_helper.c | 20 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 5 +++++ target/riscv/tcg/translate.c | 15 +++++++++++++-- 7 files changed, 49 insertions(+), 4 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 7c42c57cca..5a7a638b08 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -64,8 +64,8 @@ struct TranslationBlock { * x86: the original user, the Code Segment virtual base, * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). - * riscv: an extension of tb->flags, + * sparc: the next pc of the instruction queue (for delay slots), + * riscv: an extension of tb->flags. */ uint64_t cs_base; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b0a0e5d51a..bbef354354 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -783,6 +783,8 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) +/* sdext single-step needs a TB flag to build 1-insn TBs */ +FIELD(EXT_TB_FLAGS, SDEXT_STEP, 34, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 533dee1765..32225471bc 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -142,6 +142,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_1(sdext_step, void, env) DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index a79efb2748..b22ecc2eeb 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -501,6 +501,12 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP) && !(env->dcsr & DCSR_STEPIE)) { + return false; + } + int interruptno =3D riscv_cpu_local_irq_pending(env); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index 53e9eb445f..dc76055b80 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -526,6 +526,22 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_step(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + CPUState *cs =3D env_cpu(env); + + if (!riscv_cpu_cfg(env)->ext_sdext || env->debug_mode || + !(env->dcsr & DCSR_STEP)) { + return; + } + + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_STEP); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); +#endif +} + void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) { CPUState *cs =3D env_cpu(env); @@ -658,6 +674,10 @@ void helper_wfi(CPURISCVState *env) (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW))))= { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP)) { + return; + } cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; cpu_loop_exit(cs); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5729112201..edc530525f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -196,6 +196,11 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *= cs) ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_= ext); ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, BIG_ENDIAN, mo_endian_env(env) =3D=3D MO_BE); +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sdext && !env->debug_mode && (env->dcsr & DCSR_STEP))= { + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, SDEXT_STEP, 1); + } +#endif =20 return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index cce3b6dc72..d6b1f9bfee 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -115,6 +115,8 @@ typedef struct DisasContext { bool ztso; /* Use icount trigger for native debug */ bool itrigger; + /* Enter Debug Mode after next instruction (sdext single-step). */ + bool sdext_step; /* FRM is known to contain a valid value. */ bool frm_valid; bool insn_start_updated; @@ -289,6 +291,9 @@ static void lookup_and_goto_ptr(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_lookup_and_goto_ptr(); } @@ -299,6 +304,9 @@ static void exit_tb(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_exit_tb(NULL, 0); } @@ -312,7 +320,8 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_= slot_idx, * Under itrigger, instruction executes one by one like singlestep, * direct block chain benefits will be small. */ - if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { + if (translator_use_goto_tb(&ctx->base, dest) && + !ctx->itrigger && !ctx->sdext_step) { /* * For pcrel, the pc must always be up-to-date on entry to * the linked TB, so that it can use simple additions for all @@ -1380,6 +1389,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->bcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); ctx->fcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); + ctx->sdext_step =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, SDEXT_STEP); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; @@ -1432,7 +1442,8 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) =20 /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { - if (ctx->itrigger || !translator_is_same_page(&ctx->base, ctx->bas= e.pc_next)) { + if (ctx->itrigger || ctx->sdext_step || + !translator_is_same_page(&ctx->base, ctx->base.pc_next)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } else { unsigned page_ofs =3D ctx->base.pc_next & ~TARGET_PAGE_MASK; --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 15 Oct 2026 18:04:03 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Chao Liu , Daniel Henrique Barboza , Tao Tang , Alistair Francis Subject: [PULL v2 27/50] target/riscv: add sdtrig trigger action=debug mode Date: Fri, 16 Oct 2026 11:02:14 +1000 Message-ID: <20261016010237.1102834-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112882765158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Allow mcontrol/mcontrol6 action=3D1 when Sdext is enabled. When such a trigger hits, enter Debug Mode with cause=3Dtrigger and stop with EXCP_DEBUG. Also report inst-count triggers in tinfo and read their action field. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260928195902.2045235-7-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/debug.c | 54 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 2537515f54..aaf2dca17e 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -34,6 +34,7 @@ #include "exec/watchpoint.h" #include "system/cpu-timers.h" #include "exec/icount.h" +#include "accel/tcg/cpu-loop.h" =20 /* * The following M-mode trigger CSRs are implemented: @@ -117,6 +118,8 @@ static trigger_action_t get_trigger_action(CPURISCVStat= e *env, action =3D (tdata1 & TYPE6_ACTION) >> 12; break; case TRIGGER_TYPE_INST_CNT: + action =3D tdata1 & ITRIGGER_ACTION; + break; case TRIGGER_TYPE_INT: case TRIGGER_TYPE_EXCP: case TRIGGER_TYPE_EXT_SRC: @@ -287,6 +290,7 @@ static target_ulong textra_validate(CPURISCVState *env,= target_ulong tdata3) =20 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_ind= ex) { + CPUState *cs =3D env_cpu(env); trigger_action_t action =3D get_trigger_action(env, trigger_index); =20 switch (action) { @@ -296,6 +300,21 @@ static void do_trigger_action(CPURISCVState *env, targ= et_ulong trigger_index) riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); break; case DBG_ACTION_DBG_MODE: + if (!env_archcpu(env)->cfg.ext_sdext) { + qemu_log_mask(LOG_GUEST_ERROR, + "trigger action=3Ddebug mode requires Sdext\n"); + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_TRIGGER); + /* + * If this came from the Trigger Module's CPU breakpoint/watchpoin= t, + * we're already returning via EXCP_DEBUG. Otherwise, stop now. + */ + if (cs->exception_index !=3D EXCP_DEBUG) { + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); + } + break; case DBG_ACTION_TRACE0: case DBG_ACTION_TRACE1: case DBG_ACTION_TRACE2: @@ -448,6 +467,7 @@ static target_ulong type2_mcontrol_validate(CPURISCVSta= te *env, { target_ulong val; uint32_t size; + uint32_t action; =20 /* validate the generic part first */ val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); @@ -455,11 +475,25 @@ static target_ulong type2_mcontrol_validate(CPURISCVS= tate *env, /* validate unimplemented (always zero) bits */ warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); - warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); =20 + action =3D (ctrl & TYPE2_ACTION) >> 12; + if (action =3D=3D DBG_ACTION_BP) { + val |=3D ctrl & TYPE2_ACTION; + } else if (action =3D=3D DBG_ACTION_DBG_MODE) { + if (env_archcpu(env)->cfg.ext_sdext) { + val |=3D ctrl & TYPE2_ACTION; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "trigger action=3Ddebug mode requires Sdext\n"); + } + } else { + qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n", + action); + } + /* validate size encoding */ size =3D type2_breakpoint_size(env, ctrl); if (access_size[size] =3D=3D -1) { @@ -576,6 +610,7 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, { target_ulong val; uint32_t size; + uint32_t action; =20 /* validate the generic part first */ val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6); @@ -583,7 +618,6 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, /* validate unimplemented (always zero) bits */ warn_always_zero_bit(ctrl, TYPE6_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain"); - warn_always_zero_bit(ctrl, TYPE6_ACTION, "action"); warn_always_zero_bit(ctrl, TYPE6_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE6_HIT, "hit"); =20 @@ -593,6 +627,21 @@ static target_ulong type6_mcontrol6_validate(CPURISCVS= tate *env, warn_always_zero_bit(ctrl, TYPE6_TIMING_0_13, "timing"); } =20 + action =3D (ctrl & TYPE6_ACTION) >> 12; + if (action =3D=3D DBG_ACTION_BP) { + val |=3D ctrl & TYPE6_ACTION; + } else if (action =3D=3D DBG_ACTION_DBG_MODE) { + if (env_archcpu(env)->cfg.ext_sdext) { + val |=3D ctrl & TYPE6_ACTION; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "trigger action=3Ddebug mode requires Sdext\n"); + } + } else { + qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n", + action); + } + /* validate size encoding */ size =3D extract32(ctrl, 16, 4); if (access_size[size] =3D=3D -1) { @@ -959,6 +1008,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) target_ulong tinfo_csr_read(CPURISCVState *env) { target_ulong val =3D BIT(TRIGGER_TYPE_AD_MATCH) | + BIT(TRIGGER_TYPE_INST_CNT) | BIT(TRIGGER_TYPE_AD_MATCH6); =20 if (debug_trigger_version_1_0(env)) { --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:06 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 28/50] tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests Date: Fri, 16 Oct 2026 11:02:15 +1000 Message-ID: <20261016010237.1102834-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112729402158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Adding proper TCG automated tests to sdext CSRs requires enabling gdbstub support for riscv64, which we don't have, since the nature of the CSRs added is that they run in a higher privilege than M mode. DCSR has bits to allow for context switching from other modes to Debug mode, but those bits must be set via an external entity (e.g. gdb) beforehand. What we can do for now is a "negative" TCG test to ensure that we'll throw illegal insn traps when trying to write sdext CSRs in machine mode. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260928195902.2045235-8-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- tests/tcg/riscv64/system/meson.build | 8 +++ tests/tcg/riscv64/test-sdext-sigill.S | 83 +++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/syste= m/meson.build index a632674832..a7478b4219 100644 --- a/tests/tcg/riscv64/system/meson.build +++ b/tests/tcg/riscv64/system/meson.build @@ -62,6 +62,14 @@ tests +=3D { } } =20 +tests +=3D { + 'test-sdext-sigill.S': { + 'exe_name': 'test-sdext-sigill', + 'cflags': cflags + ['-march=3Drv64gcv'], + 'qemu_args': ['-cpu', 'rv64,sdtrig=3Dtrue,sdext=3Dtrue', qemu_args], + } +} + if 'qemu-system-riscv64' in emulators tcg_tests +=3D { 'riscv64-softmmu': { diff --git a/tests/tcg/riscv64/test-sdext-sigill.S b/tests/tcg/riscv64/test= -sdext-sigill.S new file mode 100644 index 0000000000..80a6c06465 --- /dev/null +++ b/tests/tcg/riscv64/test-sdext-sigill.S @@ -0,0 +1,83 @@ +/* + * RISC-V sdext extension "SIGILL" test: check if sdext CSRs + * and 'dret' will throw SIGILLs outside of Debug Mode. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +.equ CSR_DCSR, 0x7b0 +.equ CSR_DPC, 0x7b1 +.equ CSR_DSCRATCH0, 0x7b2 + + .option norvc + .text + + .global _start + +_start: + la t0, trap_handler + csrw mtvec, t0 + + dret + j _fail + + li t0, 1 + csrw CSR_DPC, t0 + j _fail + + li t0, 1 + csrw CSR_DSCRATCH0, t0 + j _fail + + li t0, 1 + csrw CSR_DCSR, t0 + j _fail + + li a0, 0 + j _exit + +_fail: + li a0, 1 + +/* Exit through the semihosting SYS_EXIT_EXTENDED call with a0 as the code= . */ +_exit: + la a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + + .balign 4 +trap_handler: + csrr t4, mcause + la t5, trap_mcause + sd t4, 0(t5) + csrr t4, mtval + la t5, trap_mtval + sd t4, 0(t5) + csrr t4, mepc + + /* + * Skip 2 insns (8 increment in mepc) to skip both the + * insn that caused the trap and the "j _fail" insn + * that follows it. + */ + addi t4, t4, 8 + csrw mepc, t4 + mret + + .data + .balign 8 +semiargs: + .space 16 +trap_mcause: + .space 8 +trap_mtval: + .space 8 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:09 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Alistair Francis , Chao Liu Subject: [PULL v2 29/50] target/riscv: Add cfg property for SiFive int8 matmul extensions Date: Fri, 16 Oct 2026 11:02:16 +1000 Message-ID: <20261016010237.1102834-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112813432158500 Content-Type: text/plain; charset="utf-8" From: Max Chou Add the CPU config properties for SiFive's custom int8 matrix multiply vector extensions: - Xsfvqmaccdod: 2x8x2 int8 matrix-multiply-accumulate operations - Xsfvqmaccqoq: 4x8x4 int8 matrix-multiply-accumulate operations All instructions of these extensions require the Zve32x extension to be present whenever either extension is enabled. Validate this in riscv_cpu_validate_vendor_ext() alongside the existing vector extension validation in riscv_cpu_validate_set_extensions(). Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Max Chou Reviewed-by: Chao Liu Message-ID: <20260927082534.3228237-2-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg_fields.h.inc | 2 ++ target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 24f3606f94..bcff8f55f1 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -160,6 +160,8 @@ BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) BOOL_FIELD(ext_xmipslsp) BOOL_FIELD(ext_xlrbr) +BOOL_FIELD(ext_xsfvqmaccdod) +BOOL_FIELD(ext_xsfvqmaccqoq) =20 BOOL_FIELD(big_endian) BOOL_FIELD(mmu) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c0837c6c55..a175817e22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -301,6 +301,8 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp), + ISA_EXT_DATA_ENTRY(xsfvqmaccdod, PRIV_VERSION_1_13_0, ext_xsfvqmaccdod= ), + ISA_EXT_DATA_ENTRY(xsfvqmaccqoq, PRIV_VERSION_1_13_0, ext_xsfvqmaccqoq= ), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index edc530525f..e07ca95e49 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -436,6 +436,16 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, } } =20 +static void riscv_cpu_validate_vendor_ext(RISCVCPU *cpu, Error **errp) +{ + if ((cpu->cfg.ext_xsfvqmaccdod || cpu->cfg.ext_xsfvqmaccqoq) && + !cpu->cfg.ext_zve32x) { + error_setg(errp, "Xsfvqmaccdod/Xsfvqmaccqoq extensions require " + "Zve32x extension"); + return; + } +} + static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; @@ -813,6 +823,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + riscv_cpu_validate_vendor_ext(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { error_setg(errp, "svukte is not supported for RV32"); return; --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1792112779; cv=none; d=zohomail.com; s=zohoarc; b=cdsYsIAcDe4ZlgBvh7ubNcEYUoszvmqxwrp8pW6yqGUlJSy2hDxqoR7La84ITrfq855hG4nuFMMcjl8J3pEJF6egPld2H7zXDGqBHx91ZxIyn5IYde1PpJhCFvK32nZl09uRSKg8VNM0UxYTZhhburuZWNJS1j9Jwt6trOFLMcQ= ARC-Message-Signature: i=1; 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Thu, 15 Oct 2026 18:04:11 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Alistair Francis , Chao Liu Subject: [PULL v2 30/50] target/riscv/cpu: List one implied-ext rule per line Date: Fri, 16 Oct 2026 11:02:17 +1000 Message-ID: <20261016010237.1102834-31-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112780772158500 Content-Type: text/plain; charset="utf-8" From: Max Chou Every entry added to riscv_multi_ext_implied_rules currently has to reflow whatever line it lands on, since entries are packed several per line. List one rule per line instead so future additions are a pure append. Suggested-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Max Chou Reviewed-by: Chao Liu Message-ID: <20260927082534.3228237-3-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 58 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a175817e22..f99698b83e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2927,20 +2927,50 @@ RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rul= es[] =3D { }; =20 RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] =3D { - &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED, - &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED, - &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED, - &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED, - &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED, - &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED, - &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, - &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, - &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, - &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, - &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED, - &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, - &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, + &ZCB_IMPLIED, + &ZCD_IMPLIED, + &ZCE_IMPLIED, + &ZCF_IMPLIED, + &ZCMP_IMPLIED, + &ZCMT_IMPLIED, + &ZDINX_IMPLIED, + &ZFA_IMPLIED, + &ZFBFMIN_IMPLIED, + &ZFH_IMPLIED, + &ZFHMIN_IMPLIED, + &ZFINX_IMPLIED, + &ZHINX_IMPLIED, + &ZHINXMIN_IMPLIED, + &ZICNTR_IMPLIED, + &ZIHPM_IMPLIED, + &ZK_IMPLIED, + &ZKN_IMPLIED, + &ZKS_IMPLIED, + &ZVBB_IMPLIED, + &ZVE32F_IMPLIED, + &ZVE32X_IMPLIED, + &ZVE64D_IMPLIED, + &ZVE64F_IMPLIED, + &ZVE64X_IMPLIED, + &ZVFBFA_IMPLIED, + &ZVFBFMIN_IMPLIED, + &ZVFBFWMA_IMPLIED, + &ZVFH_IMPLIED, + &ZVFHMIN_IMPLIED, + &ZVKN_IMPLIED, + &ZVKNC_IMPLIED, + &ZVKNG_IMPLIED, + &ZVKNHB_IMPLIED, + &ZVKS_IMPLIED, + &ZVKSC_IMPLIED, + &ZVKSG_IMPLIED, + &SHA_IMPLIED, + &SSCFG_IMPLIED, + &SUPM_IMPLIED, + &SSPM_IMPLIED, + &SMCTR_IMPLIED, + &SSCTR_IMPLIED, + &SSSTATEEN_IMPLIED, NULL }; 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Thu, 15 Oct 2026 18:04:15 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Frank Chang , Daniel Henrique Barboza , Alistair Francis , Max Chou , Chao Liu Subject: [PULL v2 31/50] target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules Date: Fri, 16 Oct 2026 11:02:18 +1000 Message-ID: <20261016010237.1102834-32-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113080654158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add SiFive custom int8 matmul extension implied rules to enable the implied extensions of SiFive custom int8 matmul extension recursively. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Max Chou Reviewed-by: Chao Liu Message-ID: <20260927082534.3228237-4-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f99698b83e..9e3d096802 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2920,6 +2920,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_xsfvqmaccdod), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_xsfvqmaccqoq), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] =3D { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, @@ -2971,6 +2989,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &SMCTR_IMPLIED, &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, + &XSFVQMACCDOD_IMPLIED, + &XSFVQMACCQOQ_IMPLIED, NULL }; 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Thu, 15 Oct 2026 18:04:17 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Frank Chang , Daniel Henrique Barboza , Alistair Francis , Max Chou , Chao Liu Subject: [PULL v2 32/50] target/riscv: rvv: Add SiFive custom int8 matmul instructions Date: Fri, 16 Oct 2026 11:02:19 +1000 Message-ID: <20261016010237.1102834-33-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113041950158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add the 8 SiFive custom int8 matrix-multiply vector instructions: sf.vqmacc{u,,us,su}.4x8x4 and sf.vqmacc{u,,us,su}.2x8x2. Each name suffix encodes the signedness of vs1/vs2. The 4x8x4 forms multiply-accumulate a 4x8 by 8x4 int8 tile into a 4x4 int32 result; the 2x8x2 forms use a 2x8 by 8x2 tile producing a 2x2 int32 result. Both Xsfvqmaccqoq/Xsfvqmaccdod extensions are gated on vlenb >=3D 32, sew =3D=3D 8 and vm =3D=3D 1, per the SiFive Int8 Matrix Multiplication Extensions Specification. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Max Chou Reviewed-by: Chao Liu Message-ID: <20260927082534.3228237-5-max.chou@sifive.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 8 ++ target/riscv/cpu_cfg.h | 5 ++ target/riscv/helper.h | 10 +++ target/riscv/xsf.decode | 30 +++++++ target/riscv/tcg/translate.c | 3 + target/riscv/tcg/xsf_helper.c | 87 ++++++++++++++++++ target/riscv/tcg/insn_trans/trans_xsf.c.inc | 98 +++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/tcg/meson.build | 1 + 9 files changed, 243 insertions(+) create mode 100644 target/riscv/xsf.decode create mode 100644 target/riscv/tcg/xsf_helper.c create mode 100644 target/riscv/tcg/insn_trans/trans_xsf.c.inc diff --git a/MAINTAINERS b/MAINTAINERS index b912e4b8d8..09dc49d27f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -398,6 +398,14 @@ F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc F: disas/riscv-xventana* =20 +RISC-V SiFive (Xsf*) extensions +M: Max Chou +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/xsf.decode +F: target/riscv/tcg/insn_trans/trans_xsf.c.inc +F: target/riscv/tcg/xsf_helper.c + RENESAS RX CPUs R: Yoshinori Sato S: Orphan diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 211d0708ba..d6db1cfb7c 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -51,6 +51,11 @@ static inline bool has_xthead_p(const RISCVCPUConfig *cf= g) cfg->ext_xtheadmempair || cfg->ext_xtheadsync; } =20 +static inline bool has_xsf_p(const RISCVCPUConfig *cfg) +{ + return cfg->ext_xsfvqmaccdod || cfg->ext_xsfvqmaccqoq; +} + #define MATERIALISE_EXT_PREDICATE(ext) \ static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \ { \ diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 32225471bc..0e22210377 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1365,3 +1365,13 @@ DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, v= oid, env, tl, tl) /* Invalidate reservations overlapping a completed linux-user store. */ DEF_HELPER_3(riscv_invalidate_reservations, void, env, tl, tl) #endif + +/* SiFive Custom int8 Matrix-Multiply */ +DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmaccus_4x8x4, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmaccsu_4x8x4, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmaccu_2x8x2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmacc_2x8x2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmaccus_2x8x2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(sf_vqmaccsu_2x8x2, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/xsf.decode b/target/riscv/xsf.decode new file mode 100644 index 0000000000..bb585046ab --- /dev/null +++ b/target/riscv/xsf.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the SiFive vendor extensions +# +# Copyright (c) 2023 SiFive, Inc. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# Fields: +%rs2 20:5 +%rs1 15:5 +%rd 7:5 +%vm 25:1 + +# Argument sets: +&rmrr vm rd rs1 rs2 !extern + +# Formats: +@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=3D1 %rs2 %rs1 = %rd + +# *** Xsfvqmaccqoq: SiFive custom int8 matrix-multiply (4x8x4 tile) *** +sf_vqmaccu_4x8x4 111100 1 ..... ..... 010 ..... 1011011 @r_vm_1 +sf_vqmacc_4x8x4 111101 1 ..... ..... 010 ..... 1011011 @r_vm_1 +sf_vqmaccus_4x8x4 111110 1 ..... ..... 010 ..... 1011011 @r_vm_1 +sf_vqmaccsu_4x8x4 111111 1 ..... ..... 010 ..... 1011011 @r_vm_1 + +# *** Xsfvqmaccdod: SiFive custom int8 matrix-multiply (2x8x2 tile) *** +sf_vqmaccu_2x8x2 101100 1 ..... ..... 010 ..... 1011011 @r_vm_1 +sf_vqmacc_2x8x2 101101 1 ..... ..... 010 ..... 1011011 @r_vm_1 +sf_vqmaccus_2x8x2 101110 1 ..... ..... 010 ..... 1011011 @r_vm_1 +sf_vqmaccsu_2x8x2 101111 1 ..... ..... 010 ..... 1011011 @r_vm_1 diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index d6b1f9bfee..470a5e71b2 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -1255,10 +1255,12 @@ static uint32_t opcode_at(DisasContextBase *dcbase,= target_ulong pc) #include "decode-xthead.c.inc" #include "decode-xmips.c.inc" #include "decode-xlrbr.c.inc" +#include "decode-xsf.c.inc" #include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" #include "insn_trans/trans_xmips.c.inc" #include "insn_trans/trans_xlrbr.c.inc" +#include "insn_trans/trans_xsf.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" @@ -1279,6 +1281,7 @@ const RISCVDecoder decoder_table[] =3D { { has_xthead_p, decode_xthead}, { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, { has_xlrbr_p, decode_xlrbr}, + { has_xsf_p, decode_xsf }, }; =20 const size_t decoder_table_size =3D ARRAY_SIZE(decoder_table); diff --git a/target/riscv/tcg/xsf_helper.c b/target/riscv/tcg/xsf_helper.c new file mode 100644 index 0000000000..6e953d1249 --- /dev/null +++ b/target/riscv/tcg/xsf_helper.c @@ -0,0 +1,87 @@ +/* + * RISC-V translation helpers for the SiFive vendor extensions (xsf*) + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "internals.h" +#include "vector_internals.h" + +#define QOP_SUU_B int32_t, uint8_t, uint8_t, int32_t, int32_t +#define QOP_SUS_B int32_t, uint8_t, int8_t, int32_t, int32_t +#define QOP_SSU_B int32_t, int8_t, uint8_t, int32_t, int32_t +#define QOP_SSS_B int32_t, int8_t, int8_t, int32_t, int32_t + +/* SiFive Custom int8 Matrix-Multiply */ +/* + * vd may overlap vs2, we need to allocate an additional vd array + * to save temporary results of vd and write them back at the end. + */ +#define GEN_VEXT_SF_INT8_MATMUL(NAME, TD, T1, T2, TX1, TX2, \ + HD, HS1, HS2, ROWS, COLS, TILE_SIZE) \ +void HELPER(NAME)(void *vd, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + int it, il, in, im, ivd, ivs1, ivs2; \ + TD *vds; \ + \ + if (env->vl % TILE_SIZE) { \ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); \ + return; \ + } \ + \ + VSTART_CHECK_EARLY_EXIT(env, env->vl); \ + \ + vds =3D g_malloc0(sizeof(TD) * \ + ROWS * ROWS * (env->vl / TILE_SIZE)); \ + \ + for (it =3D 0; it < (env->vl / TILE_SIZE); it++) { \ + for (il =3D 0; il < ROWS; il++) { \ + for (in =3D 0; in < ROWS; in++) { \ + ivd =3D ROWS * ROWS * it + ROWS * il + in; \ + vds[ivd] =3D *((TD *)vd + HD(ivd)); \ + for (im =3D 0; im < COLS; im++) { \ + ivs1 =3D il * COLS + im; \ + ivs2 =3D TILE_SIZE * it + im * ROWS + in; \ + T1 s1 =3D *((T1 *)vs1 + HS1(ivs1)); \ + T2 s2 =3D *((T2 *)vs2 + HS2(ivs2)); \ + vds[ivd] +=3D (TX1)s1 * (TX2)s2; \ + } \ + } \ + } \ + } \ + \ + for (it =3D 0; it < (env->vl / TILE_SIZE); it++) { \ + for (il =3D 0; il < ROWS; il++) { \ + for (in =3D 0; in < ROWS; in++) { \ + ivd =3D ROWS * ROWS * it + ROWS * il + in; \ + *((TD *)vd + HD(ivd)) =3D vds[ivd]; \ + } \ + } \ + } \ + \ + env->vstart =3D 0; \ + g_free(vds); \ +} + +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmaccu_4x8x4, QOP_SUU_B, H4, H1, H1, + 4, 8, 32) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmacc_4x8x4, QOP_SSS_B, H4, H1, H1, + 4, 8, 32) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmaccus_4x8x4, QOP_SUS_B, H4, H1, H1, + 4, 8, 32) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmaccsu_4x8x4, QOP_SSU_B, H4, H1, H1, + 4, 8, 32) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmaccu_2x8x2, QOP_SUU_B, H4, H1, H1, + 2, 8, 16) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmacc_2x8x2, QOP_SSS_B, H4, H1, H1, + 2, 8, 16) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmaccus_2x8x2, QOP_SUS_B, H4, H1, H1, + 2, 8, 16) +RVVCALL(GEN_VEXT_SF_INT8_MATMUL, sf_vqmaccsu_2x8x2, QOP_SSU_B, H4, H1, H1, + 2, 8, 16) diff --git a/target/riscv/tcg/insn_trans/trans_xsf.c.inc b/target/riscv/tcg= /insn_trans/trans_xsf.c.inc new file mode 100644 index 0000000000..1677352689 --- /dev/null +++ b/target/riscv/tcg/insn_trans/trans_xsf.c.inc @@ -0,0 +1,98 @@ +/* + * RISC-V translation routines for the SiFive vendor extensions (xsf*) + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + +/* + * SiFive Xsfvqmaccdod/Xsfvqmaccqoq custom int8 matrix-multiply extensions + */ +static bool sf_int8_matmul_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + s->vstart_eq_zero && + (s->cfg_ptr->vlenb >=3D 32) && + (s->sew =3D=3D MO_8) && + (a->vm =3D=3D 1); +} + +static bool sf_int8_matmul_4x8x4_check(DisasContext *s, arg_rmrr *a) +{ + /* + * vd has EMUL=3D2*LMUL + * vs2 has EMUL=3DLMUL + * vs1 has EMUL=3D1 + * vd must not overlap vs1 + */ + return sf_int8_matmul_check(s, a) && + (s->cfg_ptr->ext_xsfvqmaccqoq) && + (s->lmul <=3D 2) && + require_align(a->rd, s->lmul + 1) && + require_align(a->rs2, s->lmul) && + require_align(a->rs1, 0) && + require_noover(a->rd, s->lmul + 1, a->rs2, s->lmul) && + !is_overlapped(a->rd, 1 << MAX(s->lmul + 1, 0), a->rs1, 1); +} + +static bool sf_int8_matmul_2x8x2_check(DisasContext *s, arg_rmrr *a) +{ + /* + * vd has EMUL=3DLMUL + * vs2 has EMUL=3DLMUL + * vs1 has EMUL=3D1 + * vd must not overlap vs1 + */ + return sf_int8_matmul_check(s, a) && + (s->cfg_ptr->ext_xsfvqmaccdod) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + require_align(a->rs1, 0) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1); +} + +static bool sf_int8_matmul_op(DisasContext *s, arg_rmrr *a, uint8_t seq) +{ + static gen_helper_gvec_3_ptr * const fns[8] =3D { + gen_helper_sf_vqmaccu_4x8x4, gen_helper_sf_vqmacc_4x8x4, + gen_helper_sf_vqmaccus_4x8x4, gen_helper_sf_vqmaccsu_4x8x4, + gen_helper_sf_vqmaccu_2x8x2, gen_helper_sf_vqmacc_2x8x2, + gen_helper_sf_vqmaccus_2x8x2, gen_helper_sf_vqmaccsu_2x8x2, + }; + + /* + * The helper raises an illegal-instruction exception when vl is not a + * multiple of the tile size; save the opcode so mtval/stval report the + * faulting instruction if that exception is thrown. + */ + decode_save_opc(s, 0); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), tcg_env, + s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, 0, fns[seq]); + + finalize_rvv_inst(s); + + return true; +} + +#define GEN_SF_INT8_MATMUL_TRANS(NAME, CHECK, SEQ) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + return sf_int8_matmul_op(s, a, SEQ); \ + } \ + return false; \ +} + +GEN_SF_INT8_MATMUL_TRANS(sf_vqmaccu_4x8x4, sf_int8_matmul_4x8x4_check, 0) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmacc_4x8x4, sf_int8_matmul_4x8x4_check, 1) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmaccus_4x8x4, sf_int8_matmul_4x8x4_check, 2) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmaccsu_4x8x4, sf_int8_matmul_4x8x4_check, 3) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmaccu_2x8x2, sf_int8_matmul_2x8x2_check, 4) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmacc_2x8x2, sf_int8_matmul_2x8x2_check, 5) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmaccus_2x8x2, sf_int8_matmul_2x8x2_check, 6) +GEN_SF_INT8_MATMUL_TRANS(sf_vqmaccsu_2x8x2, sf_int8_matmul_2x8x2_check, 7) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index e1b51d2bd4..da1df1e74e 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -6,6 +6,7 @@ gen =3D [ decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), decodetree.process('xmips.decode', extra_args: '--static-decode=3Ddecode= _xmips'), decodetree.process('xlrbr.decode', extra_args: '--static-decode=3Ddecode= _xlrbr'), + decodetree.process('xsf.decode', extra_args: '--static-decode=3Ddecode_x= sf'), ] =20 riscv_ss =3D ss.source_set() diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index a05ab642f4..86805b30cb 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -15,6 +15,7 @@ riscv_ss.add(files( 'vcrypto_helper.c', 'vector_helper.c', 'vector_internals.c', + 'xsf_helper.c', 'zce_helper.c')) =20 =20 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Jason Chien Add disassembler support for all SiFive custom int8 matrix-multiply instructions: sf.vqmacc{u,,us,su}.4x8x4 and sf.vqmacc{u,,us,su}.2x8x2. These instructions share opcode 0b1011011 and funct3 0b010, and are distinguished by funct6: 60-63 for the 4x8x4 (Xsfvqmaccqoq) tile and 44-47 for the 2x8x2 (Xsfvqmaccdod) tile. Signed-off-by: Jason Chien Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Max Chou Reviewed-by: Chao Liu Message-ID: <20260927082534.3228237-6-max.chou@sifive.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + disas/riscv-xsf.h | 16 +++++++++++++ disas/riscv.h | 1 + disas/riscv-xsf.c | 49 ++++++++++++++++++++++++++++++++++++++++ disas/riscv.c | 2 ++ disas/riscv-xsf-op.c.inc | 11 +++++++++ disas/meson.build | 3 ++- 7 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 disas/riscv-xsf.h create mode 100644 disas/riscv-xsf.c create mode 100644 disas/riscv-xsf-op.c.inc diff --git a/MAINTAINERS b/MAINTAINERS index 09dc49d27f..de47c4a879 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -405,6 +405,7 @@ S: Supported F: target/riscv/xsf.decode F: target/riscv/tcg/insn_trans/trans_xsf.c.inc F: target/riscv/tcg/xsf_helper.c +F: disas/riscv-xsf* =20 RENESAS RX CPUs R: Yoshinori Sato diff --git a/disas/riscv-xsf.h b/disas/riscv-xsf.h new file mode 100644 index 0000000000..b15b7aa97c --- /dev/null +++ b/disas/riscv-xsf.h @@ -0,0 +1,16 @@ +/* + * QEMU disassembler -- RISC-V specific header (xsf*). + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_RISCV_XSF_H +#define DISAS_RISCV_XSF_H + +#include "disas/riscv.h" + +const rv_opcode_data *decode_xsf(rv_decode *, rv_isa); + +#endif /* DISAS_RISCV_XSF_H */ diff --git a/disas/riscv.h b/disas/riscv.h index b0269bb709..4f1ffc4ae0 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -262,6 +262,7 @@ typedef struct { #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" #define rv_fmt_vd_vs2_uimm "O\tD,F,u" #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" +#define rv_fmt_vd_vs1_vs2 "O\tD,E,F" #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" diff --git a/disas/riscv-xsf.c b/disas/riscv-xsf.c new file mode 100644 index 0000000000..745fcc8efd --- /dev/null +++ b/disas/riscv-xsf.c @@ -0,0 +1,49 @@ +/* + * QEMU RISC-V Disassembler for xsf (SiFive vendor extensions). + * + * Copyright (c) 2023 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "disas/riscv.h" +#include "disas/riscv-xsf.h" + +#define OP(N, ...) static const rv_opcode_data op_##N =3D { __VA_ARGS__ }; +#include "riscv-xsf-op.c.inc" +#undef OP + +const rv_opcode_data *decode_xsf(rv_decode *dec, rv_isa isa) +{ + rv_inst inst =3D dec->inst; + + switch ((inst >> 0) & 0b1111111) { + case 0b1011011: + switch ((inst >> 12) & 0b111) { + case 0b010: + switch ((inst >> 26) & 0b111111) { + case 0b101100: + return &op_sf_vqmaccu_2x8x2; + case 0b101101: + return &op_sf_vqmacc_2x8x2; + case 0b101110: + return &op_sf_vqmaccus_2x8x2; + case 0b101111: + return &op_sf_vqmaccsu_2x8x2; + case 0b111100: + return &op_sf_vqmaccu_4x8x4; + case 0b111101: + return &op_sf_vqmacc_4x8x4; + case 0b111110: + return &op_sf_vqmaccus_4x8x4; + case 0b111111: + return &op_sf_vqmaccsu_4x8x4; + } + break; + } + break; + } + + return NULL; +} diff --git a/disas/riscv.c b/disas/riscv.c index ef8b7ff20f..d755172164 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -27,6 +27,7 @@ #include "disas/riscv-xthead.h" #include "disas/riscv-xventana.h" #include "disas/riscv-xlrbr.h" +#include "disas/riscv-xsf.h" =20 /* register names */ =20 @@ -3456,6 +3457,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, = rv_inst inst, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_xventanacondops }, { has_xlrbr_p, decode_xlrbr }, + { has_xsf_p, decode_xsf }, }; =20 for (size_t i =3D 0; i < ARRAY_SIZE(decoders); i++) { diff --git a/disas/riscv-xsf-op.c.inc b/disas/riscv-xsf-op.c.inc new file mode 100644 index 0000000000..c8daa7ebef --- /dev/null +++ b/disas/riscv-xsf-op.c.inc @@ -0,0 +1,11 @@ +/* Xsfvqmaccqoq */ +OP(sf_vqmaccu_4x8x4, "sf.vqmaccu.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmacc_4x8x4, "sf.vqmacc.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccus_4x8x4, "sf.vqmaccus.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccsu_4x8x4, "sf.vqmaccsu.4x8x4", rv_codec_v_r, rv_fmt_vd_vs1_vs2) + +/* Xsfvqmaccdod */ +OP(sf_vqmaccu_2x8x2, "sf.vqmaccu.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmacc_2x8x2, "sf.vqmacc.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccus_2x8x2, "sf.vqmaccus.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) +OP(sf_vqmaccsu_2x8x2, "sf.vqmaccsu.2x8x2", rv_codec_v_r, rv_fmt_vd_vs1_vs2) diff --git a/disas/meson.build b/disas/meson.build index b382550e41..9b14adf4f1 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -8,7 +8,8 @@ common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( 'riscv.c', 'riscv-xthead.c', 'riscv-xventana.c', - 'riscv-xlrbr.c' + 'riscv-xlrbr.c', + 'riscv-xsf.c' )) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:23 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Alistair Francis , Chao Liu Subject: [PULL v2 34/50] tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions Date: Fri, 16 Oct 2026 11:02:21 +1000 Message-ID: <20261016010237.1102834-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113052107158500 Content-Type: text/plain; charset="utf-8" From: Max Chou Add a test that exercises all SiFive int8 matrix-multiply instructions from the Xsfvqmaccqoq and Xsfvqmaccdod extensions. For each tile shape the test covers the four signedness variants (sf.vqmaccu / sf.vqmacc / sf.vqmaccus / sf.vqmaccsu) and the reserved-encoding path: with vl set to a value that is not a multiple of the tile size the helper raises an illegal-instruction exception. Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Max Chou Reviewed-by: Chao Liu Message-ID: <20260927082534.3228237-7-max.chou@sifive.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + tests/tcg/riscv64/system/meson.build | 7 + tests/tcg/riscv64/test-xsfvqmacc.S | 260 +++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 tests/tcg/riscv64/test-xsfvqmacc.S diff --git a/MAINTAINERS b/MAINTAINERS index de47c4a879..cceefb4cb9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -406,6 +406,7 @@ F: target/riscv/xsf.decode F: target/riscv/tcg/insn_trans/trans_xsf.c.inc F: target/riscv/tcg/xsf_helper.c F: disas/riscv-xsf* +F: tests/tcg/riscv64/test-xsfvqmacc.S =20 RENESAS RX CPUs R: Yoshinori Sato diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/syste= m/meson.build index a7478b4219..3e1c970382 100644 --- a/tests/tcg/riscv64/system/meson.build +++ b/tests/tcg/riscv64/system/meson.build @@ -70,6 +70,13 @@ tests +=3D { } } =20 +tests +=3D { + 'test-xsfvqmacc.S': { + 'cflags': cflags, + 'qemu_args': ['-cpu', 'rv64,v=3Dtrue,vlen=3D256,xsfvqmaccdod=3Dtrue,xs= fvqmaccqoq=3Dtrue', qemu_args], + } +} + if 'qemu-system-riscv64' in emulators tcg_tests +=3D { 'riscv64-softmmu': { diff --git a/tests/tcg/riscv64/test-xsfvqmacc.S b/tests/tcg/riscv64/test-xs= fvqmacc.S new file mode 100644 index 0000000000..a116712e50 --- /dev/null +++ b/tests/tcg/riscv64/test-xsfvqmacc.S @@ -0,0 +1,260 @@ +/* + * Test the SiFive Xsfvqmaccqoq/Xsfvqmaccdod custom int8 matrix-multiply + * extensions. + * + * The eight instructions widen 8-bit integer inputs to 32 bits and perform + * a matrix-multiply-accumulate into a vector of int32 accumulators: + * + * C[j] +=3D A * B[j] + * + * Xsfvqmaccqoq (4x8x4): A is 4x8, B[j] is 8x4, C[j] is 4x4 int32. One mat= rix + * operation is performed per 32 elements of vl (TILE_SIZE =3D 32). + * Xsfvqmaccdod (2x8x2): A is 2x8, B[j] is 8x2, C[j] is 2x2 int32. One mat= rix + * operation is performed per 16 elements of vl (TILE_SIZE =3D 16). + * + * The input tiles below contain bytes >=3D 0x80 so that each signedness + * variant produces a distinct result; the expected int32 tiles were compu= ted + * with an independent reference model of the specification. The accumulat= ors + * are cleared before every operation, so the expected value is the pure + * matrix product. + * + * Test exits via semihosting with status 0 on success, or the 1-based ind= ex + * of the first failing operation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + .option arch, +v + .option norvc + + .text + +/* + * Run one 4x8x4 operation: load the 32-byte A and B tiles, clear the 4x4 + * int32 accumulator (vd =3D v4:v5, EMUL =3D 2), execute the op, then comp= are the + * 16 int32 results against the expected tile. + */ +.macro RUN_QOQ id, word, exp + li a2, 32 + vsetvli t0, a2, e8, m1, ta, ma + la t1, a_qoq + vle8.v v1, (t1) + la t1, b_qoq + vle8.v v2, (t1) + vsetvli t0, x0, e32, m2, ta, ma + vmv.v.i v4, 0 + li a2, 32 + vsetvli t0, a2, e8, m1, ta, ma + .word \word + vsetvli t0, x0, e32, m2, ta, ma + la t1, result + vse32.v v4, (t1) + la a0, result + la a1, \exp + li a2, 16 + li t6, \id + call check_words +.endm + +/* + * Run one 2x8x2 operation: load the 16-byte A and B tiles, clear the 2x2 + * int32 accumulator (vd =3D v4, EMUL =3D 1), execute the op, then compare= the + * 4 int32 results against the expected tile. + */ +.macro RUN_DOD id, word, exp + li a2, 16 + vsetvli t0, a2, e8, m1, ta, ma + la t1, a_dod + vle8.v v1, (t1) + la t1, b_dod + vle8.v v2, (t1) + vsetvli t0, x0, e32, m1, ta, ma + vmv.v.i v4, 0 + li a2, 16 + vsetvli t0, a2, e8, m1, ta, ma + .word \word + vsetvli t0, x0, e32, m1, ta, ma + la t1, result + vse32.v v4, (t1) + la a0, result + la a1, \exp + li a2, 4 + li t6, \id + call check_words +.endm + + .global _start +_start: + /* Enable the vector unit (mstatus.VS =3D Initial). */ + li t0, 1 << 9 + csrs mstatus, t0 + + /* Route synchronous traps to trap_handler (mtvec direct mode). */ + la t0, trap_handler + csrw mtvec, t0 + + RUN_QOQ 1, 0xF220A25B, exp_qoq_u /* sf.vqmaccu.4x8x4 */ + RUN_QOQ 2, 0xF620A25B, exp_qoq_s /* sf.vqmacc.4x8x4 */ + RUN_QOQ 3, 0xFA20A25B, exp_qoq_us /* sf.vqmaccus.4x8x4 */ + RUN_QOQ 4, 0xFE20A25B, exp_qoq_su /* sf.vqmaccsu.4x8x4 */ + RUN_DOD 5, 0xB220A25B, exp_dod_u /* sf.vqmaccu.2x8x2 */ + RUN_DOD 6, 0xB620A25B, exp_dod_s /* sf.vqmacc.2x8x2 */ + RUN_DOD 7, 0xBA20A25B, exp_dod_us /* sf.vqmaccus.2x8x2 */ + RUN_DOD 8, 0xBE20A25B, exp_dod_su /* sf.vqmaccsu.2x8x2 */ + + /* + * Illegal-instruction reporting test (op 9). + * + * When vl is not a multiple of the tile size the instruction is + * reserved and the helper raises an illegal-instruction exception at + * runtime. + */ + la t1, trap_mtval + sd zero, 0(t1) + la t1, trap_mcause + sd zero, 0(t1) + /* vl =3D 16 is not a multiple of the 4x8x4 tile size (32 elements). */ + li a2, 16 + vsetvli t0, a2, e8, m1, ta, ma + .word 0xF220A25B /* sf.vqmaccu.4x8x4, traps */ + /* The handler skips the faulting insn, so control resumes here. */ + li a0, 9 /* fail code for this check */ + la t1, trap_mcause + ld t2, 0(t1) + li t3, 2 /* RISCV_EXCP_ILLEGAL_INST */ + bne t2, t3, _exit + la t1, trap_mtval + ld t2, 0(t1) + li t3, 0xF220A25B + bne t2, t3, _exit + + li a0, 0 + j _exit + +/* + * Machine-mode trap handler: record mcause and mtval, then advance mepc + * past the 4-byte faulting instruction and return. + */ + .balign 4 +trap_handler: + csrr t4, mcause + la t5, trap_mcause + sd t4, 0(t5) + csrr t4, mtval + la t5, trap_mtval + sd t4, 0(t5) + csrr t4, mepc + addi t4, t4, 4 + csrw mepc, t4 + mret + +/* + * check_words(a0 =3D result, a1 =3D expected, a2 =3D word count). + * Returns to the caller if every word matches; otherwise exits with the + * operation index held in t6. + */ +check_words: +1: beqz a2, 2f + lw t2, 0(a0) + lw t3, 0(a1) + bne t2, t3, 3f + addi a0, a0, 4 + addi a1, a1, 4 + addi a2, a2, -1 + j 1b +2: ret +3: mv a0, t6 + j _exit + +/* Exit through the semihosting SYS_EXIT_EXTENDED call with a0 as the code= . */ +_exit: + la a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 8 +semiargs: + .space 16 +result: + .space 64 +trap_mcause: + .space 8 +trap_mtval: + .space 8 + +/* + * A (4x8, row-major) in bytes [0, 32) of vs1. + */ +a_qoq: + .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x80 + .byte 0xFF, 0x01, 0x00, 0x02, 0x7F, 0x03, 0x04, 0x05 + .byte 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x08 + .byte 0x00, 0x00, 0x81, 0x00, 0x00, 0x02, 0x00, 0x03 +/* + * B (8x4, row-major) in bytes [0, 32) of vs2. + */ +b_qoq: + .byte 0x01, 0x02, 0x03, 0x04 + .byte 0x05, 0x06, 0x07, 0x08 + .byte 0x80, 0x7F, 0xFF, 0x01 + .byte 0x00, 0x10, 0x20, 0x30 + .byte 0x02, 0x02, 0x02, 0x02 + .byte 0xFE, 0x01, 0x00, 0x7F + .byte 0x03, 0x00, 0x81, 0x04 + .byte 0x40, 0x50, 0x60, 0x70 +/* + * A (2x8, row-major) in bytes [0, 16) of vs1. + */ +a_dod: + .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x80 + .byte 0xFF, 0x7F, 0x00, 0x02, 0x81, 0x03, 0x04, 0x05 +/* + * B (8x2, row-major) in bytes [0, 16) of vs2. + */ +b_dod: + .byte 0x01, 0x02 + .byte 0x80, 0x7F + .byte 0x03, 0xFF + .byte 0x00, 0x10 + .byte 0x02, 0xFE + .byte 0x7F, 0x01 + .byte 0x81, 0x04 + .byte 0x40, 0x50 + + .balign 4 +exp_qoq_u: + .word 0x0000279e, 0x000029db, 0x0000371f, 0x00003bf7 + .word 0x00000648, 0x000004b5, 0x00000826, 0x0000091f + .word 0x00007be0, 0x00002030, 0x000074f0, 0x000042f0 + .word 0x0000433c, 0x000040f1, 0x0000819f, 0x000002cf +exp_qoq_s: + .word 0xffffde9e, 0xffffd9db, 0xffffcd1f, 0xffffcbf7 + .word 0x00000248, 0x000002b5, 0x00000126, 0x0000051f + .word 0xffffebe0, 0x00002030, 0xffffd4f0, 0x000042f0 + .word 0x0000403c, 0xffffc1f1, 0x0000019f, 0x000001cf +exp_qoq_us: + .word 0x00001e9e, 0x000029db, 0x00002d1f, 0x00003bf7 + .word 0x00000348, 0x000004b5, 0x00000426, 0x0000091f + .word 0xffffebe0, 0x00002030, 0xffffd4f0, 0x000042f0 + .word 0xffffc03c, 0x000040f1, 0x0000009f, 0x000002cf +exp_qoq_su: + .word 0xffffe79e, 0xffffd9db, 0xffffd71f, 0xffffcbf7 + .word 0x00000548, 0x000002b5, 0x00000526, 0x0000051f + .word 0x00007be0, 0x00002030, 0x000074f0, 0x000042f0 + .word 0xffffc33c, 0xffffc1f1, 0xffff829f, 0x000001cf +exp_dod_u: + .word 0x00002795, 0x00003155, 0x00004642, 0x0000c2c0 +exp_dod_s: + .word 0xffffde95, 0xffffd955, 0xffffc042, 0x000041c0 +exp_dod_us: + .word 0x00001e95, 0x00002955, 0xffffc342, 0x000041c0 +exp_dod_su: + .word 0xffffe795, 0xffffe155, 0x00004342, 0xffffc2c0 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:27 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Andrew Jones , Alistair Francis , Chao Liu , Sunil V L Subject: [PULL v2 35/50] target/riscv/cpu.c: remove 'bare' condition for .profile Date: Fri, 16 Oct 2026 11:02:22 +1000 Message-ID: <20261016010237.1102834-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113048022158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We want to configure other CPU types to use profiles as an alternative to adding every profile extension explicitly, i.e. a profile is nothing more than an extension bundle. This means that a vendor CPU can set .profile=3Drva23s64 while having the same handling as any other vendor CPU. Same thing with all other CPU types. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Sunil V L Message-ID: <20260928201107.2049458-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9e3d096802..658a8162dd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3166,7 +3166,6 @@ static void riscv_cpu_class_base_init(ObjectClass *c,= const void *data) mcc->def->bare |=3D def->bare; if (def->profile) { assert(profile_extends(def->profile, mcc->def->profile)); - assert(mcc->def->bare); mcc->def->profile =3D def->profile; } if (def->misa_mxl_max) { --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 15 Oct 2026 18:04:30 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Icenowy Zheng , Alistair Francis , Matheus Ferst , Chao Liu , Sunil V L , Andrew Jones Subject: [PULL v2 36/50] target/riscv: add riscv-server-ref CPU Date: Fri, 16 Oct 2026 11:02:23 +1000 Message-ID: <20261016010237.1102834-37-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113034118158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The harts requirements of RISC-V server platform [1] require RVA23 ISA profile support and others. We're going for a profile-based implementation, instead of a regular CPU that can inherit RVA23, to allow future CPUs to use it internally as a starting base for their own extension sets. There's also a new 'rvserver-ref-1.0' flag that can be used to set the extensions in the command line for other CPUs, which can be used for testing/debugging purposes. Note that for all intents and purposes "riscv-server-ref" is a regular CPU and no, we're not trying to set a precedent of calling the riscv server platform spec a profile. [1] defines in rule SEE_020 that we must support at least 11 debug triggers (4 for insn address, 4 for insn load/store, 1 for icount, one for int, one for excp). We're going for the minimum. If more triggers are needed users can set any trigger amount (N <=3D 1024) with: -cpu riscv-server-ref,num-triggers=3DN [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server= _platform_requirements.adoc Suggested-by: Icenowy Zheng Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Matheus Ferst Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Message-ID: <20260928201107.2049458-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 1a28f1369c..61234842e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -42,6 +42,7 @@ #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") +#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-= ref") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 658a8162dd..306be10d10 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2437,11 +2437,37 @@ static RISCVCPUProfile RVA23S64 =3D { } }; =20 +/* + * This riscv-server-ref entry isn't a profile per se but its + * CPU definition can be modelled as a profile that extends + * RVA23, with additional things on top of it, and allowing + * future CPUs to derive from it via + * ".profile =3D &RVServerRef1_0;". + */ +static RISCVCPUProfile RVServerRef1_0 =3D { + .s_parent =3D &RVA23S64, + .name =3D "riscv-server-ref-1.0", + .satp_mode =3D VM_1_10_SV48, + .priv_spec =3D PRIV_VERSION_1_13_0, + .ext_offsets =3D { + CPU_CFG_OFFSET(ext_zkr), + CPU_CFG_OFFSET(ext_sdext), + CPU_CFG_OFFSET(ext_sdtrig), + CPU_CFG_OFFSET(ext_ssaia), + CPU_CFG_OFFSET(ext_ssccfg), + /* ssstrict is always enabled for PRIV_VER_1_12+ */ + + RISCV_PROFILE_EXT_LIST_END + } +}; + + RISCVCPUProfile *riscv_profiles[] =3D { &RVA22U64, &RVA22S64, &RVA23U64, &RVA23S64, + &RVServerRef1_0, NULL, }; =20 @@ -3829,6 +3855,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU, + .profile =3D &RVServerRef1_0, + .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 6), + .num_triggers =3D 11, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode =3D VM_1_10_SV57, --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:34 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Nutty Liu , Chao Liu , Sunil V L , Andrew Jones , Alistair Francis Subject: [PULL v2 37/50] hw/riscv: server platform reference machine Date: Fri, 16 Oct 2026 11:02:24 +1000 Message-ID: <20261016010237.1102834-38-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113054193158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The RISC-V Server Platform specification [1] defines a standardized set of hardware and software capabilities, that portable system software, such as OS and hypervisors can rely on being present in a RISC-V server platform. The main features included in this emulation are: - Based on riscv virt machine type; - A new memory map as close as virt machine as possible; - An always present IOMMU platform device (riscv-iommu-sys) that uses IRQs 36 to 39, one IRQ for queue, similar to the 'virt' board; - AIA; - No default AHCI (can be added via command line); - No default NIC (can be added via command line); - No virtio device; - No fw_cfg device; - No ACPI table provided; - Only minimal device tree nodes; - a platform bus for TPM support. A note about TPM support: TPM devices in QEMU comes usually in two flavors - emulated or passthrough. A passthrough device requires a host TPM device that the QEMU process can borrow and it's usually coupled with KVM acceleration. To use the TPM emulator we'll need help from an external TPM emulator called swtpm. More info can be found in [2]. For our purposes this is a process that, if running Ubuntu, can be installed via 'swtpm' package. We'll go back to it shortly. For now, adding support for the emulated TPM device 'tpm-tis' (other TPM flavors might work as well, 'tpm-tis' is the one tested with this work) requires a platform bus. Adding a platform bus will open the door for more devices to be added in the board. This is ok - a reference board isn't a restricted board and users are free to add devices at their leisure. Here's how to use tpm-tis with the riscv-server-ref board: - in a separated shell/term run 'swtpm' (--log is optional): $ mkdir /tmp/mytpm1 $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ --tpm2 \ --log level=3D20 Then start QEMU with: $ qemu-system-riscv64 -M riscv-server-ref (...) \ -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm\ -device tpm-tis-device,tpmdev=3Dtpm0 [1] https://github.com/riscv-non-isa/riscv-server-platform [2] https://qemu-project.gitlab.io/qemu/specs/tpm.html Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Acked-by: Alistair Francis Message-ID: <20260928201107.2049458-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- configs/devices/riscv64-softmmu/default.mak | 1 + hw/riscv/server_platform_ref.c | 776 ++++++++++++++++++++ hw/riscv/Kconfig | 17 + hw/riscv/meson.build | 1 + 4 files changed, 795 insertions(+) create mode 100644 hw/riscv/server_platform_ref.c diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/= riscv64-softmmu/default.mak index 2ba91b14d4..cb4397de0b 100644 --- a/configs/devices/riscv64-softmmu/default.mak +++ b/configs/devices/riscv64-softmmu/default.mak @@ -9,6 +9,7 @@ # CONFIG_SIFIVE_E=3Dn # CONFIG_SIFIVE_U=3Dn # CONFIG_RISCV_VIRT=3Dn +# CONFIG_RISCV_SERVER_PLATFORM_REF=3Dn # CONFIG_MICROCHIP_PFSOC=3Dn # CONFIG_SHAKTI_C=3Dn # CONFIG_XIANGSHAN_KUNMINGHU=3Dn diff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c new file mode 100644 index 0000000000..5f485b1c79 --- /dev/null +++ b/hw/riscv/server_platform_ref.c @@ -0,0 +1,776 @@ +/* + * QEMU RISC-V Server Platform Reference Board (riscv-server-ref) + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" +#include "hw/core/boards.h" +#include "hw/core/platform-bus.h" +#include "hw/core/loader.h" +#include "hw/core/sysbus.h" +#include "hw/core/qdev-properties.h" +#include "hw/char/serial.h" +#include "hw/block/flash.h" +#include "hw/ide/pci.h" +#include "hw/ide/ahci-pci.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" +#include "hw/core/sysbus-fdt.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/boot.h" +#include "hw/riscv/device-common.h" +#include "hw/riscv/fdt-common.h" +#include "hw/riscv/numa.h" +#include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" +#include "hw/intc/riscv_aclint.h" +#include "hw/intc/riscv_aplic.h" +#include "hw/intc/riscv_imsic.h" +#include "chardev/char.h" +#include "hw/char/serial-mm.h" +#include "system/device_tree.h" +#include "system/runstate.h" +#include "system/system.h" +#include "system/kvm.h" +#include "system/qtest.h" +#include "system/tcg.h" +#include "kvm/kvm_riscv.h" +#include "system/tpm.h" +#include "target/riscv/cpu.h" +#include "net/net.h" + +#include "aia.h" + +#define RVSERVER_ACLINT_TIMEBASE_FREQ 1000000000 /* 1Ghz */ +#define RVSERVER_CPUS_MAX_BITS 9 +#define RVSERVER_CPUS_MAX (1 << RVSERVER_CPUS_MAX_BIT= S) +#define RVSERVER_IRQCHIP_NUM_MSIS 255 +#define RVSERVER_IRQCHIP_NUM_SOURCES 96 +#define RVSERVER_IRQCHIP_NUM_PRIO_BITS 3 +#define RVSERVER_IRQCHIP_DEFAULT_AIA_GUESTS 5 +#define RVSERVER_IRQCHIP_MAX_GUESTS_BITS 3 +#define RVSERVER_IRQCHIP_MAX_GUESTS \ + ((1U << RVSERVER_IRQCHIP_MAX_GUESTS_BITS) - 1U) +#define RVSERVER_SOCKETS_MAX_BITS 2 +#define RVSERVER_SOCKETS_MAX (1 << RVSERVER_SOCKETS_MAX_= BITS) + +#define SYSCON_RESET 0x1 +#define SYSCON_POWEROFF 0x2 + +#define RVSERVER_PLATFORM_BUS_NUM_IRQS 8 + +#define TYPE_RISCV_SERVER_REF_MACHINE MACHINE_TYPE_NAME("riscv-server-ref") +OBJECT_DECLARE_SIMPLE_TYPE(RISCVServerRefMachineState, RISCV_SERVER_REF_MA= CHINE) + +struct RISCVServerRefMachineState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + RISCVHartArrayState soc[RVSERVER_SOCKETS_MAX]; + DeviceState *irqchip[RVSERVER_SOCKETS_MAX]; + PFlashCFI01 *flash[2]; + + int fdt_size; + int aia_guests; + const MemMapEntry *memmap; + + DeviceState *platform_bus_dev; +}; + +enum { + RVSERVER_MROM, + RVSERVER_RESET_SYSCON, + RVSERVER_RTC, + RVSERVER_IOMMU_SYS, + RVSERVER_ACLINT, + RVSERVER_APLIC_M, + RVSERVER_APLIC_S, + RVSERVER_UART0, + RVSERVER_IMSIC_M, + RVSERVER_IMSIC_S, + RVSERVER_FLASH, + RVSERVER_DRAM, + RVSERVER_PCIE_MMIO, + RVSERVER_PCIE_PIO, + RVSERVER_PLATFORM_BUS, + RVSERVER_PCIE_ECAM, + RVSERVER_PCIE_MMIO_HIGH +}; + +enum { + RVSERVER_UART0_IRQ =3D 10, + RVSERVER_RTC_IRQ =3D 11, + RVSERVER_PCIE_IRQ =3D 32, /* 32 to 35 */ + IOMMU_SYS_IRQ =3D 36, /* 36 to 39 */ + RVSERVER_PLATFORM_BUS_IRQ =3D 40, /* 40 to 47 */ +}; + +/* + * The server soc reference machine physical address space used by some of= the + * devices namely ACLINT, APLIC and IMSIC depend on number of Sockets, num= ber + * of CPUs, and number of IMSIC guest files. + * + * Various limits defined by RVSERVER_SOCKETS_MAX_BITS, RVSERVER_CPUS_MAX_= BITS, + * and RVSERVER_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization = of + * server reference machine physical address space. + */ + +#define RVSERVER_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHI= FT) +#if RVSERVER_IMSIC_GROUP_MAX_SIZE < \ + IMSIC_GROUP_SIZE(RVSERVER_CPUS_MAX_BITS, RVSERVER_IRQCHIP_MAX_GUESTS_B= ITS) +#error "Can't accommodate single IMSIC group in address space" +#endif + +#define RVSERVER_IMSIC_MAX_SIZE \ + (RVSERVER_SOCKETS_MAX * RVSERVER_IMSIC_GROUP_MAX_SIZE) +#if 0x4000000 < RVSERVER_IMSIC_MAX_SIZE +#error "Can't accommodate all IMSIC groups in address space" +#endif + +static const MemMapEntry rvserver_ref_memmap[] =3D { + [RVSERVER_MROM] =3D { 0x1000, 0xf000 }, + [RVSERVER_RESET_SYSCON] =3D { 0x100000, 0x1000 }, + [RVSERVER_RTC] =3D { 0x101000, 0x1000 }, + [RVSERVER_IOMMU_SYS] =3D { 0x102000, 0x1000 }, + [RVSERVER_ACLINT] =3D { 0x2000000, 0x10000 }, + [RVSERVER_PCIE_PIO] =3D { 0x3000000, 0x10000 }, + [RVSERVER_PLATFORM_BUS] =3D { 0x4000000, 0x2000000 }, + [RVSERVER_APLIC_M] =3D { 0xc000000, APLIC_SIZE(RVSERVER_CPUS_M= AX) }, + [RVSERVER_APLIC_S] =3D { 0xd000000, APLIC_SIZE(RVSERVER_CPUS_M= AX) }, + [RVSERVER_UART0] =3D { 0x10000000, 0x100 }, + [RVSERVER_FLASH] =3D { 0x20000000, 0x4000000 }, + [RVSERVER_IMSIC_M] =3D { 0x24000000, RVSERVER_IMSIC_MAX_SIZE }, + [RVSERVER_IMSIC_S] =3D { 0x28000000, RVSERVER_IMSIC_MAX_SIZE }, + [RVSERVER_PCIE_ECAM] =3D { 0x30000000, 0x10000000 }, + [RVSERVER_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, + [RVSERVER_DRAM] =3D { 0x80000000, 0xff80000000ull }, + [RVSERVER_PCIE_MMIO_HIGH] =3D { 0x10000000000ull, 0x10000000000ull }, +}; + +#define RVSERVER_FLASH_SECTOR_SIZE (256 * KiB) + +static void rvserver_flash_maps(RISCVServerRefMachineState *s, + MemoryRegion *sysmem) +{ + hwaddr flashsize =3D rvserver_ref_memmap[RVSERVER_FLASH].size / 2; + hwaddr flashbase =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + + riscv_init_flash_map(s->flash[0], flashbase, flashsize, + sysmem, RVSERVER_FLASH_SECTOR_SIZE); + riscv_init_flash_map(s->flash[1], flashbase + flashsize, flashsize, + sysmem, RVSERVER_FLASH_SECTOR_SIZE); +} + +static void create_fdt_pmu(RISCVServerRefMachineState *s) +{ + g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); + MachineState *ms =3D MACHINE(s); + RISCVCPU *hart =3D &s->soc[0].harts[0]; + + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart->pmu_avail_ctrs, pmu_name); +} + +static void create_fdt_sockets(RISCVServerRefMachineState *s, + const MemMapEntry *memmap, + uint32_t *phandle, + uint32_t *irq_mmio_phandle, + uint32_t *irq_pcie_phandle, + uint32_t *msi_pcie_phandle) +{ + int socket, phandle_pos; + MachineState *ms =3D MACHINE(s); + uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; + uint32_t xplic_phandles[MAX_NODES]; + g_autofree uint32_t *intc_phandles =3D NULL; + int socket_count =3D riscv_socket_count(ms); + bool numa_enabled =3D riscv_numa_enabled(ms); + bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); + IMSICFdtProps imsic_fdt_props; + APLICFdtProps aplic_fdt_props; + ACLINTFdtProps aclint_props; + + riscv_fdt_create_cpu_socket_subnode(ms->fdt, + kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) + : RVSERVER_ACLINT_TIMEBASE_FREQ); + + intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + + aclint_props.clint =3D &memmap[RVSERVER_ACLINT]; + aclint_props.aia_type =3D AIA_TYPE_APLIC_IMSIC; + aclint_props.numa_enabled =3D numa_enabled; + + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + hwaddr memaddr =3D s->memmap[RVSERVER_DRAM].base + + riscv_socket_mem_offset(ms, socket); + uint64_t memsize =3D riscv_socket_mem_size(ms, socket); + + phandle_pos -=3D s->soc[socket].num_harts; + + riscv_create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, so= cket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + phandle, &intc_phandles[phandle_pos], + numa_enabled, is_32_bit); + + riscv_create_fdt_socket_memory(ms->fdt, memaddr, memsize, + socket, riscv_numa_enabled(ms)); + + aclint_props.socket =3D socket; + aclint_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aclint(ms->fdt, &aclint_props, + &intc_phandles[phandle_pos]); + } + + imsic_fdt_props.soc =3D &s->soc; + imsic_fdt_props.socket_count =3D socket_count; + imsic_fdt_props.smp_cpus =3D ms->smp.cpus; + imsic_fdt_props.imsic_m_base =3D memmap[RVSERVER_IMSIC_M].base; + imsic_fdt_props.imsic_s_base =3D memmap[RVSERVER_IMSIC_S].base; + imsic_fdt_props.imsic_group_max_size =3D RVSERVER_IMSIC_GROUP_MAX_SIZE; + imsic_fdt_props.irqchip_num_msis =3D RVSERVER_IRQCHIP_NUM_MSIS; + imsic_fdt_props.aia_guests =3D s->aia_guests; + + riscv_create_fdt_imsic(ms->fdt, &imsic_fdt_props, phandle, intc_phandl= es, + &msi_m_phandle, &msi_s_phandle); + *msi_pcie_phandle =3D msi_s_phandle; + + aplic_fdt_props.aplic_m =3D !kvm_enabled() + ? &memmap[RVSERVER_APLIC_M] : NULL; + aplic_fdt_props.aplic_s =3D &memmap[RVSERVER_APLIC_S]; + aplic_fdt_props.platform_bus =3D &memmap[RVSERVER_PLATFORM_BUS]; + aplic_fdt_props.platform_bus_irq =3D RVSERVER_PLATFORM_BUS_IRQ; + aplic_fdt_props.num_harts =3D ms->smp.cpus; + aplic_fdt_props.numa_enabled =3D numa_enabled; + aplic_fdt_props.irqchip_num_sources =3D RVSERVER_IRQCHIP_NUM_SOURCES; + aplic_fdt_props.aia_type =3D AIA_TYPE_APLIC_IMSIC; + + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + phandle_pos -=3D s->soc[socket].num_harts; + + aplic_fdt_props.socket =3D socket; + aplic_fdt_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aplic(ms->fdt, &aplic_fdt_props, + msi_m_phandle, msi_s_phandle, phandl= e, + &intc_phandles[phandle_pos], + xplic_phandles); + } + + for (socket =3D 0; socket < socket_count; socket++) { + if (socket =3D=3D 0) { + *irq_mmio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 1) { + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + } + + riscv_socket_fdt_write_distance_matrix(ms); +} + +static void finalize_fdt(RISCVServerRefMachineState *s) +{ + uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; + uint32_t irq_pcie_phandle =3D 1, iommu_sys_phandle; + g_autofree char *name =3D NULL; + MachineState *ms =3D MACHINE(s); + + create_fdt_sockets(s, rvserver_ref_memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &msi_pcie_phandle); + + iommu_sys_phandle =3D riscv_create_fdt_riscv_iommu_sys(ms->fdt, + s->memmap[RVSERVER_IOMMU_SYS].bas= e, + s->memmap[RVSERVER_IOMMU_SYS].siz= e, + &phandle, irq_mmio_phandle, + msi_pcie_phandle, IOMMU_SYS_IRQ); + + riscv_create_fdt_pcie(ms->fdt, AIA_TYPE_APLIC_IMSIC, true, + &s->memmap[RVSERVER_PCIE_ECAM], + &s->memmap[RVSERVER_PCIE_PIO], + &s->memmap[RVSERVER_PCIE_MMIO], + &s->memmap[RVSERVER_PCIE_MMIO_HIGH], + irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle, RVSERVER_PCIE_IRQ); + + riscv_create_fdt_syscon(ms->fdt, &phandle, + rvserver_ref_memmap[RVSERVER_RESET_SYSCON].bas= e, + rvserver_ref_memmap[RVSERVER_RESET_SYSCON].siz= e, + SYSCON_RESET, SYSCON_POWEROFF, false); + + riscv_create_fdt_uart(ms->fdt, &rvserver_ref_memmap[RVSERVER_UART0], + RVSERVER_UART0_IRQ, AIA_TYPE_APLIC_IMSIC, + irq_mmio_phandle); + name =3D riscv_fdt_get_uart_nodename(rvserver_ref_memmap[RVSERVER_UART= 0].base); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); + + riscv_create_fdt_rtc(ms->fdt, &rvserver_ref_memmap[RVSERVER_RTC], + RVSERVER_RTC_IRQ, AIA_TYPE_APLIC_IMSIC, + irq_mmio_phandle); +} + +static void create_fdt(RISCVServerRefMachineState *s, + const MemMapEntry *memmap) +{ + MachineState *ms =3D MACHINE(s); + uint8_t rng_seed[32]; + g_autofree char *name =3D NULL; + + ms->fdt =3D riscv_create_board_device_tree(MACHINE_GET_CLASS(s)->desc, + "qemu,riscv-server-ref", + &s->fdt_size); + + /* + * This versioning scheme is for informing platform fw only. It is nei= ther: + * - A QEMU versioned machine type; a given version of QEMU will emula= te + * a given version of the platform. + * - A reflection of level of server platform support provided. + * + * machine-version-major: updated when changes breaking fw compatibili= ty + * are introduced. + * machine-version-minor: updated when features are added that don't b= reak + * fw compatibility. + * + * It's the same as the scheme in arm sbsa-ref. + */ + qemu_fdt_setprop_cell(ms->fdt, "/", "machine-version-major", 0); + qemu_fdt_setprop_cell(ms->fdt, "/", "machine-version-minor", 0); + + /* + * The "/soc/pci@..." node is needed for PCIE hotplugs + * that might happen before finalize_fdt(). + */ + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[RVSERVER_PCIE_ECAM].base); + qemu_fdt_add_subnode(ms->fdt, name); + + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_add_subnode(ms->fdt, "/aliases"); + + /* Pass seed to RNG */ + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); + + riscv_create_fdt_flash(ms->fdt, rvserver_ref_memmap[RVSERVER_FLASH].ba= se, + rvserver_ref_memmap[RVSERVER_FLASH].size / 2); + create_fdt_pmu(s); + +} + +static uint64_t rvserver_reset_syscon_read(void *opaque, hwaddr addr, + unsigned size) +{ + return 0; +} + +static void rvserver_reset_syscon_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + switch (val64) { + case SYSCON_POWEROFF: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + return; + case SYSCON_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + default: + break; + } +} + +static const MemoryRegionOps rvserver_reset_syscon_ops =3D { + .read =3D rvserver_reset_syscon_read, + .write =3D rvserver_reset_syscon_write, + .endianness =3D DEVICE_LITTLE_ENDIAN +}; + +static void rvserver_ref_machine_done(Notifier *notifier, void *data) +{ + RISCVServerRefMachineState *s =3D container_of( + notifier, RISCVServerRefMachineState, machine_done); + const MemMapEntry *memmap =3D rvserver_ref_memmap; + MachineState *machine =3D MACHINE(s); + hwaddr start_addr =3D memmap[RVSERVER_DRAM].base; + target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); + uint64_t fdt_load_addr; + uint64_t kernel_entry =3D 0; + BlockBackend *pflash_blk0; + RISCVBootInfo boot_info; + + /* + * An user provided dtb must include everything, including + * dynamic sysbus devices. Our FDT needs to be finalized. + */ + if (machine->dtb =3D=3D NULL) { + finalize_fdt(s); + } + + riscv_boot_info_init(&boot_info, &s->soc[0]); + + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, + &start_addr, NULL); + + pflash_blk0 =3D pflash_cfi01_get_blk(s->flash[0]); + if (pflash_blk0) { + if (machine->firmware && !strcmp(machine->firmware, "none")) { + /* + * Pflash was supplied but bios is none and not KVM guest, + * let's overwrite the address we jump to after reset to + * the base of the flash. + */ + start_addr =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + } else { + /* + * Pflash was supplied but either KVM guest or bios is not non= e. + * In this case, base of the flash would contain S-mode payloa= d. + */ + riscv_setup_firmware_boot(machine); + kernel_entry =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + } + } + + if (machine->kernel_filename && !kernel_entry) { + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, + firmware_end_addr= ); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NU= LL); + kernel_entry =3D boot_info.image_low_addr; + } + + fdt_load_addr =3D riscv_compute_fdt_addr(memmap[RVSERVER_DRAM].base, + memmap[RVSERVER_DRAM].size, + machine, &boot_info); + + riscv_load_fdt(fdt_load_addr, machine->fdt); + + /* load the reset vector */ + riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, + rvserver_ref_memmap[RVSERVER_MROM].base, + rvserver_ref_memmap[RVSERVER_MROM].size, + kernel_entry, + fdt_load_addr); +} + +static bool rvserver_aclint_allowed(void) +{ + return tcg_enabled() || qtest_enabled(); +} + +static void rvserver_ref_machine_init(MachineState *machine) +{ + const MemMapEntry *memmap =3D rvserver_ref_memmap; + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(machine); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *reset_syscon_io =3D g_new(MemoryRegion, 1); + DeviceState *mmio_irqchip, *pcie_irqchip; + int i, base_hartid, hart_count; + int socket_count =3D riscv_socket_count(machine); + int imsic_bits; + + /* Check socket count limit */ + if (RVSERVER_SOCKETS_MAX < socket_count) { + error_report("number of sockets/nodes should be less than %d", + RVSERVER_SOCKETS_MAX); + exit(1); + } + + if (!rvserver_aclint_allowed()) { + error_report("'aclint' is only available with TCG acceleration"); + exit(1); + } + + s->memmap =3D rvserver_ref_memmap; + + /* + * We can't set aia_guests with 'qtest' because it'll skip the + * TCG exclusive init code, setting a blank CPU without RVH + * (among other things). If aia_guests is not zero we'll + * enter riscv_imsic_reset_enter(), which will reset its + * external irqs via qemu_irq_lower(), and qtest will hit an + * assert in riscv_cpu_set_irq() because we don't have RVH + * for handling guest local interrupts. + * + * qtest just want to inspect realized devices using QOM and + * HMP, so do not set aia_guests in that case. + */ + if (qtest_enabled()) { + s->aia_guests =3D 0; + } + + imsic_bits =3D imsic_num_bits(s->aia_guests + 1); + + /* Initialize sockets */ + mmio_irqchip =3D pcie_irqchip =3D NULL; + for (i =3D 0; i < socket_count; i++) { + g_autofree char *soc_name =3D g_strdup_printf("soc%d", i); + + if (!riscv_socket_check_hartids(machine, i)) { + error_report("discontinuous hartids in socket%d", i); + exit(1); + } + + base_hartid =3D riscv_socket_first_hartid(machine, i); + if (base_hartid < 0) { + error_report("can't find hartid base for socket%d", i); + exit(1); + } + + hart_count =3D riscv_socket_hart_count(machine, i); + if (hart_count < 0) { + error_report("can't find hart count for socket%d", i); + exit(1); + } + + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + TYPE_RISCV_HART_ARRAY); + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", + machine->cpu_type, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", + base_hartid, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + hart_count, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); + + /* Per-socket ACLINT MTIMER */ + riscv_aclint_mtimer_create(system_memory, + memmap[RVSERVER_ACLINT].base + i * RISCV_ACLINT_DEFAULT_MT= IMER_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + base_hartid, hart_count, + RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + + /* Per-socket interrupt controller */ + s->irqchip[i] =3D riscv_create_aia(system_memory, true, s->aia_gue= sts, + IMSIC_HART_SIZE(0), + IMSIC_HART_SIZE(imsic_bits), + RVSERVER_IRQCHIP_NUM_SOURCES, + &s->memmap[RVSERVER_APLIC_M], + &s->memmap[RVSERVER_APLIC_S], + &s->memmap[RVSERVER_IMSIC_M], + &s->memmap[RVSERVER_IMSIC_S], + i, base_hartid, hart_count, + RVSERVER_IRQCHIP_NUM_MSIS, + RVSERVER_IRQCHIP_NUM_PRIO_BITS); + + /* Try to use different IRQCHIP instance based device type */ + if (i =3D=3D 0) { + mmio_irqchip =3D s->irqchip[i]; + pcie_irqchip =3D s->irqchip[i]; + } + if (i =3D=3D 1) { + pcie_irqchip =3D s->irqchip[i]; + } + } + + /* register system main memory (actual RAM) */ + memory_region_add_subregion(system_memory, memmap[RVSERVER_DRAM].base, + machine->ram); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv_rvserver_ref_board.mrom", + memmap[RVSERVER_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[RVSERVER_MROM].base, + mask_rom); + + memory_region_init_io(reset_syscon_io, NULL, &rvserver_reset_syscon_op= s, + NULL, "reset_syscon_io", + memmap[RVSERVER_RESET_SYSCON].size); + memory_region_add_subregion(system_memory, + memmap[RVSERVER_RESET_SYSCON].base, + reset_syscon_io); + + riscv_gpex_pcie_init(system_memory, pcie_irqchip, + &rvserver_ref_memmap[RVSERVER_PCIE_ECAM], + &rvserver_ref_memmap[RVSERVER_PCIE_MMIO], + &rvserver_ref_memmap[RVSERVER_PCIE_MMIO_HIGH], + &rvserver_ref_memmap[RVSERVER_PCIE_PIO], + RVSERVER_PCIE_IRQ); + + s->platform_bus_dev =3D riscv_create_platform_bus(mmio_irqchip, + &s->memmap[RVSERVER_PL= ATFORM_BUS], + RVSERVER_PLATFORM_BUS_= IRQ, + RVSERVER_PLATFORM_BUS_= NUM_IRQS); + + serial_mm_init(system_memory, memmap[RVSERVER_UART0].base, + 0, qdev_get_gpio_in(mmio_irqchip, RVSERVER_UART0_IRQ), 399193, + serial_hd(0), DEVICE_LITTLE_ENDIAN); + + sysbus_create_simple("goldfish_rtc", memmap[RVSERVER_RTC].base, + qdev_get_gpio_in(mmio_irqchip, RVSERVER_RTC_IRQ)); + + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + /* Map legacy -drive if=3Dpflash to machine properties */ + pflash_cfi01_legacy_drive(s->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + rvserver_flash_maps(s, system_memory); + + /* load/create device tree */ + if (machine->dtb) { + machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); + if (!machine->fdt) { + error_report("load_device_tree() failed"); + exit(1); + } + } else { + create_fdt(s, memmap); + } + + riscv_create_iommu_sys(mmio_irqchip, s->memmap[RVSERVER_IOMMU_SYS].bas= e, + IOMMU_SYS_IRQ, false); + + s->machine_done.notify =3D rvserver_ref_machine_done; + qemu_add_machine_init_done_notifier(&s->machine_done); +} + +static void rvserver_ref_machine_instance_init(Object *obj) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + s->flash[0] =3D riscv_flash_create(OBJECT(s), "riscv-server-ref.flash0= ", + "pflash0", RVSERVER_FLASH_SECTOR_SIZE= ); + s->flash[1] =3D riscv_flash_create(OBJECT(s), "riscv-server-ref.flash1= ", + "pflash1", RVSERVER_FLASH_SECTOR_SIZE= ); + + s->aia_guests =3D RVSERVER_IRQCHIP_DEFAULT_AIA_GUESTS; +} + +static void rvserver_ref_machine_instance_finalize(Object *obj) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + for (int i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + if (s->flash[i] && !qdev_is_realized(DEVICE(s->flash[i]))) { + object_unref(OBJECT(s->flash[i])); + } + } +} + +static char *rvserver_ref_get_aia_guests(Object *obj, Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + char val[32]; + + sprintf(val, "%d", s->aia_guests); + return g_strdup(val); +} + +static void rvserver_ref_set_aia_guests(Object *obj, const char *val, + Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + s->aia_guests =3D atoi(val); + if (s->aia_guests < 0 || s->aia_guests > RVSERVER_IRQCHIP_MAX_GUESTS) { + error_setg(errp, "Invalid number of AIA IMSIC guests"); + error_append_hint(errp, "Valid values be between 0 and %d.\n", + RVSERVER_IRQCHIP_MAX_GUESTS); + } +} + +static const HotplugHandler * +rvserver_machine_get_hotplug_handler(MachineState *ms, DeviceState *dev) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + if (device_is_dynamic_sysbus(mc, dev)) { + return HOTPLUG_HANDLER(ms); + } + + return NULL; +} + +static void rvserver_machine_device_plug_cb(const HotplugHandler *hotplug_= dev, + DeviceState *dev, Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(hotplug_dev= ); + + if (s->platform_bus_dev) { + MachineClass *mc =3D MACHINE_GET_CLASS(s); + + if (device_is_dynamic_sysbus(mc, dev)) { + platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_d= ev), + SYS_BUS_DEVICE(dev)); + } + } +} + +static void rvserver_ref_machine_class_init(ObjectClass *oc, const void *d= ata) +{ + char str[128]; + MachineClass *mc =3D MACHINE_CLASS(oc); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + TYPE_RISCV_CPU_RVSERVER_REF, + NULL + }; + + /* Note: this is used as /model in the FDT. */ + mc->desc =3D "RISC-V Server Platform Reference Board v1.0"; + mc->init =3D rvserver_ref_machine_init; + mc->max_cpus =3D RVSERVER_CPUS_MAX; + mc->default_cpu_type =3D TYPE_RISCV_CPU_RVSERVER_REF; + mc->valid_cpu_types =3D valid_cpu_types; + mc->pci_allow_0_address =3D true; + mc->default_nic =3D "e1000e"; + mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; + mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; + mc->numa_mem_supported =3D true; + /* platform instead of architectural choice */ + mc->cpu_cluster_has_numa_boundary =3D true; + mc->default_ram_id =3D "riscv_rvserver_ref_board.ram"; + + object_class_property_add_str(oc, "aia-guests", + rvserver_ref_get_aia_guests, + rvserver_ref_set_aia_guests); + sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid valu= e " + "should be between 0 and %d.", RVSERVER_IRQCHIP_MAX_GUEST= S); + object_class_property_set_description(oc, "aia-guests", str); + + assert(!mc->get_hotplug_handler); + mc->get_hotplug_handler =3D rvserver_machine_get_hotplug_handler; + hc->plug =3D rvserver_machine_device_plug_cb; +#ifdef CONFIG_TPM + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); +#endif +} + +static const TypeInfo rvserver_ref_typeinfo =3D { + .name =3D TYPE_RISCV_SERVER_REF_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D rvserver_ref_machine_class_init, + .instance_init =3D rvserver_ref_machine_instance_init, + .instance_finalize =3D rvserver_ref_machine_instance_finalize, + .instance_size =3D sizeof(RISCVServerRefMachineState), + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + }, +}; + +static void rvserver_ref_init_register_types(void) +{ + type_register_static(&rvserver_ref_typeinfo); +} + +type_init(rvserver_ref_init_register_types) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 70a331f7ae..fb05031228 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -69,6 +69,23 @@ config RISCV_VIRT select ACPI select ACPI_PCI =20 +config RISCV_SERVER_PLATFORM_REF + bool + default y + depends on RISCV64 + imply TPM_TIS_SYSBUS + select GOLDFISH_RTC + select PCI_EXPRESS_GENERIC_BRIDGE + select PCIE_DEVICES + select PFLASH_CFI01 + select PLATFORM_BUS + select RISCV_ACLINT + select RISCV_APLIC + select RISCV_IMSIC + select RISCV_IOMMU + select RISCV_NUMA + select SERIAL_MM + config SHAKTI_C bool default y diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index a40e80645b..6bdabb9544 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -7,6 +7,7 @@ riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('num= a.c')) riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_RISCV_SERVER_PLATFORM_REF', if_true: files('ser= ver_platform_ref.c')) riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:37 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Chao Liu , Nutty Liu , Alistair Francis , Sunil V L Subject: [PULL v2 38/50] tests/functional/riscv64: add riscv-server-ref tests Date: Fri, 16 Oct 2026 11:02:25 +1000 Message-ID: <20261016010237.1102834-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112923582158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add tests for the recently added riscv-server-ref machine: - a new test_opensbi.py test. The idea is to have a quick test that can catch trivial regressions that would prevent OpenSBI to finish; - a new Linux boot "thorough" test that will boot the machine up to the buildroot prompt. - a TPM specific selftest for the riscv-server-ref board. The test will be skipped if there's no 'swtpm' in the host. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Reviewed-by: Nutty Liu Reviewed-by: Alistair Francis Reviewed-by: Sunil V L Message-ID: <20260928201107.2049458-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_server_ref.py | 90 +++++++++++++++++++++ 3 files changed, 96 insertions(+) create mode 100755 tests/functional/riscv64/test_server_ref.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index 8a4f1d00f9..211ea9acfc 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -3,6 +3,7 @@ test_riscv64_timeouts =3D { 'boston' : 120, 'k230' : 120, + 'server_ref' : 120, 'tuxrun' : 120, } =20 @@ -15,6 +16,7 @@ tests_riscv64_system_thorough =3D [ 'endianness', 'boston', 'k230', + 'server_ref', 'sifive_u', 'tt_atlantis', 'tuxrun', diff --git a/tests/functional/riscv64/test_opensbi.py b/tests/functional/ri= scv64/test_opensbi.py index 0f8beb7e7a..367e131164 100755 --- a/tests/functional/riscv64/test_opensbi.py +++ b/tests/functional/riscv64/test_opensbi.py @@ -36,5 +36,9 @@ def test_riscv_virt(self): self.set_machine('virt') self.boot_opensbi() =20 + def test_riscv_server_ref(self): + self.set_machine('riscv-server-ref') + self.boot_opensbi() + if __name__ =3D=3D '__main__': QemuSystemTest.main() diff --git a/tests/functional/riscv64/test_server_ref.py b/tests/functional= /riscv64/test_server_ref.py new file mode 100755 index 0000000000..ad29094dbe --- /dev/null +++ b/tests/functional/riscv64/test_server_ref.py @@ -0,0 +1,90 @@ +#!/usr/bin/env python3 +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +""" +riscv-server-ref board test +""" + +import os +import tempfile +import subprocess + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern +from qemu_test import skipIfMissingCommands + +class RiscvServerRefTest(QemuSystemTest): + """ + Test the riscv-server-ref board + """ + + ASSET_KERNEL =3D Asset( + ('https://github.com/danielhb/qemu-machine-boot/raw/refs/heads/' + 'master/riscv/images/virt64/buildroot/Image'), + '6bacc876c769c1bb6057d2bf549eba67fbe83916e8223f9fe21c8e8fff665a36') + + ASSET_ROOTFS =3D Asset( + ('https://github.com/danielhb/qemu-machine-boot/raw/refs/heads/' + 'master/riscv/images/virt64/buildroot/rootfs.ext2'), + 'f00bb88749f945d80675540a1338bd1ccb226574685a5b6c65ab44027d0411a8') + + def do_test_boot_linux_test(self, tpmstate_dir=3DNone): + self.set_machine('riscv-server-ref') + kernel_path =3D self.ASSET_KERNEL.fetch() + rootfs_path =3D self.ASSET_ROOTFS.fetch() + + self.vm.add_args('-kernel', kernel_path) + self.vm.add_args('-append', 'rw rootwait root=3D/dev/sda') + self.vm.add_args('-drive', + f'file=3D{rootfs_path},format=3Draw,id=3Dhd0,snapshot=3Don,if= =3Dnone') + self.vm.add_args('-device', 'ich9-ahci,id=3Dahci0') + self.vm.add_args('-device', 'ide-hd,drive=3Dhd0,bus=3Dahci0.0') + self.vm.add_args('-netdev', 'user,id=3Dnet0') + self.vm.add_args('-device', 'e1000e,netdev=3Dnet0') + + if tpmstate_dir is not None: + # Note: code taken verbatim from + # tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py + + # We must put the TPM state dir in /tmp/, not the build dir, + # because some distros use AppArmor to lock down swtpm and + # restrict the set of locations it can access files in. + socket =3D os.path.join(tpmstate_dir, 'swtpm-socket') + subprocess.run(['swtpm', 'socket', '-d', '--tpm2', + '--tpmstate', f'dir=3D{tpmstate_dir}', + '--ctrl', f'type=3Dunixio,path=3D{socket}'], + check=3DTrue) + self.vm.add_args('-chardev', f'socket,id=3Dchrtpm,path=3D{sock= et}') + self.vm.add_args('-tpmdev', 'emulator,id=3Dtpm0,chardev=3Dchrt= pm') + self.vm.add_args('-device', 'tpm-tis-device,tpmdev=3Dtpm0') + + self.vm.set_console() + self.vm.launch() + + # Wait for OpenSBI + wait_for_console_pattern(self, 'OpenSBI') + + # Wait for Linux kernel boot + wait_for_console_pattern(self, 'Linux version') + wait_for_console_pattern(self, 'Machine model: RISC-V Server Platf= orm') + + # Test e1000e network card functionality + wait_for_console_pattern(self, 'e1000e') + wait_for_console_pattern(self, 'Network Connection') + + # Wait for boot to complete - system reaches login prompt + wait_for_console_pattern(self, 'Run /sbin/init as init process') + + def test_boot_linux_test(self): + self.do_test_boot_linux_test() + + @skipIfMissingCommands('swtpm') + def test_boot_linux_test_tpm(self): + with tempfile.TemporaryDirectory(prefix=3D"qemu_") as tpmstate_dir: + self.do_test_boot_linux_test(tpmstate_dir) + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:41 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , Chao Liu , Sunil V L , Andrew Jones Subject: [PULL v2 39/50] docs: add riscv-server-ref.rst Date: Fri, 16 Oct 2026 11:02:26 +1000 Message-ID: <20261016010237.1102834-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113035789158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add documentation for the new riscv-server-ref board. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Message-ID: <20260928201107.2049458-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- docs/system/riscv/riscv-server-ref.rst | 65 ++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 2 files changed, 66 insertions(+) create mode 100644 docs/system/riscv/riscv-server-ref.rst diff --git a/docs/system/riscv/riscv-server-ref.rst b/docs/system/riscv/ris= cv-server-ref.rst new file mode 100644 index 0000000000..da043ed096 --- /dev/null +++ b/docs/system/riscv/riscv-server-ref.rst @@ -0,0 +1,65 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +RISC-V Server Platform Reference board (``riscv-server-ref``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The RISC-V Server Platform specification `spec`_ defines a standardized +set of hardware and software capabilities that portable system software, +such as OS and hypervisors, can rely on being present in a RISC-V server +platform. This machine aims to emulate this specification, providing +an environment for firmware/OS development and testing. + +`spec`_ is version 1.0 at the introduction of this board. For each new +supported spec version a new versioned board will be added, keeping +"riscv-server-ref" as an alias for the newest version supported. E.g. +for spec version 2.0: + +* riscv-server-ref-1.0 - board that complies with spec version 1.0 +* riscv-server-ref-2.0 - board that complies with spec version 2.0 +* riscv-server-ref - alias for riscv-server-ref-2.0 + +The main features included in the riscv-server-ref board are: + +* IOMMU platform device (riscv-iommu-sys) +* AIA +* No AHCI (can be added via command line) +* No NIC (can be added via command line) +* No virtio mmio bus +* No fw_cfg device +* No ACPI table +* Minimal device tree nodes + +There are multiple ways of using this reference board. The spec compliant= way +is using an EDK2 image and a TPM device. The board was tested with the TPM +device ``tpm-tis`` that uses the external ``swtpm`` emulator. More info o= n how +to use this device can be found in `tpm`_. + +To use this board coupled with the tpm-tis device, first start the ``swtpm= `` +process in a shell (the ``log`` parameter is optional): + +.. code-block:: bash + + $ mkdir /tmp/mytpm1 + $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ + --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ + --tpm2 \ + --log level=3D20 + +And then start QEMU with: + +.. code-block:: bash + + qemu-system-riscv64 -M riscv-server-ref \ + -bios fw_dynamic.bin \ + -kernel EDK2.fd \ + -drive file=3Dnvme_disk.ext2,format=3Draw,id=3Dhd0,if=3Dnone \ + -device nvme,drive=3Dhd0,serial=3Dddaaddaa \ + -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm \ + -device tpm-tis-device,tpmdev=3Dtpm0 \ + -netdev user,id=3Dnet0 -device e1000e,netdev=3Dnet0 \ + -nographic + + +.. _spec: https://github.com/riscv-non-isa/riscv-server-platform +.. _tpm: https://qemu-project.gitlab.io/qemu/specs/tpm.html diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 1e49055e29..cc0ef4b64f 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -71,6 +71,7 @@ undocumented; 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charset="utf-8" From: Alistair Francis This reverts commit 5089493e45d3be2bae9ffd2a22186f57b0cabe3f. Rick reported that this patch results in large slowdowns when using multiple threads. The original patch serialises all stores, resulting in all vCPUs stopping for every store, which would explain the slowdown. The results from Rick show xz compressing 2 MB at -6, without and with the patch: without patch with patch xz -T1 5 s 122 s (identical output) xz -T8 1 s no output after 600 s That is too large of an overhead, so let's revert this patch until a better solution is found. Reported-by: Rick Signed-off-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20261001232119.1765494-1-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- linux-user/riscv/target_cpu.h | 2 - target/riscv/cpu.h | 3 -- target/riscv/helper.h | 5 --- target/riscv/cpu.c | 3 -- target/riscv/tcg/op_helper.c | 35 ----------------- target/riscv/tcg/translate.c | 38 ------------------- target/riscv/tcg/insn_trans/trans_rva.c.inc | 24 ------------ target/riscv/tcg/insn_trans/trans_rvi.c.inc | 11 ------ .../riscv/tcg/insn_trans/trans_rvzawrs.c.inc | 3 -- 9 files changed, 124 deletions(-) diff --git a/linux-user/riscv/target_cpu.h b/linux-user/riscv/target_cpu.h index eff18b37ba..9c642367a3 100644 --- a/linux-user/riscv/target_cpu.h +++ b/linux-user/riscv/target_cpu.h @@ -9,8 +9,6 @@ static inline void cpu_clone_regs_child(CPURISCVState *env,= target_ulong newsp, } =20 env->gpr[xA0] =3D 0; - env->load_res =3D -1; - env->load_res_size =3D 0; } =20 static inline void cpu_clone_regs_parent(CPURISCVState *env, unsigned flag= s) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bbef354354..61dc25e209 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -264,9 +264,6 @@ struct CPUArchState { =20 uint64_t pc; uint64_t load_res; -#ifdef CONFIG_USER_ONLY - uint64_t load_res_size; -#endif uint64_t load_val; =20 /* Floating-Point state */ diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 0e22210377..372f104972 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1361,11 +1361,6 @@ DEF_HELPER_1(ssamoswap_disabled, void, env) /* Zalrsc SC write probe */ DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl) =20 -#ifdef CONFIG_USER_ONLY -/* Invalidate reservations overlapping a completed linux-user store. */ -DEF_HELPER_3(riscv_invalidate_reservations, void, env, tl, tl) -#endif - /* SiFive Custom int8 Matrix-Multiply */ DEF_HELPER_5(sf_vqmaccu_4x8x4, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(sf_vqmacc_4x8x4, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 306be10d10..4a92dfdee7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1094,9 +1094,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) env->xl =3D riscv_cpu_mxl(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; -#ifdef CONFIG_USER_ONLY - env->load_res_size =3D 0; -#endif set_default_nan_mode(1, &env->fp_status); /* Default NaN value: sign bit clear, frac msb set */ set_float_default_nan_pattern(0b01000000, &env->fp_status); diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index dc76055b80..b8b3e43ccd 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -19,9 +19,6 @@ */ =20 #include "qemu/osdep.h" -#ifdef CONFIG_USER_ONLY -#include "qemu/rcu.h" -#endif #include "cpu.h" #include "target/riscv/tcg/csr.h" #ifndef CONFIG_USER_ONLY @@ -301,38 +298,6 @@ void helper_sc_probe_write(CPURISCVState *env, target_= ulong addr, probe_write(env, addr, size, mmu_idx, ra); } =20 -#ifdef CONFIG_USER_ONLY - -void helper_riscv_invalidate_reservations(CPURISCVState *env, - target_ulong addr, - target_ulong size) -{ - CPUState *cpu; - - /* EXCP_ATOMIC keeps other guest harts out while this list is updated.= */ - WITH_RCU_READ_LOCK_GUARD() { - CPU_FOREACH(cpu) { - CPURISCVState *other_env =3D cpu_env(cpu); - target_ulong reservation =3D other_env->load_res; - target_ulong reservation_size =3D other_env->load_res_size; - bool overlap; - - if (other_env =3D=3D env || reservation =3D=3D (target_ulong)-= 1) { - continue; - } - overlap =3D reservation < addr - ? addr - reservation < reservation_size - : reservation - addr < size; - if (overlap) { - other_env->load_res =3D -1; - other_env->load_res_size =3D 0; - } - } - } -} - -#endif - #ifndef CONFIG_USER_ONLY =20 target_ulong helper_sret(CPURISCVState *env) diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index 470a5e71b2..ede9c2563f 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv_i32 cpu_vl, cpu_vstart; static TCGv load_res; -#ifdef CONFIG_USER_ONLY -static TCGv load_res_size; -#endif static TCGv load_val; =20 /* @@ -1153,34 +1150,10 @@ static bool gen_unary_per_ol(DisasContext *ctx, arg= _r2 *a, DisasExtend ext, return gen_unary(ctx, a, ext, f_tl); } =20 -#ifdef CONFIG_USER_ONLY -static bool gen_riscv_reservation_serialize(DisasContext *ctx) -{ - /* Keep the memory operation and reservation update in one guest step.= */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - return false; - } - return true; -} - -static void gen_riscv_invalidate_reservations(TCGv addr, MemOp mop) -{ - gen_helper_riscv_invalidate_reservations(tcg_env, addr, - tcg_constant_tl(memop_size(mo= p))); -} -#endif - static bool gen_amo(DisasContext *ctx, arg_atomic *a, void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), MemOp mop) { -#ifdef CONFIG_USER_ONLY - if (!gen_riscv_reservation_serialize(ctx)) { - return false; - } -#endif TCGv dest =3D dest_gpr(ctx, a->rd); TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); MemOp size =3D mop & MO_SIZE; @@ -1195,9 +1168,6 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); func(dest, src1, src2, ctx->mem_idx, mop); -#ifdef CONFIG_USER_ONLY - gen_riscv_invalidate_reservations(src1, mop); -#endif =20 gen_set_gpr(ctx, a->rd, dest); return true; @@ -1526,10 +1496,6 @@ void riscv_translate_init(void) size_t pc_offset =3D offsetof(CPURISCVState, pc) + field_offset; size_t res_offset =3D offsetof(CPURISCVState, load_res) + field_off= set; size_t val_offset =3D offsetof(CPURISCVState, load_val) + field_off= set; -#ifdef CONFIG_USER_ONLY - size_t res_size_offset =3D offsetof(CPURISCVState, load_res_size) - + field_offset; -#endif =20 for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, @@ -1549,9 +1515,5 @@ void riscv_translate_init(void) cpu_vl =3D tcg_global_mem_new_i32(tcg_env, vl_offset, "vl"); cpu_vstart =3D tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart"= ); load_res =3D tcg_global_mem_new(tcg_env, res_offset, "load_res"); -#ifdef CONFIG_USER_ONLY - load_res_size =3D tcg_global_mem_new(tcg_env, res_size_offset, - "load_res_size"); -#endif load_val =3D tcg_global_mem_new(tcg_env, val_offset, "load_val"); } diff --git a/target/riscv/tcg/insn_trans/trans_rva.c.inc b/target/riscv/tcg= /insn_trans/trans_rva.c.inc index 248a8c60d7..44c1696fe4 100644 --- a/target/riscv/tcg/insn_trans/trans_rva.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rva.c.inc @@ -32,11 +32,6 @@ =20 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { -#ifdef CONFIG_USER_ONLY - if (!gen_riscv_reservation_serialize(ctx)) { - return false; - } -#endif TCGv src1; =20 mop |=3D MO_ALIGN; @@ -58,9 +53,6 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemO= p mop) =20 /* Put addr in load_res, data in load_val. */ tcg_gen_mov_tl(load_res, src1); -#ifdef CONFIG_USER_ONLY - tcg_gen_movi_tl(load_res_size, memop_size(mop)); -#endif gen_set_gpr(ctx, a->rd, load_val); =20 return true; @@ -68,17 +60,9 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Mem= Op mop) =20 static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { -#ifdef CONFIG_USER_ONLY - if (!gen_riscv_reservation_serialize(ctx)) { - return false; - } -#endif TCGv dest, src1, src2; TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); -#ifdef CONFIG_USER_ONLY - TCGLabel *l3 =3D gen_new_label(); -#endif =20 mop |=3D MO_ALIGN; mop |=3D ctx->mo_endianness; @@ -95,11 +79,6 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, Mem= Op mop) src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2, ctx->mem_idx, mop); -#ifdef CONFIG_USER_ONLY - tcg_gen_brcond_tl(TCG_COND_NE, dest, load_val, l3); - gen_riscv_invalidate_reservations(src1, mop); - gen_set_label(l3); -#endif tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val); gen_set_gpr(ctx, a->rd, dest); tcg_gen_br(l2); @@ -125,9 +104,6 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, Me= mOp mop) * an SC to any address, in between an LR and SC pair. */ tcg_gen_movi_tl(load_res, -1); -#ifdef CONFIG_USER_ONLY - tcg_gen_movi_tl(load_res_size, 0); -#endif =20 return true; } diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index 40b4c9aa4a..cc1b5dbbad 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -489,9 +489,6 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, = MemOp memop) } =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); -#ifdef CONFIG_USER_ONLY - gen_riscv_invalidate_reservations(addr, memop); -#endif return true; } =20 @@ -521,19 +518,11 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb = *a, MemOp memop) } tcg_gen_qemu_st_i128(t16, addrl, ctx->mem_idx, memop); } -#ifdef CONFIG_USER_ONLY - gen_riscv_invalidate_reservations(addrl, memop); -#endif return true; } =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { -#ifdef CONFIG_USER_ONLY - if (!gen_riscv_reservation_serialize(ctx)) { - return false; - } -#endif memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; diff --git a/target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc b/target/riscv= /tcg/insn_trans/trans_rvzawrs.c.inc index 1831bbcfc0..0eef033838 100644 --- a/target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc @@ -32,9 +32,6 @@ static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto = *a) =20 /* Clear the load reservation (if any). */ tcg_gen_movi_tl(load_res, -1); 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Thu, 15 Oct 2026 18:04:47 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Rick Richard , Daniel Henrique Barboza , qemu-stable@nongnu.org, Alistair Francis Subject: [PULL v2 41/50] tests/qtest/bios-tables-test: Allow changes to riscv64 virt SPCR Date: Fri, 16 Oct 2026 11:02:28 +1000 Message-ID: <20261016010237.1102834-42-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113105106158500 Content-Type: text/plain; charset="utf-8" From: Rick Richard Allow changes to the riscv64 virt board SPCR -- we are going to fix an error in the UART description there. Signed-off-by: Rick Richard Reviewed-by: Daniel Henrique Barboza Message-ID: <20261005104008.214588-2-rick@sloservers.com> Cc: qemu-stable@nongnu.org Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..aae973048a 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/riscv64/virt/SPCR", --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1792112747; 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Thu, 15 Oct 2026 18:04:49 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Rick Richard , Daniel Henrique Barboza , qemu-stable@nongnu.org, Alistair Francis Subject: [PULL v2 42/50] hw/riscv/virt-acpi-build: Fix the UART register width in SPCR Date: Fri, 16 Oct 2026 11:02:29 +1000 Message-ID: <20261016010237.1102834-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112750022158500 Content-Type: text/plain; charset="utf-8" From: Rick Richard The riscv virt board uses a 16550 UART with an 8-bit register stride, but the SPCR table reports 32, which looks to have been copied from arm virt, whose PL011 has a 32-bit stride. Change it to the correct stride for a 16550. Fixes: 3e6f1e61b4 ("hw/riscv/virt-acpi-build.c: Generate SPCR table") Signed-off-by: Rick Richard Reviewed-by: Daniel Henrique Barboza Message-ID: <20261005104008.214588-3-rick@sloservers.com> Cc: qemu-stable@nongnu.org Signed-off-by: Alistair Francis --- hw/riscv/virt-acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 8e516ec114..0475dcb5c6 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -246,7 +246,7 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISC= VVirtState *s) AcpiSpcrData serial =3D { .interface_type =3D 0x12, /* 16550 compatible */ .base_addr.id =3D AML_AS_SYSTEM_MEMORY, - .base_addr.width =3D 32, + .base_addr.width =3D 8, .base_addr.offset =3D 0, .base_addr.size =3D 1, .base_addr.addr =3D s->memmap[VIRT_UART0].base, --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Thu, 15 Oct 2026 18:04:53 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Rick Richard , Daniel Henrique Barboza , qemu-stable@nongnu.org, Alistair Francis Subject: [PULL v2 43/50] tests/qtest/bios-tables-test: Update riscv64 virt SPCR golden reference Date: Fri, 16 Oct 2026 11:02:30 +1000 Message-ID: <20261016010237.1102834-44-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112954224158500 Content-Type: text/plain; charset="utf-8" From: Rick Richard Update the riscv64 virt SPCR golden reference file to have the fix for the UART register width. Diffs from iasl: @@ -1,58 +1,58 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20230628 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembly of tests/data/acpi/riscv64/virt/SPCR, Sat Oct 3 08:44:51 2= 026 * * ACPI Data Table [SPCR] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (i= n hex) */ [000h 0000 004h] Signature : "SPCR" [Serial Port Cons= ole Redirection Table] [004h 0004 004h] Table Length : 0000005A [008h 0008 001h] Revision : 04 -[009h 0009 001h] Checksum : 13 +[009h 0009 001h] Checksum : 2B [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 001h] Interface Type : 12 [025h 0037 003h] Reserved : 000000 [028h 0040 00Ch] Serial Port Register : [Generic Address Structure] [028h 0040 001h] Space ID : 00 [SystemMemory] -[029h 0041 001h] Bit Width : 20 +[029h 0041 001h] Bit Width : 08 [02Ah 0042 001h] Bit Offset : 00 [02Bh 0043 001h] Encoded Access Width : 01 [Byte Access:8] [02Ch 0044 008h] Address : 0000000010000000 [034h 0052 001h] Interrupt Type : 10 [035h 0053 001h] PCAT-compatible IRQ : 00 [036h 0054 004h] Interrupt : 0000000A [03Ah 0058 001h] Baud Rate : 07 [03Bh 0059 001h] Parity : 00 [03Ch 0060 001h] Stop Bits : 01 [03Dh 0061 001h] Flow Control : 00 [03Eh 0062 001h] Terminal Type : 03 [04Ch 0076 001h] Reserved : 00 [040h 0064 002h] PCI Device ID : FFFF [042h 0066 002h] PCI Vendor ID : FFFF [044h 0068 001h] PCI Bus : 00 [045h 0069 001h] PCI Device : 00 [046h 0070 001h] PCI Function : 00 [047h 0071 004h] PCI Flags : 00000000 [04Bh 0075 001h] PCI Segment : 00 [04Ch 0076 004h] Reserved : 00000000 Raw Table Data: Length 90 (0x5A) - 0000: 53 50 43 52 5A 00 00 00 04 13 42 4F 43 48 53 20 // SPCRZ.....BO= CHS + 0000: 53 50 43 52 5A 00 00 00 04 2B 42 4F 43 48 53 20 // SPCRZ....+BO= CHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....= BXPC - 0020: 01 00 00 00 12 00 00 00 00 20 00 01 00 00 00 10 // ......... ..= .... + 0020: 01 00 00 00 12 00 00 00 00 08 00 01 00 00 00 10 // ............= .... 0030: 00 00 00 00 10 00 0A 00 00 00 07 00 01 00 03 00 // ............= .... 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0050: 00 00 00 00 02 00 58 00 2E 00 // ......X... Signed-off-by: Rick Richard Reviewed-by: Daniel Henrique Barboza Message-ID: <20261005104008.214588-4-rick@sloservers.com> Cc: qemu-stable@nongnu.org Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/riscv64/virt/SPCR | Bin 90 -> 90 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index aae973048a..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/riscv64/virt/SPCR", diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/vi= rt/SPCR index 59d2c8f7f2..6003c230b1 100644 Binary files a/tests/data/acpi/riscv64/virt/SPCR and b/tests/data/acpi/risc= v64/virt/SPCR differ --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:04:55 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: dodochicha , qemu-stable@nongnu.org, Alistair Francis Subject: [PULL v2 44/50] target/riscv: Check Svnapot PTE before updating A/D bits Date: Fri, 16 Oct 2026 11:02:31 +1000 Message-ID: <20261016010237.1102834-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112807217158500 Content-Type: text/plain; charset="utf-8" From: dodochicha Reserved Svnapot PTE encodings must raise a page fault without modifying the PTE. Currently the A/D bits may be updated before the Svnapot encoding is validated. Move the Svnapot validation before the A/D update so reserved PTEs fault without changing the PTE. Cc: qemu-stable@nongnu.org Signed-off-by: dodochicha Message-ID: <20261005115916.21196-1-kevincheng60303@gmail.com> Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/tcg/cpu_helper.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index b22ecc2eeb..58e98e975c 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -1498,6 +1498,13 @@ static int get_physical_address(CPURISCVState *env, = hwaddr *physical, return sstack_page ? TRANSLATE_PMP_FAIL : TRANSLATE_FAIL; } =20 + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + napot_bits =3D ctzl(ppn) + 1; + if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { + return TRANSLATE_FAIL; + } + } + target_ulong updated_pte =3D pte; =20 /* @@ -1590,13 +1597,6 @@ static int get_physical_address(CPURISCVState *env, = hwaddr *physical, /* For superpage mappings, make a fake leaf PTE for the TLB's benefit.= */ target_ulong vpn =3D addr >> PGSHIFT; =20 - if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { - napot_bits =3D ctzl(ppn) + 1; - if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { - return TRANSLATE_FAIL; - } - } - napot_mask =3D (1 << napot_bits) - 1; *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | (vpn & (((target_ulong)1 << ptshift) - 1)) --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 15 Oct 2026 18:05:00 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Anirudh Srinivasan , Portia Stephens , Joel Stanley , Alistair Francis Subject: [PULL v2 45/50] hw/misc: Add Tenstorrent Atlantis PRCM model Date: Fri, 16 Oct 2026 11:02:32 +1000 Message-ID: <20261016010237.1102834-46-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112803169158500 Content-Type: text/plain; charset="utf-8" From: Anirudh Srinivasan This device present in Tenstorrent Atlantis has registers that control clocks, reset and other misc functionality in the SoC. This commit adds models for the RCPU, HSIO, PCIE, MM and 2 DDR PRCMs. Co-developed-by: Portia Stephens Signed-off-by: Portia Stephens Reviewed-by: Joel Stanley Signed-off-by: Anirudh Srinivasan Acked-by: Alistair Francis Message-ID: <20261001-atlantis_prcm-v4-1-95d33c470eeb@oss.tenstorrent.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 2 + include/hw/misc/tt_atlantis_prcm.h | 51 ++++ hw/misc/tt_atlantis_prcm.c | 428 +++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + 5 files changed, 486 insertions(+) create mode 100644 include/hw/misc/tt_atlantis_prcm.h create mode 100644 hw/misc/tt_atlantis_prcm.c diff --git a/MAINTAINERS b/MAINTAINERS index cceefb4cb9..0455e8e6b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1843,7 +1843,9 @@ R: Portia Stephens L: qemu-riscv@nongnu.org S: Supported F: docs/system/riscv/tt_*.rst +F: hw/misc/tt_*.c F: hw/riscv/tt_*.c +F: include/hw/misc/tt_*.h F: include/hw/riscv/tt_*.h F: tests/functional/riscv64/test_tt_*.py =20 diff --git a/include/hw/misc/tt_atlantis_prcm.h b/include/hw/misc/tt_atlant= is_prcm.h new file mode 100644 index 0000000000..4b72618346 --- /dev/null +++ b/include/hw/misc/tt_atlantis_prcm.h @@ -0,0 +1,51 @@ +/* + * PRCM (Clock and Reset Controller) in Tenstorrent Atlantis SoC + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2026 Tenstorrent + */ + +#ifndef TT_ATLANTIS_PRCM_H +#define TT_ATLANTIS_PRCM_H + +#include "hw/core/sysbus.h" + +#define TYPE_TT_ATLANTIS_PRCM "tt.atlantis.prcm" +#define TYPE_TT_ATLANTIS_PRCM_RCPU "tt.atlantis.prcm.rcpu" +#define TYPE_TT_ATLANTIS_PRCM_HSIO "tt.atlantis.prcm.hsio" +#define TYPE_TT_ATLANTIS_PRCM_PCIE "tt.atlantis.prcm.pcie" +#define TYPE_TT_ATLANTIS_PRCM_MM "tt.atlantis.prcm.mm" +#define TYPE_TT_ATLANTIS_PRCM_DDRC0 "tt.atlantis.prcm.ddrc0" +#define TYPE_TT_ATLANTIS_PRCM_DDRC1 "tt.atlantis.prcm.ddrc1" +OBJECT_DECLARE_TYPE(TTAtlantisPRCMState, TTAtlantisPRCMClass, + TT_ATLANTIS_PRCM); + + +enum { + TT_ATLANTIS_PRCM_DOMAIN_RCPU =3D 0, + TT_ATLANTIS_PRCM_DOMAIN_HSIO =3D 1, + TT_ATLANTIS_PRCM_DOMAIN_PCIE =3D 2, + TT_ATLANTIS_PRCM_DOMAIN_MM =3D 3, + TT_ATLANTIS_PRCM_DOMAIN_DDRC0 =3D 4, + TT_ATLANTIS_PRCM_DOMAIN_DDRC1 =3D 5, + TT_ATLANTIS_PRCM_DOMAIN_COUNT =3D 6 +}; + +struct TTAtlantisPRCMState { + SysBusDevice parent; + + MemoryRegion mmio; + + uint32_t *regs; +}; + +struct TTAtlantisPRCMClass { + SysBusDeviceClass parent_class; + + uint32_t domain; + uint32_t regs_size; + const MemoryRegionOps *ops; +}; + +#endif diff --git a/hw/misc/tt_atlantis_prcm.c b/hw/misc/tt_atlantis_prcm.c new file mode 100644 index 0000000000..31caca08fc --- /dev/null +++ b/hw/misc/tt_atlantis_prcm.c @@ -0,0 +1,428 @@ +/* + * PRCM (Clock and Reset Controller) in Tenstorrent Atlantis SoC + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2026 Tenstorrent + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/misc/tt_atlantis_prcm.h" +#include "trace.h" + +#define TO_REG(offset) ((offset) >> 2) + +#define PLL_LOCK_BIT 31 +#define PLL_FBDIV_LSB 14 +#define PLL_POSTDIV2_LSB 11 +#define PLL_POSTDIV1_LSB 8 +#define PLL_REFDIV_LSB 2 +#define PLL_BYPASS_BIT 1 + +#define PLL_RESET_VAL(BYPASS, REFDIV, POSTDIV1, POSTDIV2, FBDIV, LOCK) = \ + ((LOCK << PLL_LOCK_BIT) | (FBDIV << PLL_FBDIV_LSB) | = \ + (POSTDIV2 << PLL_POSTDIV2_LSB) | (POSTDIV1 << PLL_POSTDIV1_LSB) | = \ + (REFDIV << PLL_REFDIV_LSB) | (BYPASS << PLL_BYPASS_BIT)) + +#define RCPU_PLL_RCPU_CFG TO_REG(0x000) +#define RCPU_PLL_NOCC_CFG TO_REG(0x004) +#define RCPU_NOCC_CLK_CFG TO_REG(0x008) +#define RCPU_RCPU_DIV_CFG TO_REG(0x00c) +#define RCPU_RCPU_BLK_CG TO_REG(0x014) +#define RCPU_LSIO_BLK_CG TO_REG(0x018) +#define RCPU_RCPU_BLK_RST TO_REG(0x01c) +#define RCPU_LSIO_BLK_RST TO_REG(0x020) +#define RCPU_PLL_RCPU_EN TO_REG(0x11c) +#define RCPU_PLL_NOCC_EN TO_REG(0x120) +#define RCPU_PLL_MM_EN TO_REG(0x124) +#define RCPU_PLL1_MM_EN TO_REG(0x128) +#define RCPU_PLL_HSIO_EN TO_REG(0x12c) +#define RCPU_PLL_PCIE_EN TO_REG(0x138) +#define RCPU_PLL_I2S_EN TO_REG(0x13c) +#define RCPU_PLL_MM_CFG TO_REG(0x19c) +#define RCPU_PLL_HSIO_CFG TO_REG(0x1a0) +#define RCPU_PLL_PCIE_CFG TO_REG(0x1ac) +#define RCPU_BOOT_MODE_CFG TO_REG(0x1b0) +#define RCPU_PLL_I2S_CFG TO_REG(0x1f4) +#define RCPU_I2S_DIV_CFG TO_REG(0x1f8) +#define RCPU_BUS_CFG TO_REG(0x1fc) +#define RCPU_PLL1_MM_CFG TO_REG(0x2a4) + +#define HSIO_HSIO_DIV_CFG TO_REG(0x00) +#define HSIO_HSIO_DIV_CFG1 TO_REG(0x04) +#define HSIO_HSIO_BLK_CG TO_REG(0x08) +#define HSIO_HSIO_BLK_RST TO_REG(0x0c) +#define HSIO_HSIO_GMAC_DIV_CFG TO_REG(0x10) + +#define PCIE_SUBS_RST_CTL TO_REG(0x0) +#define PCIE_SUBS_CG_CTL TO_REG(0x4) +#define PCIE_SUBS_CK_CTL TO_REG(0x8) + +#define MM_MM_CLK_GATE_CFG TO_REG(0x008) +#define MM_MM_CLK_DIV_CFG TO_REG(0x00c) +#define MM_MM_CLK_SEL_CFG TO_REG(0x010) +#define MM_MM_RSTN TO_REG(0x014) +#define MM_MM_CLK_DIV_CFG1 TO_REG(0x130) + +#define DDRC_STAT TO_REG(0x10014) +#define DDRC_DFISTAT TO_REG(0x10514) +#define DDRC_SWSTAT TO_REG(0x10c84) + +#define PLL_EN BIT(0) +#define RCPU_PLL_BUS_CG_EN BIT(7) +#define HSIO_PLL_BUS_CG_EN BIT(3) +#define PCIE_PLL_BUS_CG_EN BIT(1) +#define NOCC_PLL_BUS_CG_EN BIT(0) + +#define RCPU_BOOT_MODE_UART (0x0 << 4) +#define RCPU_BOOT_MODE_NOR (0x1 << 4) +#define RCPU_BOOT_MODE_SD (0x2 << 4) + +#define RCPU_DOMAIN_SIZE 0x10000 +#define HSIO_DOMAIN_SIZE 0x510 +#define PCIE_DOMAIN_SIZE 0x100 +#define MM_DOMAIN_SIZE 0x1000 +#define DDRC0_DOMAIN_SIZE 0x101000 +#define DDRC1_DOMAIN_SIZE 0x101000 + +static uint64_t tt_atlantis_prcm_read(void *opaque, hwaddr offset, + unsigned size) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(opaque); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + uint32_t data; + + if (offset >=3D c->regs_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, offset); + return 0; + } + data =3D s->regs[TO_REG(offset)]; + + trace_tt_atlantis_prcm_read(c->domain, offset, data); + return data; +} + +static void tt_atlantis_prcm_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(opaque); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + + if (offset >=3D c->regs_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + trace_tt_atlantis_prcm_write(c->domain, offset, data); + + s->regs[TO_REG(offset)] =3D data; +} + +static void tt_atlantis_prcm_rcpu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(opaque); + uint32_t pll_reg_offset; + + tt_atlantis_prcm_write(opaque, offset, data, size); + + switch (TO_REG(offset)) { + case RCPU_PLL_RCPU_EN: + pll_reg_offset =3D RCPU_PLL_RCPU_CFG; + break; + case RCPU_PLL_NOCC_EN: + pll_reg_offset =3D RCPU_PLL_NOCC_CFG; + break; + case RCPU_PLL_HSIO_EN: + pll_reg_offset =3D RCPU_PLL_HSIO_CFG; + break; + case RCPU_PLL_PCIE_EN: + pll_reg_offset =3D RCPU_PLL_PCIE_CFG; + break; + case RCPU_PLL_MM_EN: + pll_reg_offset =3D RCPU_PLL_MM_CFG; + break; + case RCPU_PLL1_MM_EN: + pll_reg_offset =3D RCPU_PLL1_MM_CFG; + break; + case RCPU_PLL_I2S_EN: + pll_reg_offset =3D RCPU_PLL_I2S_CFG; + break; + default: + return; + } + + if (data & PLL_EN) { + s->regs[pll_reg_offset] |=3D BIT(PLL_LOCK_BIT); + } else { + s->regs[pll_reg_offset] &=3D ~BIT(PLL_LOCK_BIT); + } +} + +static const MemoryRegionOps tt_atlantis_prcm_ops =3D { + .read =3D tt_atlantis_prcm_read, + .write =3D tt_atlantis_prcm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static const MemoryRegionOps tt_atlantis_prcm_rcpu_ops =3D { + .read =3D tt_atlantis_prcm_read, + .write =3D tt_atlantis_prcm_rcpu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static void tt_atlantis_prcm_realize(DeviceState *dev, Error **errp) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + + assert(c->domain < TT_ATLANTIS_PRCM_DOMAIN_COUNT); + + s->regs =3D g_new0(uint32_t, TO_REG(c->regs_size)); + + memory_region_init_io(&s->mmio, OBJECT(s), c->ops, s, + TYPE_TT_ATLANTIS_PRCM, c->regs_size); + sysbus_init_mmio(sbd, &s->mmio); +} + +static void tt_atlantis_prcm_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + + memset(s->regs, 0, c->regs_size); +} + +static void tt_atlantis_prcm_rcpu_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[RCPU_PLL_RCPU_CFG] =3D PLL_RESET_VAL(1, 0, 4, 0, 100, 1); + s->regs[RCPU_PLL_NOCC_CFG] =3D PLL_RESET_VAL(0, 2, 2, 2, 267, 1); + s->regs[RCPU_NOCC_CLK_CFG] =3D (0x25f31 << 1) | BIT(0); + s->regs[RCPU_RCPU_DIV_CFG] =3D (0xb8c2 << 1); + s->regs[RCPU_RCPU_BLK_CG] =3D 0; + s->regs[RCPU_LSIO_BLK_CG] =3D 0; + s->regs[RCPU_RCPU_BLK_RST] =3D 0xffffffff; + s->regs[RCPU_LSIO_BLK_RST] =3D 0xffffffff; + s->regs[RCPU_PLL_RCPU_EN] =3D PLL_EN; + s->regs[RCPU_PLL_NOCC_EN] =3D PLL_EN; + s->regs[RCPU_PLL_HSIO_EN] =3D 0; + s->regs[RCPU_PLL_MM_EN] =3D 0; + s->regs[RCPU_PLL1_MM_EN] =3D 0; + s->regs[RCPU_PLL_I2S_EN] =3D 0; + s->regs[RCPU_PLL_PCIE_EN] =3D 0; + s->regs[RCPU_PLL_HSIO_CFG] =3D PLL_RESET_VAL(0, 1, 2, 1, 50, 0); + s->regs[RCPU_PLL_PCIE_CFG] =3D PLL_RESET_VAL(0, 2, 3, 1, 250, 0); + s->regs[RCPU_BOOT_MODE_CFG] =3D RCPU_BOOT_MODE_SD; + s->regs[RCPU_PLL_MM_CFG] =3D PLL_RESET_VAL(0, 1, 2, 1, 50, 1); + s->regs[RCPU_PLL1_MM_CFG] =3D PLL_RESET_VAL(0, 1, 2, 1, 50, 1); + s->regs[RCPU_PLL_I2S_CFG] =3D PLL_RESET_VAL(0, 1, 6, 6, 33, 0); + s->regs[RCPU_I2S_DIV_CFG] =3D 0xde69ad31; + s->regs[RCPU_BUS_CFG] =3D NOCC_PLL_BUS_CG_EN | HSIO_PLL_BUS_CG_EN; +} + +static void tt_atlantis_prcm_ddrc_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[DDRC_STAT] =3D 0x1; + s->regs[DDRC_DFISTAT] =3D 0x1; + s->regs[DDRC_SWSTAT] =3D 0x1; +} + +static void tt_atlantis_prcm_hsio_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[HSIO_HSIO_DIV_CFG] =3D 0x20821731; + s->regs[HSIO_HSIO_DIV_CFG1] =3D 0x8; + s->regs[HSIO_HSIO_BLK_CG] =3D 0; + s->regs[HSIO_HSIO_BLK_RST] =3D 0; + s->regs[HSIO_HSIO_GMAC_DIV_CFG] =3D 0; +} + +static void tt_atlantis_prcm_pcie_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[PCIE_SUBS_RST_CTL] =3D 0; + s->regs[PCIE_SUBS_CG_CTL] =3D 0; + s->regs[PCIE_SUBS_CK_CTL] =3D 0x44908; +} + +static void tt_atlantis_prcm_mm_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[MM_MM_CLK_GATE_CFG] =3D 0; + s->regs[MM_MM_CLK_DIV_CFG] =3D 0xddc8312; + s->regs[MM_MM_CLK_SEL_CFG] =3D 0; + s->regs[MM_MM_RSTN] =3D 0; + s->regs[MM_MM_CLK_DIV_CFG1] =3D 0x333; +} + +static void tt_atlantis_prcm_unrealize(DeviceState *dev) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(dev); + + g_free(s->regs); +} + +static void tt_atlantis_prcm_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->realize =3D tt_atlantis_prcm_realize; + dc->unrealize =3D tt_atlantis_prcm_unrealize; + dc->desc =3D "Tenstorrent Atlantis PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_reset_hold; + c->ops =3D &tt_atlantis_prcm_ops; +} + +static void tt_atlantis_prcm_rcpu_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis RCPU PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_rcpu_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_RCPU; + c->regs_size =3D RCPU_DOMAIN_SIZE; + c->ops =3D &tt_atlantis_prcm_rcpu_ops; +} + +static void tt_atlantis_prcm_hsio_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis HSIO PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_hsio_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_HSIO; + c->regs_size =3D HSIO_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_pcie_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis PCIE PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_pcie_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_PCIE; + c->regs_size =3D PCIE_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_mm_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis MM PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_mm_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_MM; + c->regs_size =3D MM_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_ddrc0_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis DDR Memory Controller 0 PRCM"; + rc->phases.hold =3D tt_atlantis_prcm_ddrc_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_DDRC0; + c->regs_size =3D DDRC0_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_ddrc1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis DDR Memory Controller 1 PRCM"; + rc->phases.hold =3D tt_atlantis_prcm_ddrc_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_DDRC1; + c->regs_size =3D DDRC1_DOMAIN_SIZE; +} + +static const TypeInfo tt_atlantis_prcm_types[] =3D { + { + .name =3D TYPE_TT_ATLANTIS_PRCM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TTAtlantisPRCMState), + .class_init =3D tt_atlantis_prcm_class_init, + .class_size =3D sizeof(TTAtlantisPRCMClass), + .abstract =3D true, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_RCPU, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_rcpu_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_HSIO, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_hsio_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_PCIE, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_pcie_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_MM, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_mm_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_DDRC0, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_ddrc0_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_DDRC1, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_ddrc1_class_init, + }, +}; + +DEFINE_TYPES(tt_atlantis_prcm_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 244bf278a9..8a94aba751 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -40,6 +40,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files= ('sifive_u_otp.c')) system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.= c')) system_ss.add(when: 'CONFIG_K230_DECOMP_GZIP', if_true: files('k230_decomp= _gzip.c')) system_ss.add(when: 'CONFIG_SOPHGO_CV1800B_CLK', if_true: files('cv1800b_c= lk.c')) +system_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis_prcm= .c')) =20 subdir('macio') =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 6db4934dc5..7fde3f8a76 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -460,3 +460,7 @@ launch_update_write(void) "" vmlaunch_reset_enter(void) "" vm_launchupdate_finalize(void) "" restore_host_x86_igvm(void) "" + +# tt_atlantis_prcm.c +tt_atlantis_prcm_read(uint32_t domain, uint64_t offset, uint64_t data) "do= main 0x%02x offset 0x%" PRIx64 " data 0x%" PRIx64 +tt_atlantis_prcm_write(uint32_t domain, uint64_t offset, uint64_t data) "d= omain 0x%02x offset 0x%" PRIx64 " data 0x%" PRIx64 --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:05:03 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Anirudh Srinivasan , Chao Liu , Joel Stanley , Alistair Francis Subject: [PULL v2 46/50] hw/riscv/tt-atlantis: Add PRCMs to tt-atlantis model Date: Fri, 16 Oct 2026 11:02:33 +1000 Message-ID: <20261016010237.1102834-47-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112807335158500 Content-Type: text/plain; charset="utf-8" From: Anirudh Srinivasan Atlantis has 4 PRCMs that are visible from S mode by the Ascalon Core (RCPU, HSIO, PCIe and MM). The remaining 2 are only accessed by the boot cpu which isn't modelled yet. This commit adds these 4 PRCM blocks to the tt-atlantis model, along with necessary device tree nodes for them. Reviewed-by: Chao Liu Reviewed-by: Joel Stanley Signed-off-by: Anirudh Srinivasan Acked-by: Alistair Francis Message-ID: <20261001-atlantis_prcm-v4-2-95d33c470eeb@oss.tenstorrent.com> Signed-off-by: Alistair Francis --- docs/system/riscv/tt_atlantis.rst | 1 + include/hw/riscv/tt_atlantis.h | 22 +++++++ hw/riscv/tt_atlantis.c | 104 ++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlan= tis.rst index 1f2880d617..539c22354f 100644 --- a/docs/system/riscv/tt_atlantis.rst +++ b/docs/system/riscv/tt_atlantis.rst @@ -14,6 +14,7 @@ tt-atlantis QEMU model features * 8-core Ascalon-X CPU Cluster * RISC-V compliant Advanced Interrupt Architecture * 16550A compatible UART +* 4 PRCMs (Clock and Reset Controllers) =20 Known limitations ----------------- diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 3923308b7c..db1dfed157 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -14,6 +14,7 @@ #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" #include "hw/misc/unimp.h" +#include "hw/misc/tt_atlantis_prcm.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -23,6 +24,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_M= ACHINE) OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) =20 #define TT_ATL_NUM_I2C 5 +#define TT_ATL_NUM_PRCM 4 =20 struct TTAtlantisSoCState { /*< private >*/ @@ -41,6 +43,7 @@ struct TTAtlantisSoCState { DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; MemoryRegion bootrom; + TTAtlantisPRCMState prcm[TT_ATL_NUM_PRCM]; =20 uint32_t num_harts; char *cpu_type; @@ -81,6 +84,25 @@ enum { TT_ATL_SAPLIC, TT_ATL_SIMSIC, TT_ATL_UART1, + TT_ATL_PRCM_RCPU, + TT_ATL_PRCM_HSIO, + TT_ATL_PRCM_PCIE, + TT_ATL_PRCM_MM, +}; + +/* + * RCPU PRCM Clock IDs, sourced from linux dt-bindings + * include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h + */ +enum { + TT_ATL_CLK_RCPU_PLL =3D 0, + TT_ATL_CLK_RCPU_ROOT =3D 1, + TT_ATL_CLK_NOC_PLL =3D 25, + TT_ATL_CLK_NOCC_CLK =3D 26, + TT_ATL_CLK_HSIO_PLL =3D 54, + TT_ATL_CLK_PCIE_PLL =3D 55, + TT_ATL_CLK_MM_PLL0 =3D 56, + TT_ATL_CLK_MM_PLL1 =3D 57, }; =20 #endif diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8a219afef7..10ae3c2850 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -27,6 +27,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/riscv_aclint.h" #include "hw/misc/unimp.h" +#include "hw/misc/tt_atlantis_prcm.h" =20 #include "system/system.h" #include "system/device_tree.h" @@ -58,12 +59,16 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_ACLINT] =3D { 0xa2180000, 0x10000 }, [TT_ATL_SIMSIC] =3D { 0xa4000000, 0x200000 }, [TT_ATL_MAPLIC] =3D { 0xcc000000, 0x4000000 }, + [TT_ATL_PRCM_RCPU] =3D { 0xd0000000, 0x10000 }, [TT_ATL_I2C0] =3D { 0xd4040000, 0x10000 }, [TT_ATL_I2C1] =3D { 0xd4050000, 0x10000 }, [TT_ATL_I2C2] =3D { 0xd4060000, 0x10000 }, [TT_ATL_I2C3] =3D { 0xd4070000, 0x10000 }, [TT_ATL_I2C4] =3D { 0xd4080000, 0x10000 }, [TT_ATL_UART1] =3D { 0xd4110000, 0x10000 }, + [TT_ATL_PRCM_PCIE] =3D { 0xd8000000, 0x100 }, + [TT_ATL_PRCM_MM] =3D { 0xdc000000, 0x1000 }, + [TT_ATL_PRCM_HSIO] =3D { 0xe00c0000, 0x510 }, [TT_ATL_SAPLIC] =3D { 0xe8000000, 0x4000000 }, [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, }; @@ -327,11 +332,34 @@ static void create_fdt_i2c_device(void *fdt, TTAtlant= isSoCState *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 +static char *create_fdt_prcm(void *fdt, const MemMapEntry *mem, + const char *prcm_name) +{ + hwaddr base =3D mem->base; + hwaddr size =3D mem->size; + char *name =3D g_strdup_printf("/soc/clock-controller@%" PRIx64, + base); + g_autofree char *compatible =3D + g_strdup_printf("tenstorrent,atlantis-prcm-%s", prcm_name); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", compatible); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, base, 2, size); + qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "#reset-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "phandle", next_phandle()); + + return name; +} + static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); uint32_t periph_clk_phandle =3D next_phandle(); + uint32_t osc_24m_phandle =3D next_phandle(); + uint32_t prcm_rcpu_phandle; + g_autofree char *rcpu_name, *hsio_name, *pcie_name, *mm_name; =20 create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); =20 @@ -348,6 +376,30 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState= *s) aplic_s_phandle); =20 create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); + create_fdt_clk(fdt, "osc-24m", 24000000, osc_24m_phandle); + + rcpu_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_RCPU], "rcpu= "); + prcm_rcpu_phandle =3D qemu_fdt_get_phandle(fdt, rcpu_name); + qemu_fdt_setprop_cells(fdt, rcpu_name, "clocks", osc_24m_phandle); + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clocks", + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_ROOT, + prcm_rcpu_phandle, TT_ATL_CLK_NOCC_CLK); + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clock-parents", + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_PLL, + prcm_rcpu_phandle, TT_ATL_CLK_NOC_PLL); + + hsio_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_HSIO], "hsio= "); + qemu_fdt_setprop_cells(fdt, hsio_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_HSIO_PLL); + + pcie_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_PCIE], "pcie= "); + qemu_fdt_setprop_cells(fdt, pcie_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_PCIE_PLL); + + mm_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_MM], "mm"); + qemu_fdt_setprop_cells(fdt, mm_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL0, + prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL1); =20 for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { create_fdt_i2c(fdt, @@ -491,6 +543,19 @@ static void tt_atlantis_soc_init(Object *obj) object_initialize_child(obj, "uart1", &s->uart1, TYPE_UNIMPLEMENTED_DEVICE); =20 + object_initialize_child(obj, "prcm-rcpu", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU], + TYPE_TT_ATLANTIS_PRCM_RCPU); + object_initialize_child(obj, "prcm-hsio", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO], + TYPE_TT_ATLANTIS_PRCM_HSIO); + object_initialize_child(obj, "prcm-pcie", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE], + TYPE_TT_ATLANTIS_PRCM_PCIE); + object_initialize_child(obj, "prcm-mm", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM], + TYPE_TT_ATLANTIS_PRCM_MM); + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_DESIGNWARE_I2C); @@ -587,6 +652,44 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); + + /* 4 PRCM blocks */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RC= PU]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_RCPU].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HS= IO]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_HSIO].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PC= IE]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_PCIE].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM= ]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_MM].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM]), 0)); + /* * Atlantis contains a DesignWare uart while the QEMU machine * uses the serial_mm model with the base ns16550 register set. @@ -654,6 +757,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), &error_abort); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); =20 /* I2C peripherals: qemu specific */ --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:05:05 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Anirudh Srinivasan , Alistair Francis Subject: [PULL v2 47/50] hw/riscv/tt-atlantis: Update UART and I2C to use clk from PRCM Date: Fri, 16 Oct 2026 11:02:34 +1000 Message-ID: <20261016010237.1102834-48-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792113098961158500 Content-Type: text/plain; charset="utf-8" From: Anirudh Srinivasan Now that we have the PRCM modelled, update the DT nodes for UART1 and the 5 I2C controllers to use the rcpu_prcm as a clock provider. This also allows us to eliminate the periph_clk that was added to the DT previously. Signed-off-by: Anirudh Srinivasan Acked-by: Alistair Francis Message-ID: <20261001-atlantis_prcm-v4-3-95d33c470eeb@oss.tenstorrent.com> Signed-off-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 6 ++++++ hw/riscv/tt_atlantis.c | 23 ++++++++++++++--------- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index db1dfed157..577c867d71 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -99,6 +99,12 @@ enum { TT_ATL_CLK_RCPU_ROOT =3D 1, TT_ATL_CLK_NOC_PLL =3D 25, TT_ATL_CLK_NOCC_CLK =3D 26, + TT_ATL_CLK_I2C0_PCLK =3D 33, + TT_ATL_CLK_I2C1_PCLK =3D 34, + TT_ATL_CLK_I2C2_PCLK =3D 35, + TT_ATL_CLK_I2C3_PCLK =3D 36, + TT_ATL_CLK_I2C4_PCLK =3D 37, + TT_ATL_CLK_UART1_PCLK =3D 39, TT_ATL_CLK_HSIO_PLL =3D 54, TT_ATL_CLK_PCIE_PLL =3D 55, TT_ATL_CLK_MM_PLL0 =3D 56, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 10ae3c2850..4e6c39982c 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -265,7 +265,8 @@ static void create_fdt_cpu(void *fdt, TTAtlantisSoCStat= e *s, } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, - int irqchip_phandle) + int irqchip_phandle, uint32_t clk_parent_phand= le, + uint32_t clk_phandle) { g_autofree char *name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIX, mem->base); @@ -275,6 +276,8 @@ static void create_fdt_uart(void *fdt, const MemMapEntr= y *mem, int irq, qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2); qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_parent_phandle, + clk_phandle); qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); @@ -305,7 +308,9 @@ static void create_fdt_clk(void *fdt, const char *clock= _name, } =20 static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq, - uint32_t irqchip_phandle, uint32_t clk_phandle) + uint32_t irqchip_phandle, + uint32_t clk_parent_phandle, + uint32_t clk_phandle) { g_autofree char *name =3D g_strdup_printf("/soc/i2c@%"HWADDR_PRIX, mem= ->base); =20 @@ -314,7 +319,8 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry= *mem, uint32_t irq, qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); - qemu_fdt_setprop_cell(fdt, name, "clocks", clk_phandle); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_parent_phandle, + clk_phandle); qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 100000); qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); @@ -356,7 +362,6 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState = *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); - uint32_t periph_clk_phandle =3D next_phandle(); uint32_t osc_24m_phandle =3D next_phandle(); uint32_t prcm_rcpu_phandle; g_autofree char *rcpu_name, *hsio_name, *pcie_name, *mm_name; @@ -372,10 +377,6 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState= *s) * aplic_s_phandle); */ =20 - create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ, - aplic_s_phandle); - - create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); 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Thu, 15 Oct 2026 18:05:08 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Zephyr Li , Daniel Henrique Barboza , Chao Liu , Alistair Francis Subject: [PULL v2 48/50] target/riscv: fix RV32 fixed counter accesses Date: Fri, 16 Oct 2026 11:02:35 +1000 Message-ID: <20261016010237.1102834-49-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112895026158500 Content-Type: text/plain; charset="utf-8" From: Zephyr Li Since commit cfc96df65e01, riscv_pmu_ctr_get_fixed_counters_val() returns the complete 64-bit fixed-counter value. The RV32 counter access paths, however, still perform parts of the offset calculation on separately extracted 32-bit halves. In particular, riscv_pmu_write_ctrh() deposits the low 32 bits of the complete fixed-counter value into the high half of mhpmcounter_prev. riscv_pmu_read_ctr() also subtracts a 32-bit half of the previous value from the complete 64-bit fixed-counter value. Consequently, writes to mcycleh can be lost and carries between the low and high halves are not handled correctly. Keep the fixed-counter offset calculation entirely in 64 bits. Before a running counter is partially written, materialize its current architectural value and reset the fixed-counter baseline. On reads, calculate the complete 64-bit counter value before extracting the half requested by RV32. Register RV32 system TCG tests with the Meson build. Add a test for high-half writes, low-to-high carry, and preserving the carried high half across a subsequent low-half write. Fixes: cfc96df65e01 ("target/riscv: Remove upper_half from riscv_pmu_ctr_ge= t_fixed_counters_val") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4219 Signed-off-by: Zephyr Li Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Message-ID: <20261008035150.2223-1-fritchleybohrer@gmail.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + target/riscv/tcg/csr.c | 32 ++++++++++---------- meson_options.txt | 4 +++ scripts/meson-buildoptions.sh | 2 ++ tests/tcg/meson.build | 1 + tests/tcg/riscv32/meson.build | 6 ++++ tests/tcg/riscv32/semihost.ld | 23 ++++++++++++++ tests/tcg/riscv32/system/meson.build | 36 ++++++++++++++++++++++ tests/tcg/riscv32/test-mcycle.S | 45 ++++++++++++++++++++++++++++ 9 files changed, 135 insertions(+), 15 deletions(-) create mode 100644 tests/tcg/riscv32/meson.build create mode 100644 tests/tcg/riscv32/semihost.ld create mode 100644 tests/tcg/riscv32/system/meson.build create mode 100644 tests/tcg/riscv32/test-mcycle.S diff --git a/MAINTAINERS b/MAINTAINERS index 0455e8e6b9..b3ed343e17 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -377,6 +377,7 @@ F: include/hw/riscv/ F: common-user/host/riscv* F: tests/functional/riscv32 F: tests/functional/riscv64 +F: tests/tcg/riscv32/ F: tests/tcg/riscv64/ F: tests/qtest/iommu-riscv-test.c =20 diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 2ad66239ae..64be8ca309 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -1340,23 +1340,23 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVS= tate *env, target_ulong val, int deposit_size =3D rv32 ? 32 : 64; uint64_t ctr; =20 - counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, - 0, deposit_size, val); - if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); - counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, - 0, deposit_size, ctr); + counter->mhpmcounter_val +=3D ctr - counter->mhpmcounter_prev; + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 0, deposit_size, val); + counter->mhpmcounter_prev =3D ctr; if (ctr_idx > 2) { riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 0, deposit_size, val); /* Other counters can keep incrementing from the given value */ counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 0, deposit_size, val); - } =20 return RISCV_EXCP_NONE; @@ -1366,20 +1366,22 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCV= State *env, target_ulong val, uint32_t ctr_idx) { PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t ctrh; + uint64_t ctr; =20 - counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, - 32, 32, val); if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { - ctrh =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); - counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, - 32, 32, ctrh); + ctr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx); + counter->mhpmcounter_val +=3D ctr - counter->mhpmcounter_prev; + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 32, 32, val); + counter->mhpmcounter_prev =3D ctr; if (ctr_idx > 2) { riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx); } } else { + counter->mhpmcounter_val =3D deposit64(counter->mhpmcounter_val, + 32, 32, val); counter->mhpmcounter_prev =3D deposit64(counter->mhpmcounter_prev, 32, 32, val); } @@ -1410,12 +1412,11 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *en= v, target_ulong *val, bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; int start =3D upper_half ? 32 : 0; int length =3D rv32 ? 32 : 64; - uint64_t ctr_prev, ctr_val; + uint64_t ctr_val; =20 /* Ensure upper_half is only set for XLEN =3D=3D 32 */ g_assert(rv32 || !upper_half); =20 - ctr_prev =3D extract64(counter->mhpmcounter_prev, start, length); ctr_val =3D extract64(counter->mhpmcounter_val, start, length); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { @@ -1434,7 +1435,8 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env,= target_ulong *val, if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { uint64_t cntr =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_id= x) - - ctr_prev + ct= r_val; + counter->mhpmcounter_prev + + counter->mhpmcounter_val; *val =3D extract64(cntr, start, length); } else { *val =3D ctr_val; diff --git a/meson_options.txt b/meson_options.txt index c9247e9de1..895c6e63c2 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -473,6 +473,10 @@ option('tcg_tests_cross_cc_ppc64le', type: 'string', description: 'cc for ppc64le tcg tests') option('tcg_tests_cross_cflags_ppc64le', type: 'string', description: 'cflags for ppc64le tcg tests') +option('tcg_tests_cross_cc_riscv32', type: 'string', + description: 'cc for riscv32 tcg tests') +option('tcg_tests_cross_cflags_riscv32', type: 'string', + description: 'cflags for riscv32 tcg tests') option('tcg_tests_cross_cc_riscv64', type: 'string', description: 'cc for riscv64 tcg tests') option('tcg_tests_cross_cflags_riscv64', type: 'string', diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 064e1429a4..14990966d3 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -547,6 +547,7 @@ _meson_option_parse() { --tcg-tests-cross-cc-or1k=3D*) quote_sh "-Dtcg_tests_cross_cc_or1k=3D$= 2" ;; --tcg-tests-cross-cc-ppc64=3D*) quote_sh "-Dtcg_tests_cross_cc_ppc64= =3D$2" ;; --tcg-tests-cross-cc-ppc64le=3D*) quote_sh "-Dtcg_tests_cross_cc_ppc64= le=3D$2" ;; + --tcg-tests-cross-cc-riscv32=3D*) quote_sh "-Dtcg_tests_cross_cc_riscv= 32=3D$2" ;; --tcg-tests-cross-cc-riscv64=3D*) quote_sh "-Dtcg_tests_cross_cc_riscv= 64=3D$2" ;; --tcg-tests-cross-cc-s390x=3D*) quote_sh "-Dtcg_tests_cross_cc_s390x= =3D$2" ;; --tcg-tests-cross-cc-sh4=3D*) quote_sh "-Dtcg_tests_cross_cc_sh4=3D$2"= ;; @@ -573,6 +574,7 @@ _meson_option_parse() { --tcg-tests-cross-cflags-or1k=3D*) quote_sh "-Dtcg_tests_cross_cflags_= or1k=3D$2" ;; --tcg-tests-cross-cflags-ppc64=3D*) quote_sh "-Dtcg_tests_cross_cflags= _ppc64=3D$2" ;; --tcg-tests-cross-cflags-ppc64le=3D*) quote_sh "-Dtcg_tests_cross_cfla= gs_ppc64le=3D$2" ;; + --tcg-tests-cross-cflags-riscv32=3D*) quote_sh "-Dtcg_tests_cross_cfla= gs_riscv32=3D$2" ;; --tcg-tests-cross-cflags-riscv64=3D*) quote_sh "-Dtcg_tests_cross_cfla= gs_riscv64=3D$2" ;; --tcg-tests-cross-cflags-s390x=3D*) quote_sh "-Dtcg_tests_cross_cflags= _s390x=3D$2" ;; --tcg-tests-cross-cflags-sh4=3D*) quote_sh "-Dtcg_tests_cross_cflags_s= h4=3D$2" ;; diff --git a/tests/tcg/meson.build b/tests/tcg/meson.build index 4c0e30756d..184edcdbbc 100644 --- a/tests/tcg/meson.build +++ b/tests/tcg/meson.build @@ -186,6 +186,7 @@ subdir('mips64el') subdir('or1k') subdir('ppc64') subdir('ppc64le') +subdir('riscv32') subdir('riscv64') subdir('s390x') subdir('sh4') diff --git a/tests/tcg/riscv32/meson.build b/tests/tcg/riscv32/meson.build new file mode 100644 index 0000000000..862f1349c2 --- /dev/null +++ b/tests/tcg/riscv32/meson.build @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +cc =3D 'riscv64-linux-gnu-gcc' +cc_dockerfile =3D 'debian-all-test-cross' + +subdir('system') diff --git a/tests/tcg/riscv32/semihost.ld b/tests/tcg/riscv32/semihost.ld new file mode 100644 index 0000000000..874838a865 --- /dev/null +++ b/tests/tcg/riscv32/semihost.ld @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +ENTRY(_start) + +SECTIONS +{ + /* virt machine, RAM starts at 2gb */ + . =3D 0x80000000; + .text : { + *(.text) + } + .rodata : { + *(.rodata) + } + /* align r/w section to next 2mb */ + . =3D ALIGN(1 << 21); + .data : { + *(.data) + } + .bss : { + *(.bss) + } +} diff --git a/tests/tcg/riscv32/system/meson.build b/tests/tcg/riscv32/syste= m/meson.build new file mode 100644 index 0000000000..f8e55ad3d4 --- /dev/null +++ b/tests/tcg/riscv32/system/meson.build @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +tests =3D [] + +link_script =3D files('../semihost.ld')[0] +cflags =3D ['-march=3Drv32im_zicsr', + '-mabi=3Dilp32', + '-nostdlib', + '-ffreestanding', + '-Wa,--noexecstack', + '-Wl,-T', link_script] +qemu_args =3D ['-M', 'virt', + '-display', 'none', + '-serial', 'stdio', + '-semihosting', + '-bios'] + +tests +=3D { + 'test-mcycle.S': { + 'cflags': cflags, + 'qemu_args': ['-icount', 'shift=3D1', qemu_args], + }, +} + +if 'qemu-system-riscv32' in emulators + tcg_tests +=3D { + 'riscv32-softmmu': { + 'cc': cc, + 'cc_dockerfile': cc_dockerfile, + 'folder': 'riscv32', + 'gdb_arch': 'riscv32', + 'qemu': emulators['qemu-system-riscv32'], + 'tests': tests, + } + } +endif diff --git a/tests/tcg/riscv32/test-mcycle.S b/tests/tcg/riscv32/test-mcycl= e.S new file mode 100644 index 0000000000..189d1e13a2 --- /dev/null +++ b/tests/tcg/riscv32/test-mcycle.S @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + .option norvc + + .text + .global _start +_start: + /* Exercise writes while mcycle is running. */ + csrw mcountinhibit, zero + csrw mcycle, zero + + /* A write to the high half must be immediately observable. */ + li s0, 0x1234ffff + csrw mcycleh, s0 + csrr t0, mcycleh + bne t0, s0, fail + + /* Check carry from the low half into the high half. */ + li s0, 0x12345678 + csrw mcycleh, s0 + li t0, 0xfffffff0 + csrw mcycle, t0 + .rept 32 + nop + .endr + csrr t0, mcycleh + addi s0, s0, 1 + bne t0, s0, fail + + /* A low-half write must preserve the carried high half. */ + li t0, 0x22222222 + csrw mcycle, t0 + csrr t0, mcycleh + bne t0, s0, fail + + li t0, 0x100000 + li t1, 0x5555 /* FINISHER_PASS */ + sw t1, 0(t0) + j . + +fail: + li t0, 0x100000 + li t1, 0x13333 /* status =3D FINISHER_FAIL, code =3D 1 */ + sw t1, 0(t0) + j . --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 15 Oct 2026 18:05:10 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: wangyang , Alistair Francis Subject: [PULL v2 49/50] target/riscv: write back fsgnjn.h and fsgnjx.h results Date: Fri, 16 Oct 2026 11:02:36 +1000 Message-ID: <20261016010237.1102834-50-alistair.francis@wdc.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261016010237.1102834-1-alistair.francis@wdc.com> References: <20261016010237.1102834-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_HEX=0.1 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792112984957158500 Content-Type: text/plain; charset="utf-8" From: wangyang Under Zfinx/Zhinx, trans_fsgnjn_h() and trans_fsgnjx_h() compute their results into a temporary but return without calling gen_set_fpr_hs(). The instructions consequently retire without updating the corresponding integer register. Add the missing writeback calls, matching trans_fsgnj_h(). Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4407 Signed-off-by: wangyang Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- target/riscv/tcg/insn_trans/trans_rvzfh.c.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc b/target/riscv/t= cg/insn_trans/trans_rvzfh.c.inc index b17ef9541c..4af717ce54 100644 --- a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc @@ -319,6 +319,7 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnj= n_h *a) if (ctx->cfg_ptr->ext_zfinx) { tcg_gen_ext16s_i64(dest, dest); } + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -363,6 +364,7 @@ static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnj= x_h *a) if (ctx->cfg_ptr->ext_zfinx) { tcg_gen_ext16s_i64(dest, dest); } + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } --=20 2.55.0 From nobody Sat Oct 24 15:41:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: wangyang Only jvt.mode=3D0 is implemented by QEMU. write_jvt() currently retains reserved mode bits, so a legal WARL write of base|1 is read back unchanged and causes a subsequent cm.jt to trap. Mask the write with JVT_BASE to normalize the unsupported mode. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4408 Signed-off-by: wangyang Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- target/riscv/tcg/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 64be8ca309..063590f56a 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -6086,7 +6086,7 @@ static RISCVException read_jvt(CPURISCVState *env, in= t csrno, static RISCVException write_jvt(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - env->jvt =3D val; + env->jvt =3D val & JVT_BASE; return RISCV_EXCP_NONE; } =20 --=20 2.55.0