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Fri, 16 Oct 2026 02:41:30 -0700 (PDT) From: Jim MacArthur Date: Fri, 16 Oct 2026 10:40:51 +0100 Subject: [PATCH 1/2] hw/arm/smmuv3: define Root registers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261016-jmac-smmu-root-registers-v1-1-e78e8879d347@linaro.org> References: <20261016-jmac-smmu-root-registers-v1-0-e78e8879d347@linaro.org> In-Reply-To: <20261016-jmac-smmu-root-registers-v1-0-e78e8879d347@linaro.org> To: qemu-devel@nongnu.org Cc: Eric Auger , Peter Maydell , qemu-arm@nongnu.org, Leif Lindholm , Jim MacArthur , Pierrick Bouvier X-Mailer: b4 0.17-dev-6be7c Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792143744594158500 From: Pierrick Bouvier Adds all the non-optional SMMUv3.3 Root registers. These registers do nothing at the moment, but RW registers can be written and all registers can be read. Based on original work by Pierrick Bouvier Signed-off-by: Jim MacArthur --- hw/arm/smmuv3.c | 229 +++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/smmuv3-common.h | 22 ++++ include/hw/arm/smmuv3.h | 13 +++ 3 files changed, 264 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ed19536a4d..9d9bc2601b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -316,6 +316,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s) s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); s->aidr =3D 0x1; smmuv3_accel_idr_override(s); + + /* Initialize Root bank */ + s->root.idr0 =3D FIELD_DP32(s->root.idr0, ROOT_IDR0, ROOT_IMPL, 1); + /* Set this to 1 when SMMU Realms are implemented */ + s->root.idr0 =3D FIELD_DP32(s->root.idr0, ROOT_IDR0, REALM_IMPL, 0); } =20 bool smmuv3_ats_enabled(SMMUv3State *s) @@ -1769,6 +1774,111 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwad= dr offset, return MEMTX_OK; } =20 +/* + * Check we are from the Root PA space to read from or write to the + * SMMU Root register area. + */ +static bool smmu_check_root_access(SMMUv3State *s, MemTxAttrs attrs, + hwaddr offset, bool is_read) +{ + /* Check if the access is from Root PA */ + if (!(attrs.space =3D=3D ARMSS_Root)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Non-root %s attempt at offset 0x%" PRIx64 " (%s)\n", + __func__, is_read ? "read" : "write", offset, + is_read ? "RAZ" : "WI"); + return false; + } + return true; +} + +static MemTxResult smmu_root_writel(SMMUv3State *s, hwaddr offset, + uint64_t data, MemTxAttrs attrs) +{ + switch (offset) { + case A_ROOT_IDR0: + case A_ROOT_IIDR: + case A_ROOT_CR0ACK: + /* RO registers, write ignored */ + return MEMTX_OK; + case A_ROOT_TLBI_CTRL: + /* Optional, not implemented. Present if IDR0.RGPTM =3D=3D 1 */ + return MEMTX_OK; + case A_ROOT_GPT_BASE_UPDATE: + /* Unimplemented at present; has side effects */ + return MEMTX_OK; + case A_ROOT_CR0: + s->root.cr0 =3D data; + s->root.cr0ack =3D s->root.cr0; + return MEMTX_OK; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled 32-bit access at 0x%"PRIx64" (WI)\n", + __func__, offset); + /* + * Locations not associated with a register (including registers t= hat we + * have not implemented yet) are RES0, and will follow RAZ/WI beha= viour. + */ + return MEMTX_OK; + } +} + +static MemTxResult smmu_root_writell(SMMUv3State *s, hwaddr offset, + uint64_t data, MemTxAttrs attrs) +{ + switch (offset) { + case A_ROOT_GPT_BASE: + s->root.gpt_base =3D data; + return MEMTX_OK; + case A_ROOT_GPT_BASE_CFG: + s->root.gpt_base_cfg =3D data; + return MEMTX_OK; + case A_ROOT_GPF_FAR: + s->root.gpf_far =3D data; + return MEMTX_OK; + case A_ROOT_GPT_CFG_FAR: + s->root.gpt_cfg_far =3D data; + return MEMTX_OK; + case A_ROOT_TLBI: + /* Optional, not implemented. Present if ROOT_IDR0.RGPTM =3D=3D 1 = */ + return MEMTX_OK; + case A_ROOT_GPT_BASE2: + s->root.gpt_base2 =3D data; + return MEMTX_OK; + case A_ROOT_GPCBW: + /* Optional, not implemented. Present if ROOT_IDR0.GPTS =3D=3D 1 */ + return MEMTX_OK; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled 64-bit access at 0x%"PRIx64" (WI)\n", + __func__, offset); + /* RES0; See smmu_root_writel */ + return MEMTX_OK; + } +} + +static MemTxResult smmu_write_mmio_root(SMMUv3State *s, hwaddr offset, + uint64_t data, unsigned size, + MemTxAttrs attrs) +{ + MemTxResult r; + + switch (size) { + case 8: + r =3D smmu_root_writell(s, offset, data, attrs); + break; + case 4: + r =3D smmu_root_writel(s, offset, data, attrs); + break; + default: + r =3D MEMTX_ERROR; + break; + } + + trace_smmuv3_write_mmio(offset, data, size, r); + return r; +} + static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t d= ata, unsigned size, MemTxAttrs attrs) { @@ -1776,6 +1886,18 @@ static MemTxResult smmu_write_mmio(void *opaque, hwa= ddr offset, uint64_t data, SMMUv3State *s =3D ARM_SMMUV3(sys); MemTxResult r; =20 + if (offset >=3D SMMU_ROOT_REG_START) { + if (!smmu_check_root_access(s, attrs, offset, false)) { + /* + * As per 6.2.8, accesses in any PA space other + * than Root are completed as RAZ/WI. + */ + trace_smmuv3_write_mmio(offset, data, size, MEMTX_OK); + return MEMTX_OK; + } + return smmu_write_mmio_root(s, offset, data, size, attrs); + } + /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */ offset &=3D ~0x10000; =20 @@ -1918,6 +2040,100 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwadd= r offset, } } =20 +static MemTxResult smmu_root_readl(SMMUv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) +{ + switch (offset) { + case A_ROOT_IDR0: + *data =3D s->root.idr0; + return MEMTX_OK; + case A_ROOT_IIDR: + *data =3D s->root.iidr; + return MEMTX_OK; + case A_ROOT_TLBI_CTRL: + /* Optional, not implemented. Present if ROOT_IDR0.RGPTM =3D=3D 1 = */ + *data =3D 0; + return MEMTX_OK; + case A_ROOT_GPT_BASE_UPDATE: + /* Not a regular register; reads as 0 once update is complete */ + *data =3D 0; + return MEMTX_OK; + case A_ROOT_CR0: + *data =3D s->root.cr0; + return MEMTX_OK; + case A_ROOT_CR0ACK: + *data =3D s->root.cr0ack; + return MEMTX_OK; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled 32-bit access at 0x%"PRIx64" (RAZ)\n", + __func__, offset); + *data =3D 0; + /* RES0; See smmu_root_writel */ + return MEMTX_OK; + } +} + +static MemTxResult smmu_root_readll(SMMUv3State *s, hwaddr offset, + uint64_t *data, MemTxAttrs attrs) +{ + switch (offset) { + case A_ROOT_GPT_BASE: + *data =3D s->root.gpt_base; + return MEMTX_OK; + case A_ROOT_GPT_BASE_CFG: + *data =3D s->root.gpt_base_cfg; + return MEMTX_OK; + case A_ROOT_GPF_FAR: + *data =3D s->root.gpf_far; + return MEMTX_OK; + case A_ROOT_GPT_CFG_FAR: + *data =3D s->root.gpt_cfg_far; + return MEMTX_OK; + case A_ROOT_TLBI: + /* Optional, not implemented. Present if ROOT_IDR0.RGPTM =3D=3D 1 = */ + *data =3D 0; + return MEMTX_OK; + case A_ROOT_GPT_BASE2: + *data =3D s->root.gpt_base2; + return MEMTX_OK; + case A_ROOT_GPCBW: + /* Optional, not implemented. Present if ROOT_IDR0.GPTS =3D=3D 0 */ + *data =3D 0; + return MEMTX_OK; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled 64-bit access at 0x%"PRIx64" (RAZ)\n", + __func__, offset); + *data =3D 0; + /* RES0; See smmu_root_writel */ + return MEMTX_OK; + } +} + +static MemTxResult smmu_read_mmio_root(SMMUv3State *s, hwaddr offset, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + MemTxResult r; + + switch (size) { + case 8: + r =3D smmu_root_readll(s, offset, data, attrs); + break; + case 4: + r =3D smmu_root_readl(s, offset, data, attrs); + break; + default: + r =3D MEMTX_ERROR; + break; + } + + trace_smmuv3_read_mmio(offset, *data, size, r); + return r; +} + + static MemTxResult smmu_read_mmio(void *opaque, hwaddr offset, uint64_t *d= ata, unsigned size, MemTxAttrs attrs) { @@ -1925,6 +2141,19 @@ static MemTxResult smmu_read_mmio(void *opaque, hwad= dr offset, uint64_t *data, SMMUv3State *s =3D ARM_SMMUV3(sys); MemTxResult r; =20 + if (offset >=3D SMMU_ROOT_REG_START) { + if (!smmu_check_root_access(s, attrs, offset, true)) { + /* + * As per 6.2.8, accesses in any PA space other + * than Root are completed as RAZ/WI. + */ + trace_smmuv3_read_mmio(offset, *data, size, MEMTX_OK); + return MEMTX_OK; + } + + return smmu_read_mmio_root(s, offset, data, size, attrs); + } + /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */ offset &=3D ~0x10000; =20 diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 4609975edf..a538334066 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -411,6 +411,28 @@ REG32(EVENTQ_IRQ_CFG2, 0xbc) =20 #define A_IDREGS 0xfd0 =20 +#define SMMU_ROOT_REG_START 0x20000 + +REG32(ROOT_IDR0, 0x0) + FIELD(ROOT_IDR0, ROOT_IMPL, 0, 1) + FIELD(ROOT_IDR0, BGTPM, 1, 1) + FIELD(ROOT_IDR0, RGPTM, 2, 1) + FIELD(ROOT_IDR0, REALM_IMPL, 3, 1) + FIELD(ROOT_IDR0, BA_REALM, 22, 10) + +REG32(ROOT_IIDR, 0x8) +REG32(ROOT_CR0, 0x20) +REG32(ROOT_CR0ACK, 0x24) +REG64(ROOT_GPT_BASE, 0x28) +REG64(ROOT_GPT_BASE_CFG, 0x30) +REG64(ROOT_GPF_FAR, 0x38) +REG64(ROOT_GPT_CFG_FAR, 0x40) +REG64(ROOT_TLBI, 0x50) +REG32(ROOT_TLBI_CTRL, 0x58) +REG64(ROOT_GPT_BASE2, 0x60) +REG32(ROOT_GPT_BASE_UPDATE, 0x68) +REG32(ROOT_GPCBW, 0x70) + /* Commands */ =20 typedef enum SMMUCommandType { diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d39fe8850b..e2708e13fe 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -34,6 +34,18 @@ typedef struct SMMUQueue { uint8_t log2size; } SMMUQueue; =20 +typedef struct SMMUv3RootRegBank { + uint32_t idr0; + uint32_t iidr; + uint32_t cr0; + uint32_t cr0ack; + uint64_t gpt_base; + uint64_t gpt_base_cfg; + uint64_t gpf_far; + uint64_t gpt_cfg_far; + uint64_t gpt_base2; +} SMMUv3RootRegBank; + struct SMMUv3State { SMMUState smmu_state; =20 @@ -80,6 +92,7 @@ struct SMMUv3State { OnOffAuto cmdqv; =20 Notifier machine_done; + SMMUv3RootRegBank root; }; =20 typedef enum { --=20 2.43.0 From nobody Sat Oct 24 15:41:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1792143746; cv=none; d=zohomail.com; s=zohoarc; b=nwgZQCVee9cF+GkGk0wCW2oQODVHcMv5R9Lpxsd6vosvomM27AZnefHwD3zmYDUOEquZ+PwqtfULnm8S62rOtEj0OCKV3oVpP7Ncu967fAvVwuP7PjuQUqGrDpE6OlBP4S+Qt8DKLr6dkHfld26KQ4ttlhzVVKygxNxt/UCNf8s= ARC-Message-Signature: i=1; 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Fri, 16 Oct 2026 02:41:31 -0700 (PDT) From: Jim MacArthur Date: Fri, 16 Oct 2026 10:40:52 +0100 Subject: [PATCH 2/2] hw/arm/sbsa-ref.c: Increase SMMU space for Root registers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261016-jmac-smmu-root-registers-v1-2-e78e8879d347@linaro.org> References: <20261016-jmac-smmu-root-registers-v1-0-e78e8879d347@linaro.org> In-Reply-To: <20261016-jmac-smmu-root-registers-v1-0-e78e8879d347@linaro.org> To: qemu-devel@nongnu.org Cc: Eric Auger , Peter Maydell , qemu-arm@nongnu.org, Leif Lindholm , Jim MacArthur X-Mailer: b4 0.17-dev-6be7c Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1792143748492158500 In our implementation, SMMU Root registers are directly after the non-optional SMMU registers. Realms registers will be added above the root registers later. Signed-off-by: Jim MacArthur Acked-by: Leif Lindholm --- hw/arm/sbsa-ref.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 158b461eb4..0747f5ca9f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -129,7 +129,7 @@ static const MemMapEntry sbsa_ref_memmap[] =3D { [SBSA_GPIO] =3D { 0x60020000, 0x00001000 }, [SBSA_SECURE_UART] =3D { 0x60030000, 0x00001000 }, [SBSA_SECURE_UART_MM] =3D { 0x60040000, 0x00001000 }, - [SBSA_SMMU] =3D { 0x60050000, 0x00020000 }, + [SBSA_SMMU] =3D { 0x60050000, 0x00040000 }, /* Space here reserved for more SMMUs */ [SBSA_AHCI] =3D { 0x60100000, 0x00010000 }, [SBSA_XHCI] =3D { 0x60110000, 0x00010000 }, --=20 2.43.0