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[108.93.236.139]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-679b1f0784bsm1720484d50.19.2026.10.16.17.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 17:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1792198699; x=1792803499; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=DkIunV21cUzVdGY+O6vqW5yMBXiu3QheTjcP4l9v15c=; b=e0tUeZlxPy83AOhAqtz9n+iyqwDSVp2mWsadC5E+j9PMTiuQvKtCnVtSX8u7cB4Gah q1lXp0WgJYSkD3kRgsz+eZIVdNA7PRnPdBAfJ3PX49trCGS6hY2Xz3nkXuqgsisE7kOf 8wN9/1k6MPismFfGSa0tXYzMEQMKVEu9urgOjXrNvCBHAp8xiSrDLj0+GL1ljGcDLJSt JyU16aZot2XACupWlueENnrTa4kzPYMFhTMEVBHlv6IzcdmFz5by2r+te6ctDtwHquYQ bD3KxedjShea9wKMcbpP+rXnJAphP/YS0rAir0BCs7Rh87G0W8AHJPB3RxgO7ODVRvT0 hCOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792198699; x=1792803499; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=DkIunV21cUzVdGY+O6vqW5yMBXiu3QheTjcP4l9v15c=; b=UY4NdQj5TAHGD3GiIbm6vnjiLDMHWf6YCFO8as4xRZoi27J1bpSKRUw+dE04Wv3P/L qaFYgOgsxzk7qqEDnnEZsVhHd8AsKXlZJ0cdVbu/sn8RHgoSOOAnY5rePzZQ3btp9SmY WJ6sFLrQl3H3Q+tPbhX3kYjJvedn9Ruq2gqRN88Ayxd5pOEfvyVGSDcahOGBQTEwuYK4 lTikM+5iTsgBrqhlxCyz9ySa83wNBPrPaUItSr9uSq8xrRpfvBbC5X7EnXvkwcUhK+Tk 1STWkgPDjUb6JszIcxYtSBns+EONzLyL9A6KqNffLN5vgjOUULGMfuKRv2thPEdFPuQV mgjw== X-Gm-Message-State: AFq9FYIFJQ2i32uICeRtytd2FhR1T8XcE1yrT8BFksce+2cU/VRTgDKV 1G89xx/2hRphHa2ywaWlmslhgtdUNlHk64JWwWwLroka5KsICeP/cB5haqnTdQ== X-Gm-Gg: AYBFou1a7lni15L34+tZdEV9sfj3eUMsGB0ECWdL75//0NMPU5Qde0/mHhTsijiJ8K5 JZryBq/nHp7YW088RkHUwaWhQkuPB7mXNkMRj5upbYnrwkf3MRuukv+XCSxhTuGLn7D12nxXL/U nx0QCS7K3g0AGvz7AWu3AU//fbmgliqq1GDy9/fgiWFpP3zT8zN1bgKVSxSyrpsjUBOBNs7D8tF SYpyMdcrVVvdZpSILgEHjZs1tWJqgdMOc3gRf4ME1RooZ4vgKnnBOwV+SBuEb2mt9oQdpQHx2eW qTqZ/Q9YRVrsndvfrid284wFkvWGzpARTtWMqjDnyVYe1ljooipldgRTqbiIHnG7sfJnLBRZaFW POnMFW+CrXpZGPW1xkbPuxkzGWrdO3JPeDhzDshetGn0wxLjULU1OdcECbhVlv76tviywCoe4mQ j1oQcBLo/+Oa8u2bqLk8ofIPnTM8GnFRB117av38NTYRCcJuUF6S5/KcXdnzogHUMK2H3PI05Jz fz+6KJPtN/G0UD862tEcADbnva/zNGGhCTT6DNlT2WvOdn9/C+oaevxv5UywAUDHcIBejUSRjAU rwkZGyBPaPHShQi2bDr1qnXg6pPFU9JptsSbGdnf X-Received: by 2002:a05:690e:191c:b0:679:a6c1:d70f with SMTP id 956f58d0204a3-679ca4c92f9mr385349d50.2.1792198698578; Fri, 16 Oct 2026 17:58:18 -0700 (PDT) From: Matt Turner Date: Fri, 16 Oct 2026 20:58:02 -0400 Subject: [PATCH v2 1/2] target/alpha: Record masked exceptions in FPCR for /S insns MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261016-alpha-fpcr-status-s-v2-1-4719bec02b3b@gmail.com> References: <20261016-alpha-fpcr-status-s-v2-0-4719bec02b3b@gmail.com> In-Reply-To: <20261016-alpha-fpcr-status-s-v2-0-4719bec02b3b@gmail.com> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Matt Turner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2160; i=mattst88@gmail.com; h=from:subject:message-id; bh=0pkxiGBvdw6UTe1mcPDHBrjEdVtSijf+h4dRRHjaC3M=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLIunZCapn/S/WKMCEfOkdANSyY+nHRK7rBOzfslrmF/O hRrax9M6PjIwiDGxTBTTJElbr0iy6y2HUt9Tkv/gpnDygQyRFqkgQEIWBj4chPzSo10jPRMtQ31 DIEMHaN4iJweg0ZmcXFpapFuWkGRQ15+SWJJZn5esV5+QWpeQXqBXlpmWklGRn5RcSrQCL281BJ TV0c3I0MDE0tHCzMnC0dTE2dnJ0MnN0dHZ1cnI0tzEwNnS0cTV0tzBi5OAZhrdtxlZHj3SSbt79 2mxK+y3//bbHSaOZn1k3M/+5rjnlO28x/OmveE4Z/Zhx8l967PiC58NC/rcJSOUtJ9Z59aCa7PC +0fvpOQ5+cCAA== X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b130; envelope-from=mattst88@gmail.com; helo=mail-yx1-xb130.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1792198726936158500 The trap qualifiers (/U, /V, /I) control whether an exception traps, but EV6 still records every exception in the FPCR status bits. Commit 471d493047 ("target-alpha: Set fpcr_exc_status even for disabled exceptions") made helper_fp_exc_raise follow this, but in helper_fp_exc_raise_s it only added a second "exc &=3D ~ignore" and left the mask in the initializer, so for insns with software completion the masked exceptions still never reached env->fpcr. The most visible effect is on inexact: the IEEE-mode code generated by gcc -mieee (e.g. ADDT/SU, DIVT/SUD) has no /I qualifier, so FE_INEXACT was never set. Many of glibc's math tests fail because of that, and the narrowing functions such as f32addf64 return results 1ulp off because their round-to-odd step depends on inexact. Record all exceptions first and only then apply the ignore mask, as helper_fp_exc_raise does. Which exceptions trap is unchanged. Fixes: 471d493047 ("target-alpha: Set fpcr_exc_status even for disabled exc= eptions") Signed-off-by: Matt Turner Reviewed-by: Richard Henderson --- target/alpha/fpu_helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 529eadca9f..643ce641e8 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -86,9 +86,17 @@ void helper_fp_exc_raise(CPUAlphaState *env, uint32_t ig= nore, uint32_t regno) /* Raise exceptions for ieee fp insns with software completion. */ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t r= egno) { - uint32_t exc =3D env->error_code & ~ignore; + uint32_t exc =3D env->error_code; if (exc) { + /* + * The qualifiers can suppress the raising of exceptions, + * but real hardware still records that they occurred. + */ env->fpcr |=3D exc; + exc &=3D ~ignore; + if (!exc) { + return; + } exc &=3D env->fpcr_exc_enable; /* * In system mode, the software handler gets invoked --=20 2.55.0 From nobody Fri Oct 23 14:30:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1792198740; cv=none; d=zohomail.com; s=zohoarc; b=TzxWuVOrfEg2TIZ/9FePz6CF3zOK1qrQpiD6zxXl8KondLTcDqs5ffRWYV0lk9TA5+8VgxwsHROpXl4nsmZCGkM7ILgv1g4b9oLmrKM3dgVXNLkv8bsKLLFAjNDemFgiKUb/wawTwbg8WgQrMhxHeRsHgsJyA1RFQoWiMyRgwtY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792198740; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IXNEHBFnJVqtUDewbcVFdo2fMaPeEsitr7a1CmyxrXs=; b=WX8E9sEqXX/Q8dNKR1O0Gk4397azMf+mDPqEKD6/v9mrtLhYlb/3UZMG1TqDGfuLVHV/33PK7d6bl/G9kPBQklck1Gvos+RSRuGHClhFqbfQtshkb60hXngcWN3HxYVkpFSCKT1hJY5u7/8X6d5Ph9b6qsoQsHfMCYOVcggUDTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792198740054159.05165584081692; Fri, 16 Oct 2026 17:59:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHskp-0001VC-4X; Fri, 16 Oct 2026 20:58:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHskm-0001U5-TX for qemu-devel@nongnu.org; Fri, 16 Oct 2026 20:58:28 -0400 Received: from mail-yw1-x1136.google.com ([2607:f8b0:4864:20::1136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHskk-000118-Ur for qemu-devel@nongnu.org; Fri, 16 Oct 2026 20:58:28 -0400 Received: by mail-yw1-x1136.google.com with SMTP id 00721157ae682-8a83d2706fdso3993357b3.0 for ; Fri, 16 Oct 2026 17:58:26 -0700 (PDT) Received: from localhost (108-93-236-139.lightspeed.chtnsc.sbcglobal.net. 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The two disagree about a result that rounds up to the smallest normal: 0x4p-1024 / 0x1.0000000000001p+0 in FE_UPWARD =3D 0x4p-1024 The binade below DBL_MIN has a finer spacing than the denormals, so with an unbounded exponent the quotient rounds to a value below DBL_MIN and softfloat raises underflow. Alpha does not. glibc marks math/test-float32x-float64-div as XFAIL on Alpha because of this (glibc commit a32db99a38), and under qemu that test unexpectedly passes. Every result that is tiny by Alpha's rule is also tiny by the IEEE one, so there is no need for another tininess mode in softfloat. Pass soft_to_fpcr_exc whether the delivered result is normal, and drop underflow when it is. Only the S and T format add, sub, mul, div and cvtts helpers can underflow; the rest pass false. An insn with a denormal operand is different. Unless DNZ is set it traps for software completion and the kernel computes the result, and the kernel's emulation raises underflow in the same situation: 0x3.ffffffffffffcp-1024 / 0x1.fffffffffffffp-1 in FE_UPWARD =3D 0x4p-1024, FPCR_UNF set That result is tiny whether tininess is detected before rounding, as math-emu does, or after rounding, as softfloat does. linux-user computes these results in the helper instead of trapping, so keep softfloat's underflow when float_flag_input_denormal_used is set. That check is for CONFIG_USER_ONLY only: in system mode gen_ieee_input raises the trap before the helper runs, and with DNZ set the operand is flushed rather than used. Signed-off-by: Matt Turner Reviewed-by: Richard Henderson --- target/alpha/fpu_helper.c | 60 +++++++++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 643ce641e8..e91e907c21 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -38,7 +38,11 @@ void helper_setflushzero(CPUAlphaState *env, uint32_t va= l) #define CONVERT_BIT(X, SRC, DST) \ (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) =20 -static uint32_t soft_to_fpcr_exc(CPUAlphaState *env) +/* + * NORMAL is whether the delivered result is normal. Operations that + * cannot underflow pass false. + */ +static uint32_t soft_to_fpcr_exc(CPUAlphaState *env, bool normal) { FloatExceptionFlags exc =3D get_float_exception_flags(&FP_STATUS); uint32_t ret =3D 0; @@ -48,8 +52,24 @@ static uint32_t soft_to_fpcr_exc(CPUAlphaState *env) ret |=3D CONVERT_BIT(exc, float_flag_invalid, FPCR_INV); ret |=3D CONVERT_BIT(exc, float_flag_divbyzero, FPCR_DZE); ret |=3D CONVERT_BIT(exc, float_flag_overflow, FPCR_OVF); - ret |=3D CONVERT_BIT(exc, float_flag_underflow, FPCR_UNF); ret |=3D CONVERT_BIT(exc, float_flag_inexact, FPCR_INE); + + /* + * Alpha raises no underflow when the delivered result is normal. + * softfloat does when that result was rounded up to the smallest + * normal, so drop it. In user mode, a denormal operand means the + * result is the one the kernel's software completion would comput= e, + * and that does raise underflow. + */ + if (exc & float_flag_underflow) { + bool tiny =3D !normal; +#ifdef CONFIG_USER_ONLY + tiny |=3D exc & float_flag_input_denormal_used; +#endif + if (tiny) { + ret |=3D FPCR_UNF; + } + } } =20 return ret; @@ -227,7 +247,7 @@ uint64_t helper_adds(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D s_to_float32(a); fb =3D s_to_float32(b); fr =3D float32_add(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float32_is_normal(fr)); =20 return float32_to_s(fr); } @@ -239,7 +259,7 @@ uint64_t helper_subs(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D s_to_float32(a); fb =3D s_to_float32(b); fr =3D float32_sub(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float32_is_normal(fr)); =20 return float32_to_s(fr); } @@ -251,7 +271,7 @@ uint64_t helper_muls(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D s_to_float32(a); fb =3D s_to_float32(b); fr =3D float32_mul(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float32_is_normal(fr)); =20 return float32_to_s(fr); } @@ -263,7 +283,7 @@ uint64_t helper_alpha_divs(CPUAlphaState *env, uint64_t= a, uint64_t b) fa =3D s_to_float32(a); fb =3D s_to_float32(b); fr =3D float32_div(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float32_is_normal(fr)); =20 return float32_to_s(fr); } @@ -274,7 +294,7 @@ uint64_t helper_sqrts(CPUAlphaState *env, uint64_t a) =20 fa =3D s_to_float32(a); fr =3D float32_sqrt(fa, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return float32_to_s(fr); } @@ -304,7 +324,7 @@ uint64_t helper_addt(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D t_to_float64(a); fb =3D t_to_float64(b); fr =3D float64_add(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float64_is_normal(fr)); =20 return float64_to_t(fr); } @@ -316,7 +336,7 @@ uint64_t helper_subt(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D t_to_float64(a); fb =3D t_to_float64(b); fr =3D float64_sub(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float64_is_normal(fr)); =20 return float64_to_t(fr); } @@ -328,7 +348,7 @@ uint64_t helper_mult(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D t_to_float64(a); fb =3D t_to_float64(b); fr =3D float64_mul(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float64_is_normal(fr)); =20 return float64_to_t(fr); } @@ -340,7 +360,7 @@ uint64_t helper_divt(CPUAlphaState *env, uint64_t a, ui= nt64_t b) fa =3D t_to_float64(a); fb =3D t_to_float64(b); fr =3D float64_div(fa, fb, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float64_is_normal(fr)); =20 return float64_to_t(fr); } @@ -351,7 +371,7 @@ uint64_t helper_sqrtt(CPUAlphaState *env, uint64_t a) =20 fa =3D t_to_float64(a); fr =3D float64_sqrt(fa, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return float64_to_t(fr); } @@ -368,7 +388,7 @@ uint64_t helper_cmptun(CPUAlphaState *env, uint64_t a, = uint64_t b) if (float64_unordered_quiet(fa, fb, &FP_STATUS)) { ret =3D 0x4000000000000000ULL; } - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return ret; } @@ -384,7 +404,7 @@ uint64_t helper_cmpteq(CPUAlphaState *env, uint64_t a, = uint64_t b) if (float64_eq_quiet(fa, fb, &FP_STATUS)) { ret =3D 0x4000000000000000ULL; } - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return ret; } @@ -400,7 +420,7 @@ uint64_t helper_cmptle(CPUAlphaState *env, uint64_t a, = uint64_t b) if (float64_le(fa, fb, &FP_STATUS)) { ret =3D 0x4000000000000000ULL; } - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return ret; } @@ -416,7 +436,7 @@ uint64_t helper_cmptlt(CPUAlphaState *env, uint64_t a, = uint64_t b) if (float64_lt(fa, fb, &FP_STATUS)) { ret =3D 0x4000000000000000ULL; } - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return ret; } @@ -429,7 +449,7 @@ uint64_t helper_cvtts(CPUAlphaState *env, uint64_t a) =20 fa =3D t_to_float64(a); fr =3D float64_to_float32(fa, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, float32_is_normal(fr)); =20 return float32_to_s(fr); } @@ -441,7 +461,7 @@ uint64_t helper_cvtst(CPUAlphaState *env, uint64_t a) =20 fa =3D s_to_float32(a); fr =3D float32_to_float64(fa, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return float64_to_t(fr); } @@ -449,7 +469,7 @@ uint64_t helper_cvtst(CPUAlphaState *env, uint64_t a) uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a) { float32 fr =3D int64_to_float32(a, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); =20 return float32_to_s(fr); } @@ -504,7 +524,7 @@ uint64_t helper_cvttq_c(CPUAlphaState *env, uint64_t a) uint64_t helper_cvtqt(CPUAlphaState *env, uint64_t a) { float64 fr =3D int64_to_float64(a, &FP_STATUS); - env->error_code =3D soft_to_fpcr_exc(env); + env->error_code =3D soft_to_fpcr_exc(env, false); return float64_to_t(fr); } =20 --=20 2.55.0