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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094671079158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 2 - target/hexagon/cpu_helper.h | 6 --- target/hexagon/translate.h | 2 - target/hexagon/cpu.c | 1 - target/hexagon/cpu_helper.c | 79 ------------------------------------- target/hexagon/machine.c | 2 +- target/hexagon/translate.c | 21 ---------- 7 files changed, 1 insertion(+), 112 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 65fd2b29830..2da3b586b5a 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -151,7 +151,6 @@ typedef struct CPUArchState { hex_lock_state_t k0_lock_state; uint32_t tlb_lock_count; uint32_t k0_lock_count; - uint64_t t_cycle_count; #endif uint32_t imprecise_exception; target_ulong new_value_usr; @@ -226,7 +225,6 @@ static inline HexagonHVXContext *hex_hvx(CPUHexagonStat= e *env) =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) FIELD(TB_FLAGS, MMU_INDEX, 1, 3) -FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) FIELD(TB_FLAGS, HVX_COPROC_ENABLED, 5, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 95a8f6587b6..8b1fb98a51a 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -24,11 +24,5 @@ void hexagon_start_threads(CPUHexagonState *env, uint32_= t mask); void hexagon_stop_thread(CPUHexagonState *env); void hexagon_nmi(CPUHexagonState *env, uint32_t thread_mask); void hexagon_resume_threads(CPUHexagonState *env, uint32_t mask); -uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env); -uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env); -uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env); -void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val); -void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val); -void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val); =20 #endif diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 2d1ed5208b7..ccf9d52997a 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -97,10 +97,8 @@ typedef struct DisasContext { TCGv new_pred_value[NUM_PREGS]; TCGv branch_taken; TCGv dczero_addr; - bool pcycle_enabled; bool hvx_coproc_enabled; bool hvx_check_emitted; - uint32_t num_cycles; } DisasContext; =20 bool is_gather_store_insn(DisasContext *ctx); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 6550e7fa800..1bdc3d8aed6 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -349,7 +349,6 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState = *cs) cpu =3D env_archcpu(env); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, cpu_mmu_index(env_cpu(env), false)); - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED, cpu->hvx_ctx[0] && GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]= )); diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index c2fc27f1c02..1fdd81ad9b4 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -132,85 +132,6 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_= env, int index) g_assert_not_reached(); } =20 -uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env) -{ - uint64_t total =3D 0; - CPUState *cs; - - BQL_LOCK_GUARD(); - CPU_FOREACH(cs) { - CPUHexagonState *thread_env =3D cpu_env(cs); - total +=3D thread_env->t_cycle_count; - } - return total; -} - -uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env) -{ - return (uint32_t)(hexagon_get_sys_pcycle_count(env) >> 32); -} - -uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) -{ - return (uint32_t)(hexagon_get_sys_pcycle_count(env)); -} - -/* - * Every function in this family takes the BQL itself, so the guard below - * holds it across the read-modify-write. Nested guards are no-ops. - */ -void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val) -{ - uint64_t old; - - BQL_LOCK_GUARD(); - old =3D hexagon_get_sys_pcycle_count(env); - old =3D deposit64(old, 32, 32, val); - hexagon_set_sys_pcycle_count(env, old); -} - -void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val) -{ - uint64_t old; - - BQL_LOCK_GUARD(); - old =3D hexagon_get_sys_pcycle_count(env); - old =3D deposit64(old, 0, 32, val); - hexagon_set_sys_pcycle_count(env, old); -} - -void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val) -{ - CPUState *cs; - uint64_t total; - int num_threads; - int64_t delta, per_thread, remainder; - - BQL_LOCK_GUARD(); - total =3D hexagon_get_sys_pcycle_count(env); - - /* Count active threads */ - num_threads =3D 0; - CPU_FOREACH(cs) { - num_threads++; - } - g_assert(num_threads > 0); - - /* - * Distribute the delta evenly across all threads. - * Any remainder goes to the calling thread. - */ - delta =3D (int64_t)(val - total); - per_thread =3D delta / num_threads; - remainder =3D delta - per_thread * num_threads; - - CPU_FOREACH(cs) { - CPUHexagonState *thread_env =3D cpu_env(cs); - thread_env->t_cycle_count +=3D per_thread; - } - env->t_cycle_count +=3D remainder; -} - static void hexagon_resume_thread(CPUHexagonState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index f3e97224d81..36fee33d333 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -35,7 +35,7 @@ const VMStateDescription vmstate_hexagon_cpu =3D { VMSTATE_UINT32(env.k0_lock_count, HexagonCPU), VMSTATE_UINT32(env.threadId, HexagonCPU), VMSTATE_UINT32(env.cause_code, HexagonCPU), - VMSTATE_UINT64(env.t_cycle_count, HexagonCPU), + VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_UINT32(env.imprecise_exception, HexagonCPU), =20 VMSTATE_END_OF_LIST() diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index cd1abdf1461..beee09bc4cb 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -63,7 +63,6 @@ TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; #ifndef CONFIG_USER_ONLY -TCGv_i64 hex_cycle_count; TCGv hex_imprecise_exception; #endif TCGv hex_vstore_addr[VSTORES_MAX]; @@ -144,16 +143,6 @@ static void gen_precise_exception(int cause, uint32_t = PC) tcg_constant_i32(PC)); } =20 -#ifndef CONFIG_USER_ONLY -static void gen_pcycle_counters(DisasContext *ctx) -{ - if (ctx->pcycle_enabled) { - tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles= ); - } -} -#endif - - static void gen_exec_counters(DisasContext *ctx) { tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], @@ -162,9 +151,6 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); -#ifndef CONFIG_USER_ONLY - gen_pcycle_counters(ctx); -#endif } =20 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -1128,8 +1114,6 @@ static void gen_commit_hvx(DisasContext *ctx) } } =20 -#define PCYCLES_PER_PACKET 1 - static void update_exec_counters(DisasContext *ctx) { int num_real_insns =3D 0; @@ -1149,7 +1133,6 @@ static void update_exec_counters(DisasContext *ctx) ctx->num_packets++; ctx->num_insns +=3D num_real_insns; ctx->num_hvx_insns +=3D num_hvx_insns; - ctx->num_cycles +=3D PCYCLES_PER_PACKET; } =20 #ifndef CONFIG_USER_ONLY @@ -1335,8 +1318,6 @@ static void hexagon_tr_init_disas_context(DisasContex= tBase *dcbase, ctx->hex_def =3D HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def; ctx->ieee_fp_extension =3D hex_cpu->cfg.ieee_fp_extension; #ifndef CONFIG_USER_ONLY - ctx->num_cycles =3D 0; - ctx->pcycle_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED= ); ctx->hvx_coproc_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED); ctx->hvx_check_emitted =3D false; @@ -1489,8 +1470,6 @@ void hexagon_translate_init(void) hex_cause_code =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUHexagonState, cause_code), "cause_code"); #ifndef CONFIG_USER_ONLY - hex_cycle_count =3D tcg_global_mem_new_i64(tcg_env, - offsetof(CPUHexagonState, t_cycle_count), "t_cycle_count"); hex_imprecise_exception =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, imprecise_exception), "imprecise_excepti= on"); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094675168158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon_globalreg.h | 5 + target/hexagon/helper.h | 2 + hw/hexagon/hexagon_globalreg.c | 129 +++++++++++++++++++++++++ target/hexagon/cpu.c | 9 +- target/hexagon/genptr.c | 8 ++ target/hexagon/hexswi.c | 10 +- target/hexagon/op_helper.c | 45 +++++++++ hw/hexagon/trace-events | 1 + 8 files changed, 205 insertions(+), 4 deletions(-) diff --git a/include/hw/hexagon/hexagon_globalreg.h b/include/hw/hexagon/he= xagon_globalreg.h index 07437dfabb1..2d5c3c166b1 100644 --- a/include/hw/hexagon/hexagon_globalreg.h +++ b/include/hw/hexagon/hexagon_globalreg.h @@ -33,6 +33,10 @@ struct HexagonGlobalRegState { /* Global performance cycle counter base */ uint64_t g_pcycle_base; =20 + /* Global performance cycle counter clock state */ + int64_t pcycle_start_ns; + bool pcycle_running; + /* Properties for global register reset values */ uint32_t boot_evb; /* Boot Exception Vector Base (HEX_SREG_E= VB) */ uint64_t config_table_addr; /* Configuration table base */ @@ -56,6 +60,7 @@ void hexagon_globalreg_write_masked(HexagonGlobalRegState= *s, uint32_t reg, uint32_t value); =20 /* Global performance cycle counter access */ +uint64_t hexagon_globalreg_read_pcycle(HexagonGlobalRegState *s); uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s); void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s, uint64_t value); diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 997d87e38e6..47958c48ea9 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -130,6 +130,8 @@ DEF_HELPER_2(getimask, i32, env, i32) DEF_HELPER_3(setimask, void, env, i32, i32) DEF_HELPER_2(sreg_read, i32, env, i32) DEF_HELPER_2(sreg_read_pair, i64, env, i32) +DEF_HELPER_2(upcycle_read, i32, env, i32) +DEF_HELPER_1(upcycle_read_pair, i64, env) DEF_HELPER_2(greg_read, i32, env, i32) DEF_HELPER_2(greg_read_pair, i64, env, i32) DEF_HELPER_3(sreg_write_masked, void, env, i32, i32) diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c index 616cddf3048..22ec4020665 100644 --- a/hw/hexagon/hexagon_globalreg.c +++ b/hw/hexagon/hexagon_globalreg.c @@ -18,6 +18,7 @@ #include "target/hexagon/cpu.h" #include "target/hexagon/hex_regs.h" #include "qemu/log.h" +#include "qemu/timer.h" #include "trace.h" #include "qapi/error.h" =20 @@ -157,6 +158,85 @@ static inline bool is_timer_reg(uint32_t reg) return reg =3D=3D HEX_SREG_TIMERLO || reg =3D=3D HEX_SREG_TIMERHI; } =20 +static inline bool is_pcycle_reg(uint32_t reg) +{ + return reg =3D=3D HEX_SREG_PCYCLELO || reg =3D=3D HEX_SREG_PCYCLEHI; +} + +static inline bool modectl_any_thread_running(uint32_t modectl) +{ + uint32_t enabled =3D modectl & 0xffff; + uint32_t waiting =3D modectl >> 16; + return (enabled & ~waiting) !=3D 0; +} + +static uint64_t pcycle_value_now(HexagonGlobalRegState *s) +{ + uint64_t cycles =3D s->g_pcycle_base; + + if (s->pcycle_running) { + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int64_t elapsed =3D now - s->pcycle_start_ns; + + if (elapsed > 0) { + cycles +=3D elapsed; + } + } + return cycles; +} + +static void pcycle_fold(HexagonGlobalRegState *s) +{ + int64_t now; + int64_t elapsed; + + if (!s->pcycle_running) { + return; + } + + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + elapsed =3D now - s->pcycle_start_ns; + if (elapsed > 0) { + s->g_pcycle_base +=3D elapsed; + } + s->pcycle_start_ns =3D now; +} + +static bool pcycle_enabled(uint32_t syscfg) +{ + return extract32(syscfg, reg_field_info[SYSCFG_PCYCLEEN].offset, + reg_field_info[SYSCFG_PCYCLEEN].width); +} + +uint64_t hexagon_globalreg_read_pcycle(HexagonGlobalRegState *s) +{ + g_assert(s); + return pcycle_enabled(s->regs[HEX_SREG_SYSCFG]) ? + pcycle_value_now(s) : 0; +} +static void pcycle_set_running(HexagonGlobalRegState *s, bool running) +{ + if (running =3D=3D s->pcycle_running) { + return; + } + if (running) { + s->pcycle_start_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } else { + s->g_pcycle_base =3D pcycle_value_now(s); + } + s->pcycle_running =3D running; + trace_hexagon_pcycle_run_state(s->pcycle_running, s->g_pcycle_base); +} + +static void pcycle_write(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value) +{ + pcycle_fold(s); + s->g_pcycle_base =3D deposit64(s->g_pcycle_base, + reg =3D=3D HEX_SREG_PCYCLELO ? 0 : 32, 32, + value); +} + static uint32_t get_reg_value(HexagonGlobalRegState *s, uint32_t reg) { if (is_vid_reg(reg)) { @@ -167,16 +247,38 @@ static uint32_t get_reg_value(HexagonGlobalRegState *= s, uint32_t reg) qct_qtimer_get_timer_lo(s->qtimer) : qct_qtimer_get_timer_hi(s->qtimer); } + if (is_pcycle_reg(reg)) { + uint64_t value =3D hexagon_globalreg_read_pcycle(s); + return reg =3D=3D HEX_SREG_PCYCLELO ? + (uint32_t)value : (uint32_t)(value >> 32); + } return s->regs[reg]; } =20 static void set_reg_value(HexagonGlobalRegState *s, uint32_t reg, uint32_t value) { + bool pcycle_enable =3D reg =3D=3D HEX_SREG_SYSCFG && + !pcycle_enabled(s->regs[reg]) && pcycle_enabled(value); + + if (is_pcycle_reg(reg)) { + pcycle_write(s, reg, value); + return; + } + s->regs[reg] =3D value; + if (pcycle_enable) { + s->g_pcycle_base =3D 0; + if (s->pcycle_running) { + s->pcycle_start_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + } if (is_vid_reg(reg)) { l2vic_update_vid(s->l2vic, reg =3D=3D HEX_SREG_VID ? 0 : 1, value); } + if (reg =3D=3D HEX_SREG_MODECTL) { + pcycle_set_running(s, modectl_any_thread_running(value)); + } } =20 uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, @@ -256,6 +358,7 @@ static void do_hexagon_globalreg_reset(HexagonGlobalReg= State *s) memset(s->regs, 0, sizeof(s->regs)); =20 s->g_pcycle_base =3D 0; + s->pcycle_running =3D false; =20 s->regs[HEX_SREG_EVB] =3D s->boot_evb; s->regs[HEX_SREG_CFGBASE] =3D HEXAGON_CFG_ADDR_BASE(s->config_table_ad= dr); @@ -275,6 +378,8 @@ static void do_hexagon_globalreg_reset(HexagonGlobalReg= State *s) } s->regs[HEX_SREG_ISDBEN] =3D isdben_val; s->regs[HEX_SREG_MODECTL] =3D 0x1; + pcycle_set_running(s, + modectl_any_thread_running(s->regs[HEX_SREG_MODECTL= ])); =20 /* * These register indices are placeholders in these arrays @@ -316,10 +421,34 @@ static void hexagon_globalreg_realize(DeviceState *de= v, Error **errp) } } =20 +static int hexagon_globalreg_pre_save(void *opaque) +{ + HexagonGlobalRegState *s =3D opaque; + + /* Migrate a stable value, not a timestamp from the source clock. */ + pcycle_fold(s); + return 0; +} + +static int hexagon_globalreg_post_load(void *opaque, + int version_id G_GNUC_UNUSED) +{ + HexagonGlobalRegState *s =3D opaque; + + s->pcycle_running =3D modectl_any_thread_running( + s->regs[HEX_SREG_MODECTL]); + if (s->pcycle_running) { + s->pcycle_start_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + return 0; +} + static const VMStateDescription vmstate_hexagon_globalreg =3D { .name =3D "hexagon_globalreg", .version_id =3D 1, .minimum_version_id =3D 1, + .pre_save =3D hexagon_globalreg_pre_save, + .post_load =3D hexagon_globalreg_post_load, .fields =3D (const VMStateField[]){ VMSTATE_UINT32_ARRAY(regs, HexagonGlobalRegState, NUM_SREGS), VMSTATE_UINT64(g_pcycle_base, HexagonGlobalRegState), diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1bdc3d8aed6..796bb6df9db 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -861,15 +861,20 @@ uint32_t hexagon_greg_read(CPUHexagonState *env, uint= 32_t reg) { uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; int ssr_ce =3D GET_SSR_FIELD(SSR_CE, ssr); + HexagonCPU *cpu =3D env_archcpu(env); =20 if (reg <=3D HEX_GREG_G3) { return env->greg[reg]; } switch (reg) { case HEX_GREG_GPCYCLELO: - return ssr_ce ? hexagon_get_sys_pcycle_count_low(env) : 0; + return ssr_ce ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_PCYCLELO, + env->threadId) : 0; case HEX_GREG_GPCYCLEHI: - return ssr_ce ? hexagon_get_sys_pcycle_count_high(env) : 0; + return ssr_ce ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_PCYCLEHI, + env->threadId) : 0; default: return env->greg[reg]; } diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 90197c6e72e..e19b9c359b3 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -443,6 +443,12 @@ static inline void gen_read_ctrl_reg(DisasContext *ctx= , const int reg_num, } else if (reg_num =3D=3D HEX_REG_UTIMERHI) { gen_helper_sreg_read(dest, tcg_env, tcg_constant_i32(HEX_SREG_TIMERHI)); + } else if (reg_num =3D=3D HEX_REG_UPCYCLELO) { + gen_helper_upcycle_read(dest, tcg_env, + tcg_constant_i32(HEX_SREG_PCYCLELO)); + } else if (reg_num =3D=3D HEX_REG_UPCYCLEHI) { + gen_helper_upcycle_read(dest, tcg_env, + tcg_constant_i32(HEX_SREG_PCYCLEHI)); #else } else if (reg_num =3D=3D HEX_REG_UTIMERLO) { TCGv_i64 utimer =3D tcg_temp_new_i64(); @@ -488,6 +494,8 @@ static inline void gen_read_ctrl_reg_pair(DisasContext = *ctx, const int reg_num, gen_helper_sreg_read(lo, tcg_env, tcg_constant_i32(HEX_SREG_TIMERL= O)); gen_helper_sreg_read(hi, tcg_env, tcg_constant_i32(HEX_SREG_TIMERH= I)); tcg_gen_concat_i32_i64(dest, lo, hi); + } else if (reg_num =3D=3D HEX_REG_UPCYCLELO) { + gen_helper_upcycle_read_pair(dest, tcg_env); #else } else if (reg_num =3D=3D HEX_REG_UTIMERLO) { /* One helper call, so the pair is a coherent 64-bit snapshot. */ diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index ef1d558dfc4..e7362b56650 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -692,8 +692,14 @@ static void sim_handle_trap0(CPUHexagonState *env) =20 case HEX_SYS_READ_PCYCLES: { - env->gpr[HEX_REG_R00] =3D hexagon_get_sys_pcycle_count_low(env); - env->gpr[HEX_REG_R01] =3D hexagon_get_sys_pcycle_count_high(env); + HexagonCPU *cpu =3D env_archcpu(env); + uint64_t pcycles; + + BQL_LOCK_GUARD(); + pcycles =3D cpu->globalregs ? + hexagon_globalreg_read_pcycle(cpu->globalregs) : 0; + env->gpr[HEX_REG_R00] =3D (uint32_t)pcycles; + env->gpr[HEX_REG_R01] =3D (uint32_t)(pcycles >> 32); break; } =20 diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index accadd7927a..8c292854de3 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1943,27 +1943,72 @@ uint32_t HELPER(sreg_read)(CPUHexagonState *env, ui= nt32_t reg) =20 uint64_t HELPER(sreg_read_pair)(CPUHexagonState *env, uint32_t reg) { + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); =20 + if (reg =3D=3D HEX_SREG_PCYCLELO && cpu->globalregs) { + return hexagon_globalreg_read_pcycle(cpu->globalregs); + } return deposit64((uint64_t) sreg_read(env, reg), 32, 32, sreg_read(env, reg + 1)); } =20 +/* + * UPCYCLELO/UPCYCLEHI are the user-visible alias of PCYCLELO/PCYCLEHI, + * readable without privilege but only once SSR[CE] is set. + */ +uint32_t HELPER(upcycle_read)(CPUHexagonState *env, uint32_t sreg) +{ + uint32_t ssr; + + BQL_LOCK_GUARD(); + ssr =3D env->t_sreg[HEX_SREG_SSR]; + if (!GET_SSR_FIELD(SSR_CE, ssr)) { + return 0; + } + return sreg_read(env, sreg); +} + +uint64_t HELPER(upcycle_read_pair)(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ssr; + + BQL_LOCK_GUARD(); + ssr =3D env->t_sreg[HEX_SREG_SSR]; + if (!GET_SSR_FIELD(SSR_CE, ssr)) { + return 0; + } + return cpu->globalregs ? + hexagon_globalreg_read_pcycle(cpu->globalregs) : 0; +} + uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg) =20 { + BQL_LOCK_GUARD(); return hexagon_greg_read(env, reg); } =20 uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg) =20 { + HexagonCPU *cpu =3D env_archcpu(env); + + BQL_LOCK_GUARD(); g_assert((reg & 1) =3D=3D 0); =20 if (reg =3D=3D HEX_GREG_G0 || reg =3D=3D HEX_GREG_G2) { return (uint64_t)(env->greg[reg]) | (((uint64_t)(env->greg[reg + 1])) << 32); } + if (reg =3D=3D HEX_GREG_GPCYCLELO) { + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + + return GET_SSR_FIELD(SSR_CE, ssr) && cpu->globalregs ? + hexagon_globalreg_read_pcycle(cpu->globalregs) : 0; + } return (uint64_t)hexagon_greg_read(env, reg) | ((uint64_t)(hexagon_greg_read(env, reg + 1)) << 32); } diff --git a/hw/hexagon/trace-events b/hw/hexagon/trace-events index 5d623ed2516..8c906a30ebd 100644 --- a/hw/hexagon/trace-events +++ b/hw/hexagon/trace-events @@ -1,3 +1,4 @@ # Hexagon global register access hexagon_globalreg_read(uint32_t htid, const char *reg_name, uint32_t value= ) "htid=3D%u reg=3D%s value=3D0x%x" hexagon_globalreg_write(uint32_t htid, const char *reg_name, uint32_t valu= e) "htid=3D%u reg=3D%s value=3D0x%x" +hexagon_pcycle_run_state(bool running, uint64_t base) "running=3D%u base= =3D%" PRIu64 --=20 2.34.1 From nobody Fri Oct 23 14:30:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094667014158500 Mark scalar and pair reads of *PCYCLE* regs as I/O so icount synchronizes before reading. Cover the read paths of {U,G}{PCYCLE,TIMER}{LO,HI,} registers. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 8 ++++++-- target/hexagon/genptr.c | 30 ++++++++++++++++++++++++++---- target/hexagon/hex_common.py | 8 ++++---- 3 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index c9f6b41a877..413ccc97f7b 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/target/hexagon/gen_tcg_sys.h @@ -84,10 +84,14 @@ } while (0) =20 #define fGEN_TCG_Y2_resume(SHORTCODE) \ - gen_helper_resume(tcg_env, RsV) + do { \ + gen_helper_resume(tcg_env, RsV); \ + } while (0) =20 #define fGEN_TCG_Y2_start(SHORTCODE) \ - gen_helper_start(tcg_env, RsV) + do { \ + gen_helper_start(tcg_env, RsV); \ + } while (0) =20 #define fGEN_TCG_Y2_stop(SHORTCODE) \ do { \ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index e19b9c359b3..1a68d8c1b8d 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -297,6 +297,9 @@ static void gen_log_sreg_write(DisasContext *ctx, int r= num, TCGv_i32 val) { uint32_t reg_mask =3D sreg_immut_masks[rnum]; =20 + if (rnum =3D=3D HEX_SREG_MODECTL || rnum =3D=3D HEX_SREG_SYSCFG) { + translator_io_start(&ctx->base); + } if (rnum =3D=3D HEX_SREG_IMASK && ctx->hex_def->hex_version < HEX_VER_V81) { reg_mask =3D 0xffff0000; @@ -331,8 +334,12 @@ static void gen_log_sreg_write_pair(DisasContext *ctx,= int rnum, TCGv_i64 val) } =20 G_GNUC_UNUSED -static void gen_read_sreg(TCGv_i32 dst, int reg_num) +static void gen_read_sreg(DisasContext *ctx, TCGv_i32 dst, int reg_num) { + if (reg_num =3D=3D HEX_SREG_TIMERLO || reg_num =3D=3D HEX_SREG_TIMERHI= || + reg_num =3D=3D HEX_SREG_PCYCLELO || reg_num =3D=3D HEX_SREG_PCYCLE= HI) { + translator_io_start(&ctx->base); + } if (reg_num >=3D HEX_SREG_GLB_START || reg_num =3D=3D HEX_SREG_BADVA) { gen_helper_sreg_read(dst, tcg_env, tcg_constant_i32(reg_num)); } else { @@ -341,8 +348,11 @@ static void gen_read_sreg(TCGv_i32 dst, int reg_num) } =20 G_GNUC_UNUSED -static void gen_read_sreg_pair(TCGv_i64 dst, int reg_num) +static void gen_read_sreg_pair(DisasContext *ctx, TCGv_i64 dst, int reg_nu= m) { + if (reg_num =3D=3D HEX_SREG_TIMERLO || reg_num =3D=3D HEX_SREG_PCYCLEL= O) { + translator_io_start(&ctx->base); + } if (reg_num < HEX_SREG_GLB_START) { if (reg_num + 1 =3D=3D HEX_SREG_BADVA) { TCGv_i32 badva =3D tcg_temp_new_i32(); @@ -359,8 +369,11 @@ static void gen_read_sreg_pair(TCGv_i64 dst, int reg_n= um) } =20 G_GNUC_UNUSED -static void gen_read_greg(TCGv_i32 dst, int reg_num) +static void gen_read_greg(DisasContext *ctx, TCGv_i32 dst, int reg_num) { + if (reg_num =3D=3D HEX_GREG_GPCYCLELO || reg_num =3D=3D HEX_GREG_GPCYC= LEHI) { + translator_io_start(&ctx->base); + } if (reg_num <=3D HEX_GREG_G3) { tcg_gen_mov_i32(dst, hex_greg[reg_num]); } else { @@ -369,8 +382,11 @@ static void gen_read_greg(TCGv_i32 dst, int reg_num) } =20 G_GNUC_UNUSED -static void gen_read_greg_pair(TCGv_i64 dst, int reg_num) +static void gen_read_greg_pair(DisasContext *ctx, TCGv_i64 dst, int reg_nu= m) { + if (reg_num =3D=3D HEX_GREG_GPCYCLELO) { + translator_io_start(&ctx->base); + } if (reg_num =3D=3D HEX_GREG_G0 || reg_num =3D=3D HEX_GREG_G2) { tcg_gen_concat_i32_i64(dst, hex_greg[reg_num], hex_greg[reg_num + 1]); @@ -438,15 +454,19 @@ static inline void gen_read_ctrl_reg(DisasContext *ct= x, const int reg_num, ctx->num_hvx_insns); #ifndef CONFIG_USER_ONLY } else if (reg_num =3D=3D HEX_REG_UTIMERLO) { + translator_io_start(&ctx->base); gen_helper_sreg_read(dest, tcg_env, tcg_constant_i32(HEX_SREG_TIMERLO)); } else if (reg_num =3D=3D HEX_REG_UTIMERHI) { + translator_io_start(&ctx->base); gen_helper_sreg_read(dest, tcg_env, tcg_constant_i32(HEX_SREG_TIMERHI)); } else if (reg_num =3D=3D HEX_REG_UPCYCLELO) { + translator_io_start(&ctx->base); gen_helper_upcycle_read(dest, tcg_env, tcg_constant_i32(HEX_SREG_PCYCLELO)); } else if (reg_num =3D=3D HEX_REG_UPCYCLEHI) { + translator_io_start(&ctx->base); gen_helper_upcycle_read(dest, tcg_env, tcg_constant_i32(HEX_SREG_PCYCLEHI)); #else @@ -489,12 +509,14 @@ static inline void gen_read_ctrl_reg_pair(DisasContex= t *ctx, const int reg_num, tcg_gen_concat_i32_i64(dest, hvx_cnt, hex_gpr[reg_num + 1]); #ifndef CONFIG_USER_ONLY } else if (reg_num =3D=3D HEX_REG_UTIMERLO) { + translator_io_start(&ctx->base); TCGv lo =3D tcg_temp_new(); TCGv hi =3D tcg_temp_new(); gen_helper_sreg_read(lo, tcg_env, tcg_constant_i32(HEX_SREG_TIMERL= O)); gen_helper_sreg_read(hi, tcg_env, tcg_constant_i32(HEX_SREG_TIMERH= I)); tcg_gen_concat_i32_i64(dest, lo, hi); } else if (reg_num =3D=3D HEX_REG_UPCYCLELO) { + translator_io_start(&ctx->base); gen_helper_upcycle_read_pair(dest, tcg_env); #else } else if (reg_num =3D=3D HEX_REG_UTIMERLO) { diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 9d4650f52fb..94e70b8657d 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1244,7 +1244,7 @@ def decl_tcg(self, f, tag, regno): self.gen_check_impl(f, regno) f.write(code_fmt(f"""\ TCGv_i32 {self.reg_tcg()} =3D tcg_temp_new_i32(); - gen_read_greg({self.reg_tcg()}, {self.reg_num}); + gen_read_greg(ctx, {self.reg_tcg()}, {self.reg_num}); """)) def analyze_read(self, f, regno): pass @@ -1275,7 +1275,7 @@ def decl_tcg(self, f, tag, regno): self.gen_check_impl(f, regno) f.write(code_fmt(f"""\ TCGv_i64 {self.reg_tcg()} =3D tcg_temp_new_i64(); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094626262158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- include/exec/translator.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 104e6d4f361..4e6e424e7cf 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -168,9 +168,8 @@ bool translator_use_goto_tb(DisasContextBase *db, vaddr= dest); * translator_io_start * @db: Disassembly context * - * If icount is enabled, set cpu->can_do_io, adjust db->is_jmp to - * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true. - * Otherwise return false. + * Adjust db->is_jmp to DISAS_TOO_MANY if it is still DISAS_NEXT and return + * true. The instruction will then be the last instruction in the TB. */ bool translator_io_start(DisasContextBase *db); =20 --=20 2.34.1 From nobody Fri Oct 23 14:30:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792094680; cv=none; d=zohomail.com; s=zohoarc; b=UrB7EzA/rOBnQdee42K0RspXo12eLPmfkICwwu8Mzn8pAJn0NHW2GkiAKdUxK5ZuGAtkUHaei3DriAqLKTg3HJKHiPM+wV6alTz2JvhoAgY8Gn4fBzbDrPRmgZBHxUSY7MPkkoylAiAenl01GcflP2gJGjFDvrypCbaJysnunKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792094680; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s3ooICaj01Zvsubfx0Nme1qs6VRzP6EX60pJq4RBxv4=; b=k3g0VxleJBbb/Zq2O3soUtmb7IxEOuwn/8dOdVMMSdkHxfPTJQ+Qf1FIGtVJNJkv4RB7sxfJv6cJpF/9kspqfVVH9MfQeOEj6ttcIPZhL/yqA4drGB84EBNz+j2NzXQwpcEaAgkLgSL+G4+Ot0+nujnZBAPFomoSHMo0r7H3/Xs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792094680255434.0610218684676; Thu, 15 Oct 2026 13:04:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHRfx-0003Ra-CX; Thu, 15 Oct 2026 16:03:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHRft-0003LF-6Y for qemu-devel@nongnu.org; Thu, 15 Oct 2026 16:03:37 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHRfq-0003EO-1s for qemu-devel@nongnu.org; Thu, 15 Oct 2026 16:03:36 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69FFd1uv2416945 for ; Thu, 15 Oct 2026 20:03:32 GMT Received: from mail-dl1-f70.google.com (mail-dl1-f70.google.com [74.125.82.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4haqdhkv9s-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 15 Oct 2026 20:03:32 +0000 (GMT) Received: by mail-dl1-f70.google.com with SMTP id a92af1059eb24-1383723dfddso4662539c88.0 for ; Thu, 15 Oct 2026 13:03:32 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094681203158500 Fixes: 9831d3cab168 ("target/hexagon: Add privilege check, use tag_ignore()= ") Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 1 + target/hexagon/cpu.c | 2 ++ target/hexagon/translate.c | 15 +++++++++++++++ target/hexagon/gen_tcg_funcs.py | 16 ++++++++++------ 5 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2da3b586b5a..c1a944920e8 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -226,6 +226,7 @@ static inline HexagonHVXContext *hex_hvx(CPUHexagonStat= e *env) FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) FIELD(TB_FLAGS, MMU_INDEX, 1, 3) FIELD(TB_FLAGS, HVX_COPROC_ENABLED, 5, 1) +FIELD(TB_FLAGS, CPU_MODE, 6, 2) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index ccf9d52997a..dc0c6b18bf1 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -45,6 +45,7 @@ typedef struct DisasContext { DECLARE_BITMAP(gpr_uncond, TOTAL_PER_THREAD_REGS); bool implicit_usr_write; #ifndef CONFIG_USER_ONLY + uint32_t cpu_mode; int greg_log[GREG_WRITES_MAX]; int greg_log_idx; DECLARE_BITMAP(gregs_written, NUM_GREGS); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 796bb6df9db..474c4b3c550 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -352,6 +352,8 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState = *cs) hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED, cpu->hvx_ctx[0] && GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]= )); + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, CPU_MODE, + get_cpu_mode(env)); #else hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); #endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index beee09bc4cb..e2a5038a1a5 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1289,6 +1289,20 @@ static void decode_and_translate_packet(CPUHexagonSt= ate *env, DisasContext *ctx) HEX_CAUSE_REG_WRITE_CONFLICT); return; } +#ifndef CONFIG_USER_ONLY + if (check_for_attrib(&ctx->pkt, A_PRIV) && + ctx->cpu_mode !=3D HEX_CPU_MODE_MONITOR) { + hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_SINSN); + ctx->base.pc_next +=3D ctx->pkt.encod_pkt_size_in_bytes; + return; + } + if (check_for_attrib(&ctx->pkt, A_GUEST) && + ctx->cpu_mode =3D=3D HEX_CPU_MODE_USER) { + hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_GINSN); + ctx->base.pc_next +=3D ctx->pkt.encod_pkt_size_in_bytes; + return; + } +#endif gen_start_packet(ctx); for (i =3D 0; i < ctx->pkt.num_insns; i++) { ctx->insn =3D &ctx->pkt.insn[i]; @@ -1321,6 +1335,7 @@ static void hexagon_tr_init_disas_context(DisasContex= tBase *dcbase, ctx->hvx_coproc_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED); ctx->hvx_check_emitted =3D false; + ctx->cpu_mode =3D FIELD_EX32(hex_flags, TB_FLAGS, CPU_MODE); #endif } =20 diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index b09ce7c285f..61effa38cfa 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -58,16 +58,20 @@ def gen_tcg_func(f, tag, regs, imms): =20 f.write(" Insn *insn G_GNUC_UNUSED =3D ctx->insn;\n") =20 - if "A_PRIV" in hex_common.attribdict[tag]: + if ( + "A_PRIV" in hex_common.attribdict[tag] + or "A_GUEST" in hex_common.attribdict[tag] + ): f.write(dedent("""\ #ifdef CONFIG_USER_ONLY - hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_SINSN); -#else """)) - if "A_GUEST" in hex_common.attribdict[tag]: + if "A_PRIV" in hex_common.attribdict[tag]: + f.write(" hex_gen_exception_end_tb(ctx, " + "HEX_CAUSE_PRIV_USER_NO_SINSN);\n") + else: + f.write(" hex_gen_exception_end_tb(ctx, " + "HEX_CAUSE_PRIV_USER_NO_GINSN);\n") f.write(dedent("""\ -#ifdef CONFIG_USER_ONLY - hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_GINSN); #else """)) if hex_common.need_ea(tag): --=20 2.34.1 From nobody Fri Oct 23 14:30:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792094667; cv=none; d=zohomail.com; s=zohoarc; b=VsCrHOWWFFXsvEKExyEx7FHucbKUUqBhfvTO11Lpdhyz15JdOMdGw9hCAer/AGgJ8CsE624tpEvEgAkeFAcL3cj3tuZz7nKYu+isZ2+mrnIDm0MBOe1L1srdaxBngmbZy5iKWzljYWGNxRJ0uRveArCdaqYnq7uPHnAbUiXyn7E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094669028158500 Wake the selected K0 or TLB lock waiter when ownership passes. Update its interrupt state and kick the vCPU. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 2 ++ target/hexagon/hex_interrupts.c | 8 ++++++-- target/hexagon/hex_mmu.c | 3 +++ target/hexagon/op_helper.c | 2 ++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 1fdd81ad9b4..6f172270865 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -373,6 +373,7 @@ static uint32_t set_enable_mask(CPUHexagonState *env) thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); thread_enabled_mask |=3D 0x1 << env->threadId; SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_E, thread_enabled_mask= ); + hex_interrupt_update(env); return thread_enabled_mask; } =20 @@ -393,6 +394,7 @@ static uint32_t clear_enable_mask(CPUHexagonState *env) thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); thread_enabled_mask &=3D ~(0x1 << env->threadId); SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_E, thread_enabled_mask= ); + hex_interrupt_update(env); return thread_enabled_mask; } static void do_start_thread(CPUState *cs, run_on_cpu_data tbd) diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupt= s.c index ab66d548a1e..03e1f28da9b 100644 --- a/target/hexagon/hex_interrupts.c +++ b/target/hexagon/hex_interrupts.c @@ -240,8 +240,10 @@ static bool hex_is_qualified_for_int(CPUHexagonState *= env, int int_num) bool ssr_ie =3D get_ssr_ie(env); bool ssr_ex =3D get_ssr_ex(env); bool imask =3D get_imask_bit(env, int_num); + bool lock_pending =3D env->k0_lock_state !=3D HEX_LOCK_UNLOCKED || + env->tlb_lock_state !=3D HEX_LOCK_UNLOCKED; =20 - return syscfg_gie && !iad && ssr_ie && !ssr_ex && !imask; + return syscfg_gie && !iad && ssr_ie && !ssr_ex && !imask && !lock_pend= ing; } =20 static void clear_pending_locks(CPUHexagonState *env) @@ -257,7 +259,9 @@ static void clear_pending_locks(CPUHexagonState *env) =20 static bool should_not_exec(CPUHexagonState *env) { - return (get_exe_mode(env) =3D=3D HEX_EXE_MODE_WAIT); + return get_exe_mode(env) =3D=3D HEX_EXE_MODE_WAIT || + env->k0_lock_state =3D=3D HEX_LOCK_WAITING || + env->tlb_lock_state =3D=3D HEX_LOCK_WAITING; } =20 static void restore_state(CPUHexagonState *env, bool int_accepted) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index 0ca52ed666d..637873b2668 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -19,6 +19,7 @@ #include "sys_macros.h" #include "hw/hexagon/hexagon_tlb.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hex_interrupts.h" =20 static inline void hex_log_tlbw(uint32_t index, uint64_t entry) { @@ -271,6 +272,8 @@ void hex_tlb_unlock(CPUHexagonState *env) unlock_thread->tlb_lock_state =3D HEX_LOCK_QUEUED; SET_SYSCFG_FIELD(unlock_thread, SYSCFG_TLBLOCK, 1); cpu_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK); + hex_interrupt_update(unlock_thread); + qemu_cpu_kick(cs); } =20 if (qemu_loglevel_mask(CPU_LOG_MMU)) { diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 8c292854de3..82d38dc0b08 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1397,6 +1397,8 @@ static void hex_k0_unlock(CPUHexagonState *env) unlock_thread->k0_lock_state =3D HEX_LOCK_QUEUED; SET_SYSCFG_FIELD(unlock_thread, SYSCFG_K0LOCK, 1); cpu_interrupt(cs, CPU_INTERRUPT_K0_UNLOCK); + hex_interrupt_update(unlock_thread); + qemu_cpu_kick(cs); } =20 } --=20 2.34.1 From nobody Fri Oct 23 14:30:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792094654; cv=none; d=zohomail.com; s=zohoarc; b=WS8a4WTfVYPo5BG59znUD4KxBo/Pt1F3tzzlxpKXITT6ZQys7rA4WoMdRyIPFrE/2JdsgdDWLRyMusF1qCHY5Qw6ux35unJyhFpl+6vcutmiSzJhjFLBOTPDsqXm7HXHAJv3UTErP4B31uodYhnaNhzs4BYhsbAyVV3r3ca28Mk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792094654; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094654667158500 Set PC to the tlblock instruction and leave the CPU loop when the lock is contended. This retries tlblock after ownership is passed and prevents execution without the lock. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index 637873b2668..79a19797a05 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -12,6 +12,7 @@ #include "system/cpus.h" #include "internal.h" #include "exec/cpu-interrupt.h" +#include "accel/tcg/cpu-loop.h" #include "cpu_helper.h" #include "exec/cputlb.h" #include "hex_mmu.h" @@ -180,6 +181,7 @@ void hex_tlb_lock(CPUHexagonState *env, uint32_t PC) ", thread may hang\n", PC); CPUState *cs =3D env_cpu(env); cpu_interrupt(cs, CPU_INTERRUPT_HALT); + cpu_loop_exit(cs); return; } env->tlb_lock_state =3D HEX_LOCK_WAITING; @@ -191,6 +193,7 @@ void hex_tlb_lock(CPUHexagonState *env, uint32_t PC) env->gpr[HEX_REG_PC] =3D PC; CPUState *cs =3D env_cpu(env); cpu_interrupt(cs, CPU_INTERRUPT_HALT); + cpu_loop_exit(cs); } else { env->tlb_lock_count++; env->tlb_lock_state =3D HEX_LOCK_OWNER; --=20 2.34.1 From nobody Fri Oct 23 14:30:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792094642; cv=none; d=zohomail.com; s=zohoarc; b=bPjM7H7KH+JnUuYhQfgu+ryhwoWY3IgbPtPxxISnOtrEpG1KqNbyqBKmhmDRb/BBrXtO/wxd7DdJZo5RpHdYPROF+4PJTKMcqOxiSvxsDmH1a7ew4okTwE3Nc75KSbW+yNtZt6G+wGnt/vNL3GzdbaPaQPPqJOX8UT6wj0r2D5g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792094642; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3XSaT0IebdrV9pFi417K7itqeQXP6nNeTiSDYDl96oU=; b=Zvy9K/0D1rvyJ+bPwO9CpfjXXhrEBor1D67F9BqwjdOJXWu4vf6p4GsHFW6ZF9esU4ghf45Og9uNCMUrAN5twPHwQbwBEmvY+Wa9J/z8H8+IJyZ2BaPRvHBMUdqO1kOkX9cRQym06lGVPPcYxdFFZ68OLp3lLrkac6E5wRQYRFs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792094642383252.4423432977918; Thu, 15 Oct 2026 13:04:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHRfz-0003Wb-N6; Thu, 15 Oct 2026 16:03:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHRfw-0003Pg-0J for qemu-devel@nongnu.org; Thu, 15 Oct 2026 16:03:40 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHRfu-0003FC-9n for qemu-devel@nongnu.org; Thu, 15 Oct 2026 16:03:39 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69FFDtqt2678119 for ; Thu, 15 Oct 2026 20:03:37 GMT Received: from mail-dl1-f71.google.com (mail-dl1-f71.google.com [74.125.82.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hb19t94mf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 15 Oct 2026 20:03:37 +0000 (GMT) Received: by mail-dl1-f71.google.com with SMTP id a92af1059eb24-1665200f4c2so7865940c88.0 for ; Thu, 15 Oct 2026 13:03:37 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094644504158500 Set MODECTL.E when start retires rather than when the target thread runs. T= his makes the thread state visible to software immediately after start. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 6f172270865..6dc06401ad5 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -417,6 +417,9 @@ static void do_start_thread(CPUState *cs, run_on_cpu_da= ta tbd) void hexagon_start_threads(CPUHexagonState *current_env, uint32_t mask) { CPUState *cs; + + BQL_LOCK_GUARD(); + CPU_FOREACH(cs) { CPUHexagonState *env =3D cpu_env(cs); if (!(mask & (0x1 << env->threadId))) { @@ -424,6 +427,7 @@ void hexagon_start_threads(CPUHexagonState *current_env= , uint32_t mask) } =20 if (current_env->threadId !=3D env->threadId) { + set_enable_mask(env); async_safe_run_on_cpu(cs, do_start_thread, RUN_ON_CPU_NULL); } } --=20 2.34.1 From nobody Fri Oct 23 14:30:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792094642; cv=none; d=zohomail.com; s=zohoarc; b=lLUbSEDYfYe+v0VJWv6lDtd3TXDLbakWR+uUlzzrXaemprBYZqIiudv2Yc/kYXQING6mhTlKv98CvcfttWTWpifOGC+OTxRXbk2qdv1ZxfRB6SYqXkaf4pCAS70lz4Bl2dtPswi37hBJkdJyJdefK82x6KxzKVR2b5OPv7Uq0Qo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792094642; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+wdQOWWjrb2A+1zKjaniSXLm1/gTrVOZcbWWQj2p5Vs=; b=HJ7+lpUu5iaABiVr8SQLmMoU1oEwUyx9PIOybqs5D+brMj/0Gb7muvqSEGtm1zila68sQ1sLgD1asDrAoUD/weUQ++t7WgyjOgfoXSAlONMZWxvZatOo1Wb39DyMVUHRInx8ON/BTKMp9+9uhLmT0JwER81GNqQJ/6SCfeYAvu8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792094642364799.8101705950971; Thu, 15 Oct 2026 13:04:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHRg0-0003Wq-5B; Thu, 15 Oct 2026 16:03:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHRfw-0003QP-RN for qemu-devel@nongnu.org; Thu, 15 Oct 2026 16:03:41 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHRfu-0003FE-Pt for qemu-devel@nongnu.org; Thu, 15 Oct 2026 16:03:40 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69FFHNM52999177 for ; Thu, 15 Oct 2026 20:03:37 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hausm2qck-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 15 Oct 2026 20:03:37 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-35a4d2e39acso4425263eec.1 for ; Thu, 15 Oct 2026 13:03:37 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792094644531158500 Add the lock_verify test case to verify the k0/tlblock behavior, add the minivm tests to cover start() and more. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/functional/hexagon/meson.build | 1 + tests/functional/hexagon/test_minivm.py | 48 +++++++++++++++++++++++ tests/functional/hexagon/test_systests.py | 3 ++ 3 files changed, 52 insertions(+) create mode 100755 tests/functional/hexagon/test_minivm.py diff --git a/tests/functional/hexagon/meson.build b/tests/functional/hexago= n/meson.build index 44053e64676..e182bc98a06 100644 --- a/tests/functional/hexagon/meson.build +++ b/tests/functional/hexagon/meson.build @@ -3,6 +3,7 @@ tests_hexagon_system_thorough =3D [ 'arch_tests', 'systests', + 'minivm', ] =20 test_hexagon_timeouts =3D { diff --git a/tests/functional/hexagon/test_minivm.py b/tests/functional/hex= agon/test_minivm.py new file mode 100755 index 00000000000..115f3cf3710 --- /dev/null +++ b/tests/functional/hexagon/test_minivm.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# +# Copyright(c) 2024-2025 Qualcomm Innovation Center, Inc. All Rights Reser= ved. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset + +class MiniVMTest(QemuSystemTest): + ''' + minivm is a Hexagon hypervisor that implements the Hexagon VM + specification. These test cases boot minivm and then load test cases + to the address specified by MiniVMTest.GUEST_ENTRY and + execute a minvm-guest program to exercise minivm virtualization + features. + ''' + timeout =3D 180 + GUEST_ENTRY =3D 0xc0000000 + ASSET_TARBALL =3D Asset( + 'https://github.com/qualcomm/qemu-hexagon-testing/releases/' + 'download/v0.2.21/hexagon_minivm.tar.gz', + '5980740c5fa505f55cacd1646088831202df4ccbf9e2ddc34b690673574169ba') + + def run_minivm_test(self, test_case): + self.set_machine('sim') + self.archive_extract(self.ASSET_TARBALL) + rootfs_path =3D self.scratch_file('hexagon-unknown-linux-musl-root= fs') + kernel_path =3D f'{rootfs_path}/boot/minivm' + + vm =3D self.get_vm(name=3Dtest_case) + vm.add_args('-kernel', kernel_path, '-device', + f'loader,addr=3D{hex(self.GUEST_ENTRY)},' + f'file=3D{rootfs_path}/boot/{test_case}') + vm.launch() + vm.wait() + self.assertEqual(vm.exitcode(), 0) + + def test_mmu(self): + self.run_minivm_test('test_mmu') + + def test_interrupts(self): + self.run_minivm_test('test_interrupts') + + def test_processors(self): + self.run_minivm_test('test_processors') + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() diff --git a/tests/functional/hexagon/test_systests.py b/tests/functional/h= exagon/test_systests.py index 20c58f84f67..0489db0af91 100755 --- a/tests/functional/hexagon/test_systests.py +++ b/tests/functional/hexagon/test_systests.py @@ -108,5 +108,8 @@ def test_hvx_multi(self): def test_standalone_vec(self): self.run_exit_zero("standalone_vec") =20 + def test_lock_verify(self): + self.run_exit_zero("lock_verify") + if __name__ =3D=3D "__main__": QemuSystemTest.main() --=20 2.34.1