From nobody Sun Oct 25 02:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.tenstorrent.com ARC-Seal: i=1; a=rsa-sha256; t=1792024227; cv=none; d=zohomail.com; s=zohoarc; b=M9ocvG+8bRvruckmlBimXrgu5IBlwzqARs0Nxc0boRMgPIfXzOjzsHcT8ZyXoxHe9N8H8n5rZbi32ZKdT+qB6QguRtHzjceylv9Ch5QVANkcdg8ufVtJYteDLIGJLR+ir8BVp33iMmWUYNyFG1URn6NYgsHJcRjcgz+zjD7t3P4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792024227; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W6iQt/nJGJKSfexDx17afcIMBhxPEbv2eHDhVLE1BZQ=; b=LDvmP5mWkJ4SumoiLDIpydEwt2Lom/SRZ37SlQzJjRVMNhYDhVC3LJqO6YxTG3YyOo/O6Ti1aJXfJ7NcZagi79gs+3+MDYCdOkprSCZYiTE/p26BI15Po/2Q18MSu5OG5tUZAUITaKEBNNnzOnogz2DY6FhP/31F7HcO8Y9ig5k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792024227708184.98133228244558; Wed, 14 Oct 2026 17:30:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xH9LK-0001d0-3O; Wed, 14 Oct 2026 20:29:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xH9LH-0001cB-9Y for qemu-devel@nongnu.org; Wed, 14 Oct 2026 20:29:07 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xH9LF-0000wb-7G for qemu-devel@nongnu.org; Wed, 14 Oct 2026 20:29:07 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-38ecc48b3deso314390a91.0 for ; Wed, 14 Oct 2026 17:29:04 -0700 (PDT) Received: from lima-default.tail89d63.ts.net ([159.196.41.205]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac92a49d7bsm795730a91.0.2026.10.14.17.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 17:29:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tenstorrent.com; s=google; t=1792024144; x=1792628944; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=W6iQt/nJGJKSfexDx17afcIMBhxPEbv2eHDhVLE1BZQ=; b=I0aU5GSGT+YCrsGJRVyDUPmZSpde8Nq4RX6tb9iDejCYueGjZgvQaVrkD1HqRG+Re9 Yyusxmf5ijy7nE3NR1ss3Rv0U2hJqFQWCpMY0IbNm4tCSWpm4aUfRZ8tW6XVCtEXGO51 50J1axNbE8Az6GtM9+55+zGiJKN6/0BmMsyOHrRPFy9bINXujP/Jc1/6Wa6ne0cides+ QqQsXZ/ylhrZZ9Ez98W2bmndzVkH3L3odgyXVmDXK4VoZ5s9HbGJGVTu4sM1nLBLc5Y7 Umhu+yK5JMLd5r65DTevn333laDU2/+kr4Cj1qsu6ZcFohpZ7W5/leKEXC8BDpCEpr0z nBaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792024144; x=1792628944; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=W6iQt/nJGJKSfexDx17afcIMBhxPEbv2eHDhVLE1BZQ=; b=cW6Iu8S75YZn7UsQf/+pmhUYpeipykP80HE2B1GkLh/fGdYy2B3cUMWjqXlKo9P5Yo Efd3H2xo8Xg/Eq40CoV9K2Gz0ViUpPpEv/FHSdgXT1k8PVmpOU6OMgxTXt1M7T+mQ0cW 44592ztwkVb0gl8x6nvENwwf8fYCRmRpAIT5i8cAOTCEGNExOglLefyYHpoXNvMPm/vt EuYfjh+A+UA43KdBGrSr+LmsDi1QyVN0veRH//5XUxCyq/+l3xvri/QfOwP6SoJB9pP7 AGg3J2310WwJ7RP+8YY9etueCoZGZwwY1tBwQ57i1bZh24irZpPNmOdrA6EelKdWW+7c uQug== X-Gm-Message-State: AFq9FYIWffVHK/i8R5VCwkVDKAoOrdDY0Qhxnll6bQwtwhkwDAIEGq5v kcbf+HRcWgn/QmjD8DHa7IUTNHTdfddLC5lVmb5CHvlJY6K9zG9lefK6muZ1FumJNI1FkdBX3T5 6TRu3sXQ= X-Gm-Gg: AYBFou0uUcc2qb6iGWoL+bhXMhwMs2+I9m4h9O/6Z6ECZZiDGgUUz9im6ftNz7n+4sI F2TLCurUnVx1ttomnIXHeANNR01hBp3+lDploQkJlxkXkph5vLNsvF2KiRQOxJFgDJlGc2XGluE 2E4UFSGpNP1gBGr27rz4OTOKvLsdFy8eyERXyaHK/s0HdqWj7aNKTZRQF2yLCtz2V/1SXzHxwVJ jy7H1YGDH7TzRsucapjQ/gMD0INMMmD+ZouI4SDXh2e0347xnXK7rCsE9e1sbs04FwNSzqlwSh7 v3Z8MAEED4RbHSCu4Xw+iyB/i0E9LPofYs5ttDgM4tj2QT6y+x3JJaejkWEtuOpzoEfFWubx4Qg 9ozLF4fBCww+kHO6ZqiEt1nlYSgsh0NKsXDNiW0zvajqkLXpzV0aLlGmZQcLxys9EusKU1mqk0w d6uAwu+9iB6HGDKA8eF3yL4YyFzW3cZszwPdZ5gMK4o2JvpjpoV0PYZic065n+NXLux0UlwbbDO PE/SdHAX/sRZTOlNiDH4OnXaH3gZqkEDZyGTIOyoMXlMc8= X-Received: by 2002:a17:90b:1a90:b0:3a8:1759:2217 with SMTP id 98e67ed59e1d1-3ab3a393867mr26528758a91.2.1792024143827; Wed, 14 Oct 2026 17:29:03 -0700 (PDT) From: Portia Stephens To: qemu-devel@nongnu.org Cc: Chao Liu , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Portia Stephens , qemu-riscv@nongnu.org, Michael Ellerman , Anirudh Srinivasan , Alistair Francis , Joel Stanley , Pierrick Bouvier , Paolo Bonzini , Weiwei Li , Daniel Henrique Barboza , Palmer Dabbelt , Liu Zhiwei , Nicholas Piggin Subject: [PATCH v5 1/3] hw/riscv/atlantis: Use dw8250 UART model Date: Thu, 15 Oct 2026 10:28:47 +1000 Message-ID: <20261015002849.1640109-2-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261015002849.1640109-1-portias@oss.tenstorrent.com> References: <20261015002849.1640109-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=portias@tenstorrent.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1792024229638158500 Content-Type: text/plain; charset="utf-8" Replace the ns16550 UART with a Designware UART now that a model is available. The hack which sets the rest of the UART register space as unimplemented can be removed. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 2 +- hw/riscv/tt_atlantis.c | 48 +++++++++++----------------------- include/hw/riscv/tt_atlantis.h | 4 +-- 3 files changed, 18 insertions(+), 36 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb05031228..d89fdfcc86 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -144,7 +144,7 @@ config TENSTORRENT select RISCV_ACLINT select RISCV_APLIC select RISCV_IMSIC - select SERIAL_MM + select DW8250 select DEVICE_TREE select DESIGNWARE_I2C select DS1338 diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 4e6c39982c..dfd6bc6ba6 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -24,9 +24,8 @@ #include "hw/riscv/fdt-common.h" #include "hw/riscv/riscv_hart.h" =20 -#include "hw/char/serial-mm.h" +#include "hw/char/dw8250.h" #include "hw/intc/riscv_aclint.h" -#include "hw/misc/unimp.h" #include "hw/misc/tt_atlantis_prcm.h" =20 #include "system/system.h" @@ -268,11 +267,15 @@ static void create_fdt_uart(void *fdt, const MemMapEn= try *mem, int irq, int irqchip_phandle, uint32_t clk_parent_phand= le, uint32_t clk_phandle) { + static const char * const compat[2] =3D { + "snps,dw-apb-uart", "ns16550a" + }; g_autofree char *name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIX, mem->base); =20 qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_string_array(fdt, name, "compatible", + (char **)&compat, ARRAY_SIZE(compat)); qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2); qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4); @@ -466,17 +469,6 @@ static void load_fdt(TTAtlantisState *ams) create_fdt_memory(ms->fdt, &ams->soc); } =20 -static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, - const char *name, hwaddr addr, uint64_t= size) -{ - qdev_prop_set_string(DEVICE(dev), "name", name); - qdev_prop_set_uint64(DEVICE(dev), "size", size); - sysbus_realize(dev, &error_abort); - - memory_region_add_subregion_overlap(memory, addr, - sysbus_mmio_get_region(dev, 0), -1= 000); -} - static void tt_atlantis_machine_done(Notifier *n, void *data) { TTAtlantisState *ams =3D container_of(n, TTAtlantisState, machine_done= ); @@ -545,8 +537,7 @@ static void tt_atlantis_soc_init(Object *obj) =20 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); =20 - object_initialize_child(obj, "uart1", &s->uart1, - TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "uart1", &s->uart1, TYPE_DW8250); =20 object_initialize_child(obj, "prcm-rcpu", &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU], @@ -653,11 +644,6 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, &s->bootrom); =20 - /* UART1, the soc console (UART0 is for the boot microcontroller) */ - serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, - qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), - 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); - /* 4 PRCM blocks */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RC= PU]), errp)) { @@ -695,18 +681,14 @@ static void tt_atlantis_soc_realize(DeviceState *dev,= Error **errp) sysbus_mmio_get_region( SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM]), 0)); =20 - /* - * Atlantis contains a DesignWare uart while the QEMU machine - * uses the serial_mm model with the base ns16550 register set. - * Linux's dw driver writes outside of serial_mm's 0x20 sized - * mapping and faults. - * - * Create an unimplemented device region so writes don't fault - * and reads return zero, which keeps Linux happy. - */ - mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), - "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, - s->memmap[TT_ATL_UART1].size); + /* UART1, the soc console (UART0 is for the boot microcontroller) */ + qdev_prop_set_chr(DEVICE(&s->uart1), "chardev", serial_hd(0)); + sysbus_realize(SYS_BUS_DEVICE(&s->uart1), &error_fatal); + memory_region_add_subregion(s->memory, + s->memmap[TT_ATL_UART1].base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->= uart1), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart1), 0, + qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ)); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 577c867d71..fc7a4337cc 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -13,8 +13,8 @@ #include "hw/core/sysbus.h" #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" -#include "hw/misc/unimp.h" #include "hw/misc/tt_atlantis_prcm.h" +#include "hw/char/dw8250.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -41,7 +41,7 @@ struct TTAtlantisSoCState { RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; - UnimplementedDeviceState uart1; + DW8250State uart1; MemoryRegion bootrom; TTAtlantisPRCMState prcm[TT_ATL_NUM_PRCM]; =20 --=20 2.43.0 From nobody Sun Oct 25 02:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.tenstorrent.com ARC-Seal: i=1; a=rsa-sha256; t=1792024205; cv=none; d=zohomail.com; s=zohoarc; b=hNnLQrF6hlq50YMkCI6mLy/8iy8hFF82JboBLvwPwPFGiFfm5tjaz9rMOBCk3npCzF9xB5Bm4PBEPGskO/AZP2uGMxUa0AIIbR6gcQ/Nhd5b+g12tP6O/u99V9wJwuDawPbHatQm4ofV1CBkfcCrbhn4KAn1GWzW5Fdcz3FUgUM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792024205; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=96m7yUeEnu5RNF8FuHUfexVxOzeNw847xHOd8FX3/3U=; b=D3inrU5HyUcKREr+5c/f2ohDrfLOLPLN6Ns1k0I6zFHHVQThCmlCILhibpE+4xsLVTRih21cPnyu+vZ06T5tdGUqUjO/5xOJFE2jxlwv+vKuAzgQqMpxC0vpumey/a2QhAtsuJU8AA8GrVkn/9mss+r9BgKNbm56axMMYKNq4po= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792024204735168.89944461990535; Wed, 14 Oct 2026 17:30:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xH9LS-0001eH-EF; Wed, 14 Oct 2026 20:29:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xH9LM-0001dD-Uz for qemu-devel@nongnu.org; Wed, 14 Oct 2026 20:29:12 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xH9LL-0000x0-9o for qemu-devel@nongnu.org; Wed, 14 Oct 2026 20:29:12 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-396affa9420so579361a91.3 for ; Wed, 14 Oct 2026 17:29:10 -0700 (PDT) Received: from lima-default.tail89d63.ts.net ([159.196.41.205]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac92a49d7bsm795730a91.0.2026.10.14.17.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 17:29:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tenstorrent.com; s=google; t=1792024150; x=1792628950; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=96m7yUeEnu5RNF8FuHUfexVxOzeNw847xHOd8FX3/3U=; b=glqtFOXMzq7wVTsLQSQzd9vWuPTjrcGENlH5FO9VziWsxJMsFW8vb8DZEe+uuhPN2t RO9aXkrAZdHFxAyZwGuCeaIjNsTr4OcLKIfAyIdtJ34NkLxHCrzSmenjoYHWXMJWiVuq 5kTmPjlKTBTzOktzqz4oqsEC4WINoT9vUpAMPwbapamcrGBaUyK5jFzko3wHrHAW6J3G OPI9OyZ8n0FqhIRUGrDxSyaFG8IMSp2kq99gqxjOQ5AMQlFGyKlsHNkSspSL8EF05SDD HgUcZgr+nbu7IfJ6q61SEicjAukPL9d9uDf0z4yTKuotKHd/NnrOrYS9uB1Gn4M3pbn8 LqMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792024150; x=1792628950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=96m7yUeEnu5RNF8FuHUfexVxOzeNw847xHOd8FX3/3U=; b=PdJ+BYBsx/EI5jf3KF81WnIYWXbsz/haZiGVftHFKeaElxUp6rZQzJ2Ae2U0MzdxOB 6bzxkVbfd02gisj+VTIE625H8WaiV5aIbEury7N5/dzZ82KtpfrpdQF0MepNgeqeDtJi cEG2y5HzoHTe7vh58QmIJ+ma+/sxfnBivytlUl66Wza8OM1Uent3+IrBKlbXyxnJ/CVJ YeYE8sq+0ty1shWlljPj7WSbCIQrpDlWx9d6odUg2fl6yyZ3yg8ZrhBcnE6Wtl8l1cp3 xYIjO/YoF89hggpvYhutdvH6ZOwvh52v1nCoPM+Efz5YqYexvXZjH9CbQw/fsI2y3f3D D3Cg== X-Gm-Message-State: AFq9FYJsyMMmdlUWhJj9ECJnCPmZ9yMOkJOeO4BElH42vspelJOZTRyf A8IkFEoqYI1VStdyJmLWK05hr6bYXAdG+llSOQIUS91U16mHXjVAwwd6IMwDuEJfBU5CtPuYl/Y TnAVVjYU= X-Gm-Gg: AYBFou1THqyotDjebkCaHtdHWZc6E2qB8tiavZjwMa7gG4bIpvxbZU+qNYA7PmodyUy ZTJRVtjRv0xFznzbpCqm30LRzJmYlo/iJEsD5gOZeELnwNDjLDrurnNeABWB5RRs9HuUOSq3n+b TIGUGDrvaTcO9+P7HxRTgQliL/qj/5vRCFoNyhgnZB28KGOLKQXxW/1qwTqf5MVN7wlFyaCX3i4 KAL+Wcg/iA+OfwznZigP7m+kfp091FseZmhv27pJHvxAbwCBHIZFZp9q2ym36GqwujbZUELEJl/ Yk1staVkRl0cK+6v9zhh0zDQlghA1qcson/+yabDnhyEorp4rN4SsVYO4guemMUQ6NHtFCg1so2 +HwkO9JNAPuFEb8Irhn7vXEAX37A/TcbvznRBVRyx/tQT/j3B8PJvYerjenmPul4ZqRLh3gfCrQ x86YeFk0HZIu03TAaWBTjQXPEEdYaLCHhSoGkSG4n92lhjqPyamBe0nWKXMmbA5CtC73APILJG/ hFcq0aGWS8zESAd4I/L3LMG/Usi1+cSvULbTdn49IvI1vcNxNF7wLtNsg== X-Received: by 2002:a17:90a:d44d:b0:3a6:e1d1:e511 with SMTP id 98e67ed59e1d1-3ab3aaf4689mr23525449a91.4.1792024149904; Wed, 14 Oct 2026 17:29:09 -0700 (PDT) From: Portia Stephens To: qemu-devel@nongnu.org Cc: Chao Liu , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Portia Stephens , qemu-riscv@nongnu.org, Michael Ellerman , Anirudh Srinivasan , Alistair Francis , Joel Stanley , Pierrick Bouvier , Paolo Bonzini , Weiwei Li , Daniel Henrique Barboza , Palmer Dabbelt , Liu Zhiwei , Nicholas Piggin Subject: [PATCH v5 2/3] hw/riscv/atlantis: Add all UARTs for Atlantis SoC Date: Thu, 15 Oct 2026 10:28:48 +1000 Message-ID: <20261015002849.1640109-3-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261015002849.1640109-1-portias@oss.tenstorrent.com> References: <20261015002849.1640109-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=portias@tenstorrent.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1792024207357158500 Content-Type: text/plain; charset="utf-8" Previously only the Ascalon console UART was enabled, this enables all 5 UARTs on the SoC. Only UART1 is added to the serial interface for now. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/tt_atlantis.c | 36 ++++++++++++++++++++++++++-------- include/hw/riscv/tt_atlantis.h | 11 ++++++++++- 2 files changed, 38 insertions(+), 9 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index dfd6bc6ba6..311de64eda 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -64,7 +64,11 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_I2C2] =3D { 0xd4060000, 0x10000 }, [TT_ATL_I2C3] =3D { 0xd4070000, 0x10000 }, [TT_ATL_I2C4] =3D { 0xd4080000, 0x10000 }, + [TT_ATL_UART0] =3D { 0xd4100000, 0x10000 }, [TT_ATL_UART1] =3D { 0xd4110000, 0x10000 }, + [TT_ATL_UART2] =3D { 0xd4120000, 0x10000 }, + [TT_ATL_UART3] =3D { 0xd4130000, 0x10000 }, + [TT_ATL_UART4] =3D { 0xd4140000, 0x10000 }, [TT_ATL_PRCM_PCIE] =3D { 0xd8000000, 0x100 }, [TT_ATL_PRCM_MM] =3D { 0xdc000000, 0x1000 }, [TT_ATL_PRCM_HSIO] =3D { 0xe00c0000, 0x510 }, @@ -531,13 +535,21 @@ static void tt_atlantis_machine_done(Notifier *n, voi= d *data) fdt_load_addr); } =20 +static inline int tt_atlantis_uart_index(int uart_dev) +{ + return uart_dev - TT_ATL_UART0; +} + static void tt_atlantis_soc_init(Object *obj) { TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(obj); =20 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); =20 - object_initialize_child(obj, "uart1", &s->uart1, TYPE_DW8250); + for (int i =3D 0; i < TT_ATL_NUM_UARTS; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], + TYPE_DW8250); + } =20 object_initialize_child(obj, "prcm-rcpu", &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU], @@ -682,13 +694,21 @@ static void tt_atlantis_soc_realize(DeviceState *dev,= Error **errp) SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM]), 0)); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ - qdev_prop_set_chr(DEVICE(&s->uart1), "chardev", serial_hd(0)); - sysbus_realize(SYS_BUS_DEVICE(&s->uart1), &error_fatal); - memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_UART1].base, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->= uart1), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart1), 0, - qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ)); + qdev_prop_set_chr(DEVICE(&s->uart[tt_atlantis_uart_index(TT_ATL_UART1)= ]), + "chardev", serial_hd(0)); + + for (int i =3D 0; i < TT_ATL_NUM_UARTS; i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->uart[i]); + if (!sysbus_realize(sbd, errp)) { + return; + } + + memory_region_add_subregion(s->memory, + s->memmap[TT_ATL_UART0 + i].base, + sysbus_mmio_get_region(sbd, 0)); + sysbus_connect_irq(sbd, 0, + qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ += i)); + } =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index fc7a4337cc..f965bf23fc 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -25,6 +25,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTI= S_SOC) =20 #define TT_ATL_NUM_I2C 5 #define TT_ATL_NUM_PRCM 4 +#define TT_ATL_NUM_UARTS 5 =20 struct TTAtlantisSoCState { /*< private >*/ @@ -41,7 +42,7 @@ struct TTAtlantisSoCState { RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; - DW8250State uart1; + DW8250State uart[TT_ATL_NUM_UARTS]; MemoryRegion bootrom; TTAtlantisPRCMState prcm[TT_ATL_NUM_PRCM]; =20 @@ -66,7 +67,11 @@ enum { TT_ATL_I2C2_IRQ =3D 35, TT_ATL_I2C3_IRQ =3D 36, TT_ATL_I2C4_IRQ =3D 37, + TT_ATL_UART0_IRQ =3D 38, TT_ATL_UART1_IRQ =3D 39, + TT_ATL_UART2_IRQ =3D 40, + TT_ATL_UART3_IRQ =3D 41, + TT_ATL_UART4_IRQ =3D 42, }; =20 enum { @@ -83,7 +88,11 @@ enum { TT_ATL_MIMSIC, TT_ATL_SAPLIC, TT_ATL_SIMSIC, + TT_ATL_UART0, TT_ATL_UART1, + TT_ATL_UART2, + TT_ATL_UART3, + TT_ATL_UART4, TT_ATL_PRCM_RCPU, TT_ATL_PRCM_HSIO, TT_ATL_PRCM_PCIE, --=20 2.43.0 From nobody Sun Oct 25 02:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.tenstorrent.com ARC-Seal: i=1; a=rsa-sha256; t=1792024204; cv=none; d=zohomail.com; s=zohoarc; b=elH/P9M8P0UskzUgVc56JA734fGJPUMsdEA/OwVM8E7yQbNGntX6K1p4DfjZk6zizWMFhxF9SRj47VBl7qKWFvJPcyp7986pIzuMd1nbfLnsjma9CRtFIgD6RYxu6tLuxomPMSQLxPT6EOj7HG9yZMsB+EBo8fvym4jR3/PTCcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792024204; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EgVncG2NAYs4I+Cx+kp7rFgEZbzHj90F8O/5aLpub/I=; b=ipGOtwaW1tuoCVgq5E+xX+yf7XZnGcuTN3SYAWevN4suQh+9K0L3v7r5m3mTLuCWI6DzYNOeahTWnr9hoQndn3PUwGhaG0crRZ0LL3TKUz6VFHmNm0lTFxfbVrrwafwcdf/s1TwM06pGXFqhuY86pAHe/xfLOm1FGgVw6smhtic= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792024204569989.0571100119315; Wed, 14 Oct 2026 17:30:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xH9LW-0001f1-S0; Wed, 14 Oct 2026 20:29:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xH9LT-0001eN-W0 for qemu-devel@nongnu.org; Wed, 14 Oct 2026 20:29:20 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xH9LR-0000xM-AU for qemu-devel@nongnu.org; Wed, 14 Oct 2026 20:29:18 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-3ac7a053626so128369a91.0 for ; Wed, 14 Oct 2026 17:29:16 -0700 (PDT) Received: from lima-default.tail89d63.ts.net ([159.196.41.205]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac92a49d7bsm795730a91.0.2026.10.14.17.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 17:29:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tenstorrent.com; s=google; t=1792024156; x=1792628956; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=EgVncG2NAYs4I+Cx+kp7rFgEZbzHj90F8O/5aLpub/I=; b=U4GDIRUDTzeFfEbVUmesqLXaqS/yPGZ2GyFj0+2Tc3oftBPsTwQoejN/IZUWqkj5kc ZHORmrflhhbDR3GoyJ36dRDJiaghQj20NewXZEujYOLbFlu5QoaaAMwAblQ1L/kmo+Dq aBQYHz0IGpxwxEhtKFEtgzy/aWjwGmGROhVIXzIa5ruURWkpgweuwaGUqbEFk8xGiYqV us+RtNNQ12vmoS1JQH90wBP3ajHdkNDXK/8b8v+zIMmNolaLB/gR1H+H062UVeWxQ4fh UIl+t+f9KPjmmwPx2jMRTxpX5i0O2cm5LWCatv8O93Jq4Q6qnxsQMw9nWtw3sP0Q5ks+ bD0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792024156; x=1792628956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=EgVncG2NAYs4I+Cx+kp7rFgEZbzHj90F8O/5aLpub/I=; b=FA1C0AvyxSbdKQwYht2LpVV0yQr0+anfV/IGabRVdyatUdjtoHJ3slIt5ofuz3bP6J EMhNpzr5aC68gqDZqy+UbcuFpVBYzoBnTR3Sf9ZXbpiERAOhHem3YM7Zd9Lf5wODKVnO qXyf7HiWCe6vaKFqtiBohw1n+MzQrxhAtJ8Ev90E3sdApB+oZWuJs0+V/s9DL0/9c2r3 Uykmo1iC4tPdpJe4dmo80nnCiMzczXwgqhuxsKrjFw6TuHqiuORIu59sDKbLhxchVzE2 1igzzzxmK5IxYGqAQS/BFDOEz6UFRS6lbfOgEsxGxqM7RmZvcQgP9YFBcHGt6J8QXvRN HAmw== X-Gm-Message-State: AFq9FYIAcUAoEJbO7ndsnOO3aYi/pGYOGNSdLdGFPnA2hQ2NXKjTnsy8 OK/gyPL9zc2wTk4jrjz4TLNsCDCuEGLHI+m7MsPJ7L3GfOBc/t/vdHFL2ZgmtuHWie2A4Cg1rhx /9HoH6i4= X-Gm-Gg: AYBFou3WznfyAZHRY4RiKDNhhnEzpyw+4MYTfW+swCH0PO4Z10QFy57rJIcB5JSQetN wmxKL6DKiEtWwDFpDMHN/RgL0/5OaSa1wtKPWcePesr5xhLQdRRjlIunqkXPjW93uNmTutzReye 7ReMbSayhihAWKV/fNM/R3Pt93UMaFHuU5mivYF9hlp0opjKRk9Gt/ijLEtfPmP/M1Y7b2G7h97 15rCfnBRubSMjnlS9N4cDM7y/JKn2mnPE+lU+BK8xYUxW1wdSV3Sn8/z0LuoZeYOxsMbUYxNPXv 8RbmtR+Onl7+X4koy4uX6E8EBkusIJS7YPu8v7f2WaEGbPb/S5XFcmbaqGAhk+Iw1nYb+rpwjzR ikOxheIp/5dsB08TGn860T1I/tKbHDPvmEjWGGWdG22Gw6ZXExoHbtv4LFvL0geUAtY7CaePc0W LepYW3UQDqRq2EmQV9o85SB0v/clsOlHDSG8P5f5ScIHvEx1RhFnzd4LJS74LZOGw2LGGeXMxXt OqcxcVn1PYSG32hM1VuoHCmUi5X0Xiko0gOYSluJMYT+Wc= X-Received: by 2002:a17:90a:d44d:b0:3a0:c162:51af with SMTP id 98e67ed59e1d1-3ab39fed8b6mr23063896a91.0.1792024155483; Wed, 14 Oct 2026 17:29:15 -0700 (PDT) From: Portia Stephens To: qemu-devel@nongnu.org Cc: Chao Liu , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Portia Stephens , qemu-riscv@nongnu.org, Michael Ellerman , Anirudh Srinivasan , Alistair Francis , Joel Stanley , Pierrick Bouvier , Paolo Bonzini , Weiwei Li , Daniel Henrique Barboza , Palmer Dabbelt , Liu Zhiwei , Nicholas Piggin Subject: [PATCH v5 3/3] docs/atlantis: Update Atlantis UART documentation Date: Thu, 15 Oct 2026 10:28:49 +1000 Message-ID: <20261015002849.1640109-4-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261015002849.1640109-1-portias@oss.tenstorrent.com> References: <20261015002849.1640109-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=portias@tenstorrent.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1792024207225158500 Content-Type: text/plain; charset="utf-8" Update Atlantis documentation to describe the DesignWare UART used. Signed-off-by: Portia Stephens Reviewed-by: Alistair Francis --- docs/system/riscv/tt_atlantis.rst | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlan= tis.rst index 539c22354f..d94d064f4f 100644 --- a/docs/system/riscv/tt_atlantis.rst +++ b/docs/system/riscv/tt_atlantis.rst @@ -13,7 +13,7 @@ tt-atlantis QEMU model features =20 * 8-core Ascalon-X CPU Cluster * RISC-V compliant Advanced Interrupt Architecture -* 16550A compatible UART +* DW8250 compatible UART x5 * 4 PRCMs (Clock and Reset Controllers) =20 Known limitations @@ -25,9 +25,8 @@ real platform. Notably: * There is no PCI host bridge, so virtio-pci devices cannot be attached. Boots that need block storage must use ``-initrd`` with an initramfs. -* The DesignWare UART is modelled with QEMU's ns16550-compatible - ``serial_mm`` device; DesignWare-specific registers beyond that - set return 0. +* The Atlantis platform has 5 UARTs but only ``UART1`` is currently exposed + on the command line serial interface. ``UART1`` is the Ascalon console. =20 Supported software ------------------ --=20 2.43.0