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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd68144fsm43698635e9.4.2026.10.15.03.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:24:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059854; x=1792664654; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=vlJ0YMKurtXs9nd1yudaJA57cD2SNCrzN2aA7xi4zDY=; b=roV4LyNh+WjtZlD+VVlXIv0bGLSYZA5gtBpAbBjfvaSM/UV5BX0aAuAOBkbTRn+rbe 1NOSFQTlQSLJj/l2aniBMlWEo/QmqvSTPvb1vpMIvKb9qXIUBnWQJR1kmjQO2OfhCBo9 S0FWHNsbMKrbNdZr4I2SzEeTxqcxpXtk/qOTx6GwAoeEgPZrzUMGAKtFFxr8pbZuJuay y0CEGhI8AxpsGvJkydeNeEacOxj3q+rrZkND8LDbSIFaFH0oFEEDII7itxAy1lgZGUFm Qt693tBC1uJJiIx0jnTLKttqQQV5/E9/zWoaQoQNxweJyTcicRdsIMFOg7jRPA+5ybUB S3SA== X-Gm-Message-State: AFq9FYJNxCM5BA9f/KGq6ocXxgeH1U2d6AZZZWMTcRQmk4R/i0XQAdyC esZQsL4GV8rO7TSab3iWUV2fYGjRjf7xWMVSoU6r6muwfvzZHlRZZsWsqarBZrjJ X-Gm-Gg: AYBFou3t0h14b2wLoZCfK7jMlT5XbqRi7lCMHg+IBrm0dMAAj5/ZSWlWvZ8Yaf+eszJ /Br7+obBbA02gLc25chOlfwUce1XF0+mUeokW2I1lgzYDpTY62dxCE9s+AGrVx1HmsSniEMn4/A 4yq7ySIXKQB3kC8Te6uiwhy9SR2fshVk+XM820Z1XAzubcs/aQLzUbGgic2FMTOj+IX0bIs3qWe JIGToxycZoyn1TQvqY7y9FxC+Hvs4vJVSlyeRRljd9zc5oiJiuNufOxjuTDzdJLnuW2f5yOb8z5 0mT/EcbLQSE9n8klMEg6TjPvYmddL9UpCcW8lVNdUk3QUKDNBFLTcmpEymPZn7/KvUect7sq51Y OdnR28lVUUFiP1X4SwPsHPtwkn9Wl18CLTnci+bP2rnyIgNp1YqS+R6f+qt+m/V53RaksgvDM7q kurnMhtv/FGvUeiLYMUuqDfpM9kpmdvUgwCR8YuHYqiZNw0xZzwIWklt9cSdobdfnmsCAyoRlGf HmA2tak7PTyXehjXSxZFz33FBfQHglYylkSTa/hPcvIjg== X-Received: by 2002:a05:600d:82e4:b0:4a1:a45a:88f with SMTP id 5b1f17b1804b1-4a1a45a08f7mr231984865e9.20.1792059854088; Thu, 15 Oct 2026 03:24:14 -0700 (PDT) Date: Thu, 15 Oct 2026 11:27:48 +0200 Subject: [PATCH v3 01/50] docs/system/arm/aspeed: add the catalina-bmc machine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-1-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , Jamin Lin , =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056474; l=2095; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=ohO/cxfhzUynwcpNUOnDO3N8MbcDCcR99qBjLp7ftAQ=; b=ZKsJLrtK7bOG060LP680C6YTJKyi/EjFZFOJ/P4eeqVxAIDrSPCn/737cUSu4Exy21Ag4JMsf xBXb2C5eUyLC7z3z0GM9LpOxpFlMcRaifRPj9Xe87pn7RY1SeXko9Wr X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.51; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f51.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792059948769158500 The Facebook Catalina BMC machine is supported by hw/arm but has never been listed in the Aspeed documentation. Add it to the AST2600 machine table. While at it, shorten the document title. Listing every machine name in the title duplicates the tables right below it, and made the title (and its underline) grow past 350 columns. The machine list stays available where it is readable, in the per-SoC tables. Reviewed-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- docs/system/arm/aspeed.rst | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 2d51ceeb84..933df41f96 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -1,5 +1,5 @@ -Aspeed family boards (``anacapa-bmc``, ``ast2500-evb``, ``ast2600-evb``, `= `bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``g220a-bm= c``, ``palmetto-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc`= `, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``wi= therspoon-bmc``, ``yosemitev2-bmc``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed family boards +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of various OpenPOWER systems and Aspeed evaluation boards. They are based on different releases of the @@ -33,6 +33,7 @@ AST2600 SoC based machines : - ``fuji-bmc`` Facebook Fuji BMC - ``bletchley-bmc`` Facebook Bletchley BMC - ``fby35-bmc`` Facebook fby35 BMC +- ``catalina-bmc`` Facebook Catalina BMC - ``anacapa-bmc`` Facebook Anacapa BMC - ``gb200nvl-bmc`` Nvidia GB200nvl BMC =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792059941; cv=none; d=zohomail.com; s=zohoarc; b=gEkPvwzqKXPlZmDUnjwl5vyGm4GavtYUYAZWt06J07xbhb+0HNDgobJLe19/IhrlbudAOFXqMz/nY2fXtQaz44twhD+B+ExW3z72nudHBMwnuPzCDUyYvObys+20rdxrEqAqjFmK4UwYLRMFqJrXpokx7GxEoVrlf5hsZGEsOcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792059941; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=0Pey2/h5d4egpWMShENSUMjJQuRdUBUW9uGkG9/qdms=; b=lkCUlZOuXzUhH3AMpcc5r8aD7g6DVFH2My8MVSUKvWNl7xDlq6XGIfFBcm09+PUJ+wgp0EsifsXlmmIqgIMyhl5oewoGcUxgsCAsaBXyFPYHA915V/Q7BpZNSswwob0aLyb0omMrXOxMJAaqvkMHyd8J32zHV5fLiAo6Ho3aF74= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792059941379358.5334401119526; Thu, 15 Oct 2026 03:25:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIdf-0000Zy-51; Thu, 15 Oct 2026 06:24:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIdM-0000WL-F4 for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:26 -0400 Received: from mail-wm1-f50.google.com ([209.85.128.50]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIdK-0003D5-7u for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:24 -0400 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4a17baef589so17029025e9.0 for ; Thu, 15 Oct 2026 03:24:21 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. [89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd96fed4sm61274505e9.2.2026.10.15.03.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:24:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059861; x=1792664661; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=0Pey2/h5d4egpWMShENSUMjJQuRdUBUW9uGkG9/qdms=; b=QvZeDBn1Bo8iQjIrbc9j0ewVxVcSyvYAUZrTjR8JND956+Iik+ZyraftxabQSnt/Wh DeciFHfueTZoGgcCvGU8kNyscUBZhFgAuX/+SpkTDRfBhuxJWNlMhEntkGVrzahZyI4+ GPFmmx3ZfEwGn8DzcKIIPSyezOFBICA+gI2ZXbxQIZ0cZLCzssMMpfCc2VvNHd+pkTvH jq1w6Ko6oOk+OwAtxKG5Mhkh5QyrkK7ow2stXvwjDIoGszkCVj/dMf25vAVR7j3ynUZV Ee7bPvK+ammNLEKybYJH/n1iv2Z6zDtST0Fjc7I7kjrnljyLCjtUJKMa5cO6kZGVdh9N D88g== X-Gm-Message-State: AFq9FYK3qGYIclT1v7GDC7QYP8dY11nMNTUStlsnZb6E+X9J2WSG/2ho vBca/bdqkhFQpmLMpbeps/zfLG7WResxvVx0YKvmIjZ7yM8NSbjZNjrLYZ0ywatG X-Gm-Gg: AYBFou2dpmG2T09sWytMtQMsboAq91D9DW50tJdcM7HwreiikqvXq3qAp8WPEjvVdLT kJS1ekoCyDg3pFwW/cvuaSuRyxVpmdn24wUXf4F5zyUoHN8Sm+XiNt5skxM9XrzfueYA5Dz9uf7 Vk19Wk/FVEWZ0/nh6m1kIyc1Xax3WNCZzlThHu6jam0iRJ1YaN38XaZCLyZ/JPKx4H2jE81gLzI tdwxMmje/cNGhlsJc/O8uTBsE2wZxZh/u1jbC3+FEkhppguj+g2T4PeM6XZE+xDQPMa2Oqx37/2 LVLrQDVEYaEdNxr/FSPqMLqTx05+s+j4IKAIV+hHq74BVqq+pxs3g5mNv1Cp0G6QB94MCQxLYxt yvnl3SVMQMrLWqHy6VjEAvHiFvdRAqo3PwZ03eMzWPiWYgA7eZoZa1SrUcGDeVKFNEBKYqe/fEZ S2brEBopgY2WoipFZOwT6pyki9npZZeh1Vm+2GjhVgFZsemO4Qlm79w2P7iYn3vihpC9UCYCl7b Mwtc2sR/cNa7dXps5223Bx2Z26b/mPnsvJv5HJ+rpt4NQ== X-Received: by 2002:a05:600c:1d11:b0:4a0:25db:4591 with SMTP id 5b1f17b1804b1-4a18e4a4c33mr393827345e9.23.1792059860573; Thu, 15 Oct 2026 03:24:20 -0700 (PDT) Date: Thu, 15 Oct 2026 11:27:49 +0200 Subject: [PATCH v3 02/50] docs/system/arm/aspeed: add the sanmiguel-bmc machine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-2-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , Jamin Lin , =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056474; l=930; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=f+ewNztwtHsQvjNwITmtmh2RHXZRe5TnF0pSYWV+BZo=; b=n/hPuH2OEZgEqvXG6jHRYPpF9OlmfLfbELivf7KRVn5BQ+oqc7dr1sZZmfoggz0VECaiEa2uW RReHHGEWT46CyBc+PauWC/CC/Di9uE27c3SaS/WDKTwCS3fFywj+scs X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.50; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f50.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792059944358158500 The Facebook SanMiguel BMC machine is supported by hw/arm but has never been listed in the Aspeed documentation. Add it to the AST2600 machine table. Reviewed-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- docs/system/arm/aspeed.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 933df41f96..f38f33cbe1 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -34,6 +34,7 @@ AST2600 SoC based machines : - ``bletchley-bmc`` Facebook Bletchley BMC - ``fby35-bmc`` Facebook fby35 BMC - ``catalina-bmc`` Facebook Catalina BMC +- ``sanmiguel-bmc`` Facebook SanMiguel BMC - ``anacapa-bmc`` Facebook Anacapa BMC - ``gb200nvl-bmc`` Nvidia GB200nvl BMC =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060066; cv=none; d=zohomail.com; s=zohoarc; b=f/KdLvrR1eSIfNVCwioT+YlPjFi/8Wjgb0h+mivVkFjYZpvU5sjQ1HVX+6GDi73ExAYTXwPqKIbD6JaF98H0OV0rn0RCVKPP3V9Gspfl/r435DFi/T2+rYWkwCGA+YNY/7tcYdjMdVrtDJyU5koscdiOQsvS8cn0/HXCNi+hfEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=dNC31SG6tiYYAq8uQ1zQOLn6F7XfN2if+RjCHtoxlkE=; b=j7oGA2ZjW+cMcZWtDmZWdrkUgv/Nuf+ZTq3BId7aIT80iWmQg6Yy/sx7Tdd0SJho02w4Wrz/NY0btBRo9/oVELEzzTGaZvBDlo30sWeQvHLSNXV9sOW9k5I4K5vzXXnK4WkZODXoVKO7lX/+iFgrEiF35vFJeWc+tGwk3sKtdsU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060066397323.3761923275749; Thu, 15 Oct 2026 03:27:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIdj-0000db-QP; Thu, 15 Oct 2026 06:24:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIdU-0000Xu-Ay for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:33 -0400 Received: from mail-wm1-f46.google.com ([209.85.128.46]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIdR-0003Dw-Sq for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:32 -0400 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4a022fee0caso48096255e9.1 for ; Thu, 15 Oct 2026 03:24:28 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Advertising a part there presents the guest with a flash device the hardware does not have. While here, add the missing year to the copyright line. Reviewed-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/arm/aspeed_ast2600_sanmiguel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast2600_sanmiguel.c b/hw/arm/aspeed_ast2600_sanm= iguel.c index 345a9c9416..ac2aef740a 100644 --- a/hw/arm/aspeed_ast2600_sanmiguel.c +++ b/hw/arm/aspeed_ast2600_sanmiguel.c @@ -1,7 +1,7 @@ /* * Facebook SanMiguel BMC * - * Copyright (c) Meta Platforms, Inc. and affiliates. + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. * * SPDX-License-Identifier: GPL-2.0-or-later */ @@ -384,7 +384,7 @@ static void aspeed_machine_sanmiguel_class_init(ObjectC= lass *oc, amc->hw_strap1 =3D SANMIGUEL_BMC_HW_STRAP1; amc->hw_strap2 =3D SANMIGUEL_BMC_HW_STRAP2; amc->fmc_model =3D "mx66l1g45g"; - amc->spi_model =3D "mx66l1g45g"; + amc->spi_model =3D NULL; amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC0_ON; amc->i2c_init =3D sanmiguel_bmc_i2c_init; --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060060; cv=none; d=zohomail.com; s=zohoarc; b=Yk3uJlfWJQK1WKxnwphtnMUiutGRmXfZ19N+x6XZXrLzPRugjpa5cwnUoqzDQS8zDEblnGU737dGmQUxzxBJsuslb5KOK/ofsSgAWEnUJp3pprWUDK/hd+AlcJx1h9dCMuiP+JeAvfVXm8EeCkgKu/tGlZogjIsdZULU+zTUZGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060060; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=wyuy2rktXggsAmL76/K7kLk/zQD6P6G+cIxBCgNKHGg=; b=dt3lyjMLCTGOsu9P0cidYYygqjEMD7PYniRwXk4q/V+4/14zDAzXIzVpJ/sAEwxRWcVBvhxDbtMZslUIqBp9XtcLQlUzqnl0HKUXaadJZsNSXLQ6MH1eWf7eEfd3yn0Cpv7+haPuE7crsDw6NrHrXHQQfmd3vUapdKaDJDkH2TA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060059880817.1349806870305; Thu, 15 Oct 2026 03:27:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIdk-0000eU-Nd; Thu, 15 Oct 2026 06:24:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIdd-0000a0-ER for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:43 -0400 Received: from mail-wm1-f43.google.com ([209.85.128.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIdZ-0003Ey-DN for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:39 -0400 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4956869750eso33947255e9.2 for ; Thu, 15 Oct 2026 03:24:35 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Remove them. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/i2c/i2c_mux_pca954x.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c index c603446028..c8e75da8b2 100644 --- a/hw/i2c/i2c_mux_pca954x.c +++ b/hw/i2c/i2c_mux_pca954x.c @@ -15,15 +15,12 @@ */ =20 #include "qemu/osdep.h" -#include "qapi/error.h" #include "hw/i2c/i2c.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_slave.h" #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" -#include "hw/core/sysbus.h" #include "qemu/log.h" -#include "qemu/module.h" #include "qemu/queue.h" #include "qom/object.h" #include "trace.h" --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060264; cv=none; d=zohomail.com; s=zohoarc; b=Gj/1eyORSz9ry4Nm+Wt32uHTR9MXbP3MPCVM9N7DcFcz8RDjZps4CFFDvU7NKsmxRqP1JIpKcMWob6jA/8OhC2B2EJPJTWWh6BM99PwAI9pzFTjd2Ewo3wo8vg1l4PIIYpiQ1rUkrZ8o6m4ssv8kptqW9qvYiwogB9ycJ8hh8tA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060264; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=X3AXgFUD8AgKXPTW4/FZ6BTazwwBpf6seraziZlMdxg=; b=Go0vEaZF9hJas33lteuVS5sLgAAfE4OsYKesgwTCR5JbaGUegeNcYJn9XWWsswgAaQtLaK3IX0SzwhJjVDMLLAZCKjsK9YIDq7q9AstJm9w4dJn+am8MWU9R8TmVEwmm2KITDtaCQLpWJ4GTW6v8tqMRbYW7cXi6z5ymknNhZ6I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179206026474133.669208430387016; Thu, 15 Oct 2026 03:31:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIdl-0000fy-W3; Thu, 15 Oct 2026 06:24:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIdk-0000dt-6U for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:48 -0400 Received: from mail-wm1-f52.google.com ([209.85.128.52]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIdg-0003Gp-Q0 for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:47 -0400 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4a1ad2e2391so20826575e9.0 for ; Thu, 15 Oct 2026 03:24:42 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. [89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd5f4319sm27078275e9.0.2026.10.15.03.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:24:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059881; x=1792664681; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=X3AXgFUD8AgKXPTW4/FZ6BTazwwBpf6seraziZlMdxg=; b=peHE0m5/xuzGjOLkvp0V+5R1kw/dRJw91mxHKI0aGH10VGVYCMjSvn6iIEDcxu5pD9 ReC4IA7VKt4O1gfFDP61DOjZuWUl5gXiAicHFCk9locNSNUV65Zcqy9KYDZGNj7glpOY K3jm5FooFyFqKFBkdTLtVGRinceOfk+ZNTmCT76OXO7MLhf6au9juF+/Sw4aRcVgoV6Y TM2c1azSCfarvXLxXlEqTyjhX1dqwRVarEN7FhfTYnJT1KgvESt0WdhH6qKOxB7udwJX QruX2U8yoC0dKZyj4MpN4v6sIc/fTKBU8qFkeoz4zXX7bE3BwOA/4a6Z5x/D0lERwsU2 wQ9w== X-Gm-Message-State: AFq9FYK3H4N7HD5HzteueKFwhd1rQqhJPadun80BMN0Ya7w+d48AfoA0 JH+ys/y9XAhGMy6crNec5+vlcSPRlVl5zhPXg379HUOBX+N3xpShykga5w2l04rw X-Gm-Gg: AYBFou0vZysLJ8uZFDstSwHdaQsZ05OSfyXYcoOE8Jlx+cFaVdgIGNEvPuldOb4VLCi M8GNd2XaASJPsDHwDGzXodDh6X/lKmMHNbZvhg1N8zLWFt3Xg3v6yNIjGbL50K5yESwi9Vy+5A/ 9Pht40NHNMdk5wIWa9NExgNDqj8QLdCIWhVjD+YNP6B3ALcbpcC8ZlbSmMprB76AKbAP0GkdvwM c8JADlajUwN+RYWUFs9YLs0Xk+9lJ4bijHegM4YctVBl/Zc7saNIO0/8/Wb6ldl3fzqZKwJPzSV IR1hxhC2seSqUfxDvrX1jftHFGShIIJvGecjggWlNtg6y7VmtbhsqtVTlgzHM4W7tJJJ6FSTRp9 nAWBcD71PJf1KBJiW08E2tckjQdOcAyh8d37crJ0i54txXwqu5IMCz/TC+QBp0OiVFluHnqcpAn V1K+nxMfuYoRCeRY9sK1NSPinOgrRRfjcvTce6eZjJJ3Po/ZpZIaBZZ3nY8Ae9eVIKUuFWuV9Gy Y8tw3XUP1o3LbCD9WgNK88fvLnxjJKZXpr1VOn20d9NqQ== X-Received: by 2002:a05:600c:8b74:b0:4a0:2847:b6ee with SMTP id 5b1f17b1804b1-4a18e4fb8c1mr378168995e9.35.1792059881396; Thu, 15 Oct 2026 03:24:41 -0700 (PDT) Date: Thu, 15 Oct 2026 11:27:52 +0200 Subject: [PATCH v3 05/50] hw/i2c: pca954x: add PCA9545 4-channel mux model MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-5-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056474; l=6669; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=ykcUlVqHhqJGuTff7Rzxb+RiDS389J6oA8jUVbC79jg=; b=5txR5Ef196CTG75Bcpc4to3b7o5Wn9yehvmwClGsUT3x3/apdycdPTJlArnF//6UXbEzeTM6P hIiyA5i++iiCGMKdRmog2S5PLus+z4swWqy7sIEcAijGmWQTgo5teG4 X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.52; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f52.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060266549158500 The PCA9545 is a 4-channel I2C mux/switch. What sets it apart from the plain PCA9546 is its interrupt logic: one INTn input per channel and a shared INT output, both active low, asserted whenever any channel interrupt is active. Model this behind a new has_irq class flag. The PCA9545 gains four named "interrupt" GPIO inputs and an "interrupt-out" output, and its control read-back merges the latched status nibble; the plain PCA9546/PCA9548 switches keep their previous behaviour. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/i2c/i2c_mux_pca954x.c | 71 ++++++++++++++++++++++++++++++++++++= ++-- include/hw/i2c/i2c_mux_pca954x.h | 1 + 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c index c8e75da8b2..4bb078a03c 100644 --- a/hw/i2c/i2c_mux_pca954x.c +++ b/hw/i2c/i2c_mux_pca954x.c @@ -12,12 +12,20 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. + * + * Limitations: + * - A control write longer than one byte is rejected rather than retainin= g the + * last received byte as the datasheet specifies. + * - On reset the cached per-channel interrupt state is cleared; a downstr= eam + * INT input that stays asserted across the reset is not re-sampled unti= l it + * next toggles. */ =20 #include "qemu/osdep.h" #include "hw/i2c/i2c.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_slave.h" +#include "hw/core/irq.h" #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" #include "qemu/log.h" @@ -26,11 +34,15 @@ #include "trace.h" =20 #define PCA9548_CHANNEL_COUNT 8 +#define PCA9545_CHANNEL_COUNT 4 #define PCA9546_CHANNEL_COUNT 4 =20 /* * struct Pca954xState - The pca954x state object. * @control: The value written to the mux control. + * @int_status: Per-channel interrupt status, for parts with interrupt log= ic. + * @int_out: The mux INT output, driven low while any channel interrupt is + * active. * @channel: The set of i2c channel buses that act as channels which own t= he * i2c children. */ @@ -38,6 +50,8 @@ typedef struct Pca954xState { SMBusDevice parent; =20 uint8_t control; + uint8_t int_status; + qemu_irq int_out; =20 bool enabled[PCA9548_CHANNEL_COUNT]; I2CBus *bus[PCA9548_CHANNEL_COUNT]; @@ -48,11 +62,13 @@ typedef struct Pca954xState { /* * struct Pca954xClass - The pca954x class object. * @nchans: The number of i2c channels this device has. + * @has_irq: Whether the part implements interrupt logic. */ typedef struct Pca954xClass { SMBusDeviceClass parent; =20 uint8_t nchans; + bool has_irq; } Pca954xClass; =20 #define TYPE_PCA954X "pca954x" @@ -116,8 +132,10 @@ static void pca954x_enable_channel(Pca954xState *s, ui= nt8_t enable_mask) =20 static void pca954x_write(Pca954xState *s, uint8_t data) { - s->control =3D data; - pca954x_enable_channel(s, data); + Pca954xClass *c =3D PCA954X_GET_CLASS(s); + + s->control =3D c->has_irq ? data & ((1 << c->nchans) - 1) : data; + pca954x_enable_channel(s, s->control); =20 trace_pca954x_write_bytes(data); } @@ -148,16 +166,45 @@ static int pca954x_write_data(SMBusDevice *d, uint8_t= *buf, uint8_t len) static uint8_t pca954x_read_byte(SMBusDevice *d) { Pca954xState *s =3D PCA954X(d); + Pca954xClass *c =3D PCA954X_GET_CLASS(s); uint8_t data =3D s->control; + + /* + * On parts with interrupt logic the read-back byte carries the per-ch= annel + * interrupt status in the upper nibble. + */ + if (c->has_irq) { + data =3D (s->int_status << 4) | (s->control & 0x0f); + } + trace_pca954x_read_data(data); return data; } =20 +/* + * A downstream device drives one of the INTn inputs. INTn and INT are act= ive + * low, and both carry the physical level: 0 is asserted, 1 is idle. + */ +static void pca954x_irq_handler(void *opaque, int n, int level) +{ + Pca954xState *s =3D PCA954X(opaque); + + if (level) { + s->int_status &=3D ~(1 << n); + } else { + s->int_status |=3D (1 << n); + } + + qemu_set_irq(s->int_out, s->int_status =3D=3D 0); +} + static void pca954x_enter_reset(Object *obj, ResetType type) { Pca954xState *s =3D PCA954X(obj); /* Reset will disable all channels. */ pca954x_write(s, 0); + s->int_status =3D 0; + qemu_set_irq(s->int_out, 1); /* INT released */ } =20 I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel) @@ -169,6 +216,13 @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t cha= nnel) return pca954x->bus[channel]; } =20 +static void pca9545_class_init(ObjectClass *klass, const void *data) +{ + Pca954xClass *s =3D PCA954X_CLASS(klass); + s->nchans =3D PCA9545_CHANNEL_COUNT; + s->has_irq =3D true; +} + static void pca9546_class_init(ObjectClass *klass, const void *data) { Pca954xClass *s =3D PCA954X_CLASS(klass); @@ -184,12 +238,20 @@ static void pca9548_class_init(ObjectClass *klass, co= nst void *data) static void pca954x_realize(DeviceState *dev, Error **errp) { Pca954xState *s =3D PCA954X(dev); + Pca954xClass *c =3D PCA954X_GET_CLASS(dev); DeviceState *d =3D DEVICE(s); if (s->name) { d->id =3D g_strdup(s->name); } else { d->id =3D g_strdup_printf("pca954x[%x]", s->parent.i2c.address); } + + if (c->has_irq) { + /* One INTn input per channel, plus the shared INT output. */ + qdev_init_gpio_in_named(dev, pca954x_irq_handler, "interrupt", + c->nchans); + qdev_init_gpio_out_named(dev, &s->int_out, "interrupt-out", 1); + } } =20 static void pca954x_init(Object *obj) @@ -242,6 +304,11 @@ static const TypeInfo pca954x_info[] =3D { .class_init =3D pca954x_class_init, .abstract =3D true, }, + { + .name =3D TYPE_PCA9545, + .parent =3D TYPE_PCA954X, + .class_init =3D pca9545_class_init, + }, { .name =3D TYPE_PCA9546, .parent =3D TYPE_PCA954X, diff --git a/include/hw/i2c/i2c_mux_pca954x.h b/include/hw/i2c/i2c_mux_pca9= 54x.h index 3dd25ec983..19a1050505 100644 --- a/include/hw/i2c/i2c_mux_pca954x.h +++ b/include/hw/i2c/i2c_mux_pca954x.h @@ -3,6 +3,7 @@ =20 #include "hw/i2c/i2c.h" =20 +#define TYPE_PCA9545 "pca9545" #define TYPE_PCA9546 "pca9546" #define TYPE_PCA9548 "pca9548" =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060059; cv=none; d=zohomail.com; s=zohoarc; b=FgT93aB88yxooQZo+08gkknExUWLUVDEKZcjlNQqLtByj7Rzze5XqG1speGXGQratpTROG3FAbgN24k80DeeTMgErsNH7vW/KgVuQEmuAlDDEE/TVld3UnxrPo2MBh6cG97dwwf5Yj+3+NLz9ckyH9n58g/MEKfLJNkRGwxJrdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060059; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=JjVEKQw/S4Vf3YjNZwTZdRS7A1MNMQtDr+WqsJKWaZY=; b=ZsWFPqDntVlqE11do935+ysNOYGGzbJa1kLkNpR+NoS6KojEWmrZ44T/PssGPa1K8UaGbOyefZvTeJE8SiPejrdG7d4sq6lKcdYuO3vuCBqKnM+aaLjunhJV+1sAw8CKSwCS3S4mPISJzLMpe6kkiHHAY4ma49yFIK7e57ymcXo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060059666813.3155460738246; Thu, 15 Oct 2026 03:27:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIdq-0000iA-Cc; Thu, 15 Oct 2026 06:24:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIdo-0000hQ-9E for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:52 -0400 Received: from mail-wm1-f48.google.com ([209.85.128.48]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIdl-0003JF-SU for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:52 -0400 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4a180fbeef5so46388545e9.1 for ; Thu, 15 Oct 2026 03:24:49 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. [89.93.216.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0ac4f65sm18029670f8f.39.2026.10.15.03.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:24:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059888; x=1792664688; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=JjVEKQw/S4Vf3YjNZwTZdRS7A1MNMQtDr+WqsJKWaZY=; b=hs2S7jSLSM2Kk7CjOEYcfdYEUooT1/yLp7Q/iiDsF2qe8ZmAPjhWtu4yUiCk7ATcpy JZnRaywTopmNsXeA7Bv9ySS3HffIGy4CwZmf2VLfGYB+zsohxdPOiw+pWHm9gxyKSYvz KhihTEdhanLP+tjca0ateZbfSTXPQH6Xl587ikMKZAsnUQ+jZHLvfi3HUnkwpdnacQ3o m9ueqJjKikKuG8M68oIV1qXX+k3EWMrFoYS911xTgdTxH/6vNYkVBwmfvQy3nmC9d0fV ed/nfytmww2+YWOKqA21zzBXkcl/OXb5DijxvBphbLISYF+YmK7V/7tHLcJQTsEQiii/ R6lA== X-Gm-Message-State: AFq9FYJuOo+PPEely5pWKTHI59hJmGl7TeUU5FCXBZcC262754jeDj7W JlKgOG7iCSOxOh3Zi+j9s5alhtWUuHiDgOwC0/erfjrSnffZf8f1eo86NW3mAueR X-Gm-Gg: AYBFou0POlVoYjgCV1Ms6LX949VNoWzPz8akuZL+CU/YZSfque+ISLlhlgtkuLhHoB9 La0bAdpzD2pmvGV1CvmLDBcY4wu7u4+7XdP6J7a4wMbLlFLoKFrOcq7tNd9Mz9eHTemMguwLCJB WuBdpGzjsSJSCW2Q2l4HNPAJJebe3I1l2F/V7h1YKbhTIQFH1fziESi3DVx3H6T31KPrRlcFywj wMWIZpZNfiDRsp8ufBxK78vZiiPd4IKzstaBgkivR5M3xQdn4QP/evxuL2OFwcHIhb50IS8Ou+r V2Pre2kqKS8UAQqm8CKF+BBwKxG9BSo0zDy339YBh4KHPM/IWl2N6xtoXv1ilueV+LLIJczh0gr 1u2fz4ILcECPqDxSdBE76aKKTKspygEw/haItdCDPFIqTQPF4N44zr7zmH3v5OcPIc9MxQaG1f7 Sw7AXni7MT6qUoKpniAPOfkmmtBwXYHKeU7bmYW2p5DBcBccqeeLSzAJVVgN1rNBpKDF+qH7PMV YX4/oJKvxAv+Syl3oTI62CoPg/oX4OD5pEbRJQQSzQRPQ== X-Received: by 2002:a05:600c:548f:b0:4a1:a39b:e71e with SMTP id 5b1f17b1804b1-4a1a39becefmr227675705e9.5.1792059888163; Thu, 15 Oct 2026 03:24:48 -0700 (PDT) Date: Thu, 15 Oct 2026 11:27:53 +0200 Subject: [PATCH v3 06/50] hw/i2c: pca954x: migrate mux state MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-6-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056474; l=1966; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=t4t1cTl1TBk4ZFey4DyqPbSCs2Si9Ly258qm/fFJSEU=; b=RTok9Uwq6hu+67AmOoubb0na8Uw7B/SmD2aMaJ10Gg1O+bpY9eZEIbEGn5USrsV78uXyULqjh O6rYKduPQU7Aq9mP4TQqZg3SD/g2XgxQ5sDAkEAujERHEJqdO0eAEJc X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.48; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f48.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060060535158500 The pca954x model had no VMStateDescription, so neither the channel selection nor the PCA9545 interrupt status survived a migration. This changes the migration stream of the pre-existing PCA9546 and PCA9548, which an older QEMU rejects. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/i2c/i2c_mux_pca954x.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c index 4bb078a03c..597e57d99a 100644 --- a/hw/i2c/i2c_mux_pca954x.c +++ b/hw/i2c/i2c_mux_pca954x.c @@ -28,6 +28,7 @@ #include "hw/core/irq.h" #include "hw/core/qdev.h" #include "hw/core/qdev-properties.h" +#include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/queue.h" #include "qom/object.h" @@ -270,6 +271,28 @@ static void pca954x_init(Object *obj) } } =20 +static int pca954x_post_load(void *opaque, int version_id) +{ + Pca954xState *s =3D PCA954X(opaque); + + pca954x_enable_channel(s, s->control); + qemu_set_irq(s->int_out, s->int_status =3D=3D 0); + return 0; +} + +static const VMStateDescription vmstate_pca954x =3D { + .name =3D "pca954x", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D pca954x_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_SMBUS_DEVICE(parent, Pca954xState), + VMSTATE_UINT8(control, Pca954xState), + VMSTATE_UINT8(int_status, Pca954xState), + VMSTATE_END_OF_LIST() + }, +}; + static const Property pca954x_props[] =3D { DEFINE_PROP_STRING("name", Pca954xState, name), }; @@ -287,6 +310,7 @@ static void pca954x_class_init(ObjectClass *klass, cons= t void *data) =20 dc->desc =3D "Pca954x i2c-mux"; dc->realize =3D pca954x_realize; + dc->vmsd =3D &vmstate_pca954x; =20 k->write_data =3D pca954x_write_data; k->receive_byte =3D pca954x_read_byte; --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792059985; cv=none; d=zohomail.com; s=zohoarc; b=NHNaao9VFLAzWkHZgm0aQNISLENhSdlVJ9Cqr7+auLDAghn7raeL+eMtBybwCLtapst6O9FBvWq1Ci8x0hlzHEaJsZN59+qh1TAezivXNP43XUpC7k2Y2I53g2Qao35y9yMfxv4HpZc3wUgHvPU4lYFUW+NVLRqXgohyzV3fUBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792059985; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=61NEYluxRsQGvtMueBIKvSSCDkn5fQLszcxox8Hk6CM=; b=PrBjsFyrh7725nGOf+8sMogFSMqoc4yiNaK4bHHwNxjvHCFPkrZTcTkKRu6UPxr33mQIMd4BgCPdhaxeYZbtMGf1Fuc9IPLl51rhuqQ4IYbwCS94I2ZLZ2pRcQGwGoRQdyWlD9VVv5sd0oCzSDv9wQIPhFPO8zqQSD+qaCwu5iI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792059985660113.03327590161143; Thu, 15 Oct 2026 03:26:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIdx-0000mf-7q; Thu, 15 Oct 2026 06:25:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIdv-0000lH-D8 for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:59 -0400 Received: from mail-wr1-f48.google.com ([209.85.221.48]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIds-0003KZ-FC for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:24:59 -0400 Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-48c4649b35bso258772f8f.3 for ; Thu, 15 Oct 2026 03:24:56 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- tests/qtest/meson.build | 1 + tests/qtest/pca9545-test.c | 116 +++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 117 insertions(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 200abf6f36..e05d8a07b9 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -336,6 +336,7 @@ qos_test_ss.add( 'ne2000-test.c', 'tulip-test.c', 'nvme-test.c', + 'pca9545-test.c', 'pca9552-test.c', 'pca9554-test.c', 'pca9555-test.c', diff --git a/tests/qtest/pca9545-test.c b/tests/qtest/pca9545-test.c new file mode 100644 index 0000000000..91f56db92f --- /dev/null +++ b/tests/qtest/pca9545-test.c @@ -0,0 +1,116 @@ +/* + * QTest testcase for the PCA9545 4-channel I2C switch with interrupt logic + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "libqos/qgraph.h" +#include "libqos/i2c.h" + +#define PCA9545_TEST_ID "pca9545-test" +#define PCA9545_TEST_ADDR 0x70 +#define PCA9545_TEST_PATH "/machine/peripheral/" PCA9545_TEST_ID + +/* INTn and INT are active low: level 0 is asserted. */ +#define INT_ASSERTED 0 +#define INT_RELEASED 1 + +/* The mux has no register pointer: a read/write moves a single control by= te. */ +static uint8_t pca9545_get(QI2CDevice *dev) +{ + uint8_t val; + + qi2c_recv(dev, &val, 1); + return val; +} + +static void pca9545_set(QI2CDevice *dev, uint8_t val) +{ + qi2c_send(dev, &val, 1); +} + +static void pca9545_set_int(unsigned chan, int level) +{ + qtest_set_irq_in(global_qtest, PCA9545_TEST_PATH, "interrupt", chan, l= evel); +} + +/* Channel selection is the lower nibble; the upper nibble reads back 0. */ +static void test_channel_select(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0x00); + + pca9545_set(dev, 0x05); /* channels 0 and 2 */ + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0x05); + + pca9545_set(dev, 0x0f); /* all channels */ + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0x0f); + + pca9545_set(dev, 0x00); + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0x00); +} + +/* + * The interrupt status is reported in the upper nibble (INT3..INT0) and is + * latched regardless of which channels are selected (PCA9545A Table 5). + */ +static void test_interrupt_status(void *obj, void *data, QGuestAllocator *= alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + pca9545_set_int(1, INT_ASSERTED); + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0x20); + + pca9545_set(dev, 0x01); + pca9545_set_int(3, INT_ASSERTED); + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0xa1); /* INT3 | INT1 | chan= nel 0 */ + + pca9545_set_int(1, INT_RELEASED); + g_assert_cmphex(pca9545_get(dev), =3D=3D, 0x81); /* INT3 | channel 0 */ +} + +/* The INT output is pulled low while any channel interrupt is active. */ +static void test_interrupt_output(void *obj, void *data, QGuestAllocator *= alloc) +{ + qtest_irq_intercept_out_named(global_qtest, PCA9545_TEST_PATH, + "interrupt-out"); + + /* + * Interception starts with no recorded level, so drive an idle input + * first to make the mux publish the released state of its output. + */ + pca9545_set_int(0, INT_RELEASED); + g_assert_true(get_irq(0)); + + pca9545_set_int(0, INT_ASSERTED); + g_assert_false(get_irq(0)); + + pca9545_set_int(2, INT_ASSERTED); + g_assert_false(get_irq(0)); + + pca9545_set_int(0, INT_RELEASED); + g_assert_false(get_irq(0)); + pca9545_set_int(2, INT_RELEASED); + g_assert_true(get_irq(0)); +} + +static void pca9545_register_nodes(void) +{ + QOSGraphEdgeOptions opts =3D { + .extra_device_opts =3D "id=3D" PCA9545_TEST_ID ",address=3D0x70" + }; + add_qi2c_address(&opts, &(QI2CAddress) { PCA9545_TEST_ADDR }); + + qos_node_create_driver("pca9545", i2c_device_create); + qos_node_consumes("pca9545", "i2c-bus", &opts); + + qos_add_test("channel-select", "pca9545", test_channel_select, NULL); + qos_add_test("interrupt-status", "pca9545", test_interrupt_status, NUL= L); + qos_add_test("interrupt-output", "pca9545", test_interrupt_output, NUL= L); +} +libqos_init(pca9545_register_nodes); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 2 +- include/hw/rtc/ds1338.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 5f1ee2e410..f8b3340bf0 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -12,6 +12,7 @@ =20 #include "qemu/osdep.h" #include "hw/i2c/i2c.h" +#include "hw/rtc/ds1338.h" #include "migration/vmstate.h" #include "qemu/bcd.h" #include "qom/object.h" @@ -29,7 +30,6 @@ #define HOURS_PM 0x20 #define CTRL_OSF 0x20 =20 -#define TYPE_DS1338 "ds1338" OBJECT_DECLARE_SIMPLE_TYPE(DS1338State, DS1338) =20 struct DS1338State { diff --git a/include/hw/rtc/ds1338.h b/include/hw/rtc/ds1338.h new file mode 100644 index 0000000000..f4cfe6a8e7 --- /dev/null +++ b/include/hw/rtc/ds1338.h @@ -0,0 +1,20 @@ +/* + * MAXIM DS1338 I2C RTC+NVRAM + * + * Copyright (c) 2009 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GNU GPL v2. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_RTC_DS1338_H +#define HW_RTC_DS1338_H + +#define TYPE_DS1338 "ds1338" + +#endif --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060512; cv=none; d=zohomail.com; s=zohoarc; b=ldgHRxBu4i33dIPIljkD7yhDI3ft0x6MiYLoQcMQunxryYSuXOPgNvFgCJ7EEoNQmsy0F3m6lVZIf30iXIIFhw/DtmPmaXgXybLNkXvL2djsHfJf+8ZXWesN5yxCPxZTMw2WrFBrUYxSHgAWRwOVLmPKV1KJYwzeD3Ny3z8Yp9g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060512; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=SfzPIisKau/guu9CGMEvhUvPFp7BlVrgkg8vEC0f/kM=; b=IrFzi02Qq9yEqwvaK2amVPytqiCdm66rQ7mwV5xv14tyOeNyc4sK79XQOMRH0VEvn1tqSF39Cab53HbQtdpV2CUVh19APWYYavsAeE1BKEvl+FNTJpWDqchS5Ni/7L2LaicIi6T60mhLTtAKxkbfacHnF8K0d2KHz8AI8mKRPrU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060512511815.0742607709492; Thu, 15 Oct 2026 03:35:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIeK-0001Al-9Z; Thu, 15 Oct 2026 06:25:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIeD-00015e-5F for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:18 -0400 Received: from mail-wm1-f53.google.com ([209.85.128.53]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIe9-0003dP-3T for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:16 -0400 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4a022fee0caso48103615e9.1 for ; Thu, 15 Oct 2026 03:25:08 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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No functional change. Reviewed-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Acked-by: Bernhard Beschow Signed-off-by: Emmanuel Blot --- hw/arm/aspeed_ast2400_palmetto.c | 4 +++- hw/arm/aspeed_ast2400_supermicrox11.c | 4 +++- hw/arm/aspeed_ast2500_romulus.c | 4 +++- hw/arm/aspeed_ast2500_supermicro-x11spi.c | 4 +++- hw/arm/aspeed_ast2500_witherspoon.c | 4 +++- hw/arm/aspeed_ast2600_bletchley.c | 3 ++- hw/arm/aspeed_ast2600_catalina.c | 2 +- hw/arm/aspeed_ast2600_sanmiguel.c | 3 +-- hw/arm/realview.c | 3 ++- hw/arm/versatilepb.c | 3 ++- hw/ppc/e500.c | 3 ++- hw/riscv/tt_atlantis.c | 3 ++- 12 files changed, 27 insertions(+), 13 deletions(-) diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palme= tto.c index e2350e5b6c..185185f0bb 100644 --- a/hw/arm/aspeed_ast2400_palmetto.c +++ b/hw/arm/aspeed_ast2400_palmetto.c @@ -11,6 +11,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/i2c/smbus_eeprom.h" +#include "hw/rtc/ds1338.h" =20 /* Palmetto hardware value: 0x120CE416 */ #define PALMETTO_BMC_HW_STRAP1 ( \ @@ -36,7 +37,8 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) * The palmetto platform expects a ds3231 RTC but a ds1338 is * enough to provide basic RTC features. Alarms will be missing */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x= 68); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), TYPE_DS1338, + 0x68); =20 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_= supermicrox11.c index c75898cc6d..051e072c5a 100644 --- a/hw/arm/aspeed_ast2400_supermicrox11.c +++ b/hw/arm/aspeed_ast2400_supermicrox11.c @@ -11,6 +11,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/i2c/smbus_eeprom.h" +#include "hw/rtc/ds1338.h" =20 /* TODO: Find the actual hardware value */ #define SUPERMICROX11_BMC_HW_STRAP1 ( \ @@ -36,7 +37,8 @@ static void supermicrox11_bmc_i2c_init(AspeedMachineState= *bmc) * The palmetto platform expects a ds3231 RTC but a ds1338 is * enough to provide basic RTC features. Alarms will be missing */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x= 68); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), TYPE_DS1338, + 0x68); =20 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulu= s.c index 340a74408b..87f90ed361 100644 --- a/hw/arm/aspeed_ast2500_romulus.c +++ b/hw/arm/aspeed_ast2500_romulus.c @@ -10,6 +10,7 @@ #include "qapi/error.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" +#include "hw/rtc/ds1338.h" =20 /* Romulus hardware value: 0xF10AD206 */ #define ROMULUS_BMC_HW_STRAP1 ( \ @@ -29,7 +30,8 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc) * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is * good enough */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_DS1338, + 0x32); } =20 static void aspeed_machine_romulus_class_init(ObjectClass *oc, diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2= 500_supermicro-x11spi.c index 5a7e49d6cc..dc0248422d 100644 --- a/hw/arm/aspeed_ast2500_supermicro-x11spi.c +++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c @@ -11,6 +11,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/i2c/smbus_eeprom.h" +#include "hw/rtc/ds1338.h" =20 /* TODO: Find the actual hardware value */ #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ @@ -32,7 +33,8 @@ static void supermicro_x11spi_bmc_i2c_init(AspeedMachineS= tate *bmc) * The palmetto platform expects a ds3231 RTC but a ds1338 is * enough to provide basic RTC features. Alarms will be missing */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x= 68); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), TYPE_DS1338, + 0x68); =20 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_wi= therspoon.c index 26ddb67347..c69065846c 100644 --- a/hw/arm/aspeed_ast2500_witherspoon.c +++ b/hw/arm/aspeed_ast2500_witherspoon.c @@ -14,6 +14,7 @@ #include "hw/sensor/tmp105.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/gpio/pca9552.h" +#include "hw/rtc/ds1338.h" =20 /* Witherspoon hardware value: 0xF10AD216 */ #define WITHERSPOON_BMC_HW_STRAP1 ( \ @@ -70,7 +71,8 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *= bmc) * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is * good enough */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0= x32); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_DS1338, + 0x32); =20 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, eeprom_buf); diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_blet= chley.c index 6fa606c047..0e746055a2 100644 --- a/hw/arm/aspeed_ast2600_bletchley.c +++ b/hw/arm/aspeed_ast2600_bletchley.c @@ -12,6 +12,7 @@ #include "hw/arm/aspeed_soc.h" #include "hw/gpio/pca9552.h" #include "hw/nvram/eeprom_at24c.h" +#include "hw/rtc/ds1338.h" =20 #define TYPE_TMP421 "tmp421" /* Bletchley hardware value */ @@ -44,7 +45,7 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bm= c) /* Bus 6 */ at24c_eeprom_init(i2c[6], 0x56, 65536); /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ - i2c_slave_create_simple(i2c[6], "ds1338", 0x51); + i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x51); =20 =20 /* Bus 7 */ diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 4f2b396f6f..b15d932086 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -14,6 +14,7 @@ #include "hw/gpio/pca9552.h" #include "hw/gpio/pca9554.h" #include "hw/nvram/eeprom_at24c.h" +#include "hw/rtc/ds1338.h" #include "hw/sensor/tmp105.h" =20 /* Catalina hardware value */ @@ -22,7 +23,6 @@ #define CATALINA_BMC_RAM_SIZE (2 * GiB) =20 #define TYPE_TMP421 "tmp421" -#define TYPE_DS1338 "ds1338" =20 /* * "BMC Storage Module" FRU data. Generated with frugen. diff --git a/hw/arm/aspeed_ast2600_sanmiguel.c b/hw/arm/aspeed_ast2600_sanm= iguel.c index ac2aef740a..b0935683e2 100644 --- a/hw/arm/aspeed_ast2600_sanmiguel.c +++ b/hw/arm/aspeed_ast2600_sanmiguel.c @@ -13,6 +13,7 @@ #include "hw/gpio/pca9552.h" #include "hw/gpio/pca9554.h" #include "hw/nvram/eeprom_at24c.h" +#include "hw/rtc/ds1338.h" #include "hw/sensor/tmp105.h" =20 /* SanMiguel hardware values */ @@ -20,8 +21,6 @@ #define SANMIGUEL_BMC_HW_STRAP2 0x00000000 #define SANMIGUEL_BMC_RAM_SIZE (2 * GiB) =20 -#define TYPE_DS1338 "ds1338" - /* * "Front IO" FRU data. Generated with frugen. * diff --git a/hw/arm/realview.c b/hw/arm/realview.c index ceba0331b0..4cdf939511 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -28,6 +28,7 @@ #include "hw/intc/realview_gic.h" #include "hw/core/irq.h" #include "hw/i2c/arm_sbcon_i2c.h" +#include "hw/rtc/ds1338.h" #include "hw/sd/sd.h" #include "target/arm/cpu-qom.h" =20 @@ -323,7 +324,7 @@ static void realview_init(MachineState *machine, =20 dev =3D sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL); i2c =3D (I2CBus *)qdev_get_child_bus(dev, "i2c"); - i2c_slave_create_simple(i2c, "ds1338", 0x68); + i2c_slave_create_simple(i2c, TYPE_DS1338, 0x68); =20 /* Memory map for RealView Emulation Baseboard: */ /* 0x10000000 System registers. */ diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index f94bf96599..737cd21c27 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -18,6 +18,7 @@ #include "hw/pci/pci.h" #include "hw/i2c/i2c.h" #include "hw/i2c/arm_sbcon_i2c.h" +#include "hw/rtc/ds1338.h" #include "hw/core/irq.h" #include "hw/core/boards.h" #include "hw/block/flash.h" @@ -346,7 +347,7 @@ static void versatile_init(MachineState *machine, int b= oard_id) =20 dev =3D sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL); i2c =3D (I2CBus *)qdev_get_child_bus(dev, "i2c"); - i2c_slave_create_simple(i2c, "ds1338", 0x68); + i2c_slave_create_simple(i2c, TYPE_DS1338, 0x68); =20 /* Add PL041 AACI Interface to the LM4549 codec */ pl041 =3D qdev_new("pl041"); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 1876882a04..469cef9d2f 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -50,6 +50,7 @@ #include "hw/core/platform-bus.h" #include "hw/net/fsl_etsec/etsec.h" #include "hw/i2c/i2c.h" +#include "hw/rtc/ds1338.h" #include "hw/core/irq.h" #include "hw/sd/sdhci.h" #include "hw/misc/unimp.h" @@ -1025,7 +1026,7 @@ void ppce500_init(MachineState *machine) memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, sysbus_mmio_get_region(s, 0)); i2c =3D I2C_BUS(qdev_get_child_bus(dev, "i2c")); - i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); + i2c_slave_create_simple(i2c, TYPE_DS1338, RTC_REGS_OFFSET); =20 /* eSDHC */ if (pmc->has_esdhc) { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8a219afef7..910713c6bb 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -27,6 +27,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/riscv_aclint.h" #include "hw/misc/unimp.h" +#include "hw/rtc/ds1338.h" =20 #include "system/system.h" #include "system/device_tree.h" @@ -657,7 +658,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); 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Convert ds1338_reset() into a proper Resettable hold phase, dropping the legacy shim. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index f8b3340bf0..74aee6c746 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -208,9 +208,9 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) return 0; } =20 -static void ds1338_reset(DeviceState *dev) +static void ds1338_reset_hold(Object *obj, ResetType type) { - DS1338State *s =3D DS1338(dev); + DS1338State *s =3D DS1338(obj); =20 /* The clock is running and synchronized with the host */ s->offset =3D 0; @@ -224,11 +224,12 @@ static void ds1338_class_init(ObjectClass *klass, con= st void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 k->event =3D ds1338_event; k->recv =3D ds1338_recv; k->send =3D ds1338_send; - device_class_set_legacy_reset(dc, ds1338_reset); + rc->phases.hold =3D ds1338_reset_hold; dc->vmsd =3D &vmstate_ds1338; } =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792059941; cv=none; d=zohomail.com; s=zohoarc; b=lF8ZSWsd3Y5mYy/0ylOaQvNFDmLGWvzGKmydQjLp1xcbM01M1tMwfmrSJxfFw2C8pT9dsp7ZePNmsngkzn4MPR0NbonJAU2sXMFdjDFmLlI2y7edmLNc7f2Ku8VVwirbv063aSTf8SUjcICGwQ6fOQDTlBDT3mJQPC3vvkzPyhM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792059941; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=55Fgqc9VQyRpyCCP2Jau8AxqRXuSeRGIW2uq0lzhQEw=; b=Jlwswjs0JRSacSNo8V02f0En2yU5j4LyqviZwzUWvkQqqywfPbDfhoqm450NKlf23p6i5tH0yR+GcIzNXZQIbhadZklF4oQ5LCLCJavwuHLB5QBJAoc7zYaOIQptV3kBKJBEHjhamG5sC7oOFk1MDw666oKiiNQb8rvJ0cgUggk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792059940952936.8800055230369; Thu, 15 Oct 2026 03:25:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIeS-0001NM-O4; Thu, 15 Oct 2026 06:25:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIeL-0001F5-1H for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:25 -0400 Received: from mail-wm1-f52.google.com ([209.85.128.52]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIeI-0003iY-5E for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:24 -0400 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4a172eb31f0so44201505e9.1 for ; Thu, 15 Oct 2026 03:25:21 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 74aee6c746..1755a3a37c 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -57,7 +57,7 @@ static const VMStateDescription vmstate_ds1338 =3D { } }; =20 -static void capture_current_time(DS1338State *s) +static void ds1338_capture_current_time(DS1338State *s) { /* Capture the current time into the secondary registers * which will be actually read by the data transfer operation. @@ -85,7 +85,7 @@ static void capture_current_time(DS1338State *s) s->nvram[6] =3D to_bcd(now.tm_year - 100); } =20 -static void inc_regptr(DS1338State *s) +static void ds1338_inc_regptr(DS1338State *s) { /* The register pointer wraps around after 0x3F; wraparound * causes the current time/date to be retransferred into @@ -93,7 +93,7 @@ static void inc_regptr(DS1338State *s) */ s->ptr =3D (s->ptr + 1) & (NVRAM_SIZE - 1); if (!s->ptr) { - capture_current_time(s); + ds1338_capture_current_time(s); } } =20 @@ -108,7 +108,7 @@ static int ds1338_event(I2CSlave *i2c, enum i2c_event e= vent) * START_SEND, because the guest can't get at that data * without going through a START_RECV which would overwrite it. */ - capture_current_time(s); + ds1338_capture_current_time(s); break; case I2C_START_SEND: s->addr_byte =3D true; @@ -129,7 +129,7 @@ static uint8_t ds1338_recv(I2CSlave *i2c) =20 trace_ds1338_recv(s->ptr, res); =20 - inc_regptr(s); + ds1338_inc_regptr(s); return res; } =20 @@ -204,7 +204,7 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) } else { s->nvram[s->ptr] =3D data; } - inc_regptr(s); + ds1338_inc_regptr(s); return 0; } =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792059986; cv=none; d=zohomail.com; s=zohoarc; b=OGflTdyO24vTarfP1KgMEbCXw1+mAlD/PY5DNAGKzX6GBAsKwRIUpFee2CbjMtCSuN3YKIx/7vvCXkHnTVfuK+Tw4kCKiWUaZkhFURcSWy7/iiACQZ4e5FTLYy5RI72GIBWWF5AONsuy8VBLpMurzyLEYjcf4elHp0rvPzceYqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792059986; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=HXzz1QMMzZ/n/bvN4ExUkbI8aUO54r3IoptKCcv3x0M=; b=iEYBKFvDwS7Jx3cYsbvGQ9A9T9rDDmm2xdK6IrbNubs2eGDd9Gvhk6NuxW87iSXd9H+SEnZCdJScGd25ngBWTdE+s9nnVjUpu7oQAHsgY+Br5qdqNYZBTWp3u2DhlXlIaYNN4p5AyIjxIyhvAMhLSPYeqwypojPc/BB171tM9YY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792059986385849.0472512987423; Thu, 15 Oct 2026 03:26:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIea-0001Us-Cy; Thu, 15 Oct 2026 06:25:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIeS-0001Ox-Rl for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:33 -0400 Received: from mail-wm1-f54.google.com ([209.85.128.54]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIeO-0003kQ-Hp for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:32 -0400 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4a01933b584so43891425e9.0 for ; Thu, 15 Oct 2026 03:25:28 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. [89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd9b8b5fsm64707865e9.9.2026.10.15.03.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:25:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059927; x=1792664727; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=HXzz1QMMzZ/n/bvN4ExUkbI8aUO54r3IoptKCcv3x0M=; b=rLfmbcSpEttKbKbY5FrvhsERyMP66euVECgL2w51Q20qE692fHDA6MLkcVcpdyKiBh PwKxrC5VoDspQAr2z0c4Z4sIhzu+ikieppOIxDelYXgnbedKg96whoGvXCw/g8OAbbjo qbJ0isCcGQ/RCtwHo7NAoq2aA8DnYkGKW80XsFOuMjZAw3DizLNyO5k00k3BXGPChJUq HwVGFwWVXFrbiHvhl+Qfr6JMFReAVGSjhgEeFizMkyJQQXbemSytlaWj2VTdov0TBbXX 1TQ39geudqDzlS1DqmdSf+Fgl0b9uvOr6T72qEqN2iC3gYNMQSaxMwmrzZ/8yF4/T48S F7wg== X-Gm-Message-State: AFq9FYLoLZjje4KVEztNcr6LgZhzlKVc8eSYQVENskyJs3ZzOSYkDwH6 MHJtPJ00aIEAu0Sp7URnqkhMXN9Jt8qCuV8m3UWnCzESyElWPKXdEZ8XNYOOEay1 X-Gm-Gg: AYBFou2lnkukDLvLrDRQgVoFlarAM1uUuQHuS1RXBYrRyogovvmuw4JZrjNlD9z3R8j yh6kfIZT8BNvGm96iMAmeqUqvojMG6WIHWZ8T1D33mz/NxOXO8vefu/n1N57o/oTkadnhohd7Yr TcRp2g2daxoLGCiWyhowGLefOQHNHgKi0GOVh/RYxqwomjLU7t9xcGvVg8KK9DrXNwOPTqBS1O5 tQhnqyI/rdOEKIOJvV5WfKdc2/ITH43puCNeuAtth3/qf/s+8IZ68mRBg3kYmZGjsjYRfA/hewo 8ccQxEISXdaYSkXlERmZu7rQh9iaifEIm0p0+MflIXWtNE4TLJ9cNFCrVFmk8ekgbEZZfygJoNG RyWxgwNzQOqBJggsvlxGFqKZHl/mX92fEf2nDdWHHxftfxmERdNFeE1MtgksWexyo8lpa95TTPP vZ1pKAVNjLXX2jgQ+XyJCLhJyUlREpwNIqzfeK+tbt5JQR4I4dZ7RTMHXTrSIY8EpiJlabp39Ss UXnoSqKjtqRa6X8Ev9DzYtPVW8+EeUH0Z7NEGQvdGwq+Q== X-Received: by 2002:a05:600c:4e01:b0:49f:ce78:3567 with SMTP id 5b1f17b1804b1-4a18e4afc3amr359952785e9.24.1792059926852; Thu, 15 Oct 2026 03:25:26 -0700 (PDT) Date: Thu, 15 Oct 2026 11:27:59 +0200 Subject: [PATCH v3 12/50] hw/rtc: ds1338: parameterise the register map via a device class MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-12-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056475; l=6152; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=niz1W2ft4OO1YofOLf1Lxh2AyTzJFOItAAqnZjDIB4k=; b=Ygv8bDxOTK8E2FKEGjhcxFe1cli3Hv7JzkKuV83w69/LRJK2KU397QdXlLiZqN4SEJPN3kdlc ajqbL2f8hXVBNFKf7c7DKHXg0vsRlmGnz0a7Mi6dcb/svx806mrTCck X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.54; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f54.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792059989112158500 In preparation for a register-compatible variant, refactor DS1338 register map. Introduce DS1338Class, carrying the register-pointer wrap boundary and the control/OSF register location and masks, and drive inc_regptr() and the control-register handling. The control-register power-on value is parameterised along with them, so the part comes up holding the contents its datasheet specifies rather than zero, and its oscillator-stop flag now reads set at power-on. Encode the year register modulo 100 (tm_year % 100) instead of tm_year - 100. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 71 ++++++++++++++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 53 insertions(+), 18 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 1755a3a37c..7eaa663113 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -30,7 +30,14 @@ #define HOURS_PM 0x20 #define CTRL_OSF 0x20 =20 -OBJECT_DECLARE_SIMPLE_TYPE(DS1338State, DS1338) +/* DS1338 register map */ +#define DS1338_NUM_REGS NVRAM_SIZE /* 0x00..0x3f, then wraps */ +#define DS1338_CONTROL 0x07 +#define DS1338_CTRL_MASK 0xb3 /* bits 2, 3 and 6 read back as ze= ro */ +/* POR: OUT, OSF, SQWE and both rate-select bits come up set. */ +#define DS1338_CTRL_RESET 0xb3 + +OBJECT_DECLARE_TYPE(DS1338State, DS1338Class, DS1338) =20 struct DS1338State { I2CSlave parent_obj; @@ -42,6 +49,17 @@ struct DS1338State { bool addr_byte; }; =20 +struct DS1338Class { + I2CSlaveClass parent_class; + + uint8_t num_regs; /* register-pointer wrap boundary */ + uint8_t ctrl_addr; /* control register address */ + uint8_t ctrl_mask; /* writable/read-back bits of the control reg = */ + uint8_t osf_addr; /* register holding the OSF flag */ + uint8_t osf_mask; /* OSF bit within osf_addr */ + uint8_t ctrl_reset; /* control-register power-on value */ +}; + static const VMStateDescription vmstate_ds1338 =3D { .name =3D "ds1338", .version_id =3D 2, @@ -82,16 +100,19 @@ static void ds1338_capture_current_time(DS1338State *s) s->nvram[3] =3D (now.tm_wday + s->wday_offset) % 7 + 1; s->nvram[4] =3D to_bcd(now.tm_mday); s->nvram[5] =3D to_bcd(now.tm_mon + 1); - s->nvram[6] =3D to_bcd(now.tm_year - 100); + s->nvram[6] =3D to_bcd(now.tm_year % 100); } =20 static void ds1338_inc_regptr(DS1338State *s) { - /* The register pointer wraps around after 0x3F; wraparound - * causes the current time/date to be retransferred into - * the secondary registers. + DS1338Class *k =3D DS1338_GET_CLASS(s); + + /* + * The register pointer wraps around after the last register; wraparou= nd + * causes the current time/date to be retransferred into the secondary + * registers. */ - s->ptr =3D (s->ptr + 1) & (NVRAM_SIZE - 1); + s->ptr =3D (s->ptr + 1) % k->num_regs; if (!s->ptr) { ds1338_capture_current_time(s); } @@ -136,11 +157,12 @@ static uint8_t ds1338_recv(I2CSlave *i2c) static int ds1338_send(I2CSlave *i2c, uint8_t data) { DS1338State *s =3D DS1338(i2c); + DS1338Class *k =3D DS1338_GET_CLASS(i2c); =20 trace_ds1338_send(s->ptr, data); =20 if (s->addr_byte) { - s->ptr =3D data & (NVRAM_SIZE - 1); + s->ptr =3D data % k->num_regs; s->addr_byte =3D false; return 0; } @@ -190,18 +212,19 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) break; } s->offset =3D qemu_timedate_diff(&now); - } else if (s->ptr =3D=3D 7) { - /* Control register. */ - - /* Ensure bits 2, 3 and 6 will read back as zero. */ - data &=3D 0xB3; - - /* Attempting to write the OSF flag to logic 1 leaves the - value unchanged. */ - data =3D (data & ~CTRL_OSF) | (data & s->nvram[s->ptr] & CTRL_OSF); - - s->nvram[s->ptr] =3D data; } else { + if (s->ptr =3D=3D k->ctrl_addr) { + /* Control register: reserved bits read back as zero. */ + data &=3D k->ctrl_mask; + } + if (s->ptr =3D=3D k->osf_addr) { + /* + * Attempting to write the OSF flag to logic 1 leaves the + * value unchanged. + */ + data =3D (data & ~k->osf_mask) | + (data & s->nvram[s->ptr] & k->osf_mask); + } s->nvram[s->ptr] =3D data; } ds1338_inc_regptr(s); @@ -211,11 +234,13 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) static void ds1338_reset_hold(Object *obj, ResetType type) { DS1338State *s =3D DS1338(obj); + DS1338Class *k =3D DS1338_GET_CLASS(s); =20 /* The clock is running and synchronized with the host */ s->offset =3D 0; s->wday_offset =3D 0; memset(s->nvram, 0, NVRAM_SIZE); + s->nvram[k->ctrl_addr] =3D k->ctrl_reset; s->ptr =3D 0; s->addr_byte =3D false; } @@ -225,12 +250,21 @@ static void ds1338_class_init(ObjectClass *klass, con= st void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); I2CSlaveClass *k =3D I2C_SLAVE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DS1338Class *dsc =3D DS1338_CLASS(klass); =20 k->event =3D ds1338_event; k->recv =3D ds1338_recv; k->send =3D ds1338_send; rc->phases.hold =3D ds1338_reset_hold; + dc->desc =3D "DS1338 I2C RTC with 56-byte NV RAM"; dc->vmsd =3D &vmstate_ds1338; + + dsc->num_regs =3D DS1338_NUM_REGS; + dsc->ctrl_addr =3D DS1338_CONTROL; + dsc->ctrl_mask =3D DS1338_CTRL_MASK; + dsc->osf_addr =3D DS1338_CONTROL; + dsc->osf_mask =3D CTRL_OSF; + dsc->ctrl_reset =3D DS1338_CTRL_RESET; } =20 static const TypeInfo ds1338_types[] =3D { @@ -238,6 +272,7 @@ static const TypeInfo ds1338_types[] =3D { .name =3D TYPE_DS1338, .parent =3D TYPE_I2C_SLAVE, .instance_size =3D sizeof(DS1338State), + .class_size =3D sizeof(DS1338Class), .class_init =3D ds1338_class_init, }, }; --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd68144fsm43754785e9.4.2026.10.15.03.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:25:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059934; x=1792664734; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=/7vqyfsfQSXKfw69CwuMNDomx2TM2p1e+fdBs9WDTis=; b=FInfuDkRmyKQ7C+BNtjOKc4h8hSFEV2pkHVrOXU5uyHsqCNWJrMMBlZn98bz2Skkjx ZfqrXtSSSN7E/NPjNIM4xg9oLVKP/LKnKf8l2kqNrW1JSeuHRTfIa779XtrqkuV15UJt zB/o5Ce6m919CVAtKD/AWaJeQKAY4ZAttbV1AqmF51F/D+LaVmCzcUJASTbayhD5Ngbt aF3DU/fdkz7jhpMYUplFfJuPeZ9/OB5SiqH1LSatLhwQT4mxH+mGTPIs6vS1H3FpH+rH Au5RGjxUKdO3CnvpkF6rqoWd/t2ueyT7TYOgfg3x+hBEumB5EbOpfr84jo7vklEzsyOD kHxw== X-Gm-Message-State: AFq9FYKCBDpNYJFzIpuh2pJbtPD5N3dU/I4u2gGDANChMnL47GoVxFH0 MuDD7xM7jXp/QZxu/Ae2pXjMGLG0P2pHKKFa+pUnZJeO3NzpVxXMN79bdWH0Mkxv X-Gm-Gg: AYBFou3Iv+lUwwsEmqOzBiFHdTgsH8vhCLjiVFLr8vyNFn6Djaje2L/p8hFTQTqgaQ+ 8kO08nO+O4EuZgUnzlGHpZ/b8mdQuSnKQHNvmlT8kt17cz9M67T31bzpdTEv9A94rZdJjZ6LO8F 3LEhng/+58HLAmXLv7WDB9lHMb9MXoGROfW2NNZhJxfRYiqv9pkhdpD9WZlCl+MO94U4C4ZGH4k Oe5Bc+ashnTaDz6wFd84J/796xmsgZm+uT4MxtLLRuDo6E0VefGl08vHbLPEJvOuleJfSdVHmr1 gltw7FMrAmlNCEpVcD39Kdcm3XKSdqb7ojD3dfB84A19s5b9t+pq4ugnQIOEzmESoi1j5sYFp0V 0b73Q0m9oz4Z7iSlSbSSUV5PoaZ5w6Gx1eJ261mPhWYpIUVzFbOW6keMIbwU1pvmCCGoJKAJBw3 rWGfDOdHQpQ4fb837jDYLQJLxSPGvVQQx5WmwScCQOF2jbK0wg1BCUb22ns//KlP8Zt342jFoej yf0yd9O+VaDWdG6gD8SyNOl2fB8n2yenuxDFgQ1GYEsAw== X-Received: by 2002:a05:600c:1d0b:b0:4a0:13ea:2ec3 with SMTP id 5b1f17b1804b1-4a18e4ddca6mr373974445e9.35.1792059933158; Thu, 15 Oct 2026 03:25:33 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:00 +0200 Subject: [PATCH v3 13/50] hw/rtc: ds1338: program the clock from the time registers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-13-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056475; l=6068; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=uej/UOj+V/lpxWjtnR1AN5iwpDxP7F3nxb3Qip3BUmg=; b=+WaU57kgTcaSV+G3yvRq6EYp7j5INJrXeUH8WFLguWiiFv+TvFUn9GrnEVfKmes/chigPXsyW Qd0nTma3H8aB8/yd0+xFZbukgmVlzvIqV4TKPeXsOWJLZCbbDHpuKiq X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.51; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f51.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060072691158500 A write to a time register rebuilt a struct tm from the current date, substituted the field being written and folded the result back into the offset. Every byte of a multi-byte transfer was therefore normalised against the fields the guest had not written yet: a date of 31 programmed while the month register still held a 30-day month moved the clock into the following month. Keep the written value in the register file and derive the offset from the file as a whole. This needs the registers refreshed on a START_SEND, as the hardware does on any START. Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 116 ++++++++++++++++++++++++++++++----------------------= ---- 1 file changed, 63 insertions(+), 53 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 7eaa663113..862e03bd32 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -8,6 +8,12 @@ * * Contributions after 2012-01-13 are licensed under the terms of the * GNU GPL, version 2 or (at your option) any later version. + * + * Limitations: + * - Writing the seconds register does not reset the internal countdown ch= ain, + * so the sub-second phase of the clock is not modelled. + * - Leap years follow the Gregorian rule, where the parts stop at 2100: t= hey + * derive the leap year from the two-digit year alone. */ =20 #include "qemu/osdep.h" @@ -75,6 +81,41 @@ static const VMStateDescription vmstate_ds1338 =3D { } }; =20 +/* Reconstruct a struct tm from the BCD time registers in nvram. */ +static void ds1338_time_from_regs(DS1338State *s, struct tm *now) +{ + qemu_get_timedate(now, s->offset); + now->tm_sec =3D from_bcd(s->nvram[0] & 0x7f); + now->tm_min =3D from_bcd(s->nvram[1] & 0x7f); + if (s->nvram[2] & HOURS_12) { + int tmp =3D from_bcd(s->nvram[2] & (HOURS_PM - 1)); + if (s->nvram[2] & HOURS_PM) { + tmp +=3D 12; + } + if (tmp % 12 =3D=3D 0) { + tmp -=3D 12; + } + now->tm_hour =3D tmp; + } else { + now->tm_hour =3D from_bcd(s->nvram[2] & (HOURS_12 - 1)); + } + now->tm_mday =3D from_bcd(s->nvram[4] & 0x3f); + now->tm_mon =3D from_bcd(s->nvram[5] & 0x1f) - 1; + now->tm_year =3D from_bcd(s->nvram[6]) + 100; +} + +static void ds1338_resync_from_regs(DS1338State *s) +{ + struct tm now; + int user_wday; + + ds1338_time_from_regs(s, &now); + s->offset =3D qemu_timedate_diff(&now); + qemu_get_timedate(&now, s->offset); + user_wday =3D (s->nvram[3] & 7) - 1; + s->wday_offset =3D (user_wday - now.tm_wday + 7) % 7; +} + static void ds1338_capture_current_time(DS1338State *s) { /* Capture the current time into the secondary registers @@ -123,16 +164,16 @@ static int ds1338_event(I2CSlave *i2c, enum i2c_event= event) DS1338State *s =3D DS1338(i2c); =20 switch (event) { - case I2C_START_RECV: - /* In h/w, capture happens on any START condition, not just a - * START_RECV, but there is no need to actually capture on - * START_SEND, because the guest can't get at that data - * without going through a START_RECV which would overwrite it. - */ - ds1338_capture_current_time(s); - break; case I2C_START_SEND: s->addr_byte =3D true; + /* fall through */ + case I2C_START_RECV: + /* + * In h/w the time is transferred to the user registers on any STA= RT + * condition, so a write modifies the running time rather than + * whatever the last read left behind. + */ + ds1338_capture_current_time(s); break; default: break; @@ -167,51 +208,20 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) return 0; } if (s->ptr < 7) { - /* Time register. */ - struct tm now; - qemu_get_timedate(&now, s->offset); - switch(s->ptr) { - case 0: - /* TODO: Implement CH (stop) bit. */ - now.tm_sec =3D from_bcd(data & 0x7f); - break; - case 1: - now.tm_min =3D from_bcd(data & 0x7f); - break; - case 2: - if (data & HOURS_12) { - int tmp =3D from_bcd(data & (HOURS_PM - 1)); - if (data & HOURS_PM) { - tmp +=3D 12; - } - if (tmp % 12 =3D=3D 0) { - tmp -=3D 12; - } - now.tm_hour =3D tmp; - } else { - now.tm_hour =3D from_bcd(data & (HOURS_12 - 1)); - } - break; - case 3: - { - /* The day field is supposed to contain a value in - the range 1-7. Otherwise behavior is undefined. - */ - int user_wday =3D (data & 7) - 1; - s->wday_offset =3D (user_wday - now.tm_wday + 7) % 7; - } - break; - case 4: - now.tm_mday =3D from_bcd(data & 0x3f); - break; - case 5: - now.tm_mon =3D from_bcd(data & 0x1f) - 1; - break; - case 6: - now.tm_year =3D from_bcd(data) + 100; - break; - } - s->offset =3D qemu_timedate_diff(&now); + /* + * Time register. The write lands in the register file and the clo= ck + * is then rebuilt from it as a whole: a transfer that programs the + * date before the month it belongs to must not be normalised away + * against the month still held from the previous date. + * + * TODO: Implement CH (stop) bit. + */ + static const uint8_t valid[7] =3D { + 0x7f, 0x7f, 0x7f, 0x07, 0x3f, 0x1f, 0xff + }; + + s->nvram[s->ptr] =3D data & valid[s->ptr]; + ds1338_resync_from_regs(s); } else { if (s->ptr =3D=3D k->ctrl_addr) { /* Control register: reserved bits read back as zero. */ --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060026; cv=none; d=zohomail.com; s=zohoarc; b=aElT58Gifp9cTuWwoMhsUCJ6ZDCB7a7jcD/akuKw/V1hUCIlA4v2cM17hfS7kG8AKXsq13AyQzENcGWyDRh8v2Czf7UgTXwO9h0hZd7aPnHHWZBYPTu4xOcuMlxwZHBgZdk3blrvjnw5oXBc2Ixox7Y9ZI4ceUEwwuhR8qkbJlM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060026; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=W5PhRPYjPeVIiLmDaG68Pb9QynlP1yOMDtzh8f0rn+Q=; b=Ea6Ovas1m89Bt2An6CsQPImgcvBtXDts+08+r27yoVNjROcs/ReTazH8Ve4jNQ6GwrbWtvO5oRqChjr8DWTgX9MgvnL7bNkxSEJNbsResNvX9niKsFiEH9r3IkuwF7eAAeaaqk62wrqJ9BfbSS04hKKc0Pn8qLKIdot/Sql5tEU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060026400609.1507334695615; Thu, 15 Oct 2026 03:27:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIfE-0002MU-NT; Thu, 15 Oct 2026 06:26:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIeg-0001hD-Hp for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:54 -0400 Received: from mail-wr1-f53.google.com ([209.85.221.53]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIec-0003nA-31 for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:44 -0400 Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-48bbb06e746so863464f8f.3 for ; Thu, 15 Oct 2026 03:25:41 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. [89.93.216.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0967affsm16109509f8f.1.2026.10.15.03.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:25:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059939; x=1792664739; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=W5PhRPYjPeVIiLmDaG68Pb9QynlP1yOMDtzh8f0rn+Q=; b=ZNoLSB+FLD2t/NtRY7LGHil3jaCIic1mMS0HaR2AbHV1SNO4VCUb0wj1L+SnFB+7bT dPslLNKg5VlQwksPrxRsDseVdgfukDID6UbtRvNzqDWuIpNJBYbNq/NDxwHK9zXp6YA0 MTGFZmiCgTsDQ5i41vhWxET6uo3zl65YeGcAQaQ1bsB3ivR3gMN4uuawwpAwCxc5Gla8 vglggt6j6cyGfpxPol8x+1NuT9jjdMf2/p7XMyHc86IF0Q0W8On+FXX7geB2wFZ9/6E3 zAf3pj8/JDymUT++fNwN4Xn4IhXAACFYRYQSCPl5HgQINt0aWWemr27SrLdht8cXeVd9 ei7Q== X-Gm-Message-State: AFq9FYKEGL5maGBtBcznqsbRruisj47dlAIpyFU+9doN0AHMzXPLkfZ6 enbw2v6eqasEyGjel7GrvpwfTzMFyN7lAoE5DLOBMwJmgNcxEo8gzgS9mQmTIUwq X-Gm-Gg: AYBFou3WrtUOSHpXyrvE4pBaKIOFvBh6DwSkxKtdtXYWgbZ6K89miclN2l5MqZtnKvo 3mVDF1Af3y3j2VXeIUh1iEjw8Cg8snZO1D/IjYQTdPL/e4j1J4XBCzpOByfxxh3PrpYGkH/+d+M hm1o8RRHAzD8sfyWIV8Eab/hTkVQsDFuo4tFTU58bqP3nqsefHT7h1qC3EGp2FTtr4ranZUwWju llO4dy5FG1ZcNdPiRRbK0Rzysvds3jurKo0m4MmbgBGJRpUn3dgr6EUMxOd0EwWq154ZSV4Hkae 6T8M9g8dgr6xcPcsYp4jcezxPaEoWLDGNyfmadp9JllSGay/bvWh87VZjLoQtRBgeU0plHEfeAM uoYegGNKr9npYWimwv/L02RSEJ+QbrJ0l37bYW8Y9UhCZG3iTJaWu/u3cm3RG6PgnyQYswB27RB Zw32Sv4Uv31ArW+Uk8e03m8STdHcHmTRxWKFeVE+xxrG4/yeSSIelwAUIYK/LTpTRUeFb7iWlIz TdOaT62MdImuhFPqVgNSVpk2TlZWKl29hXNu/3Nb/DtJw== X-Received: by 2002:a05:6000:4694:b0:48c:67d8:abd1 with SMTP id ffacd0b85a97d-48dba9be288mr25519734f8f.13.1792059939384; Thu, 15 Oct 2026 03:25:39 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:01 +0200 Subject: [PATCH v3 14/50] hw/rtc: ds1338: implement the DS1338 clock-halt bit MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-14-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056475; l=4398; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=Kzt6qfQ8xw5u2qhWKCAbs8upbxPA4Z4PtksNYulDrzo=; b=zIeN5UVvq13Nz2bsi2czZzqePs3GsxgGsdMwKogSUbKN2sAf7mp21XbHwLdmaLu+l9l+DVJSl xNaVjnGC9L9ARGqYeN1dsKxLbY7Cul0qUuzYJnF8SlYXRl8YE3WF57Z X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.221.53; envelope-from=eblot.ml@gmail.com; helo=mail-wr1-f53.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060028373158500 Bit 7 of the seconds register disables the oscillator, and the guest is expected to clear it before trusting the time. The bit was masked away on every write, so it always read back zero and the clock never stopped. The reset value stays clear rather than set as on real hardware, keeping the model's convention that the clock comes up running and synchronised with the host. Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 862e03bd32..79bcff4599 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -14,6 +14,7 @@ * so the sub-second phase of the clock is not modelled. * - Leap years follow the Gregorian rule, where the parts stop at 2100: t= hey * derive the leap year from the two-digit year alone. + * - The model comes up with the clock running; real hardware comes up hal= ted. */ =20 #include "qemu/osdep.h" @@ -53,6 +54,7 @@ struct DS1338State { uint8_t nvram[NVRAM_SIZE]; int32_t ptr; bool addr_byte; + bool osc_stopped; /* oscillator halted: time is frozen */ }; =20 struct DS1338Class { @@ -64,11 +66,12 @@ struct DS1338Class { uint8_t osf_addr; /* register holding the OSF flag */ uint8_t osf_mask; /* OSF bit within osf_addr */ uint8_t ctrl_reset; /* control-register power-on value */ + uint8_t ch_mask; /* Clock-halt bit in the seconds reg */ }; =20 static const VMStateDescription vmstate_ds1338 =3D { .name =3D "ds1338", - .version_id =3D 2, + .version_id =3D 3, .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { VMSTATE_I2C_SLAVE(parent_obj, DS1338State), @@ -77,6 +80,7 @@ static const VMStateDescription vmstate_ds1338 =3D { VMSTATE_UINT8_ARRAY(nvram, DS1338State, NVRAM_SIZE), VMSTATE_INT32(ptr, DS1338State), VMSTATE_BOOL(addr_byte, DS1338State), + VMSTATE_BOOL_V(osc_stopped, DS1338State, 3), VMSTATE_END_OF_LIST() } }; @@ -122,6 +126,11 @@ static void ds1338_capture_current_time(DS1338State *s) * which will be actually read by the data transfer operation. */ struct tm now; + + if (s->osc_stopped) { + return; + } + qemu_get_timedate(&now, s->offset); s->nvram[0] =3D to_bcd(now.tm_sec); s->nvram[1] =3D to_bcd(now.tm_min); @@ -213,15 +222,30 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) * is then rebuilt from it as a whole: a transfer that programs the * date before the month it belongs to must not be normalised away * against the month still held from the previous date. - * - * TODO: Implement CH (stop) bit. */ static const uint8_t valid[7] =3D { 0x7f, 0x7f, 0x7f, 0x07, 0x3f, 0x1f, 0xff }; + uint8_t mask =3D valid[s->ptr]; + bool halt =3D s->osc_stopped; =20 - s->nvram[s->ptr] =3D data & valid[s->ptr]; - ds1338_resync_from_regs(s); + if (s->ptr =3D=3D 0) { + mask |=3D k->ch_mask; + if (k->ch_mask) { + halt =3D data & k->ch_mask; + } + } + + if (halt && !s->osc_stopped) { + /* CH set: freeze the counters before the register is stored. = */ + ds1338_capture_current_time(s); + s->nvram[k->osf_addr] |=3D k->osf_mask; + } + s->nvram[s->ptr] =3D data & mask; + s->osc_stopped =3D halt; + if (!halt) { + ds1338_resync_from_regs(s); + } } else { if (s->ptr =3D=3D k->ctrl_addr) { /* Control register: reserved bits read back as zero. */ @@ -253,6 +277,7 @@ static void ds1338_reset_hold(Object *obj, ResetType ty= pe) s->nvram[k->ctrl_addr] =3D k->ctrl_reset; s->ptr =3D 0; s->addr_byte =3D false; + s->osc_stopped =3D false; } =20 static void ds1338_class_init(ObjectClass *klass, const void *data) @@ -275,6 +300,7 @@ static void ds1338_class_init(ObjectClass *klass, const= void *data) dsc->osf_addr =3D DS1338_CONTROL; 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Doing it from the shared pointer increment meant a write transfer long enough to wrap overwrote the bytes the guest had just sent with the current time. Move the refresh to the read path. Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 79bcff4599..c5fc74e6ca 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -12,6 +12,8 @@ * Limitations: * - Writing the seconds register does not reset the internal countdown ch= ain, * so the sub-second phase of the clock is not modelled. + * - The user registers are refreshed on a START and on a read that wraps = the + * register pointer, but not on a STOP. * - Leap years follow the Gregorian rule, where the parts stop at 2100: t= hey * derive the leap year from the two-digit year alone. * - The model comes up with the clock running; real hardware comes up hal= ted. @@ -157,15 +159,7 @@ static void ds1338_inc_regptr(DS1338State *s) { DS1338Class *k =3D DS1338_GET_CLASS(s); =20 - /* - * The register pointer wraps around after the last register; wraparou= nd - * causes the current time/date to be retransferred into the secondary - * registers. - */ s->ptr =3D (s->ptr + 1) % k->num_regs; - if (!s->ptr) { - ds1338_capture_current_time(s); - } } =20 static int ds1338_event(I2CSlave *i2c, enum i2c_event event) @@ -201,6 +195,10 @@ static uint8_t ds1338_recv(I2CSlave *i2c) trace_ds1338_recv(s->ptr, res); =20 ds1338_inc_regptr(s); + if (!s->ptr) { + /* Read-only: a wrapping write must keep the bytes it just sent. */ + ds1338_capture_current_time(s); + } return res; } =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060234; cv=none; d=zohomail.com; s=zohoarc; b=eJUv/clCqGonmZdgV3lpPSd/p/yQbyQxtSqYxFIhzdNGwED8S1zmMPZF6fM/spiahV1en+OBOOwKaWaVJxHjo01Z6waMgXdG81WTsFmSRXVw/esGZMdRq615KZY67yll31h4ImFpI+uWt2E340dA6D1eBKW/7iHGn0vR9Mw70sE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060234; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=9jZpvK/2JIYvTgChmDwtU9W+dxG3f61FuvNfLFka24M=; b=lJ8vym/qBLINOd8FvBoF+7fA1OV1xBDaSSmGWEb6A4nfMVInO9FOeOr5unLSZTOiQQfnbXTZeh26x5YbBHZTfjIHD15dRZ4mB5Nnr33LKmpu/j5hp37nOXxhE7mEi7KlKmKTJ6HAp55mCsb5Hl23C1D3yqyeyA6I7vUdMrabiPo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17920602342824.1287531792442; Thu, 15 Oct 2026 03:30:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIg2-0003LU-O4; Thu, 15 Oct 2026 06:27:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIet-0001oN-QQ for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:59 -0400 Received: from mail-wm1-f48.google.com ([209.85.128.48]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIep-0003oo-Tb for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:25:59 -0400 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-49fbb2acc90so43210165e9.2 for ; Thu, 15 Oct 2026 03:25:53 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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The model instead wiped the registers on every reset and resynchronised the clock with the host. Add a property selecting between the two. It defaults off, leaving every board as it was. Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index c5fc74e6ca..21deb94689 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -22,6 +22,7 @@ #include "qemu/osdep.h" #include "hw/i2c/i2c.h" #include "hw/rtc/ds1338.h" +#include "hw/core/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/bcd.h" #include "qom/object.h" @@ -56,7 +57,8 @@ struct DS1338State { uint8_t nvram[NVRAM_SIZE]; int32_t ptr; bool addr_byte; - bool osc_stopped; /* oscillator halted: time is frozen */ + bool osc_stopped; /* oscillator halted: time is frozen */ + bool persist_on_reset; /* keep the registers across a reset */ }; =20 struct DS1338Class { @@ -263,9 +265,8 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) return 0; } =20 -static void ds1338_reset_hold(Object *obj, ResetType type) +static void ds1338_power_on(DS1338State *s) { - DS1338State *s =3D DS1338(obj); DS1338Class *k =3D DS1338_GET_CLASS(s); =20 /* The clock is running and synchronized with the host */ @@ -273,11 +274,29 @@ static void ds1338_reset_hold(Object *obj, ResetType = type) s->wday_offset =3D 0; memset(s->nvram, 0, NVRAM_SIZE); s->nvram[k->ctrl_addr] =3D k->ctrl_reset; + s->osc_stopped =3D false; +} + +static void ds1338_realize(DeviceState *dev, Error **errp) +{ + ds1338_power_on(DS1338(dev)); +} + +static void ds1338_reset_hold(Object *obj, ResetType type) +{ + DS1338State *s =3D DS1338(obj); + + if (!s->persist_on_reset) { + ds1338_power_on(s); + } s->ptr =3D 0; s->addr_byte =3D false; - s->osc_stopped =3D false; } =20 +static const Property ds1338_properties[] =3D { + DEFINE_PROP_BOOL("persist-on-reset", DS1338State, persist_on_reset, fa= lse), +}; + static void ds1338_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -289,6 +308,8 @@ static void ds1338_class_init(ObjectClass *klass, const= void *data) k->recv =3D ds1338_recv; k->send =3D ds1338_send; rc->phases.hold =3D ds1338_reset_hold; + dc->realize =3D ds1338_realize; + device_class_set_props(dc, ds1338_properties); dc->desc =3D "DS1338 I2C RTC with 56-byte NV RAM"; dc->vmsd =3D &vmstate_ds1338; =20 --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060401; cv=none; d=zohomail.com; s=zohoarc; b=fjIGhtaxup/7zCIoTTa3gvCTH46rxqieyZZ+76O55wDk8ZxVOotryG9dTQRQV7UlzaQStIhxTrJQWOMQqXTTA4X50Gmkd4X35Gxls1GHkVpSD3l16lV3rv230/39bhIbAxU629JCZKc7bzX1Z68DlKQPNWeMzmic+iMjLxeIDwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060401; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=xmNroMpGWl2lemJA5PX/kG1o2rPRZcL22w1qYRUbH5U=; b=ddOHzYvtS/vHs/nA4NsXuRYIuoHraHAKTWXjEo/bJVNyawFXRzEx+Hjmr8FQ8q08KagFpD1+8Da8t0ERTovJ6Sak+ATy9uYREvVrrivLh8Ia/KAMohihMUiMierzfXuwjbtE/LaKxw42Nao8hwIuGDCyZxVkDSgOZ9gWFuDjqKA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060401468286.8580444625079; Thu, 15 Oct 2026 03:33:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIga-0004hF-TB; Thu, 15 Oct 2026 06:27:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIex-0001yq-RI for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:04 -0400 Received: from mail-wm1-f47.google.com ([209.85.128.47]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIeu-0003qA-GX for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:03 -0400 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4a19cba5c14so46017875e9.3 for ; Thu, 15 Oct 2026 03:26:00 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Pin the values it holds for this part, so a later change cannot alter them unnoticed. Signed-off-by: Emmanuel Blot --- tests/qtest/ds1338-test.c | 67 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/tests/qtest/ds1338-test.c b/tests/qtest/ds1338-test.c index b8d0e65ec4..6066a34846 100644 --- a/tests/qtest/ds1338-test.c +++ b/tests/qtest/ds1338-test.c @@ -24,6 +24,15 @@ =20 #define DS1338_ADDR 0x68 =20 +/* DS1338 register map */ +#define DS1338_SECONDS 0x00 +#define DS1338_CONTROL 0x07 +#define DS1338_NVRAM 0x08 +#define DS1338_NUM_REGS 0x40 + +#define DS1338_CTRL_OSF 0x20 + +/* The clock and calendar come up on the host time. */ static void send_and_receive(void *obj, void *data, QGuestAllocator *alloc) { QI2CDevice *i2cdev =3D (QI2CDevice *)obj; @@ -32,7 +41,7 @@ static void send_and_receive(void *obj, void *data, QGues= tAllocator *alloc) time_t now =3D time(NULL); struct tm *tm_ptr =3D gmtime(&now); =20 - i2c_read_block(i2cdev, 0, resp, sizeof(resp)); + i2c_read_block(i2cdev, DS1338_SECONDS, resp, sizeof(resp)); =20 /* check retrieved time against local time */ g_assert_cmpuint(from_bcd(resp[4]), =3D=3D , tm_ptr->tm_mday); @@ -40,6 +49,56 @@ static void send_and_receive(void *obj, void *data, QGue= stAllocator *alloc) g_assert_cmpuint(2000 + from_bcd(resp[6]), =3D=3D , 1900 + tm_ptr->tm_= year); } =20 +/* Writable control bits round-trip; the reserved ones read back zero. */ +static void test_control_register(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1338_CONTROL, 0x93); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL), =3D=3D, 0x93); + + i2c_set8(i2cdev, DS1338_CONTROL, 0x4c); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL), =3D=3D, 0x00); +} + +/* The oscillator-stop flag can only be cleared by a write, never set. */ +static void test_osf_write_protect(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, + =3D=3D, DS1338_CTRL_OSF); + i2c_set8(i2cdev, DS1338_CONTROL, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, = =3D=3D, 0); + i2c_set8(i2cdev, DS1338_CONTROL, DS1338_CTRL_OSF); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, = =3D=3D, 0); +} + +/* The user RAM returns what the guest wrote to it. */ +static void test_nvram(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, 0x08, 0xaa); + i2c_set8(i2cdev, 0x20, 0x55); + i2c_set8(i2cdev, 0x3f, 0xc3); + + g_assert_cmphex(i2c_get8(i2cdev, 0x08), =3D=3D, 0xaa); + g_assert_cmphex(i2c_get8(i2cdev, 0x20), =3D=3D, 0x55); + g_assert_cmphex(i2c_get8(i2cdev, 0x3f), =3D=3D, 0xc3); +} + +/* The register pointer wraps at the end of the map. */ +static void test_address_wrap(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1338_NVRAM, 0x5a); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_NVRAM + DS1338_NUM_REGS), =3D= =3D, 0x5a); +} + static void ds1338_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -49,6 +108,12 @@ static void ds1338_register_nodes(void) =20 qos_node_create_driver("ds1338", i2c_device_create); qos_node_consumes("ds1338", "i2c-bus", &opts); + qos_add_test("tx-rx", "ds1338", send_and_receive, NULL); + qos_add_test("control-register", "ds1338", test_control_register, NULL= ); + qos_add_test("osf-write-protect", "ds1338", test_osf_write_protect, NU= LL); + qos_add_test("nvram", "ds1338", test_nvram, NULL); + qos_add_test("address-wrap", "ds1338", test_address_wrap, NULL); } + libqos_init(ds1338_register_nodes); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060231; 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1338-test.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tests/qtest/ds1338-test.c b/tests/qtest/ds1338-test.c index 6066a34846..fad0ca53d4 100644 --- a/tests/qtest/ds1338-test.c +++ b/tests/qtest/ds1338-test.c @@ -31,6 +31,7 @@ #define DS1338_NUM_REGS 0x40 =20 #define DS1338_CTRL_OSF 0x20 +#define DS1338_CTRL_POR 0xb3 =20 /* The clock and calendar come up on the host time. */ static void send_and_receive(void *obj, void *data, QGuestAllocator *alloc) @@ -49,6 +50,14 @@ static void send_and_receive(void *obj, void *data, QGue= stAllocator *alloc) g_assert_cmpuint(2000 + from_bcd(resp[6]), =3D=3D , 1900 + tm_ptr->tm_= year); } =20 +/* The control register comes up in its documented power-on state. */ +static void test_reset_defaults(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL), =3D=3D, DS1338_CTRL_= POR); +} + /* Writable control bits round-trip; the reserved ones read back zero. */ static void test_control_register(void *obj, void *data, QGuestAllocator *alloc) @@ -110,6 +119,7 @@ static void ds1338_register_nodes(void) qos_node_consumes("ds1338", "i2c-bus", &opts); =20 qos_add_test("tx-rx", "ds1338", send_and_receive, NULL); + qos_add_test("reset-defaults", "ds1338", test_reset_defaults, NULL); qos_add_test("control-register", "ds1338", test_control_register, NULL= ); qos_add_test("osf-write-protect", "ds1338", test_osf_write_protect, NU= LL); qos_add_test("nvram", "ds1338", test_nvram, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060369; cv=none; d=zohomail.com; s=zohoarc; b=OpReNbEyGy+3lZBrMVfWDRzr97KlsFdINYK0lWK4+WXMr+WjULApJFT46MacS6JgQ2X7SK43FjDoELXoi2pfLP3DzWdnLEtMWsnwv3j5VOc91Vy5GwQoWeDgVfuJs5lbO8paQfxHdEEwJKs76haQAaCPV6LY/eDlZQVX5bIYeyg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060369; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=QSX7oFL3j7413Q4nQT+SGQuVL91uJZdU8V0ijp2OEps=; b=aTOdKG8atwn9iPbT2dgYg+Owk/8obpxv0RyTwzuOQW3aSHAQ/Nah2Sg1EjzxXft8KOPWdCaZut6xIUOUvdqlKqG7hI+oD/zDnLE9T1DZP0YftH8Z9xhw/iJebbPxIoR8nTOLddnHAZuQT0P+KuEEV2ACROx0nK62MBko2LVJcRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060369223613.1688599435304; Thu, 15 Oct 2026 03:32:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIgV-0004ao-RX; Thu, 15 Oct 2026 06:27:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIfE-0002PQ-TR for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:22 -0400 Received: from mail-wm1-f50.google.com ([209.85.128.50]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIfB-0003tY-8M for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:19 -0400 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4a01933b584so43899545e9.0 for ; Thu, 15 Oct 2026 03:26:16 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1338-test.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/tests/qtest/ds1338-test.c b/tests/qtest/ds1338-test.c index fad0ca53d4..1b73dca98d 100644 --- a/tests/qtest/ds1338-test.c +++ b/tests/qtest/ds1338-test.c @@ -32,6 +32,7 @@ =20 #define DS1338_CTRL_OSF 0x20 #define DS1338_CTRL_POR 0xb3 +#define DS1338_SEC_CH 0x80 =20 /* The clock and calendar come up on the host time. */ static void send_and_receive(void *obj, void *data, QGuestAllocator *alloc) @@ -85,6 +86,42 @@ static void test_osf_write_protect(void *obj, void *data, g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, = =3D=3D, 0); } =20 +/* Halting the clock freezes the counters; clearing the halt resumes them.= */ +static void test_clock_halt(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + uint8_t frozen[7], again[7]; + unsigned idx; + + /* Clear OSF first, so that halting the clock is what sets it again. */ + i2c_set8(i2cdev, DS1338_CONTROL, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, = =3D=3D, 0); + + i2c_set8(i2cdev, DS1338_SECONDS, DS1338_SEC_CH | 0x30); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_SECONDS), =3D=3D, + DS1338_SEC_CH | 0x30); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, + =3D=3D, DS1338_CTRL_OSF); + + i2c_read_block(i2cdev, DS1338_SECONDS, frozen, sizeof(frozen)); + g_usleep(1200 * 1000); + i2c_read_block(i2cdev, DS1338_SECONDS, again, sizeof(again)); + g_assert_cmpmem(frozen, sizeof(frozen), again, sizeof(again)); + + i2c_set8(i2cdev, DS1338_SECONDS, 0x30); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_SECONDS) & DS1338_SEC_CH, =3D= =3D, 0); + for (idx =3D 0; idx < 50; idx++) { + if (i2c_get8(i2cdev, DS1338_SECONDS) !=3D 0x30) { + break; + } + g_usleep(100 * 1000); + } + g_assert_cmpuint(from_bcd(i2c_get8(i2cdev, DS1338_SECONDS)), >, 30); + + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL) & DS1338_CTRL_OSF, + =3D=3D, DS1338_CTRL_OSF); +} + /* The user RAM returns what the guest wrote to it. */ static void test_nvram(void *obj, void *data, QGuestAllocator *alloc) { @@ -122,6 +159,7 @@ static void ds1338_register_nodes(void) qos_add_test("reset-defaults", "ds1338", test_reset_defaults, NULL); qos_add_test("control-register", "ds1338", test_control_register, NULL= ); qos_add_test("osf-write-protect", "ds1338", test_osf_write_protect, NU= LL); + qos_add_test("clock-halt", "ds1338", test_clock_halt, NULL); qos_add_test("nvram", "ds1338", test_nvram, NULL); qos_add_test("address-wrap", "ds1338", test_address_wrap, NULL); } --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060264; cv=none; d=zohomail.com; s=zohoarc; b=mG0UHFIUWNHqubcn/AbC+th3SqfhoELMFfj+fC5/EwSXYui1plCTog5lTaYpRMaNcACeL7EEuT7+BfvuPs3dqPfwpK0rgfLNygub4EzjVzuyyHmkejy8N5fUO2a8SxEUwr7rTH1DexJedfgZZT6NQQ90Kl2Rx5li/0IosuWdewE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1338-test.c | 54 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/tests/qtest/ds1338-test.c b/tests/qtest/ds1338-test.c index 1b73dca98d..1b9c02d931 100644 --- a/tests/qtest/ds1338-test.c +++ b/tests/qtest/ds1338-test.c @@ -20,12 +20,15 @@ #include "qemu/osdep.h" #include "qemu/bcd.h" #include "libqtest.h" +#include "libqtest-single.h" #include "libqos/i2c.h" +#include "qobject/qdict.h" =20 #define DS1338_ADDR 0x68 =20 /* DS1338 register map */ #define DS1338_SECONDS 0x00 +#define DS1338_YEAR 0x06 #define DS1338_CONTROL 0x07 #define DS1338_NVRAM 0x08 #define DS1338_NUM_REGS 0x40 @@ -136,6 +139,50 @@ static void test_nvram(void *obj, void *data, QGuestAl= locator *alloc) g_assert_cmphex(i2c_get8(i2cdev, 0x3f), =3D=3D, 0xc3); } =20 +/* A reset restores the power-on state, unless persist-on-reset is set. */ +static void check_reset(QI2CDevice *i2cdev, bool persists) +{ + uint8_t year =3D i2c_get8(i2cdev, DS1338_YEAR); + /* A year the clock is not already showing, so the check discriminates= . */ + uint8_t marker =3D year =3D=3D 0x42 ? 0x77 : 0x42; + QDict *rsp; + + i2c_set8(i2cdev, DS1338_NVRAM, 0xa5); + i2c_set8(i2cdev, DS1338_CONTROL, 0x00); + i2c_set8(i2cdev, DS1338_YEAR, marker); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_NVRAM), =3D=3D, 0xa5); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_YEAR), =3D=3D, marker); + + rsp =3D qmp("{ 'execute': 'system_reset' }"); + g_assert(qdict_haskey(rsp, "return")); + qobject_unref(rsp); + qmp_eventwait("RESET"); + + if (persists) { + g_assert_cmphex(i2c_get8(i2cdev, DS1338_NVRAM), =3D=3D, 0xa5); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_YEAR), =3D=3D, marker); + } else { + g_assert_cmphex(i2c_get8(i2cdev, DS1338_NVRAM), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1338_CONTROL), =3D=3D, DS1338_C= TRL_POR); + /* Back on host time, which is where the year came from. */ + g_assert_cmphex(i2c_get8(i2cdev, DS1338_YEAR), =3D=3D, year); + } +} + +/* Without persist-on-reset, a reset takes the part back to power-on. */ +static void test_reset_clears(void *obj, void *data, QGuestAllocator *allo= c) +{ + check_reset((QI2CDevice *)obj, false); +} + +/* With persist-on-reset, the registers and the clock survive a reset. */ +static void test_reset_persists(void *obj, void *data, QGuestAllocator *al= loc) +{ + check_reset((QI2CDevice *)obj, true); +} + /* The register pointer wraps at the end of the map. */ static void test_address_wrap(void *obj, void *data, QGuestAllocator *allo= c) { @@ -162,6 +209,13 @@ static void ds1338_register_nodes(void) qos_add_test("clock-halt", "ds1338", test_clock_halt, NULL); qos_add_test("nvram", "ds1338", test_nvram, NULL); qos_add_test("address-wrap", "ds1338", test_address_wrap, NULL); + qos_add_test("reset-clears", "ds1338", test_reset_clears, NULL); + + opts.extra_device_opts =3D "address=3D0x68,persist-on-reset=3Don"; + qos_node_create_driver_named("ds1338-persist", "ds1338", i2c_device_cr= eate); + qos_node_consumes("ds1338-persist", "i2c-bus", &opts); + + qos_add_test("reset-persists", "ds1338-persist", test_reset_persists, = NULL); } =20 libqos_init(ds1338_register_nodes); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060082; cv=none; d=zohomail.com; s=zohoarc; b=DXc0TrkowhVcl9VNJxInZgnarcujpyQd0l2f5MQ/jbkjUcbSvq/rkjxrCkK09pdk1+/HkA64Q12AVzfk+S5v8VwcuddvYt1WVijAUvgpzkKeJj8+KwLHW4ddhpriQDKFz+0fYC/P9ecb3K2i4ri/tfgth1yHKobYmpfSeagXMLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060082; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=oYoBAtb0sGasvrkB8IWuXlvz+SK9VWJjTLvw46YHTLI=; b=E3lvKT+lAv/jOoCqSXQjDXz8pN4HhTiEPMLhaxJF9jncyjbiqeOW6J/x2aNMb61afaYAwFmMMyUUXHyw1n/WH5uzsCUrkZMmnaTA+SQlBy6cH7vfXyHb//SlNjw2XC8rpKYYAWwcJ/P/yoSSMDxZ2H70pmdLHwZ0XWFBJayyhMA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060082749717.3378252485154; Thu, 15 Oct 2026 03:28:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIgk-0005pv-IZ; Thu, 15 Oct 2026 06:27:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIfQ-0002hB-IX for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:34 -0400 Received: from mail-wm1-f47.google.com ([209.85.128.47]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIfN-0003wB-Uj for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:32 -0400 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4a0213948d3so31236565e9.2 for ; Thu, 15 Oct 2026 03:26:28 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1338-test.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tests/qtest/ds1338-test.c b/tests/qtest/ds1338-test.c index 1b9c02d931..9e2e257307 100644 --- a/tests/qtest/ds1338-test.c +++ b/tests/qtest/ds1338-test.c @@ -125,6 +125,26 @@ static void test_clock_halt(void *obj, void *data, QGu= estAllocator *alloc) =3D=3D, DS1338_CTRL_OSF); } =20 +/* Reserved time-register bits read back zero even with the clock halted. = */ +static void test_stopped_reserved_bits(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + const uint8_t all_ones[7] =3D { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x= ff }; + uint8_t resp[7]; + + i2c_write_block(i2cdev, DS1338_SECONDS, all_ones, sizeof(all_ones)); + + i2c_read_block(i2cdev, DS1338_SECONDS, resp, sizeof(resp)); + g_assert_cmphex(resp[0], =3D=3D, 0xff); /* the halt bit is writable = here */ + g_assert_cmphex(resp[1], =3D=3D, 0x7f); + g_assert_cmphex(resp[2], =3D=3D, 0x7f); + g_assert_cmphex(resp[3], =3D=3D, 0x07); + g_assert_cmphex(resp[4], =3D=3D, 0x3f); + g_assert_cmphex(resp[5], =3D=3D, 0x1f); /* no century bit on this pa= rt */ + g_assert_cmphex(resp[6], =3D=3D, 0xff); +} + /* The user RAM returns what the guest wrote to it. */ static void test_nvram(void *obj, void *data, QGuestAllocator *alloc) { @@ -207,6 +227,8 @@ static void ds1338_register_nodes(void) qos_add_test("control-register", "ds1338", test_control_register, NULL= ); qos_add_test("osf-write-protect", "ds1338", test_osf_write_protect, NU= LL); qos_add_test("clock-halt", "ds1338", test_clock_halt, NULL); + qos_add_test("stopped-reserved-bits", "ds1338", + test_stopped_reserved_bits, NULL); qos_add_test("nvram", "ds1338", test_nvram, NULL); qos_add_test("address-wrap", "ds1338", test_address_wrap, NULL); qos_add_test("reset-clears", "ds1338", test_reset_clears, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060097; cv=none; d=zohomail.com; s=zohoarc; b=mQ7MyqTkqFBQbjzLPDpZT/h9tW2mANdF5dA7iTtuLffdaQRRnCR43ezQfhcHslTIMhKNuwRv7/c6efI9fyI3yKP3O5ruX7X44Cj7vp+DNs3qXXiFdtkHbI1Z/NQLIsRa0a/cjLSNZ/v/K8i5oLIQKSkd9DAWrnoVBld6EoRoi0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060097; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=i/fJVu0RAkQNpYAD+bvYA8hnncGtRkMKhtyQVwo+Ypc=; b=XaZO81dcQBfAFOM6NJLJxc1YLJnIX6kOuXjk+O1mze1E03fFcEsKW10GgYg1RYfmbhGxYGqpvMHDaa16DDUo+XEt0DG70oqT1HZlxbsMSYD++CNNrOJG61CRtDaQPirI3fh40M6hUtQGuujFcUzn7DnoVfwY1y4Et7jPjcHJ56c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060097117218.01836625243698; Thu, 15 Oct 2026 03:28:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIgf-0005A5-Hm; Thu, 15 Oct 2026 06:27:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIfY-0002xz-Ee for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:41 -0400 Received: from mail-wm1-f53.google.com ([209.85.128.53]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIfU-0003x2-5L for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:26:40 -0400 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-49fbb2acc90so43216565e9.2 for ; Thu, 15 Oct 2026 03:26:35 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. [89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd66ab3dsm56231155e9.2.2026.10.15.03.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:26:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792059995; x=1792664795; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=i/fJVu0RAkQNpYAD+bvYA8hnncGtRkMKhtyQVwo+Ypc=; b=BvoVChPNui6ESD76yQOus4zThJCEVEOKSZ3A4QVec1EFcKdaAEsaBJ3YC9jySmRf18 By/ALpQeJuVsE8kzYnbqU4RI1YbAD30Z4O3Bvoxo6hSFaMKomPZS6vipXqTZYyIp48Tc hTVCfpfePunYJcHG+5ewCejhdd4/9A60ynXW+BSkaWJub1kMK1YvSBVdXcPfSJLHyh/J HM/G5KjfUXYLKeJMyU+1MoDmMipBSFrwfnDNLG4vxVUU+i1XXYGmgdtYvye11OcCTsu3 qqS881NZmD2OrHLTvMlBzWK3IfGvuSq3JgnVzX27SAH9K2If+C926VAwlHEp6gWQYrfa cV/w== X-Gm-Message-State: AFq9FYIiBPCjyvrlPsqj01rl+1ru4hBn8Vr/A2YHjlw0gHfie4sbDRTm VWEPe0cmqOeQ7iViGAQCg2LjXXliJaQeKkqg4PmWqEiLkyEbPPOssiAkG5xtDA== X-Gm-Gg: AYBFou1/FDDH4az8Sl2+s3tKelXyAqQzksfzeBJ/f6Dpw/RRM6X+RyuO/ZYqxiqbehl HXr2U2gbOgfOrZcNlNLo8XHdFl1l7JH2oJaAxzEebLiIL9QrpG7a2p7zvLmAWXKUjGV6ZZIEaBu TXT1gcJgrjTh+tnUNecUCYnqGTDU7wKXVW9pYIQT8W7mxU60CJz5eK8WD1U7N9sKQ8UTJ5nkwBv S/+MbOof/BB3IqHVZ2eBqgLOms+iV2r/DhUr2E2MBWbA6j1MAxADOeFQuklteGMGZGjMa+bnSp6 FJeGCBVYgbKhNSkGUfuSd1gY0IXg3gIvVBuhZ7B6FWIy7llOdANjqOlcYfXm7F9Zi6bnrRKxe5d ZWHVUcX6krRYtRFD3/Jw/TM6clPYpZC+pXXGw/NOuAz+N4dt+NDO/GmLUZsxU/e7OfFUqqPap5+ kUkFl7plpU+nOCy83sgHxHZ4/KVfnePkGdu3acrH9ocbmA3WSN1zG07Rlgi/1Lruqowc3wccfTp MB++hVWFBsnoAHD0KqIQyPd5G/KFatx7wcn1GlRssZyHA== X-Received: by 2002:a05:600c:c104:b0:4a1:96cd:2f67 with SMTP id 5b1f17b1804b1-4a196cd3240mr228623555e9.4.1792059994503; Thu, 15 Oct 2026 03:26:34 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:09 +0200 Subject: [PATCH v3 22/50] hw/rtc: ds1338: add DS1339 variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-22-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056475; l=13377; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=renBzme08gMcnv/4M4nG6ZLUFiR64cw9Bpyli/NRkr8=; b=D5930l1enGJbPLXPU0GsTBx41FfhxGxStlEibz0Tfmc837bwgzqW+JipyOE/earGHXb6DYZOC q9fIeiwcDlZDdMJnsxC4W8MIeJbthPzFZ3l7hrEB4kCaJLUa8g6Hj9p X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.53; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f53.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060099166158500 The Dallas/Maxim DS1339 register map is only partially compatible with the DS1338: it shares the clock/calendar time registers but differs elsewhere. It has no general-purpose NVRAM, moves the control register, and relocates the oscillator-stop flag. Add a 'ds1339' variant, modelling the EOSC oscillator stop, the OSF/A2F/A1F status register and the century bit. The alarm, square-wave and trickle-charger functions are not modelled. A migrated register pointer is now range-checked; it used to index the register array unvalidated. Signed-off-by: Emmanuel Blot --- hw/rtc/ds1338.c | 180 ++++++++++++++++++++++++++++++++++++++++++++= ---- include/hw/rtc/ds1338.h | 3 +- 2 files changed, 168 insertions(+), 15 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index 21deb94689..63a049292e 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -1,5 +1,5 @@ /* - * MAXIM DS1338 I2C RTC+NVRAM + * MAXIM DS1338/DS1339 I2C RTC+NVRAM * * Copyright (c) 2009 CodeSourcery. * Written by Paul Brook @@ -10,6 +10,13 @@ * GNU GPL, version 2 or (at your option) any later version. * * Limitations: + * - The DS1339 alarm registers, the alarm-enable control bits, the A1F/A2F + * status flags and the trickle charger are stored but never evaluated: = no + * alarm matching is performed, no flag is ever set by hardware and no + * charging happens. + * - The INT#/SQW output pin is not exposed: neither alarm interrupts nor + * square-wave generation are produced. No board wires this pin and the = guest + * does not use the RTC wakealarm here. * - Writing the seconds register does not reset the internal countdown ch= ain, * so the sub-second phase of the clock is not modelled. * - The user registers are refreshed on a START and on a read that wraps = the @@ -47,6 +54,23 @@ /* POR: OUT, OSF, SQWE and both rate-select bits come up set. */ #define DS1338_CTRL_RESET 0xb3 =20 +/* Sentinel register address meaning "this variant has no such register". = */ +#define DS1338_NO_REG 0xff + +/* DS1339 register map: 0x00..0x10 only, no general-purpose NVRAM */ +#define DS1339_NUM_REGS 0x11 /* 0x00..0x10, then wraps */ +#define DS1339_CONTROL 0x0e +#define DS1339_CTRL_MASK 0xbf /* bit 6 is reserved, reads back z= ero */ +#define DS1339_CTRL_EOSC 0x80 /* EOSC: 1 stops the oscillator */ +#define DS1339_CTRL_RESET 0x18 /* POR: RS2=3DRS1=3D1 (32 kHz), re= st zero */ +#define DS1339_MONTH_CENTURY 0x80 /* Century is bit 7 of the month r= eg */ +#define DS1339_STATUS 0x0f +#define DS1339_STATUS_OSF 0x80 /* OSF is bit 7 of the status reg = */ +/* Status bits that exist (OSF | A2F | A1F); bits 6..2 are reserved, read = 0. */ +#define DS1339_STATUS_MASK 0x83 +/* All three status flags are hardware-set and clear-only (write 0). */ +#define DS1339_STATUS_W0 0x83 + OBJECT_DECLARE_TYPE(DS1338State, DS1338Class, DS1338) =20 struct DS1338State { @@ -58,6 +82,7 @@ struct DS1338State { int32_t ptr; bool addr_byte; bool osc_stopped; /* oscillator halted: time is frozen */ + uint8_t prev_century; /* century index (tm_year/100) at last capture = */ bool persist_on_reset; /* keep the registers across a reset */ }; =20 @@ -69,24 +94,70 @@ struct DS1338Class { uint8_t ctrl_mask; /* writable/read-back bits of the control reg = */ uint8_t osf_addr; /* register holding the OSF flag */ uint8_t osf_mask; /* OSF bit within osf_addr */ + uint8_t status_addr; /* status register address */ + uint8_t status_mask; /* bits that exist; reserved bits read 0 */ + uint8_t status_w0_mask; /* flags that can only be cleared */ uint8_t ctrl_reset; /* control-register power-on value */ + uint8_t status_reset; /* status-register power-on value */ + uint8_t eosc_mask; /* oscillator-disable bit in the control reg */ + uint8_t century_mask; /* Century bit in the month register */ uint8_t ch_mask; /* Clock-halt bit in the seconds reg */ }; =20 +static int ds1338_post_load(void *opaque, int version_id) +{ + DS1338State *s =3D opaque; + DS1338Class *k =3D DS1338_GET_CLASS(s); + + /* Both accessors index nvram[] with ptr before incrementing it. */ + if (s->ptr < 0 || s->ptr >=3D k->num_regs) { + return -EINVAL; + } + + /* + * prev_century did not exist before version 3, so an older incoming s= tream + * leaves it zero. + */ + if (version_id < 3) { + struct tm now; + + qemu_get_timedate(&now, s->offset); + s->prev_century =3D now.tm_year / 100; + } + return 0; +} + +static const VMStateField vmstate_ds1338_fields[] =3D { + VMSTATE_I2C_SLAVE(parent_obj, DS1338State), + VMSTATE_INT64(offset, DS1338State), + VMSTATE_UINT8_V(wday_offset, DS1338State, 2), + VMSTATE_UINT8_ARRAY(nvram, DS1338State, NVRAM_SIZE), + VMSTATE_INT32(ptr, DS1338State), + VMSTATE_BOOL(addr_byte, DS1338State), + VMSTATE_BOOL_V(osc_stopped, DS1338State, 3), + VMSTATE_UINT8_V(prev_century, DS1338State, 3), + VMSTATE_END_OF_LIST() +}; + static const VMStateDescription vmstate_ds1338 =3D { .name =3D "ds1338", .version_id =3D 3, .minimum_version_id =3D 1, - .fields =3D (const VMStateField[]) { - VMSTATE_I2C_SLAVE(parent_obj, DS1338State), - VMSTATE_INT64(offset, DS1338State), - VMSTATE_UINT8_V(wday_offset, DS1338State, 2), - VMSTATE_UINT8_ARRAY(nvram, DS1338State, NVRAM_SIZE), - VMSTATE_INT32(ptr, DS1338State), - VMSTATE_BOOL(addr_byte, DS1338State), - VMSTATE_BOOL_V(osc_stopped, DS1338State, 3), - VMSTATE_END_OF_LIST() - } + .post_load =3D ds1338_post_load, + .fields =3D vmstate_ds1338_fields, +}; + +/* + * The DS1339 reuses the DS1338 migration field list, so it migrates the f= ull + * NVRAM_SIZE-byte nvram[] array even though it only implements registers + * 0x00..0x10. + */ +static const VMStateDescription vmstate_ds1339 =3D { + .name =3D "ds1339", + .version_id =3D 3, + .minimum_version_id =3D 3, + .post_load =3D ds1338_post_load, + .fields =3D vmstate_ds1338_fields, }; =20 /* Reconstruct a struct tm from the BCD time registers in nvram. */ @@ -109,7 +180,7 @@ static void ds1338_time_from_regs(DS1338State *s, struc= t tm *now) } now->tm_mday =3D from_bcd(s->nvram[4] & 0x3f); now->tm_mon =3D from_bcd(s->nvram[5] & 0x1f) - 1; - now->tm_year =3D from_bcd(s->nvram[6]) + 100; + now->tm_year =3D s->prev_century * 100 + from_bcd(s->nvram[6]); } =20 static void ds1338_resync_from_regs(DS1338State *s) @@ -129,13 +200,22 @@ static void ds1338_capture_current_time(DS1338State *= s) /* Capture the current time into the secondary registers * which will be actually read by the data transfer operation. */ + DS1338Class *k =3D DS1338_GET_CLASS(s); struct tm now; + uint8_t century; =20 if (s->osc_stopped) { return; } =20 qemu_get_timedate(&now, s->offset); + + century =3D now.tm_year / 100; + if (k->century_mask && ((century ^ s->prev_century) & 1)) { + s->nvram[5] ^=3D k->century_mask; + } + s->prev_century =3D century; + s->nvram[0] =3D to_bcd(now.tm_sec); s->nvram[1] =3D to_bcd(now.tm_min); if (s->nvram[2] & HOURS_12) { @@ -153,7 +233,7 @@ static void ds1338_capture_current_time(DS1338State *s) } s->nvram[3] =3D (now.tm_wday + s->wday_offset) % 7 + 1; s->nvram[4] =3D to_bcd(now.tm_mday); - s->nvram[5] =3D to_bcd(now.tm_mon + 1); + s->nvram[5] =3D to_bcd(now.tm_mon + 1) | (s->nvram[5] & k->century_mas= k); s->nvram[6] =3D to_bcd(now.tm_year % 100); } =20 @@ -204,6 +284,16 @@ static uint8_t ds1338_recv(I2CSlave *i2c) return res; } =20 +/* OSF is raised by hardware whenever the oscillator stops. */ +static void ds1338_raise_osf(DS1338State *s) +{ + DS1338Class *k =3D DS1338_GET_CLASS(s); + + if (k->osf_addr !=3D DS1338_NO_REG) { + s->nvram[k->osf_addr] |=3D k->osf_mask; + } +} + static int ds1338_send(I2CSlave *i2c, uint8_t data) { DS1338State *s =3D DS1338(i2c); @@ -234,12 +324,14 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) if (k->ch_mask) { halt =3D data & k->ch_mask; } + } else if (s->ptr =3D=3D 5) { + mask |=3D k->century_mask; } =20 if (halt && !s->osc_stopped) { /* CH set: freeze the counters before the register is stored. = */ ds1338_capture_current_time(s); - s->nvram[k->osf_addr] |=3D k->osf_mask; + ds1338_raise_osf(s); } s->nvram[s->ptr] =3D data & mask; s->osc_stopped =3D halt; @@ -250,6 +342,19 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) if (s->ptr =3D=3D k->ctrl_addr) { /* Control register: reserved bits read back as zero. */ data &=3D k->ctrl_mask; + if (k->eosc_mask) { + bool now_stop =3D data & k->eosc_mask; + bool was_stop =3D s->nvram[k->ctrl_addr] & k->eosc_mask; + if (now_stop && !was_stop) { + ds1338_capture_current_time(s); + s->osc_stopped =3D true; + ds1338_raise_osf(s); + } else if (!now_stop && was_stop) { + /* EOSC cleared: resume counting from the frozen time.= */ + ds1338_resync_from_regs(s); + s->osc_stopped =3D false; + } + } } if (s->ptr =3D=3D k->osf_addr) { /* @@ -259,6 +364,13 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) data =3D (data & ~k->osf_mask) | (data & s->nvram[s->ptr] & k->osf_mask); } + if (s->ptr =3D=3D k->status_addr) { + /* Reserved bits read zero; flags are clear-only, OSF included= . */ + uint8_t cur =3D s->nvram[s->ptr]; + data &=3D k->status_mask; + data =3D (data & ~k->status_w0_mask) | + (data & cur & k->status_w0_mask); + } s->nvram[s->ptr] =3D data; } ds1338_inc_regptr(s); @@ -268,13 +380,19 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) static void ds1338_power_on(DS1338State *s) { DS1338Class *k =3D DS1338_GET_CLASS(s); + struct tm now; =20 /* The clock is running and synchronized with the host */ s->offset =3D 0; s->wday_offset =3D 0; memset(s->nvram, 0, NVRAM_SIZE); s->nvram[k->ctrl_addr] =3D k->ctrl_reset; + if (k->status_addr !=3D DS1338_NO_REG) { + s->nvram[k->status_addr] =3D k->status_reset; + } s->osc_stopped =3D false; + qemu_get_timedate(&now, 0); + s->prev_century =3D now.tm_year / 100; } =20 static void ds1338_realize(DeviceState *dev, Error **errp) @@ -318,10 +436,39 @@ static void ds1338_class_init(ObjectClass *klass, con= st void *data) dsc->ctrl_mask =3D DS1338_CTRL_MASK; dsc->osf_addr =3D DS1338_CONTROL; dsc->osf_mask =3D CTRL_OSF; + dsc->status_addr =3D DS1338_NO_REG; /* the DS1338 has no status regi= ster */ + dsc->status_mask =3D 0; + dsc->status_w0_mask =3D 0; dsc->ctrl_reset =3D DS1338_CTRL_RESET; + dsc->status_reset =3D 0; + dsc->eosc_mask =3D 0; + dsc->century_mask =3D 0; dsc->ch_mask =3D SECONDS_CH; } =20 +static void ds1339_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + DS1338Class *dsc =3D DS1338_CLASS(klass); + + dc->desc =3D "DS1339 I2C serial real-time clock"; + dc->vmsd =3D &vmstate_ds1339; + + dsc->num_regs =3D DS1339_NUM_REGS; + dsc->ctrl_addr =3D DS1339_CONTROL; + dsc->ctrl_mask =3D DS1339_CTRL_MASK; + dsc->osf_addr =3D DS1339_STATUS; /* OSF lives in the status regist= er */ + dsc->osf_mask =3D DS1339_STATUS_OSF; + dsc->status_addr =3D DS1339_STATUS; + dsc->status_mask =3D DS1339_STATUS_MASK; + dsc->status_w0_mask =3D DS1339_STATUS_W0; + dsc->ctrl_reset =3D DS1339_CTRL_RESET; + dsc->status_reset =3D DS1339_STATUS_OSF; /* OSF set at power-on */ + dsc->eosc_mask =3D DS1339_CTRL_EOSC; + dsc->century_mask =3D DS1339_MONTH_CENTURY; + dsc->ch_mask =3D 0; /* bit 7 of the seconds register reads back zero= */ +} + static const TypeInfo ds1338_types[] =3D { { .name =3D TYPE_DS1338, @@ -330,6 +477,11 @@ static const TypeInfo ds1338_types[] =3D { .class_size =3D sizeof(DS1338Class), .class_init =3D ds1338_class_init, }, + { + .name =3D TYPE_DS1339, + .parent =3D TYPE_DS1338, + .class_init =3D ds1339_class_init, + }, }; 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Cover its register map, the write-protection of the oscillator-stop flag, and the wrap of the register pointer at the end of the map. Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 166 ++++++++++++++++++++++++++++++++++++++++++= ++++ tests/qtest/meson.build | 1 + 2 files changed, 167 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c new file mode 100644 index 0000000000..08fc16acda --- /dev/null +++ b/tests/qtest/ds1339-test.c @@ -0,0 +1,166 @@ +/* + * QTest testcase for the DS1339 RTC + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/bcd.h" +#include "libqos/i2c.h" + +#define DS1339_ADDR 0x68 + +/* DS1339 register map */ +#define DS1339_SECONDS 0x00 +#define DS1339_MONTH 0x05 +#define DS1339_YEAR 0x06 +#define DS1339_ALARM1 0x07 +#define DS1339_ALARM2 0x0b +#define DS1339_CONTROL 0x0e +#define DS1339_STATUS 0x0f +#define DS1339_TRICKLE 0x10 +#define DS1339_NUM_REGS 0x11 + +#define DS1339_STATUS_OSF 0x80 + +/* The clock and calendar come up on the host time. */ +static void test_time(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + uint8_t resp[7]; + time_t now =3D time(NULL); + struct tm *tm_ptr =3D gmtime(&now); + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, sizeof(resp)); + + g_assert_cmpuint(from_bcd(resp[4]), =3D=3D, tm_ptr->tm_mday); + g_assert_cmpuint(from_bcd(resp[5]), =3D=3D, 1 + tm_ptr->tm_mon); + g_assert_cmpuint(2000 + from_bcd(resp[6]), =3D=3D, 1900 + tm_ptr->tm_y= ear); +} + +/* Writable control bits round-trip; the reserved one reads back zero. */ +static void test_control_register(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1339_CONTROL, 0x1c); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL), =3D=3D, 0x1c); + + i2c_set8(i2cdev, DS1339_CONTROL, 0xff); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL), =3D=3D, 0xbf); + + i2c_set8(i2cdev, DS1339_CONTROL, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL), =3D=3D, 0x00); +} + +/* The oscillator-stop flag can only be cleared by a write, never set. */ +static void test_osf_write_protect(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, + =3D=3D, DS1339_STATUS_OSF); + i2c_set8(i2cdev, DS1339_STATUS, DS1339_STATUS_OSF); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, + =3D=3D, DS1339_STATUS_OSF); + + i2c_set8(i2cdev, DS1339_STATUS, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, = =3D=3D, 0); + i2c_set8(i2cdev, DS1339_STATUS, DS1339_STATUS_OSF); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, = =3D=3D, 0); +} + +/* The register pointer wraps at the end of the map. */ +static void test_address_wrap(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1339_CONTROL, 0x2a); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL + DS1339_NUM_REGS), + =3D=3D, 0x2a); +} + +/* A block transfer off the end of the map carries on from the start. */ +static void test_block_wrap(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + /* The alarm 2 block, then on into the time registers once it wraps. */ + const uint8_t out[11] =3D { + 0x0b, 0x0c, 0x0d, /* alarm 2 */ + 0x18, /* control */ + 0x00, /* status */ + 0xa5, /* trickle charger */ + 0x30, 0x20, 0x10, 0x05, 0x12, /* 10:20:30, day 5, the 12th */ + }; + uint8_t resp[11]; + + /* A month and year the wrapping write never reaches. */ + i2c_set8(i2cdev, DS1339_MONTH, 0x07); + i2c_set8(i2cdev, DS1339_YEAR, 0x31); + + i2c_write_block(i2cdev, DS1339_ALARM2, out, sizeof(out)); + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, 7); + g_assert_cmphex(resp[2], =3D=3D, 0x10); + g_assert_cmphex(resp[3], =3D=3D, 0x05); + g_assert_cmphex(resp[4], =3D=3D, 0x12); + g_assert_cmphex(resp[5] & 0x1f, =3D=3D, 0x07); + g_assert_cmphex(resp[6], =3D=3D, 0x31); + + i2c_read_block(i2cdev, DS1339_ALARM2, resp, sizeof(resp)); + g_assert_cmphex(resp[0], =3D=3D, 0x0b); + g_assert_cmphex(resp[1], =3D=3D, 0x0c); + g_assert_cmphex(resp[2], =3D=3D, 0x0d); + g_assert_cmphex(resp[3], =3D=3D, 0x18); + g_assert_cmphex(resp[4], =3D=3D, 0x00); + g_assert_cmphex(resp[5], =3D=3D, 0xa5); + g_assert_cmphex(resp[8], =3D=3D, 0x10); + g_assert_cmphex(resp[9], =3D=3D, 0x05); + g_assert_cmphex(resp[10], =3D=3D, 0x12); +} + +/* The alarm and trickle registers are stored but never evaluated. */ +static void test_alarm_registers(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + static const uint8_t regs[] =3D { + DS1339_ALARM1, 0x08, 0x09, 0x0a, /* alarm 1 */ + DS1339_ALARM2, 0x0c, 0x0d, /* alarm 2 */ + DS1339_TRICKLE, + }; + static const uint8_t vals[] =3D { 0xff, 0x00, 0x5a, 0xa5 }; + unsigned reg, val; + + for (reg =3D 0; reg < ARRAY_SIZE(regs); reg++) { + for (val =3D 0; val < ARRAY_SIZE(vals); val++) { + i2c_set8(i2cdev, regs[reg], vals[val]); + g_assert_cmphex(i2c_get8(i2cdev, regs[reg]), =3D=3D, vals[val]= ); + } + } +} + +static void ds1339_register_nodes(void) +{ + QOSGraphEdgeOptions opts =3D { + .extra_device_opts =3D "address=3D0x68" + }; + add_qi2c_address(&opts, &(QI2CAddress) { DS1339_ADDR }); + + qos_node_create_driver("ds1339", i2c_device_create); + qos_node_consumes("ds1339", "i2c-bus", &opts); + + qos_add_test("time", "ds1339", test_time, NULL); + qos_add_test("control-register", "ds1339", test_control_register, NULL= ); + qos_add_test("osf-write-protect", "ds1339", test_osf_write_protect, NU= LL); + qos_add_test("address-wrap", "ds1339", test_address_wrap, NULL); + qos_add_test("block-wrap", "ds1339", test_block_wrap, NULL); + qos_add_test("alarm-registers", "ds1339", test_alarm_registers, + NULL); +} + +libqos_init(ds1339_register_nodes); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e05d8a07b9..e23eb9bbca 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -326,6 +326,7 @@ qos_test_ss.add( 'adm1272-test.c', 'adm1266-test.c', 'ds1338-test.c', + 'ds1339-test.c', 'e1000-test.c', 'eepro100-test.c', 'es1370-test.c', --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 51 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index 08fc16acda..e9dcdc36da 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -74,6 +74,53 @@ static void test_osf_write_protect(void *obj, void *data, g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, = =3D=3D, 0); } =20 +/* The control and status registers come up in their power-on state. */ +static void test_reset_defaults(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL), =3D=3D, 0x18); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, + =3D=3D, DS1339_STATUS_OSF); +} + +/* Neither the reserved status bits nor the alarm flags are guest-writable= . */ +static void test_status_register(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1339_STATUS, 0x7c); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS), =3D=3D, 0x00); + + i2c_set8(i2cdev, DS1339_STATUS, 0x03); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS), =3D=3D, 0x00); + + i2c_set8(i2cdev, DS1339_STATUS, 0xff); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS), =3D=3D, 0x00); +} + +/* Reserved time-register bits read back zero even with the clock stopped.= */ +static void test_stopped_reserved_bits(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + const uint8_t all_ones[7] =3D { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x= ff }; + uint8_t resp[7]; + + i2c_set8(i2cdev, DS1339_CONTROL, 0x18 | 0x80); + i2c_write_block(i2cdev, DS1339_SECONDS, all_ones, sizeof(all_ones)); + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, sizeof(resp)); + g_assert_cmphex(resp[0], =3D=3D, 0x7f); + g_assert_cmphex(resp[1], =3D=3D, 0x7f); + g_assert_cmphex(resp[2], =3D=3D, 0x7f); + g_assert_cmphex(resp[3], =3D=3D, 0x07); + g_assert_cmphex(resp[4], =3D=3D, 0x3f); + g_assert_cmphex(resp[5], =3D=3D, 0x9f); + g_assert_cmphex(resp[6], =3D=3D, 0xff); +} + /* The register pointer wraps at the end of the map. */ static void test_address_wrap(void *obj, void *data, QGuestAllocator *allo= c) { @@ -155,8 +202,12 @@ static void ds1339_register_nodes(void) qos_node_consumes("ds1339", "i2c-bus", &opts); =20 qos_add_test("time", "ds1339", test_time, NULL); + qos_add_test("reset-defaults", "ds1339", test_reset_defaults, NULL); qos_add_test("control-register", "ds1339", test_control_register, NULL= ); + qos_add_test("status-register", "ds1339", test_status_register, NULL); qos_add_test("osf-write-protect", "ds1339", test_osf_write_protect, NU= LL); + qos_add_test("stopped-reserved-bits", "ds1339", + test_stopped_reserved_bits, NULL); qos_add_test("address-wrap", "ds1339", test_address_wrap, NULL); qos_add_test("block-wrap", "ds1339", test_block_wrap, NULL); qos_add_test("alarm-registers", "ds1339", test_alarm_registers, --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 50 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 50 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index e9dcdc36da..ac19ebd71d 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -121,6 +121,54 @@ static void test_stopped_reserved_bits(void *obj, void= *data, g_assert_cmphex(resp[6], =3D=3D, 0xff); } =20 +/* Setting EOSC stops the oscillator and sets OSF; OSF outlives the restar= t. */ +static void test_eosc(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1339_STATUS, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, = =3D=3D, 0); + + i2c_set8(i2cdev, DS1339_CONTROL, 0x18 | 0x80); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, + =3D=3D, DS1339_STATUS_OSF); + + i2c_set8(i2cdev, DS1339_CONTROL, 0x18); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, + =3D=3D, DS1339_STATUS_OSF); + i2c_set8(i2cdev, DS1339_STATUS, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, = =3D=3D, 0); +} + +/* A stopped clock resumes from the time it was programmed with. */ +static void test_eosc_restart(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + /* 10:20:30 on the 12th of July 2031, the day counter reading 2. */ + const uint8_t tod[7] =3D { 0x30, 0x20, 0x10, 0x02, 0x12, 0x07, 0x31 }; + uint8_t resp[7]; + unsigned idx; + + i2c_set8(i2cdev, DS1339_CONTROL, 0x18 | 0x80); + i2c_write_block(i2cdev, DS1339_SECONDS, tod, sizeof(tod)); + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, sizeof(resp)); + g_assert_cmpmem(resp, sizeof(resp), tod, sizeof(tod)); + + i2c_set8(i2cdev, DS1339_CONTROL, 0x18); + /* The seconds counter steps within a second of the restart. */ + for (idx =3D 0; idx < 15 && i2c_get8(i2cdev, DS1339_SECONDS) =3D=3D 0x= 30; idx++) { + g_usleep(100 * 1000); + } + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, sizeof(resp)); + g_assert_cmpuint(from_bcd(resp[0]), >, 30); + g_assert_cmphex(resp[2], =3D=3D, 0x10); + g_assert_cmphex(resp[4], =3D=3D, 0x12); + g_assert_cmphex(resp[5] & 0x1f, =3D=3D, 0x07); + g_assert_cmphex(resp[6], =3D=3D, 0x31); +} + /* The register pointer wraps at the end of the map. */ static void test_address_wrap(void *obj, void *data, QGuestAllocator *allo= c) { @@ -206,6 +254,8 @@ static void ds1339_register_nodes(void) qos_add_test("control-register", "ds1339", test_control_register, NULL= ); qos_add_test("status-register", "ds1339", test_status_register, NULL); qos_add_test("osf-write-protect", "ds1339", test_osf_write_protect, NU= LL); + qos_add_test("eosc", "ds1339", test_eosc, NULL); + qos_add_test("eosc-restart", "ds1339", test_eosc_restart, NULL); qos_add_test("stopped-reserved-bits", "ds1339", test_stopped_reserved_bits, NULL); qos_add_test("address-wrap", "ds1339", test_address_wrap, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1c1eb3907sm38605165e9.7.2026.10.15.03.27.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:27:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792060024; x=1792664824; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Zzjq066d1DK9BL6AffnijbYCb4eLXuskQFLQ8zYtsCk=; b=tNNOmF6I1xGFKlNcIoKyIqdb53qNL24ZiCD9+XnWHK12WWdITL8g0Zmu+gd+xcYKGh vANDjEvvWGOVi64QM2mW4/ca+W+VMjcxWu3p65yTc5VnlYOqjdw+Zlz1Xiv7ygGxBr6Q KI3c96paXskL0Z7i+97zRcNOpDwZAll4KhL0lpB+buiMZPZFQ+R+uFMfFBUtD8y0x0bO 1KQ8cKnNr8nGu1tnzR9W/i/4pV4028hdA563ALWJSFQbTyLlc2opPoufkaXfpRffvkAA tOByzjS14kKLM+8TBF/nq7Mq+z4KRbXe0qwjxHfXQbMQLzufHcBCKcoN75LHi+DdSbI0 sfuQ== X-Gm-Message-State: AFq9FYI3RM9fa9fKj0fzSevEPzjxuENFgHufPjwPA9mu8oDRffjyiuR/ JzGSlk3lKb3rFIMg44Qki4cA/qY+IzcLkglhUv3MEGzHzEYzgj7FPSp7ze3qWA== X-Gm-Gg: AYBFou3CIhXcb2Fh0AJJUSkEtPxtIy34QIcDEZmzEc40HLR+ydcu3FR7aD1+7aMEPhX nZnHgcgSs/8ddEtDGEtczHemNlCsfyGKtTKAqIA+7SL5LatkmQpLja4eFJ8s7+BZhnS+MePJIdQ LP3mPSLJP2BAxcdSXf852mqLrHOJjOt0AFpPziNnZwHp1rDY5MfdI5HJMwy5xTF8Ywv2uoIhTtC KIhZ025Z0GVigTSAH56nK74huFnk3hytMrVbYRzShGgNbudY2p8ml6CcYqgWlyRBb2fAskof2Ih 4ufisZNRmP+NUUiix34SAqzVLHkZFa1usbnn54VzfOUD1KIs0KgSrwz9CfMjxK+BhphJk38uwcP lbVRqg51LzhdUo+M2A/9Ry2r9WEBYMVTh0tzED3EfPP0g7uncgGyjJrlIBSlAg1NuwcwLu4DYPq LhmhMo2m+bguToWfph2kUahx039ZQL+ipXDAktXK2fBfAz39IIvrFq/iD6M9van23f/rlhx9hE1 dUEJziiAguwo7r/D4EaRoGu30nDkgSizF//SqRxiPd3/Q== X-Received: by 2002:a05:600c:154c:b0:49f:ce78:3562 with SMTP id 5b1f17b1804b1-4a18e4a9159mr394581205e9.19.1792060024134; Thu, 15 Oct 2026 03:27:04 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:13 +0200 Subject: [PATCH v3 26/50] tests/qtest: ds1339: cover the Century bit MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-26-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056476; l=3691; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=a51PVO883sS5BmzswPWqVtyHVJ/pN81H084v6xEIBwk=; b=DjlpsYHB2et3L4f5LHVoFOtXHc+eZ1C8rXyAtVcsY7BqfmEmXTTDq0vTZ1m56jqEA2azplSrn rDqZMvBqHqHC/8p6NpfoaOyyNjjvN7tBE7M3qTfJf1+RhPLhGwXJxc3 X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.42; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f42.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060416799158500 The Century bit had no coverage: neither its guest read/write behaviour, nor the rule that only an elapsed rollover toggles it. Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 60 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 60 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index ac19ebd71d..8c144579e6 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -169,6 +169,62 @@ static void test_eosc_restart(void *obj, void *data, Q= GuestAllocator *alloc) g_assert_cmphex(resp[6], =3D=3D, 0x31); } =20 +/* The Century bit is guest-writable and survives an oscillator restart. */ +static void test_century_bit(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1339_MONTH, 0x86); /* Century | June */ + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x80); + + i2c_set8(i2cdev, DS1339_CONTROL, 0x18 | 0x80); + i2c_set8(i2cdev, DS1339_CONTROL, 0x18); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x80); + + i2c_set8(i2cdev, DS1339_MONTH, 0x06); /* June, century clear */ + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x00); +} + +/* A guest write never toggles the Century bit. */ +static void test_century_write_no_toggle(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + i2c_set8(i2cdev, DS1339_MONTH, 0x86); + i2c_set8(i2cdev, DS1339_YEAR, 0x99); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x80); + i2c_set8(i2cdev, DS1339_YEAR, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x80); + + i2c_set8(i2cdev, DS1339_MONTH, 0x06); + i2c_set8(i2cdev, DS1339_YEAR, 0x99); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x00); + i2c_set8(i2cdev, DS1339_YEAR, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x00); +} + +/* A clock-driven year rollover from 99 to 00 toggles the Century bit. */ +static void test_century_rollover(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + const uint8_t tod[7] =3D { 0x59, 0x59, 0x23, 0x01, 0x31, 0x12, 0x99 }; + unsigned idx; + + i2c_write_block(i2cdev, DS1339_SECONDS, tod, sizeof(tod)); + + for (idx =3D 0; idx < 50; idx++) { + if (i2c_get8(i2cdev, DS1339_YEAR) =3D=3D 0x00) { + break; + } + g_usleep(100 * 1000); + } + + g_assert_cmphex(i2c_get8(i2cdev, DS1339_YEAR), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_MONTH) & 0x80, =3D=3D, 0x80); +} + /* The register pointer wraps at the end of the map. */ static void test_address_wrap(void *obj, void *data, QGuestAllocator *allo= c) { @@ -258,6 +314,10 @@ static void ds1339_register_nodes(void) qos_add_test("eosc-restart", "ds1339", test_eosc_restart, NULL); qos_add_test("stopped-reserved-bits", "ds1339", test_stopped_reserved_bits, NULL); + qos_add_test("century-bit", "ds1339", test_century_bit, NULL); + qos_add_test("century-write-no-toggle", "ds1339", + test_century_write_no_toggle, NULL); + qos_add_test("century-rollover", "ds1339", test_century_rollover, NULL= ); qos_add_test("address-wrap", "ds1339", test_address_wrap, NULL); qos_add_test("block-wrap", "ds1339", test_block_wrap, NULL); qos_add_test("alarm-registers", "ds1339", test_alarm_registers, --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060231; cv=none; d=zohomail.com; s=zohoarc; b=nqP7+dds6b01+rNDPU7Y3auw5anHXAXKs2TPP554fDbXRgZKgC4CxvjBjTNw3h5UzJj+xL1nXL3Z5YnKtJKhA+ddMwHybbl6Qx4eQyEOcHScvPLZq1RP3niHGQTWOnWIchMNsNksmVdTnjKpg8+IfbAL/VLCyRQnsQGPDc14hGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060231; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de77606fbsm10342203f8f.53.2026.10.15.03.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:27:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792060031; x=1792664831; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Adz/rIkVxKmnpzPklQqKGWWgHGHy0e2h5cr4SvKWE0I=; b=dG6l+fHy33qXFV/DQf6kWiy5JZ9k0KwOy99bldZBbL+wbydunwYj2o2wv5Qnk52kTH W4MoTEsqHRNibu3SZ6k7DNNtAEFQTQbxSiDXP8l1m5+ELqUQEzO6rMtjEJ4sJ5GYBStD rWVPyISLzFFIIjUaW2reeq1Sxs+L4k8Qzg3FYSJg2AnPbZ5fa18zvDKO1l29D+NtYprA 5gvRDNfZz4CE36WZZ6Sl+9mtosq2UEymRfyQFOSw/OXWACm0MUUrDIGD6sCexMgJEAd3 b47fpeMiz0PBndWfKUwGiMYf4iqctqs9/k4yyrJWsGNWoX7g6ioHEgmTzpl25chHNxV+ npNA== X-Gm-Message-State: AFq9FYI7NZqX9BBKAsNEtP+iFLAhDrki4kTlsGNbqlyM/jco3wJXJfzA XI6rR+jq+MfqaAmg8J66huVCLH9LPauztv49HAp3FhWwdsIUOpGscuL5YScsxQ== X-Gm-Gg: AYBFou2XlJ8FmdCNQw50cTX3GOFo/HM3K0dCbWpIhkkMigVN3xUm+kL0YMSE7I+SpbC A5KmBkA1AsXQaRVjx+yWtOZwVHKzmPxI11ydgyhf4IPnIApZHoV+khjLLkv7ahF3uQJjcOdVH9o NsLR/NRwgr43ntCb6yl/UnP64wLyNqpOMrsG9/pRXMgl45FHbB/KT2SXYhQjATzs5vYAFLF3OyH j1whIKC3+1uvNd7/IvNapHKJqOMAHoKArAlG7f3YhcrsTSf+YEHzh+4gWGWx4JnituyiVtad36u MnoUVeiWjhvyrdkD6XKGO9RjJCNPVXstVSzjEsyrUWUsPogIe/icazfaU55I9amADthY7bmNHkD +grSknbZYqUszoCU0IlkZch6Y5whEPuAoBpXXXh6sqw/d+uHI+krNPgP74fBuwJa30fnJ5SmOya oXuLKQ8GQrJgOX8MdePAU1Rh/jHVJmeXN+vIxGeTdVfsiD8bUEAH/xQz/Ot+vSKKLx4Bv5e2rU1 laqbr9WUuyxAKRUexOa2noxIsfmBGt2dJOjvW9PR+q58qohjmZAPod+ X-Received: by 2002:a05:6000:29c3:b0:48c:58d5:30fb with SMTP id ffacd0b85a97d-48dba7876bemr24188526f8f.5.1792060031108; Thu, 15 Oct 2026 03:27:11 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:14 +0200 Subject: [PATCH v3 27/50] tests/qtest: ds1339: cover the end-of-month rollover MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-27-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056476; l=3758; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=iOwmzyJ4hd6oW//GUNriTfBTlQKKZhGGR+JckreHq5Q=; b=uxSFlsTndJWAU+VPfl1yjgl8aVtXUmBtubp9+4Jp1uqFi1hFBfQRZpUH9kBOP8Xnwc2ij/lVJ cCNMQq/lYArBN1yCWGlW+Y29XlcdyLB/ttRNr8of89Ecp+8nDh71DoG X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.221.45; envelope-from=eblot.ml@gmail.com; helo=mail-wr1-f45.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060233817158500 The end-of-month rollover was untested, for any of the lengths the calendar gives a month. Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 60 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 60 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index 8c144579e6..7eec163049 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -14,6 +14,7 @@ =20 /* DS1339 register map */ #define DS1339_SECONDS 0x00 +#define DS1339_DATE 0x04 #define DS1339_MONTH 0x05 #define DS1339_YEAR 0x06 #define DS1339_ALARM1 0x07 @@ -169,6 +170,61 @@ static void test_eosc_restart(void *obj, void *data, Q= GuestAllocator *alloc) g_assert_cmphex(resp[6], =3D=3D, 0x31); } =20 +/* Program 23:59:59 on the last day of a month and run the clock past it. = */ +static void check_month_rollover(QI2CDevice *i2cdev, + uint8_t date, uint8_t month, uint8_t year, + uint8_t next_date, uint8_t next_month, + uint8_t next_year) +{ + const uint8_t tod[7] =3D { 0x59, 0x59, 0x23, 0x01, date, month, year }; + uint8_t resp[7]; + unsigned idx; + + i2c_write_block(i2cdev, DS1339_SECONDS, tod, sizeof(tod)); + + for (idx =3D 0; idx < 50; idx++) { + if (i2c_get8(i2cdev, DS1339_DATE) !=3D date) { + break; + } + g_usleep(100 * 1000); + } + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, sizeof(resp)); + g_assert_cmphex(resp[4], =3D=3D, next_date); + g_assert_cmphex(resp[5] & 0x1f, =3D=3D, next_month); + g_assert_cmphex(resp[6], =3D=3D, next_year); +} + +/* A 31-day month rolls over to the first of the next. */ +static void test_month_31_days(void *obj, void *data, QGuestAllocator *all= oc) +{ + check_month_rollover((QI2CDevice *)obj, + 0x31, 0x01, 0x23, 0x01, 0x02, 0x23); +} + +/* A 30-day month rolls over to the first of the next. */ +static void test_month_30_days(void *obj, void *data, QGuestAllocator *all= oc) +{ + check_month_rollover((QI2CDevice *)obj, + 0x30, 0x04, 0x23, 0x01, 0x05, 0x23); +} + +/* Outside a leap year, February rolls over after the 28th. */ +static void test_month_28_days(void *obj, void *data, QGuestAllocator *all= oc) +{ + check_month_rollover((QI2CDevice *)obj, + 0x28, 0x02, 0x23, 0x01, 0x03, 0x23); +} + +/* In a leap year the 28th is not the last day of February. */ +static void test_month_29_days(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + + check_month_rollover(i2cdev, 0x28, 0x02, 0x24, 0x29, 0x02, 0x24); + check_month_rollover(i2cdev, 0x29, 0x02, 0x24, 0x01, 0x03, 0x24); +} + /* The Century bit is guest-writable and survives an oscillator restart. */ static void test_century_bit(void *obj, void *data, QGuestAllocator *alloc) { @@ -314,6 +370,10 @@ static void ds1339_register_nodes(void) qos_add_test("eosc-restart", "ds1339", test_eosc_restart, NULL); qos_add_test("stopped-reserved-bits", "ds1339", test_stopped_reserved_bits, NULL); + qos_add_test("month-28-days", "ds1339", test_month_28_days, NULL); + qos_add_test("month-29-days", "ds1339", test_month_29_days, NULL); + qos_add_test("month-30-days", "ds1339", test_month_30_days, NULL); + qos_add_test("month-31-days", "ds1339", test_month_31_days, NULL); qos_add_test("century-bit", "ds1339", test_century_bit, NULL); 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 45 +++++++++++++++++++++++++++++++++++++++++++= ++ 1 file changed, 45 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index 7eec163049..3259fa1df3 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -14,6 +14,7 @@ =20 /* DS1339 register map */ #define DS1339_SECONDS 0x00 +#define DS1339_HOURS 0x02 #define DS1339_DATE 0x04 #define DS1339_MONTH 0x05 #define DS1339_YEAR 0x06 @@ -26,6 +27,9 @@ =20 #define DS1339_STATUS_OSF 0x80 =20 +#define DS1339_HOURS_12 0x40 +#define DS1339_HOURS_PM 0x20 + /* The clock and calendar come up on the host time. */ static void test_time(void *obj, void *data, QGuestAllocator *alloc) { @@ -170,6 +174,46 @@ static void test_eosc_restart(void *obj, void *data, Q= GuestAllocator *alloc) g_assert_cmphex(resp[6], =3D=3D, 0x31); } =20 +/* Midnight and noon are the hours the 12-hour encoding special-cases. */ +static void test_hour_mode_12(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + const uint8_t tod[3] =3D { + 0x59, 0x59, DS1339_HOURS_12 | DS1339_HOURS_PM | 0x11 /* 11:59:59 P= M */ + }; + unsigned idx; + + i2c_set8(i2cdev, DS1339_HOURS, DS1339_HOURS_12 | 0x12); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_HOURS), =3D=3D, + DS1339_HOURS_12 | 0x12); /* 12 AM is midnight= */ + + i2c_set8(i2cdev, DS1339_HOURS, DS1339_HOURS_12 | DS1339_HOURS_PM | 0x1= 2); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_HOURS), =3D=3D, + DS1339_HOURS_12 | DS1339_HOURS_PM | 0x12); /* 12 PM no= on */ + + i2c_set8(i2cdev, DS1339_HOURS, DS1339_HOURS_12 | DS1339_HOURS_PM | 0x0= 1); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_HOURS), =3D=3D, + DS1339_HOURS_12 | DS1339_HOURS_PM | 0x01); + + i2c_set8(i2cdev, DS1339_HOURS, DS1339_HOURS_12 | 0x11); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_HOURS), =3D=3D, + DS1339_HOURS_12 | 0x11); + + i2c_set8(i2cdev, DS1339_HOURS, 0x13); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_HOURS), =3D=3D, 0x13); + + /* An elapsed midnight moves 11 PM on to 12 AM, not to 00 or 13. */ + i2c_write_block(i2cdev, DS1339_SECONDS, tod, sizeof(tod)); + for (idx =3D 0; idx < 50; idx++) { + if (i2c_get8(i2cdev, DS1339_HOURS) !=3D tod[2]) { + break; + } + g_usleep(100 * 1000); + } + g_assert_cmphex(i2c_get8(i2cdev, DS1339_HOURS), =3D=3D, + DS1339_HOURS_12 | 0x12); +} + /* Program 23:59:59 on the last day of a month and run the clock past it. = */ static void check_month_rollover(QI2CDevice *i2cdev, uint8_t date, uint8_t month, uint8_t year, @@ -370,6 +414,7 @@ static void ds1339_register_nodes(void) qos_add_test("eosc-restart", "ds1339", test_eosc_restart, NULL); qos_add_test("stopped-reserved-bits", "ds1339", test_stopped_reserved_bits, NULL); + qos_add_test("hour-mode-12", "ds1339", test_hour_mode_12, NULL); qos_add_test("month-28-days", "ds1339", test_month_28_days, NULL); qos_add_test("month-29-days", "ds1339", test_month_29_days, NULL); qos_add_test("month-30-days", "ds1339", test_month_30_days, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index 3259fa1df3..12562eff5f 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -15,6 +15,7 @@ /* DS1339 register map */ #define DS1339_SECONDS 0x00 #define DS1339_HOURS 0x02 +#define DS1339_DAY 0x03 #define DS1339_DATE 0x04 #define DS1339_MONTH 0x05 #define DS1339_YEAR 0x06 @@ -174,6 +175,36 @@ static void test_eosc_restart(void *obj, void *data, Q= GuestAllocator *alloc) g_assert_cmphex(resp[6], =3D=3D, 0x31); } =20 +/* The day counter is the guest's own numbering, and steps at midnight. */ +static void test_day_of_week(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + /* 23:59:59 on 14 June 2024, the day counter reading 7. */ + const uint8_t tod[7] =3D { 0x59, 0x59, 0x23, 0x07, 0x14, 0x06, 0x24 }; + unsigned idx; + + for (idx =3D 1; idx <=3D 7; idx++) { + i2c_set8(i2cdev, DS1339_DAY, idx); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_DAY), =3D=3D, idx); + } + + i2c_set8(i2cdev, DS1339_DAY, 0x03); + i2c_set8(i2cdev, DS1339_DATE, 0x14); + i2c_set8(i2cdev, DS1339_MONTH, 0x06); + i2c_set8(i2cdev, DS1339_YEAR, 0x24); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_DAY), =3D=3D, 0x03); + + i2c_write_block(i2cdev, DS1339_SECONDS, tod, sizeof(tod)); + for (idx =3D 0; idx < 50; idx++) { + if (i2c_get8(i2cdev, DS1339_DAY) !=3D 0x07) { + break; + } + g_usleep(100 * 1000); + } + g_assert_cmphex(i2c_get8(i2cdev, DS1339_DAY), =3D=3D, 0x01); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_DATE), =3D=3D, 0x15); +} + /* Midnight and noon are the hours the 12-hour encoding special-cases. */ static void test_hour_mode_12(void *obj, void *data, QGuestAllocator *allo= c) { @@ -414,6 +445,7 @@ static void ds1339_register_nodes(void) qos_add_test("eosc-restart", "ds1339", test_eosc_restart, NULL); qos_add_test("stopped-reserved-bits", "ds1339", test_stopped_reserved_bits, NULL); + qos_add_test("day-of-week", "ds1339", test_day_of_week, NULL); qos_add_test("hour-mode-12", "ds1339", test_hour_mode_12, NULL); qos_add_test("month-28-days", "ds1339", test_month_28_days, NULL); qos_add_test("month-29-days", "ds1339", test_month_29_days, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060497; cv=none; d=zohomail.com; s=zohoarc; b=M4ga4wMHaQbfYiroGoob2CZ4vS9dGEt9xDC8o6ZdLanwWjCj6KLkJ8w3Q0QVgqQc2p30XXX+SIN0A++NgyXuBUfBV5BPma2zm3Q2LJW2LdZErmv1/K7O4O2f/71RcqxRrt7zhO5VlPerCBnwwIKGqstrMP+Jqpbsn3cEFN4UIB4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060497; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=UoANilWHPQU+jFLM2oOvVUgxMcTpl1I7pWBnWHE9eEg=; b=gDynyHUtGDOoF0nIIjfpylXhrWLeuCEz8O8js1SpUqVPSk+jQnvKuEepj5ZdSWWG2BkA6jRxo2xXX5lc4Yv+ZlOojt+SfxQH2186aoD1uYRwOCJATlTtmhvHA7Ze2WxQV0hnZ5sIkSuIhMjphvARdE6JN/HEKPnmZ04w3zgAffI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060497923164.5553417226456; Thu, 15 Oct 2026 03:34:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIje-00019r-M0; Thu, 15 Oct 2026 06:30:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIgT-0004PV-0f for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:27:37 -0400 Received: from mail-wm1-f45.google.com ([209.85.128.45]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIgO-00048y-1x for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:27:35 -0400 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4a19cba5c14so46034885e9.3 for ; Thu, 15 Oct 2026 03:27:31 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 56 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index 12562eff5f..a1b5afb331 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -8,7 +8,10 @@ =20 #include "qemu/osdep.h" #include "qemu/bcd.h" +#include "libqtest.h" +#include "libqtest-single.h" #include "libqos/i2c.h" +#include "qobject/qdict.h" =20 #define DS1339_ADDR 0x68 =20 @@ -426,6 +429,52 @@ static void test_alarm_registers(void *obj, void *data, } } =20 +/* A reset restores the power-on state, unless persist-on-reset is set. */ +static void check_reset(QI2CDevice *i2cdev, bool persists) +{ + uint8_t year =3D i2c_get8(i2cdev, DS1339_YEAR); + /* A year the clock is not already showing, so the check discriminates= . */ + uint8_t marker =3D year =3D=3D 0x42 ? 0x77 : 0x42; + QDict *rsp; + + i2c_set8(i2cdev, DS1339_ALARM1, 0xa5); + i2c_set8(i2cdev, DS1339_STATUS, 0x00); + i2c_set8(i2cdev, DS1339_YEAR, marker); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_ALARM1), =3D=3D, 0xa5); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_YEAR), =3D=3D, marker); + + rsp =3D qmp("{ 'execute': 'system_reset' }"); + g_assert(qdict_haskey(rsp, "return")); + qobject_unref(rsp); + qmp_eventwait("RESET"); + + if (persists) { + g_assert_cmphex(i2c_get8(i2cdev, DS1339_ALARM1), =3D=3D, 0xa5); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_YEAR), =3D=3D, marker); + } else { + g_assert_cmphex(i2c_get8(i2cdev, DS1339_ALARM1), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL), =3D=3D, 0x18); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS), =3D=3D, + DS1339_STATUS_OSF); + /* Back on host time, which is where the year came from. */ + g_assert_cmphex(i2c_get8(i2cdev, DS1339_YEAR), =3D=3D, year); + } +} + +/* Without persist-on-reset, a reset takes the part back to power-on. */ +static void test_reset_clears(void *obj, void *data, QGuestAllocator *allo= c) +{ + check_reset((QI2CDevice *)obj, false); +} + +/* With persist-on-reset, the registers and the clock survive a reset. */ +static void test_reset_persists(void *obj, void *data, QGuestAllocator *al= loc) +{ + check_reset((QI2CDevice *)obj, true); +} + static void ds1339_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -459,6 +508,13 @@ static void ds1339_register_nodes(void) qos_add_test("block-wrap", "ds1339", test_block_wrap, NULL); qos_add_test("alarm-registers", "ds1339", test_alarm_registers, NULL); + qos_add_test("reset-clears", "ds1339", test_reset_clears, NULL); + + opts.extra_device_opts =3D "address=3D0x68,persist-on-reset=3Don"; + qos_node_create_driver_named("ds1339-persist", "ds1339", i2c_device_cr= eate); + qos_node_consumes("ds1339-persist", "i2c-bus", &opts); + + qos_add_test("reset-persists", "ds1339-persist", test_reset_persists, = NULL); } =20 libqos_init(ds1339_register_nodes); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Emmanuel Blot --- tests/qtest/ds1339-test.c | 61 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/tests/qtest/ds1339-test.c b/tests/qtest/ds1339-test.c index a1b5afb331..ca2378aa34 100644 --- a/tests/qtest/ds1339-test.c +++ b/tests/qtest/ds1339-test.c @@ -7,9 +7,13 @@ */ =20 #include "qemu/osdep.h" + +#include + #include "qemu/bcd.h" #include "libqtest.h" #include "libqtest-single.h" +#include "libqos/qgraph.h" #include "libqos/i2c.h" #include "qobject/qdict.h" =20 @@ -475,6 +479,62 @@ static void test_reset_persists(void *obj, void *data,= QGuestAllocator *alloc) check_reset((QI2CDevice *)obj, true); } =20 +/* The register file, the Century bit and a stopped clock all migrate. */ +static void test_migration(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev =3D (QI2CDevice *)obj; + /* 23:59:59 on the last day of 2099, Century set. */ + const uint8_t tod[7] =3D { 0x59, 0x59, 0x23, 0x03, 0x31, 0x8c, 0x99 }; + g_autofree char *tmpfs =3D NULL; + g_autofree char *mig_path =3D NULL; + g_autofree char *uri =3D NULL; + GString *dest_cmdline; + GError *err =3D NULL; + QTestState *from, *to; + uint8_t resp[7]; + QDict *rsp; + + tmpfs =3D g_dir_make_tmp("ds1339-test-XXXXXX", &err); + g_assert_no_error(err); + g_assert(tmpfs); + + mig_path =3D g_strdup_printf("%s/socket.mig", tmpfs); + uri =3D g_strdup_printf("unix:%s", mig_path); + + /* Stop the clock first, so both sides have the same time to compare. = */ + i2c_set8(i2cdev, DS1339_CONTROL, 0x18 | 0x80); + i2c_write_block(i2cdev, DS1339_SECONDS, tod, sizeof(tod)); + i2c_set8(i2cdev, DS1339_ALARM1, 0xa5); + + dest_cmdline =3D g_string_new(qos_get_current_command_line()); + g_string_append_printf(dest_cmdline, " -incoming %s", uri); + to =3D qtest_init(dest_cmdline->str); + + rsp =3D qmp("{ 'execute': 'migrate', 'arguments': { 'uri': %s } }", ur= i); + g_assert(qdict_haskey(rsp, "return")); + qobject_unref(rsp); + + qmp_eventwait("STOP"); + qtest_qmp_eventwait(to, "RESUME"); + + from =3D i2cdev->bus->qts; + i2cdev->bus->qts =3D to; + + i2c_read_block(i2cdev, DS1339_SECONDS, resp, sizeof(resp)); + g_assert_cmpmem(resp, sizeof(resp), tod, sizeof(tod)); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_ALARM1), =3D=3D, 0xa5); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_CONTROL), =3D=3D, 0x18 | 0x80); + g_assert_cmphex(i2c_get8(i2cdev, DS1339_STATUS) & DS1339_STATUS_OSF, + =3D=3D, DS1339_STATUS_OSF); + + i2cdev->bus->qts =3D from; + + qtest_quit(to); + g_unlink(mig_path); + g_rmdir(tmpfs); + g_string_free(dest_cmdline, true); +} + static void ds1339_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -509,6 +569,7 @@ static void ds1339_register_nodes(void) qos_add_test("alarm-registers", "ds1339", test_alarm_registers, NULL); qos_add_test("reset-clears", "ds1339", test_reset_clears, NULL); + qos_add_test("migration", "ds1339", test_migration, NULL); =20 opts.extra_device_opts =3D "address=3D0x68,persist-on-reset=3Don"; qos_node_create_driver_named("ds1339-persist", "ds1339", i2c_device_cr= eate); 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The device measures a differential shunt voltage and a bus voltage; the current and power registers are not measured directly but derived by the device from the shunt voltage and the guest-programmed Calibration register. The alert is modelled. Shunt and bus voltages can be injected through the "shunt-voltage" and "bus-voltage" QOM properties (in nV and uV respectively). Note: Conversion is instantaneous: the averaging and conversion-time fields are stored but have no timing effect. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- hw/arm/Kconfig | 1 + hw/sensor/Kconfig | 4 + hw/sensor/ina230.c | 597 +++++++++++++++++++++++++++++++++++++++++= ++++ hw/sensor/meson.build | 1 + hw/sensor/trace-events | 7 + include/hw/sensor/ina230.h | 14 ++ 6 files changed, 624 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4445f16f45..116d1c64ac 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -539,6 +539,7 @@ config ASPEED_SOC select TMP105 select TMP421 select EMC141X + select INA230 select OR_IRQ select UNIMP select LED diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index b459ac2240..da519159ac 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -2,6 +2,10 @@ config ADC128D818 bool depends on I2C =20 +config INA230 + bool + depends on I2C + config TMP105 bool depends on I2C diff --git a/hw/sensor/ina230.c b/hw/sensor/ina230.c new file mode 100644 index 0000000000..988d12a6c5 --- /dev/null +++ b/hw/sensor/ina230.c @@ -0,0 +1,597 @@ +/* + * Texas Instruments INA230 36V, 16-bit current/voltage/power monitor + * with an I2C interface. + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * The INA230 measures a differential shunt voltage and a bus voltage. + * Current and power are not measured directly: they are derived by the + * device from the measured shunt voltage. + * + * Limitations: + * - Conversion timing is instantaneous. A conversion runs synchronously w= hen an + * input, the calibration or the configuration changes; the per-channel + * conversion times (VSH_CT/VBUS_CT), the averaging count (AVG) and cont= inuous + * re-conversion on a timer are not modelled. A read always returns the = value + * derived from the current inputs and CVRF is set once a conversion has= run. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qom/object.h" +#include "hw/sensor/ina230.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/registerfields.h" +#include "hw/i2c/i2c.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define INA230_REG_CONFIG 0x00 +#define INA230_REG_SHUNT 0x01 +#define INA230_REG_BUS 0x02 +#define INA230_REG_POWER 0x03 +#define INA230_REG_CURRENT 0x04 +#define INA230_REG_CALIBRATION 0x05 +#define INA230_REG_MASK_ENABLE 0x06 +#define INA230_REG_ALERT_LIMIT 0x07 +#define INA230_REG_DIE_ID 0xFF + +FIELD(INA230_CONFIG, MODE, 0, 3) +FIELD(INA230_CONFIG, VSH_CT, 3, 3) +FIELD(INA230_CONFIG, VBUS_CT, 6, 3) +FIELD(INA230_CONFIG, AVG, 9, 3) +FIELD(INA230_CONFIG, RST, 15, 1) + +#define INA230_CONFIG_POR 0x4127 + +FIELD(INA230_MASK_ENABLE, LEN, 0, 1) /* alert latch enable */ +FIELD(INA230_MASK_ENABLE, APOL, 1, 1) /* alert polarity */ +FIELD(INA230_MASK_ENABLE, OVF, 2, 1) /* math overflow flag (status) */ +FIELD(INA230_MASK_ENABLE, CVRF, 3, 1) /* conversion ready flag (status) = */ +FIELD(INA230_MASK_ENABLE, AFF, 4, 1) /* alert function flag (status) */ +FIELD(INA230_MASK_ENABLE, CNVR, 10, 1) /* conversion ready alert */ +FIELD(INA230_MASK_ENABLE, POL, 11, 1) /* power over-limit */ +FIELD(INA230_MASK_ENABLE, BUL, 12, 1) /* bus under-limit */ +FIELD(INA230_MASK_ENABLE, BOL, 13, 1) /* bus over-limit */ +FIELD(INA230_MASK_ENABLE, SUL, 14, 1) /* shunt under-limit */ +FIELD(INA230_MASK_ENABLE, SOL, 15, 1) /* shunt over-limit */ + +/* Writable Mask/Enable bits: alert-function selects + APOL + LEN */ +#define INA230_ME_WMASK (R_INA230_MASK_ENABLE_SOL_MASK | \ + R_INA230_MASK_ENABLE_SUL_MASK | \ + R_INA230_MASK_ENABLE_BOL_MASK | \ + R_INA230_MASK_ENABLE_BUL_MASK | \ + R_INA230_MASK_ENABLE_POL_MASK | \ + R_INA230_MASK_ENABLE_CNVR_MASK | \ + R_INA230_MASK_ENABLE_APOL_MASK | \ + R_INA230_MASK_ENABLE_LEN_MASK) +/* Read-only status bits: AFF, CVRF, OVF */ +#define INA230_ME_STATUS_MASK (R_INA230_MASK_ENABLE_AFF_MASK | \ + R_INA230_MASK_ENABLE_CVRF_MASK | \ + R_INA230_MASK_ENABLE_OVF_MASK) + +FIELD(INA230_CALIBRATION, FS, 0, 15) +#define INA230_CAL_MASK R_INA230_CALIBRATION_FS_MASK + +#define INA230_SHUNT_LSB_NV 2500 /* 2.5 uV per LSB */ +#define INA230_BUS_LSB_UV 1250 /* 1.25 mV per LSB */ +#define INA230_SHUNT_MIN_NV (-81920000) /* -32768 * 2.5 uV */ +#define INA230_SHUNT_MAX_NV 81917500 /* 32767 * 2.5 uV */ +/* + * A real rail should not drive the pin past 36 V, so bus codes above 0x70= 80 + * are intentionally unreachable in the model. + */ +#define INA230_BUS_MAX_UV 36000000 /* bus pin rated 0..36 V */ + +#define INA230_CURRENT_DIV 2048 +#define INA230_POWER_DIV 20000 + +#define INA230_DIE_ID_VAL 0x2310 + +OBJECT_DECLARE_SIMPLE_TYPE(INA230State, INA230) + +struct INA230State { + I2CSlave parent_obj; + + qemu_irq alert; /* ALERT open-drain output */ + + /* I2C transfer state */ + uint8_t ptr; /* register pointer */ + uint8_t len; /* bytes received in current transfer */ + uint8_t wr_hi; /* pending write MSB */ + uint8_t rx_byte; /* 0: return MSB next, 1: return LSB next */ + uint16_t rx_word; /* value latched at the start of a read */ + + /* Register file */ + uint16_t config; + uint16_t calibration; + uint16_t mask_enable; + uint16_t alert_limit; + + /* Derived measurement registers */ + uint16_t shunt_reg; + uint16_t bus_reg; + uint16_t current_reg; + uint16_t power_reg; + + /* Injected physical inputs */ + int32_t shunt_nv; /* shunt voltage, nanovolts (signed: bidirectional)= */ + uint32_t bus_uv; /* bus voltage, microvolts (never negative) */ + + /* + * In latch mode AFF and the ALERT pin stay asserted until the + * Configuration register is written or the Mask/Enable register is re= ad + * (datasheet 7.3.3). + */ + bool alert_latched; + + char *description; +}; + +/* + * Evaluate the selected alert function. @shunt_fresh and @bus_fresh tell = which + * of the measurement registers hold a fresh value; a function fed by a ch= annel + * that did not convert cannot assert. + */ +static bool ina230_limit_alert(const INA230State *s, bool shunt_fresh, + bool bus_fresh) +{ + uint16_t me =3D s->mask_enable; + int16_t shunt =3D (int16_t)s->shunt_reg; + int16_t limit_s =3D (int16_t)s->alert_limit; + uint16_t limit_u =3D s->alert_limit; + + if (FIELD_EX16(me, INA230_MASK_ENABLE, SOL)) { + return shunt_fresh && shunt > limit_s; + } + if (FIELD_EX16(me, INA230_MASK_ENABLE, SUL)) { + return shunt_fresh && shunt < limit_s; + } + if (FIELD_EX16(me, INA230_MASK_ENABLE, BOL)) { + return bus_fresh && s->bus_reg > limit_u; + } + if (FIELD_EX16(me, INA230_MASK_ENABLE, BUL)) { + return bus_fresh && s->bus_reg < limit_u; + } + if (FIELD_EX16(me, INA230_MASK_ENABLE, POL)) { + return bus_fresh && s->power_reg > limit_u; + } + return false; +} + +static void ina230_refresh_alert(INA230State *s) +{ + bool latch =3D FIELD_EX16(s->mask_enable, INA230_MASK_ENABLE, LEN); + bool aff =3D latch ? s->alert_latched : ina230_limit_alert(s, true, tr= ue); + bool cnvr; + bool active; + int level; + + s->mask_enable =3D FIELD_DP16(s->mask_enable, INA230_MASK_ENABLE, AFF,= aff); + + cnvr =3D FIELD_EX16(s->mask_enable, INA230_MASK_ENABLE, CNVR) && + FIELD_EX16(s->mask_enable, INA230_MASK_ENABLE, CVRF); + + active =3D aff || cnvr; + + level =3D FIELD_EX16(s->mask_enable, INA230_MASK_ENABLE, APOL) ? + active : !active; + + trace_ina230_alert(s->description, level); + qemu_set_irq(s->alert, level); +} + +static void ina230_sample_alert(INA230State *s, bool shunt_fresh, + bool bus_fresh) +{ + if (FIELD_EX16(s->mask_enable, INA230_MASK_ENABLE, LEN) && + ina230_limit_alert(s, shunt_fresh, bus_fresh)) { + s->alert_latched =3D true; + } + ina230_refresh_alert(s); +} + +static void ina230_convert(INA230State *s) +{ + uint8_t mode =3D FIELD_EX16(s->config, INA230_CONFIG, MODE); + bool shunt_en =3D mode & 0x1; + bool bus_en =3D mode & 0x2; + int64_t sr, br, cur, pwr; + bool ovf =3D false; + + if (!shunt_en && !bus_en) { + return; + } + + if (shunt_en) { + sr =3D s->shunt_nv / INA230_SHUNT_LSB_NV; + sr =3D MAX(INT16_MIN, MIN(INT16_MAX, sr)); + s->shunt_reg =3D (uint16_t)(int16_t)sr; + + cur =3D (int64_t)(int16_t)s->shunt_reg * s->calibration / + INA230_CURRENT_DIV; + if (cur > INT16_MAX || cur < INT16_MIN) { + ovf =3D true; + cur =3D MAX(INT16_MIN, MIN(INT16_MAX, cur)); + } + s->current_reg =3D (uint16_t)(int16_t)cur; + } + + if (bus_en) { + br =3D s->bus_uv / INA230_BUS_LSB_UV; + br =3D MAX(0, MIN(INT16_MAX, br)); + s->bus_reg =3D (uint16_t)br; + } + + /* + * In bus-only mode the current register is retained from the last shu= nt + * conversion rather than measured anew, but the power register is sti= ll + * refreshed. + */ + if (bus_en) { + pwr =3D (int64_t)(int16_t)s->current_reg * s->bus_reg / INA230_POW= ER_DIV; + /* POWER is an unsigned, positive-only register (datasheet). */ + if (pwr < 0) { + pwr =3D 0; + } else if (pwr > UINT16_MAX) { + ovf =3D true; + pwr =3D UINT16_MAX; + } + s->power_reg =3D (uint16_t)pwr; + } + + /* Without a calibration the device reports neither current nor power.= */ + if (s->calibration =3D=3D 0) { + s->current_reg =3D 0; + s->power_reg =3D 0; + } + + s->mask_enable =3D FIELD_DP16(s->mask_enable, INA230_MASK_ENABLE, OVF,= ovf); + s->mask_enable =3D FIELD_DP16(s->mask_enable, INA230_MASK_ENABLE, CVRF= , 1); + + trace_ina230_convert(s->description, s->shunt_reg, s->bus_reg, + s->current_reg, s->power_reg); + + ina230_sample_alert(s, shunt_en, bus_en); +} + +/* + * A physical input or the calibration changed. + * - in continuous mode the device keeps converting and immediately tracks + * the new value + * - in a triggered mode it performs exactly one conversion per trigger + */ +static void ina230_input_update(INA230State *s) +{ + if (FIELD_EX16(s->config, INA230_CONFIG, MODE) & 0x4) { + ina230_convert(s); + } +} + +static void ina230_reset_regs(INA230State *s) +{ + s->config =3D INA230_CONFIG_POR; + s->calibration =3D 0; + s->mask_enable =3D 0; + s->alert_limit =3D 0; + s->alert_latched =3D false; + + s->ptr =3D 0; + s->len =3D 0; + s->wr_hi =3D 0; + s->rx_byte =3D 0; + s->rx_word =3D 0; + + s->shunt_reg =3D 0; + s->bus_reg =3D 0; + s->current_reg =3D 0; + s->power_reg =3D 0; + + ina230_refresh_alert(s); +} + +static uint16_t ina230_read_reg(INA230State *s, uint8_t reg) +{ + uint16_t val; + + switch (reg) { + case INA230_REG_CONFIG: + val =3D s->config; + break; + case INA230_REG_SHUNT: + val =3D s->shunt_reg; + break; + case INA230_REG_BUS: + val =3D s->bus_reg; + break; + case INA230_REG_POWER: + val =3D s->power_reg; + break; + case INA230_REG_CURRENT: + val =3D s->current_reg; + break; + case INA230_REG_CALIBRATION: + val =3D s->calibration; + break; + case INA230_REG_MASK_ENABLE: + val =3D s->mask_enable; + s->mask_enable =3D FIELD_DP16(s->mask_enable, INA230_MASK_ENABLE, + CVRF, 0); + s->alert_latched =3D false; + ina230_refresh_alert(s); + break; + case INA230_REG_ALERT_LIMIT: + val =3D s->alert_limit; + break; + case INA230_REG_DIE_ID: + val =3D INA230_DIE_ID_VAL; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: read from undefined register 0x%02x\n", + __func__, s->description, reg); + val =3D 0; + break; + } + + trace_ina230_read(s->description, reg, val); + return val; +} + +static void ina230_write_reg(INA230State *s, uint8_t reg, uint16_t val) +{ + trace_ina230_write(s->description, reg, val); + + switch (reg) { + case INA230_REG_CONFIG: + if (val & R_INA230_CONFIG_RST_MASK) { + trace_ina230_reset(s->description, "reg"); + ina230_reset_regs(s); + break; + } + s->config =3D val & ~R_INA230_CONFIG_RST_MASK; + /* + * The write itself releases a latched alert, so the release reach= es + * the ALERT pin before the conversion it triggers can relatch it. + */ + s->alert_latched =3D false; + ina230_refresh_alert(s); + ina230_convert(s); + break; + case INA230_REG_CALIBRATION: + s->calibration =3D val & INA230_CAL_MASK; + ina230_input_update(s); + break; + case INA230_REG_MASK_ENABLE: + s->mask_enable =3D (val & INA230_ME_WMASK) | + (s->mask_enable & INA230_ME_STATUS_MASK); + ina230_refresh_alert(s); + break; + case INA230_REG_ALERT_LIMIT: + s->alert_limit =3D val; + ina230_refresh_alert(s); + break; + case INA230_REG_SHUNT: + case INA230_REG_BUS: + case INA230_REG_POWER: + case INA230_REG_CURRENT: + case INA230_REG_DIE_ID: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: write to read-only register 0x%02x\n", + __func__, s->description, reg); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: write to undefined register 0x%02x\n", + __func__, s->description, reg); + break; + } +} + +static uint8_t ina230_recv(I2CSlave *i2c) +{ + INA230State *s =3D INA230(i2c); + uint8_t byte; + + if (s->rx_byte =3D=3D 0) { + s->rx_word =3D ina230_read_reg(s, s->ptr); + byte =3D s->rx_word >> 8; + s->rx_byte =3D 1; + } else { + byte =3D s->rx_word & 0xff; + s->rx_byte =3D 0; + } + + return byte; +} + +static int ina230_send(I2CSlave *i2c, uint8_t data) +{ + INA230State *s =3D INA230(i2c); + + if (s->len =3D=3D 0) { + s->ptr =3D data; + } else if ((s->len & 1) =3D=3D 1) { + s->wr_hi =3D data; + } else { + ina230_write_reg(s, s->ptr, ((uint16_t)s->wr_hi << 8) | data); + } + s->len++; + + return 0; +} + +static int ina230_event(I2CSlave *i2c, enum i2c_event event) +{ + INA230State *s =3D INA230(i2c); + + s->len =3D 0; + s->rx_byte =3D 0; + + return 0; +} + +static void ina230_get_shunt(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA230State *s =3D INA230(obj); + int64_t value =3D s->shunt_nv; + + visit_type_int(v, name, &value, errp); +} + +static void ina230_set_shunt(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA230State *s =3D INA230(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < INA230_SHUNT_MIN_NV || value > INA230_SHUNT_MAX_NV) { + error_setg(errp, + "%s: shunt-voltage %" PRId64 " out of range (%d..%d nV)= ", + s->description, value, + INA230_SHUNT_MIN_NV, INA230_SHUNT_MAX_NV); + return; + } + + s->shunt_nv =3D (int32_t)value; + ina230_input_update(s); +} + +static void ina230_get_bus(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA230State *s =3D INA230(obj); + int64_t value =3D s->bus_uv; + + visit_type_int(v, name, &value, errp); +} + +static void ina230_set_bus(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA230State *s =3D INA230(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < 0 || value > INA230_BUS_MAX_UV) { + error_setg(errp, + "%s: bus-voltage %" PRId64 " out of range (0..%d uV)", + s->description, value, INA230_BUS_MAX_UV); + return; + } + + s->bus_uv =3D (uint32_t)value; + ina230_input_update(s); +} + +static void ina230_reset_hold(Object *obj, ResetType type) +{ + INA230State *s =3D INA230(obj); + + trace_ina230_reset(s->description, "hw"); + ina230_reset_regs(s); +} + +static int ina230_post_load(void *opaque, int version_id) +{ + INA230State *s =3D opaque; + + ina230_refresh_alert(s); + + return 0; +} + +static const VMStateDescription ina230_vmstate =3D { + .name =3D "INA230", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D ina230_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(ptr, INA230State), + VMSTATE_UINT8(len, INA230State), + VMSTATE_UINT8(wr_hi, INA230State), + VMSTATE_UINT8(rx_byte, INA230State), + VMSTATE_UINT16(rx_word, INA230State), + VMSTATE_UINT16(config, INA230State), + VMSTATE_UINT16(calibration, INA230State), + VMSTATE_UINT16(mask_enable, INA230State), + VMSTATE_UINT16(alert_limit, INA230State), + VMSTATE_UINT16(shunt_reg, INA230State), + VMSTATE_UINT16(bus_reg, INA230State), + VMSTATE_UINT16(current_reg, INA230State), + VMSTATE_UINT16(power_reg, INA230State), + VMSTATE_INT32(shunt_nv, INA230State), + VMSTATE_UINT32(bus_uv, INA230State), + VMSTATE_BOOL(alert_latched, INA230State), + VMSTATE_I2C_SLAVE(parent_obj, INA230State), + VMSTATE_END_OF_LIST() + } +}; + +static void ina230_initfn(Object *obj) +{ + object_property_add(obj, "shunt-voltage", "int", ina230_get_shunt, + ina230_set_shunt, NULL, NULL); + object_property_set_description(obj, "shunt-voltage", + "Injected shunt (differential) voltage= , " + "in nanovolts"); + object_property_add(obj, "bus-voltage", "int", ina230_get_bus, + ina230_set_bus, NULL, NULL); + object_property_set_description(obj, "bus-voltage", + "Injected bus voltage, in microvolts"); +} + +static void ina230_realize(DeviceState *dev, Error **errp) +{ + INA230State *s =3D INA230(dev); + + if (!s->description) { + s->description =3D g_strdup(object_get_typename(OBJECT(dev))); + } + + qdev_init_gpio_out(dev, &s->alert, 1); +} + +static const Property ina230_properties[] =3D { + DEFINE_PROP_STRING("description", INA230State, description), +}; + +static void ina230_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *ic =3D I2C_SLAVE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + ic->event =3D ina230_event; + ic->recv =3D ina230_recv; + ic->send =3D ina230_send; + dc->realize =3D ina230_realize; + rc->phases.hold =3D ina230_reset_hold; + dc->vmsd =3D &ina230_vmstate; + device_class_set_props(dc, ina230_properties); +} + +static const TypeInfo ina230_types[] =3D { + { + .name =3D TYPE_INA230, + .parent =3D TYPE_I2C_SLAVE, + .instance_init =3D ina230_initfn, + .instance_size =3D sizeof(INA230State), + .class_init =3D ina230_class_init, + }, +}; + +DEFINE_TYPES(ina230_types) diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index fe36c9ef91..b81f001fdf 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -1,4 +1,5 @@ system_ss.add(when: 'CONFIG_ADC128D818', if_true: files('adc128d818.c')) +system_ss.add(when: 'CONFIG_INA230', if_true: files('ina230.c')) system_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) system_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) system_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c')) diff --git a/hw/sensor/trace-events b/hw/sensor/trace-events index 5a3630f7bb..f809b6b506 100644 --- a/hw/sensor/trace-events +++ b/hw/sensor/trace-events @@ -8,6 +8,13 @@ adc128d818_convert(const char *id, uint8_t channel, uint16= _t value) "%s ch %u va adc128d818_irq(const char *id, bool level) "%s level %u" adc128d818_reset(const char *id, const char *source) "%s %s" =20 +# ina230.c +ina230_read(const char *id, uint8_t reg, uint16_t value) "%s reg 0x%02x va= l 0x%04x" +ina230_write(const char *id, uint8_t reg, uint16_t value) "%s reg 0x%02x v= al 0x%04x" +ina230_convert(const char *id, uint16_t shunt, uint16_t bus, uint16_t curr= ent, uint16_t power) "%s shunt 0x%04x bus 0x%04x current 0x%04x power 0x%04= x" +ina230_alert(const char *id, bool level) "%s level %u" +ina230_reset(const char *id, const char *source) "%s %s" + # tmp105.c tmp105_read(uint8_t dev, uint8_t addr) "device: 0x%02x, addr: 0x%02x" tmp105_write(uint8_t dev, uint8_t addr) "device: 0x%02x, addr 0x%02x" diff --git a/include/hw/sensor/ina230.h b/include/hw/sensor/ina230.h new file mode 100644 index 0000000000..4394727d47 --- /dev/null +++ b/include/hw/sensor/ina230.h @@ -0,0 +1,14 @@ +/* + * Texas Instruments INA230 current/voltage/power monitor with I2C interfa= ce + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_SENSOR_INA230_H +#define HW_SENSOR_INA230_H + +#define TYPE_INA230 "ina230" + +#endif --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Cover the power-on-reset defaults and Die ID, the software reset, and the Configuration register write mask. The QMP voltage-injection helpers arrive with the following commit that exercises them. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina230-test.c | 115 ++++++++++++++++++++++++++++++++++++++++++= ++++ tests/qtest/meson.build | 1 + 2 files changed, 116 insertions(+) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c new file mode 100644 index 0000000000..f7aefd2d97 --- /dev/null +++ b/tests/qtest/ina230-test.c @@ -0,0 +1,115 @@ +/* + * QTest testcase for the INA230 current/voltage/power monitor + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqos/i2c.h" +#include "libqos/qgraph.h" +#include "libqtest-single.h" +#include "qobject/qdict.h" + +#define INA230_TEST_ID "ina230-test" +#define INA230_TEST_ADDR 0x40 + +/* Register pointer addresses */ +#define REG_CONFIG 0x00 +#define REG_SHUNT 0x01 +#define REG_BUS 0x02 +#define REG_POWER 0x03 +#define REG_CURRENT 0x04 +#define REG_CALIBRATION 0x05 +#define REG_MASK_ENABLE 0x06 +#define REG_ALERT_LIMIT 0x07 +#define REG_DIE_ID 0xFF + +/* Configuration register bits */ +#define CONFIG_POR 0x4127 +#define CONFIG_RST 0x8000 + +/* Mask/Enable register bits */ +#define ME_LEN 0x0001 +#define ME_APOL 0x0002 +#define ME_OVF 0x0004 +#define ME_CVRF 0x0008 +#define ME_AFF 0x0010 +#define ME_CNVR 0x0400 +#define ME_POL 0x0800 +#define ME_BUL 0x1000 +#define ME_BOL 0x2000 +#define ME_SUL 0x4000 +#define ME_SOL 0x8000 + +/* Injected-input scaling (datasheet fixed LSBs) */ +#define SHUNT_LSB_NV 2500 +#define BUS_LSB_UV 1250 + +#define DIE_ID_VAL 0x2310 + +/* Power-on-reset default values and the Die ID */ +static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_POR); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_CALIBRATION), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_ALERT_LIMIT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_DIE_ID), =3D=3D, DIE_ID_VAL); +} + +/* Software reset via the Configuration RST bit */ +static void test_soft_reset(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CALIBRATION, 0x1234); + i2c_set16(dev, REG_MASK_ENABLE, ME_SOL); + i2c_set16(dev, REG_ALERT_LIMIT, 0x0500); + + g_assert_cmphex(i2c_get16(dev, REG_CALIBRATION), =3D=3D, 0x1234); + g_assert_cmphex(i2c_get16(dev, REG_ALERT_LIMIT), =3D=3D, 0x0500); + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_POR); + g_assert_cmphex(i2c_get16(dev, REG_CALIBRATION), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_ALERT_LIMIT), =3D=3D, 0x0000); +} + +/* Every bit except the self-clearing RST is writable and reads back */ +static void test_config_wmask(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + /* Reserved bits are not forced: the guest value is retained */ + i2c_set16(dev, REG_CONFIG, 0x0007); + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, 0x0007); + + i2c_set16(dev, REG_CONFIG, 0x7FFF); + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, 0x7FFF); +} + +static void ina230_register_nodes(void) +{ + QOSGraphEdgeOptions opts =3D { + .extra_device_opts =3D "id=3D" INA230_TEST_ID ",address=3D0x40" + }; + add_qi2c_address(&opts, &(QI2CAddress) { INA230_TEST_ADDR }); + + qos_node_create_driver("ina230", i2c_device_create); + qos_node_consumes("ina230", "i2c-bus", &opts); + + qos_add_test("defaults", "ina230", test_defaults, NULL); + qos_add_test("soft-reset", "ina230", test_soft_reset, NULL); + qos_add_test("config-wmask", "ina230", test_config_wmask, NULL); +} +libqos_init(ina230_register_nodes); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e23eb9bbca..e413a0cc75 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -330,6 +330,7 @@ qos_test_ss.add( 'e1000-test.c', 'eepro100-test.c', 'es1370-test.c', + 'ina230-test.c', 'lsm303dlhc-mag-test.c', 'isl_pmbus_vr-test.c', 'max34451-test.c', --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina230-test.c | 124 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c index f7aefd2d97..b01f9445d1 100644 --- a/tests/qtest/ina230-test.c +++ b/tests/qtest/ina230-test.c @@ -49,6 +49,33 @@ =20 #define DIE_ID_VAL 0x2310 =20 +/* QMP helpers for injecting the physical inputs */ + +static void qmp_ina230_set(const char *property, int value) +{ + QDict *resp; + + resp =3D qmp("{ 'execute': 'qom-set', 'arguments':" + " { 'path': %s, 'property': %s, 'value': %d } }", + INA230_TEST_ID, property, value); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); +} + +static int qmp_ina230_get(const char *property) +{ + QDict *resp; + int ret; + + resp =3D qmp("{ 'execute': 'qom-get', 'arguments':" + " { 'path': %s, 'property': %s } }", + INA230_TEST_ID, property); + g_assert(qdict_haskey(resp, "return")); + ret =3D qdict_get_int(resp, "return"); + qobject_unref(resp); + return ret; +} + /* Power-on-reset default values and the Die ID */ static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) { @@ -98,6 +125,96 @@ static void test_config_wmask(void *obj, void *data, QG= uestAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, 0x7FFF); } =20 +/* Shunt voltage register, including two's-complement negatives */ +static void test_shunt_injection(void *obj, void *data, QGuestAllocator *a= lloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x1F40); + + qmp_ina230_set("shunt-voltage", -80000000); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x8300); + + g_assert_cmpint(qmp_ina230_get("shunt-voltage"), =3D=3D, -80000000); +} + +/* Bus voltage register */ +static void test_bus_injection(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + qmp_ina230_set("bus-voltage", 12000000); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x2580); + + qmp_ina230_set("bus-voltage", 11980000); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x2570); +} + +/* Calibration-derived current, using the datasheet worked example */ +static void test_calibration_current(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x2710); +} + +/* Calibration-derived power, using the datasheet worked example */ +static void test_power(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + + g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, 0x12B8); +} + +/* With Calibration =3D=3D 0 the Current and Power registers stay at zero = */ +static void test_zero_cal(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, 0x0000); +} + +/* Clamping at full scale and the OVF (math overflow) flag */ +static void test_edges_overflow(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("shunt-voltage", 81917500); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x7FFF); + qmp_ina230_set("shunt-voltage", -81920000); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x8000); + + qmp_ina230_set("bus-voltage", 36000000); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x7080); + + qmp_ina230_set("shunt-voltage", 20000000); + i2c_set16(dev, REG_CALIBRATION, 0x7FFF); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x7FFF); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_OVF, =3D=3D, ME_O= VF); +} + static void ina230_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -111,5 +228,12 @@ static void ina230_register_nodes(void) qos_add_test("defaults", "ina230", test_defaults, NULL); qos_add_test("soft-reset", "ina230", test_soft_reset, NULL); qos_add_test("config-wmask", "ina230", test_config_wmask, NULL); + qos_add_test("shunt-injection", "ina230", test_shunt_injection, NULL); + qos_add_test("bus-injection", "ina230", test_bus_injection, NULL); + qos_add_test("calibration-current", "ina230", test_calibration_current, + NULL); + qos_add_test("power", "ina230", test_power, NULL); + qos_add_test("zero-cal", "ina230", test_zero_cal, NULL); + qos_add_test("edges-overflow", "ina230", test_edges_overflow, NULL); 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina230-test.c | 97 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 97 insertions(+) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c index b01f9445d1..1c55028fcb 100644 --- a/tests/qtest/ina230-test.c +++ b/tests/qtest/ina230-test.c @@ -215,6 +215,98 @@ static void test_edges_overflow(void *obj, void *data,= QGuestAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_OVF, =3D=3D, ME_O= VF); } =20 +/* Shunt over-limit alert (transparent mode) sets the AFF flag */ +static void test_alert_shunt_over(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + i2c_set16(dev, REG_ALERT_LIMIT, 0x1000); + i2c_set16(dev, REG_MASK_ENABLE, ME_SOL); + + qmp_ina230_set("shunt-voltage", 2500000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); + + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); + + qmp_ina230_set("shunt-voltage", 2500000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); +} + +/* Latch mode holds the alert until the Mask/Enable register is read */ +static void test_alert_latch(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t me; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + i2c_set16(dev, REG_ALERT_LIMIT, 0x1000); + i2c_set16(dev, REG_MASK_ENABLE, ME_SOL | ME_LEN); + + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("shunt-voltage", 2500000); + + me =3D i2c_get16(dev, REG_MASK_ENABLE); + g_assert_cmphex(me & ME_AFF, =3D=3D, ME_AFF); + + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); +} + +/* Bus over-limit alert */ +static void test_alert_bus(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + i2c_set16(dev, REG_ALERT_LIMIT, 0x2000); + i2c_set16(dev, REG_MASK_ENABLE, ME_BOL); + + qmp_ina230_set("bus-voltage", 5000000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); + + qmp_ina230_set("bus-voltage", 12000000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); +} + +/* Power over-limit alert */ +static void test_alert_power(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + + i2c_set16(dev, REG_ALERT_LIMIT, 0x1000); + i2c_set16(dev, REG_MASK_ENABLE, ME_POL); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); + + i2c_set16(dev, REG_ALERT_LIMIT, 0x2000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); +} + +/* Conversion Ready Flag: set on conversion, cleared by reading Mask/Enabl= e */ +static void test_cvrf(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + /* A conversion (triggered by injection) sets CVRF */ + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_CVRF, =3D=3D, ME_= CVRF); + + /* The previous read cleared CVRF; no conversion since, so it stays cl= ear */ + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_CVRF, =3D=3D, 0); +} + static void ina230_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -235,5 +327,10 @@ static void ina230_register_nodes(void) qos_add_test("power", "ina230", test_power, NULL); qos_add_test("zero-cal", "ina230", test_zero_cal, NULL); qos_add_test("edges-overflow", "ina230", test_edges_overflow, NULL); + qos_add_test("alert-shunt-over", "ina230", test_alert_shunt_over, NULL= ); + qos_add_test("alert-latch", "ina230", test_alert_latch, NULL); + qos_add_test("alert-bus", "ina230", test_alert_bus, NULL); + qos_add_test("alert-power", "ina230", test_alert_power, NULL); + qos_add_test("cvrf", "ina230", test_cvrf, NULL); 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd99febesm69235935e9.15.2026.10.15.03.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:28:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792060094; x=1792664894; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=AHne2JcHx+O7G4KfyAccP7ggw7u1GmKaKZ5l2ViY6Cs=; b=QGEf8Z/A+7pBFFMlpz0xL4HYi8NGmDudgUCC0j11tOy6IaF0YHY2Z4AbYwap1vvyZs D4Qe3YTVZntNLR8aVN1g7YsRyOVhof0Md6b2DvFttSqSEl5rNE2JcLW+0jWZT5GgHB7l qrpR0E7TFiN+grkwLDw+JKXeFWwyLg2vV5hBLxcs+Uqv2gHmKtuKbtgAwJRwo/UbIk2E xkF8eCa4uG825kk0nEl8F2Cn11ml2P5ATt4B93axG8Kec/UOG65idFcDNndqLWFda5+W U0aROERxxW7tUo2hszF57kZ7LlGtvsSigFhjIkdV523kMIFSD3/yaGgFvUol4B7rGAQ7 kaPw== X-Gm-Message-State: AFq9FYJqgW1b9j81TmPsaeHyZ3Wldjq12QZRev6SLDX1585al7DWnncM AHoBe9mK4CLWDIlj5mF1n4op4epjK515pQSj7XZkCntgsTHeDxE56W5YC6lA5Q== X-Gm-Gg: AYBFou04qpxsMKzbtRJPp3WpmYAVCFhsKcGCmTRDitroaGQ6v3fa+PNq9f7nHBZgyO9 DnwCxH0rhkGdUYGVlBkTXXCKvGpiKlzOBDWoneO85y9Z+oabPJnn71mdcqYoWAu1VMWbhHxqCKt UywhZbVCFg29XJS4c3lP1vU3cKD/6rLp85Mq8VZQBHaN9bvjRjhLgPSupx8BXKzR93oIUHuq9lu AUQiL1vRpf/uK/BlyLgeYulRF9D8/B/QH3w7Shl3B1NxhzyjJOVVcoHTyXCNrktQI/+GrkFKAp5 ICkN1y/3UO7fN7ZLkoau4XSCeS9ixay7wOQqysxckdCUryo6QBdiHcyUddyz62mzbXAWlUYyLso ZpSRtecY/omxgszf8GTTjWHC9GH5cpP639ScMuqDUEB03Hq12Z/qN+psW7DALCls7ovTATrQVtl lAMylxNR9Q+MiyyyRariiUTVEDx6dzaMWvybk0v90Et9+tEiRKjl9LSid9YufkNvIGsdFyb6GqB m6LAKEwco8HNwegDl2MYQKeb3VqowkGxTge5ieq+xd268ox41qNMaV5 X-Received: by 2002:a05:600c:c16f:b0:49f:ed8c:6cad with SMTP id 5b1f17b1804b1-4a18e4ca869mr344997495e9.19.1792060093579; Thu, 15 Oct 2026 03:28:13 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:23 +0200 Subject: [PATCH v3 36/50] tests/qtest: ina230: cover the injection-property limits MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-36-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , Glenn Miles X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056476; l=4069; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=3UD9l/AEvavR8S7pGFg9evzwIlCmssJcXuU0S21eH1k=; b=NPCmA6pKJA3ME7i3oNsU8qqFMPaRLvHWa7ZqKDoxfOQwLNfQaqvv+Ht/FfeW0rK5FBZOGA/2q NBrG+DNvL6tDk7MwtYBnH5q7wBP7MM5EJ84xm8qAYVH98drTwQkDVtk X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.49; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f49.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060388308158500 Verify that the extremes of the shunt- and bus-voltage injection ranges round-trip through the QOM property without truncation or wraparound, and that values just outside are rejected rather than silently wrapped. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina230-test.c | 59 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c index 1c55028fcb..36c899efee 100644 --- a/tests/qtest/ina230-test.c +++ b/tests/qtest/ina230-test.c @@ -47,6 +47,11 @@ #define SHUNT_LSB_NV 2500 #define BUS_LSB_UV 1250 =20 +/* Injection-property limits (see ina230.c) */ +#define SHUNT_MIN_NV (-81920000) +#define SHUNT_MAX_NV 81917500 +#define BUS_MAX_UV 36000000 + #define DIE_ID_VAL 0x2310 =20 /* QMP helpers for injecting the physical inputs */ @@ -76,6 +81,18 @@ static int qmp_ina230_get(const char *property) return ret; } =20 +/* A qom-set expected to be rejected (value outside the supported range) */ +static void qmp_ina230_set_fail(const char *property, int64_t value) +{ + QDict *resp; + + resp =3D qmp("{ 'execute': 'qom-set', 'arguments':" + " { 'path': %s, 'property': %s, 'value': %lld } }", + INA230_TEST_ID, property, (long long)value); + g_assert(qdict_haskey(resp, "error")); + qobject_unref(resp); +} + /* Power-on-reset default values and the Die ID */ static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) { @@ -307,6 +324,46 @@ static void test_cvrf(void *obj, void *data, QGuestAll= ocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_CVRF, =3D=3D, 0); } =20 +/* Shunt-voltage injection limits */ +static void test_shunt_limits(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("shunt-voltage", SHUNT_MAX_NV); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x7FFF); + g_assert_cmpint(qmp_ina230_get("shunt-voltage"), =3D=3D, SHUNT_MAX_NV); + + qmp_ina230_set("shunt-voltage", SHUNT_MIN_NV); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x8000); + g_assert_cmpint(qmp_ina230_get("shunt-voltage"), =3D=3D, SHUNT_MIN_NV); + + qmp_ina230_set_fail("shunt-voltage", (int64_t)SHUNT_MAX_NV + 1); + qmp_ina230_set_fail("shunt-voltage", (int64_t)SHUNT_MIN_NV - 1); + g_assert_cmpint(qmp_ina230_get("shunt-voltage"), =3D=3D, SHUNT_MIN_NV); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x8000); +} + +/* Bus-voltage injection limits. */ +static void test_bus_limits(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina230_set("bus-voltage", 0); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x0000); + + qmp_ina230_set("bus-voltage", BUS_MAX_UV); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x7080); + g_assert_cmpint(qmp_ina230_get("bus-voltage"), =3D=3D, BUS_MAX_UV); + + qmp_ina230_set_fail("bus-voltage", (int64_t)BUS_MAX_UV + 1); + qmp_ina230_set_fail("bus-voltage", -1); + g_assert_cmpint(qmp_ina230_get("bus-voltage"), =3D=3D, BUS_MAX_UV); +} + static void ina230_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -322,6 +379,8 @@ static void ina230_register_nodes(void) qos_add_test("config-wmask", "ina230", test_config_wmask, NULL); qos_add_test("shunt-injection", "ina230", test_shunt_injection, NULL); qos_add_test("bus-injection", "ina230", test_bus_injection, NULL); + qos_add_test("shunt-limits", "ina230", test_shunt_limits, NULL); + qos_add_test("bus-limits", "ina230", test_bus_limits, NULL); qos_add_test("calibration-current", "ina230", test_calibration_current, NULL); qos_add_test("power", "ina230", test_power, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060419; cv=none; d=zohomail.com; s=zohoarc; b=XHxDU7cQtrBaNYXhPVeqNJJtw1kY+9bQB8ZcyMG70PJmCAT56xS0BUWVu/MmOud4KhXX6aiwC13pdkv9G7VzGF+L2iU9pk/ahLOmTNXVIJq44S3GqGg5wfo9ZCRi4DiuNv0pcosWRDjb58Pj8+cFNleS0vf6LZwS7xnsIDW2lLM= ARC-Message-Signature: i=1; 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd66c5e6sm40366255e9.2.2026.10.15.03.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:28:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792060100; x=1792664900; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=OOFmzhwngATj5QXbK6+ilaV21N6JVdHVnASw6Lr12jc=; b=TaB3DHUit8S2l7kZI4p5BN+QV6KdPAkewDVbXrRDZJxXT4FIP0eslODNd4PUZ+1dUr 02JHpOvyg4xW3MaQX2jga/qTfoCMpTWBuf+hjcWzOH8w0A6c45dN3/FHR22FIgf2sVcb HkXwkGgsURyTzfrDcM/HDF4Vwxkd0gllVkilCSGxztktkzKQiMzR1/dH+qLsazf0UESN PsNzoExi9L0QRGgVSlNkLEgZf7hl5qwgLeaf1w9xEm84ow9/iPvxKiTAfkySpCsygPF8 X2RW/WJipj6IhyUoohwVFzdhZbVFiVTk/zN+FaV4xPkflaRugTWmiTCdHEbt88m9N5Tf gKPw== X-Gm-Message-State: AFq9FYIwwjyHWIOvxfQHU+FfKOI5phL3K1RFD/a9hGTHo4+Oh1Z64xMJ S3k8mRjUCFNDtw02s8iBOnmcH3E8viAH3g31HwO+2uVbNYa+boMpsopLjH11GA== X-Gm-Gg: AYBFou319nvbTkEyH/P15wPEV94ug4i96VrHzyVNEzE2mOYhSHIyVLm5jO2lSmEjAZu QwcEZidKzMyPZh33VA/2Kj8FnXKARVshvszkf1fEMO1FCRYfn7GrGe3El/2lJkvr2yufbWRV+Ma A8RC81AXKUxCDzR9ooWQpPQ2pnPrBQg4G3sWi1qgFQKdU4gzv5VixCgAqqKTHUWaTILsZInSf8V +3q2DKFdLEu+4JsuIgBR5/gQwq51GlZgm+pK/7tncXxsTnjcfavVEXByo33PKIgwMLL/MFTPXx/ wqj/FBdiN9HOPqeTeKWfJKoFZDq4kA0brLwe6D5Yc3mSw8z9tL7X8GjXNSL2RdpQVUgpJFJwiqJ Cm64P5rAwfNm42t8+Ls06T02Wqlma/M2e19lZYsOsvPYID/qbSr0W83gRfK6e1Orr6EV3xj8FVf X+2wWq2iIJYs+aHVvfhd59NKzNkrl2i16QnaPLlfROp6qp40HRcsguNtIEwrAl1hPcVqJR79Mj0 TtwbJAVsExWAWYgWwhCSFMvqEyZvfbrRRhyQKwFO5lf1Qo= X-Received: by 2002:a05:600d:1b:b0:4a1:9661:14b7 with SMTP id 5b1f17b1804b1-4a196611b9amr267914405e9.32.1792060100051; Thu, 15 Oct 2026 03:28:20 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:24 +0200 Subject: [PATCH v3 37/50] tests/qtest: ina230: cover operating modes and triggered conversions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-37-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056476; l=5268; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=M/AP87tzHPyKIB2/isqSVgsUBIucUWr9P38+NmmmCT4=; b=Yg5mzoaTRKUYOwLQCo+DrFpSzZQ/xsxjaSNkp9VVBeOdH8mjTi6omkFfwMDnOncs48DVluoXG 7BNCbFgGVXOAb22pR0PGra4CZsXz52fJQINZOtClEjyUXgkAKe3SUGH X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.46; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f46.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060420933158500 Add coverage for the MODE field: power-down retains the last results, the shunt/bus channel-enable bits gate which registers track new inputs, triggered modes convert once per Config write, and bus-only mode still derives power from the retained current. Signed-off-by: Emmanuel Blot Reviewed-by: Glenn Miles --- tests/qtest/ina230-test.c | 95 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c index 36c899efee..4d601c74b5 100644 --- a/tests/qtest/ina230-test.c +++ b/tests/qtest/ina230-test.c @@ -142,7 +142,97 @@ static void test_config_wmask(void *obj, void *data, Q= GuestAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, 0x7FFF); } =20 -/* Shunt voltage register, including two's-complement negatives */ +/* Operating modes */ +static void test_modes(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + static const struct { + uint8_t mode; + uint16_t shunt, bus, current, power; + } cases[] =3D { + /* Power-down: no conversion, every register retains the baseline = */ + { 0x0, 0x1F40, 0x2570, 0x2710, 0x12B8 }, + { 0x4, 0x1F40, 0x2570, 0x2710, 0x12B8 }, + /* Shunt only (continuous): shunt and current track the probe */ + { 0x5, 0x0FA0, 0x2570, 0x1388, 0x12B8 }, + /* Shunt and bus (continuous): every register tracks the probe */ + { 0x7, 0x0FA0, 0x12C0, 0x1388, 0x04B0 }, + }; + size_t idx; + + for (idx =3D 0; idx < ARRAY_SIZE(cases); idx++) { + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + + i2c_set16(dev, REG_CONFIG, cases[idx].mode); + qmp_ina230_set("shunt-voltage", 10000000); + qmp_ina230_set("bus-voltage", 6000000); + + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, cases[idx].shun= t); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, cases[idx].bus); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, cases[idx].cu= rrent); + g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, cases[idx].powe= r); + } +} + +/* + * Triggered modes perform exactly one conversion per trigger, where the + * trigger is a Configuration-register write. Injected input changes + * between triggers are ignored until the next write. + */ +static void test_triggered(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + + i2c_set16(dev, REG_CONFIG, 0x03); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x1F40); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x2570); + + qmp_ina230_set("shunt-voltage", 10000000); + qmp_ina230_set("bus-voltage", 6000000); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x1F40); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x2570); + + i2c_set16(dev, REG_CONFIG, 0x03); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x0FA0); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x12C0); + + i2c_set16(dev, REG_CONFIG, 0x07); + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT), =3D=3D, 0x1F40); +} + +/* + * In a bus-only mode the current register is retained, but the power regi= ster + * is still refreshed on each bus conversion from that retained current. + */ +static void test_bus_only_power(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x2710); + + i2c_set16(dev, REG_CONFIG, 0x06); + qmp_ina230_set("bus-voltage", 6000000); + + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x2710); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x12C0); + g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, 0x0960); +} + +/* Shunt voltage register */ static void test_shunt_injection(void *obj, void *data, QGuestAllocator *a= lloc) { QI2CDevice *dev =3D (QI2CDevice *)obj; @@ -377,6 +467,9 @@ static void ina230_register_nodes(void) qos_add_test("defaults", "ina230", test_defaults, NULL); qos_add_test("soft-reset", "ina230", test_soft_reset, NULL); qos_add_test("config-wmask", "ina230", test_config_wmask, NULL); + qos_add_test("modes", "ina230", test_modes, NULL); + qos_add_test("triggered", "ina230", test_triggered, NULL); + qos_add_test("bus-only-power", "ina230", test_bus_only_power, NULL); qos_add_test("shunt-injection", "ina230", test_shunt_injection, NULL); qos_add_test("bus-injection", "ina230", test_bus_injection, NULL); qos_add_test("shunt-limits", "ina230", test_shunt_limits, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060621; cv=none; d=zohomail.com; s=zohoarc; b=Q5Fzbo+OxpudbX42b5+X2bD8bYAm5BHp1RQKW/qaivlNTV/LJUzUgL07WafMsv5qXi2GP+0sOaLjWI8il4Ibq6OfOs6RToFO+oO73bmrPvxspyB3CFHkbEJXVZmFUmgaIcAZ/idFkF5yZ5592KIcLRWOu7yh+9IeHpYxluNFm0s= ARC-Message-Signature: i=1; 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina230-test.c | 89 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c index 4d601c74b5..cda52bb815 100644 --- a/tests/qtest/ina230-test.c +++ b/tests/qtest/ina230-test.c @@ -364,6 +364,88 @@ static void test_alert_latch(void *obj, void *data, QG= uestAllocator *alloc) } =20 /* Bus over-limit alert */ +static void test_alert_latch_persist(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_ALERT_LIMIT, 0x1000); + i2c_set16(dev, REG_MASK_ENABLE, ME_SOL | ME_LEN); + + qmp_ina230_set("shunt-voltage", 20000000); + + /* First read shows the latched AFF and clears the latch */ + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); + + /* Fault still present but no new conversion: AFF stays cleared */ + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); + + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); +} + +/* A Configuration write releases the latch as a Mask/Enable read does. */ +static void test_alert_latch_config(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_ALERT_LIMIT, 0x1000); + i2c_set16(dev, REG_MASK_ENABLE, ME_SOL | ME_LEN); + + /* Latch a fault, then bring the input back below the limit */ + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("shunt-voltage", 2500000); + + i2c_set16(dev, REG_CONFIG, CONFIG_POR); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); + + /* With the fault present, the reconversion latches it again */ + qmp_ina230_set("shunt-voltage", 20000000); + i2c_set16(dev, REG_CONFIG, CONFIG_POR); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); +} + +/* The releasing write need not reconvert: a power-down leaves it clear. */ +static void test_alert_latch_shutdown(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_ALERT_LIMIT, 0x1000); + i2c_set16(dev, REG_MASK_ENABLE, ME_SOL | ME_LEN); + + qmp_ina230_set("shunt-voltage", 20000000); + + i2c_set16(dev, REG_CONFIG, 0x0000); /* power-down */ + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); +} + +/* + * A conversion only re-samples the alert of a channel it converted: the b= us + * register a shunt-only conversion left stale must not re-latch. + */ +static void test_alert_channel(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_ALERT_LIMIT, 0x2000); + i2c_set16(dev, REG_MASK_ENABLE, ME_BOL | ME_LEN); + + qmp_ina230_set("bus-voltage", 12000000); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, ME_A= FF); + + /* Shunt-only mode: the bus register keeps its over-limit value */ + i2c_set16(dev, REG_CONFIG, 0x0005); + qmp_ina230_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_BUS), =3D=3D, 0x2580); + g_assert_cmphex(i2c_get16(dev, REG_MASK_ENABLE) & ME_AFF, =3D=3D, 0); +} + static void test_alert_bus(void *obj, void *data, QGuestAllocator *alloc) { QI2CDevice *dev =3D (QI2CDevice *)obj; @@ -481,6 +563,13 @@ static void ina230_register_nodes(void) qos_add_test("edges-overflow", "ina230", test_edges_overflow, NULL); qos_add_test("alert-shunt-over", "ina230", test_alert_shunt_over, NULL= ); qos_add_test("alert-latch", "ina230", test_alert_latch, NULL); + qos_add_test("alert-latch-persist", "ina230", test_alert_latch_persist, + NULL); + qos_add_test("alert-latch-config", "ina230", test_alert_latch_config, + NULL); + qos_add_test("alert-latch-shutdown", "ina230", test_alert_latch_shutdo= wn, + NULL); + qos_add_test("alert-channel", "ina230", test_alert_channel, NULL); qos_add_test("alert-bus", "ina230", test_alert_bus, NULL); qos_add_test("alert-power", "ina230", test_alert_power, NULL); qos_add_test("cvrf", "ina230", test_cvrf, NULL); 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina230-test.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tests/qtest/ina230-test.c b/tests/qtest/ina230-test.c index cda52bb815..f9e8d3ab9f 100644 --- a/tests/qtest/ina230-test.c +++ b/tests/qtest/ina230-test.c @@ -301,6 +301,30 @@ static void test_zero_cal(void *obj, void *data, QGues= tAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, 0x0000); } =20 +/* Clearing the Calibration zeroes both derived registers in any mode */ +static void test_zero_cal_channels(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + static const uint8_t modes[] =3D { 0x5, 0x6, 0x7 }; + size_t idx; + + for (idx =3D 0; idx < ARRAY_SIZE(modes); idx++) { + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_CALIBRATION, 0x0A00); + qmp_ina230_set("shunt-voltage", 20000000); + qmp_ina230_set("bus-voltage", 11980000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), !=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_POWER), !=3D, 0x0000); + + i2c_set16(dev, REG_CONFIG, modes[idx]); + i2c_set16(dev, REG_CALIBRATION, 0x0000); + + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_POWER), =3D=3D, 0x0000); + } +} + /* Clamping at full scale and the OVF (math overflow) flag */ static void test_edges_overflow(void *obj, void *data, QGuestAllocator *al= loc) { @@ -560,6 +584,7 @@ static void ina230_register_nodes(void) NULL); qos_add_test("power", "ina230", test_power, NULL); qos_add_test("zero-cal", "ina230", test_zero_cal, NULL); + qos_add_test("zero-cal-channels", "ina230", test_zero_cal_channels, NU= LL); qos_add_test("edges-overflow", "ina230", test_edges_overflow, NULL); qos_add_test("alert-shunt-over", "ina230", test_alert_shunt_over, NULL= ); qos_add_test("alert-latch", "ina230", test_alert_latch, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060623; cv=none; d=zohomail.com; s=zohoarc; b=cRV/wPNKxw08KYTIZZmFwkGz/IpD+MytpyofJlZ35hZvBVbndOkVFzaB8+BMBu9LvdEmDEyxInXIYpIBJKGl2KRbiwoL11nQCUi02OiJCfG1PncgsXXwmg80Z0F+8jYE4p/saGQmQ+TKOCzdRtdEeL+BeCiVi8EqPaTXTzanV5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792060623; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=fngOWBkkxOkV7paRM5hPSBUD56RarJ9+IQKvI+mrDd4=; b=jiP60aKaO4tZ972rNvozsOoYgNyftLx8QdU3uR7bJjOz3AQqhAWq8QtDptNGAYWD1qRDoY/S+7hjF+wJpiF0DYFby3z+CxLFSBUmISW8Oe3vXb4JGiiklGAZVCgvUli/KOWPV9H9SKX8DxGEnn3118DL5lzaJdX/25t4rnq2tng= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792060623228549.9074261513625; Thu, 15 Oct 2026 03:37:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xHIlT-00047t-UV; Thu, 15 Oct 2026 06:32:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xHIho-0007yV-OD for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:29:05 -0400 Received: from mail-wr1-f52.google.com ([209.85.221.52]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xHIhc-0004R3-SH for qemu-devel@nongnu.org; Thu, 15 Oct 2026 06:28:55 -0400 Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-48afbd2c386so3025531f8f.3 for ; Thu, 15 Oct 2026 03:28:40 -0700 (PDT) Received: from localhost (89-93-216-19.hfc.dyn.abo.bbox.fr. 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The device measures a differential shunt voltage, a bus voltage and its own die temperature; the current and power registers are not measured directly but derived by the device from the shunt voltage and the guest-programmed Shunt Calibration register. The alert is modelled. Shunt and bus voltages and the die temperature can be injected through the "shunt-voltage", "bus-voltage" and "die-temperature" QOM properties. Note: Conversion is instantaneous: the averaging and conversion-time fields are stored but have no timing effect. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- hw/arm/Kconfig | 1 + hw/sensor/Kconfig | 4 + hw/sensor/ina238.c | 802 +++++++++++++++++++++++++++++++++++++++++= ++++ hw/sensor/meson.build | 1 + hw/sensor/trace-events | 7 + include/hw/sensor/ina238.h | 14 + 6 files changed, 829 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 116d1c64ac..3abe249ed5 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -540,6 +540,7 @@ config ASPEED_SOC select TMP421 select EMC141X select INA230 + select INA238 select OR_IRQ select UNIMP select LED diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index da519159ac..9b7c76fcf5 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -6,6 +6,10 @@ config INA230 bool depends on I2C =20 +config INA238 + bool + depends on I2C + config TMP105 bool depends on I2C diff --git a/hw/sensor/ina238.c b/hw/sensor/ina238.c new file mode 100644 index 0000000000..e4033771b0 --- /dev/null +++ b/hw/sensor/ina238.c @@ -0,0 +1,802 @@ +/* + * Texas Instruments INA238 85V, 16-bit current/voltage/power monitor + * with an I2C interface. + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * The INA238 measures a differential shunt voltage, a bus voltage and its= own + * die temperature. Current and power are not measured directly: they are + * derived by the device from the measured shunt voltage and the programma= ble + * Shunt Calibration register. The INA238 exposes six independent limit + * registers, all monitored simultaneously (multi-alert), a die-temperature + * sensor, a 24-bit power register and an ADCRANGE-dependent shunt LSB. + * + * Limitations (not modelled): + * - Conversion timing is instantaneous. Conversions run synchronously whe= n an + * input, the calibration, the ADC range or the ADC configuration change= s; the + * ADC conversion times (VBUSCT/VSHCT/VTCT), the averaging count (AVG) a= nd the + * CONVDLY start delay are not modelled, and continuous mode does not + * re-convert on a timer. A read always returns the value derived from t= he + * current inputs and CNVRF is set once a conversion has run. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qom/object.h" +#include "hw/sensor/ina238.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/registerfields.h" +#include "hw/i2c/i2c.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define INA238_REG_CONFIG 0x00 +#define INA238_REG_ADC_CONFIG 0x01 +#define INA238_REG_SHUNT_CAL 0x02 +#define INA238_REG_VSHUNT 0x04 +#define INA238_REG_VBUS 0x05 +#define INA238_REG_DIETEMP 0x06 +#define INA238_REG_CURRENT 0x07 +#define INA238_REG_POWER 0x08 +#define INA238_REG_DIAG_ALRT 0x0B +#define INA238_REG_SOVL 0x0C +#define INA238_REG_SUVL 0x0D +#define INA238_REG_BOVL 0x0E +#define INA238_REG_BUVL 0x0F +#define INA238_REG_TEMP_LIMIT 0x10 +#define INA238_REG_PWR_LIMIT 0x11 +#define INA238_REG_MANUFACTURER_ID 0x3E +#define INA238_REG_DEVICE_ID 0x3F + +FIELD(INA238_CONFIG, ADCRANGE, 4, 1) +FIELD(INA238_CONFIG, CONVDLY, 6, 8) +FIELD(INA238_CONFIG, RST, 15, 1) + +#define INA238_CONFIG_POR 0x0000 +#define INA238_CONFIG_WMASK (R_INA238_CONFIG_ADCRANGE_MASK | \ + R_INA238_CONFIG_CONVDLY_MASK) + +FIELD(INA238_ADC_CONFIG, AVG, 0, 3) +FIELD(INA238_ADC_CONFIG, VTCT, 3, 3) +FIELD(INA238_ADC_CONFIG, VSHCT, 6, 3) +FIELD(INA238_ADC_CONFIG, VBUSCT, 9, 3) +FIELD(INA238_ADC_CONFIG, MODE, 12, 4) + +#define INA238_ADC_CONFIG_POR 0xFB68 + +#define INA238_SHUNT_CAL_POR 0x1000 +#define INA238_SHUNT_CAL_MASK 0x7FFF /* bit 15 reserved */ + +FIELD(INA238_DIAG_ALRT, MEMSTAT, 0, 1) /* memory checksum ok (always 1)= */ +FIELD(INA238_DIAG_ALRT, CNVRF, 1, 1) /* conversion ready flag */ +FIELD(INA238_DIAG_ALRT, POL, 2, 1) /* power over-limit */ +FIELD(INA238_DIAG_ALRT, BUSUL, 3, 1) /* bus under-limit */ +FIELD(INA238_DIAG_ALRT, BUSOL, 4, 1) /* bus over-limit */ +FIELD(INA238_DIAG_ALRT, SHNTUL, 5, 1) /* shunt under-limit */ +FIELD(INA238_DIAG_ALRT, SHNTOL, 6, 1) /* shunt over-limit */ +FIELD(INA238_DIAG_ALRT, TMPOL, 7, 1) /* over temperature */ +FIELD(INA238_DIAG_ALRT, MATHOF, 9, 1) /* arithmetic overflow */ +FIELD(INA238_DIAG_ALRT, APOL, 12, 1) /* alert polarity */ +FIELD(INA238_DIAG_ALRT, SLOWALERT, 13, 1) /* alert on averaged value */ +FIELD(INA238_DIAG_ALRT, CNVR, 14, 1) /* conversion-ready on ALERT pin= */ +FIELD(INA238_DIAG_ALRT, ALATCH, 15, 1) /* alert latch enable */ + +#define INA238_DIAG_ALRT_POR 0x0001 /* MEMSTAT =3D 1 */ + +/* Control (writable) bits */ +#define INA238_DIAG_CTRL_MASK (R_INA238_DIAG_ALRT_ALATCH_MASK | \ + R_INA238_DIAG_ALRT_CNVR_MASK | \ + R_INA238_DIAG_ALRT_SLOWALERT_MASK | \ + R_INA238_DIAG_ALRT_APOL_MASK) +/* Read-only status bits (preserved across a control-bit write) */ +#define INA238_DIAG_STATUS_MASK (R_INA238_DIAG_ALRT_MATHOF_MASK | \ + R_INA238_DIAG_ALRT_TMPOL_MASK | \ + R_INA238_DIAG_ALRT_SHNTOL_MASK | \ + R_INA238_DIAG_ALRT_SHNTUL_MASK | \ + R_INA238_DIAG_ALRT_BUSOL_MASK | \ + R_INA238_DIAG_ALRT_BUSUL_MASK | \ + R_INA238_DIAG_ALRT_POL_MASK | \ + R_INA238_DIAG_ALRT_CNVRF_MASK | \ + R_INA238_DIAG_ALRT_MEMSTAT_MASK) +/* Threshold flags cleared when the DIAG_ALRT register is read */ +#define INA238_DIAG_LATCH_MASK (R_INA238_DIAG_ALRT_TMPOL_MASK | \ + R_INA238_DIAG_ALRT_SHNTOL_MASK | \ + R_INA238_DIAG_ALRT_SHNTUL_MASK | \ + R_INA238_DIAG_ALRT_BUSOL_MASK | \ + R_INA238_DIAG_ALRT_BUSUL_MASK | \ + R_INA238_DIAG_ALRT_POL_MASK) + +#define INA238_SOVL_POR 0x7FFF +#define INA238_SUVL_POR 0x8000 +#define INA238_BOVL_POR 0x7FFF +#define INA238_BUVL_POR 0x0000 +/* + * The datasheet is self-inconsistent on the TEMP_LIMIT reset value. + * Writes mask with INA238_TEMP_LIMIT_MASK and the alert comparison shifts= both + * operands >>4. + */ +#define INA238_TEMP_LIMIT_POR 0x7FF0 +#define INA238_PWR_LIMIT_POR 0xFFFF + +#define INA238_BUS_LIMIT_MASK 0x7FFF /* BOVL/BUVL are 15-bit, positiv= e */ +#define INA238_TEMP_LIMIT_MASK 0xFFF0 /* TOL occupies bits [15:4] */ + +#define INA238_MANUFACTURER_ID_VAL 0x5449 /* "TI" */ +#define INA238_DEVICE_ID_VAL 0x2381 /* DIEID 0x238, REV 0x1 */ + +/* Shunt voltage LSB depends on ADCRANGE; bus and temperature are fixed */ +#define INA238_SHUNT_LSB_NV_R0 5000 /* 5 uV per LSB (ADCRANGE =3D 0) = */ +#define INA238_SHUNT_LSB_NV_R1 1250 /* 1.25 uV per LSB (ADCRANGE =3D = 1) */ +#define INA238_BUS_LSB_UV 3125 /* 3.125 mV per LSB */ +#define INA238_TEMP_LSB_MC 125 /* 125 m-degC per LSB */ + +/* + * current =3D shunt_reg * K / SHUNT_CAL. K derives from the fixed 819.2e6 + * internal constant and the ADCRANGE=3D0 shunt LSB: 5e-6 * 819.2e6 =3D 40= 96. + * power =3D current * bus / 64 (0.2 / 3.125mV expressed in the register d= omain). + */ +#define INA238_CURRENT_K 4096 +#define INA238_POWER_DIV 64 +#define INA238_POWER_MAX 0xFFFFFF /* POWER is a 24-bit register */ + +/* Injection property ranges */ +#define INA238_SHUNT_MIN_NV (-163840000) /* -32768 * 5 uV */ +#define INA238_SHUNT_MAX_NV 163835000 /* 32767 * 5 uV */ +#define INA238_BUS_MAX_UV 85000000 /* 85 V full common-mode ra= nge */ +#define INA238_TEMP_MIN_MC (-40000) /* package limited */ +#define INA238_TEMP_MAX_MC 125000 + +OBJECT_DECLARE_SIMPLE_TYPE(INA238State, INA238) + +struct INA238State { + I2CSlave parent_obj; + + qemu_irq alert; /* ALERT open-drain output */ + + /* I2C transfer state */ + uint8_t ptr; /* register pointer */ + uint8_t len; /* bytes received in current transfer */ + uint8_t wr_hi; /* pending write MSB */ + uint8_t rx_byte; /* index of the next byte to return within rx_val */ + uint8_t rx_width; /* width in bytes of the register being read (2 or 3= ) */ + uint32_t rx_val; /* value latched at the start of a read */ + + /* Register file */ + uint16_t config; + uint16_t adc_config; + uint16_t shunt_cal; + uint16_t diag_alrt; + uint16_t sovl; + uint16_t suvl; + uint16_t bovl; + uint16_t buvl; + uint16_t temp_limit; + uint16_t pwr_limit; + + /* Derived measurement registers */ + uint16_t shunt_reg; + uint16_t bus_reg; + uint16_t dietemp_reg; + uint16_t current_reg; + uint32_t power_reg; /* 24-bit */ + + /* Injected physical inputs */ + int32_t shunt_nv; /* shunt voltage, nanovolts (signed: bidirectional)= */ + uint32_t bus_uv; /* bus voltage, microvolts (never negative) */ + int32_t temp_mc; /* die temperature, millidegrees Celsius (signed) */ + + char *description; +}; + +/* + * Update the _field_ limit flag in _diag_ from the current comparison _co= nd_. + * In latch mode (_latch_) a flag that is already set stays set until the + * register is read; in transparent mode it tracks _cond_ directly. A flag + * whose measurement register was not refreshed (_fresh_) keeps its value. + */ +#define INA238_UPD_FLAG(_diag_, _latch_, _fresh_, _field_, _cond_) = \ + do { = \ + if (_fresh_) { = \ + uint16_t _old_ =3D FIELD_EX16(_diag_, INA238_DIAG_ALRT, _field= _); \ + uint16_t _new_ =3D (uint16_t)((_cond_) || ((_latch_) && _old_)= ); \ + (_diag_) =3D FIELD_DP16(_diag_, INA238_DIAG_ALRT, _field_, _ne= w_); \ + } = \ + } while (0) + +static void ina238_refresh_alert(INA238State *s) +{ + uint16_t diag =3D s->diag_alrt; + bool active; + bool cnvr; + int level; + + /* MATHOF is a diagnostic; it does not drive the ALERT pin. */ + active =3D FIELD_EX16(diag, INA238_DIAG_ALRT, SHNTOL) || + FIELD_EX16(diag, INA238_DIAG_ALRT, SHNTUL) || + FIELD_EX16(diag, INA238_DIAG_ALRT, BUSOL) || + FIELD_EX16(diag, INA238_DIAG_ALRT, BUSUL) || + FIELD_EX16(diag, INA238_DIAG_ALRT, TMPOL) || + FIELD_EX16(diag, INA238_DIAG_ALRT, POL); + + cnvr =3D FIELD_EX16(diag, INA238_DIAG_ALRT, CNVR) && + FIELD_EX16(diag, INA238_DIAG_ALRT, CNVRF); + + active =3D active || cnvr; + /* APOL: 0 =3D active-low (default), 1 =3D active-high */ + level =3D FIELD_EX16(diag, INA238_DIAG_ALRT, APOL) ? active : !active; + + trace_ina238_alert(s->description, level); + qemu_set_irq(s->alert, level); +} + +/* + * @shunt_fresh, @bus_fresh and @temp_fresh tell which measurement registe= rs + * hold a fresh value: after a partial conversion the flags fed by the oth= er + * channels must not be re-evaluated against their stale registers. + */ +static void ina238_update_alert(INA238State *s, bool shunt_fresh, + bool bus_fresh, bool temp_fresh, + bool power_fresh) +{ + bool latch =3D FIELD_EX16(s->diag_alrt, INA238_DIAG_ALRT, ALATCH); + int16_t shunt =3D (int16_t)s->shunt_reg; + int16_t temp =3D (int16_t)s->dietemp_reg >> 4; /* sign-extend [15= :4] */ + int16_t temp_lim =3D (int16_t)s->temp_limit >> 4; + uint16_t diag =3D s->diag_alrt; + + INA238_UPD_FLAG(diag, latch, shunt_fresh, SHNTOL, shunt > (int16_t)s->= sovl); + INA238_UPD_FLAG(diag, latch, shunt_fresh, SHNTUL, shunt < (int16_t)s->= suvl); + INA238_UPD_FLAG(diag, latch, bus_fresh, BUSOL, + s->bus_reg > (s->bovl & INA238_BUS_LIMIT_MASK)); + INA238_UPD_FLAG(diag, latch, bus_fresh, BUSUL, + s->bus_reg < (s->buvl & INA238_BUS_LIMIT_MASK)); + INA238_UPD_FLAG(diag, latch, temp_fresh, TMPOL, temp > temp_lim); + INA238_UPD_FLAG(diag, latch, power_fresh, POL, + s->power_reg > ((uint32_t)s->pwr_limit << 8)); + + s->diag_alrt =3D diag; + + ina238_refresh_alert(s); +} + +static void ina238_convert(INA238State *s) +{ + uint8_t mode =3D FIELD_EX16(s->adc_config, INA238_ADC_CONFIG, MODE); + bool bus_en =3D mode & 0x1; + bool shunt_en =3D mode & 0x2; + bool temp_en =3D mode & 0x4; + bool adcrange =3D FIELD_EX16(s->config, INA238_CONFIG, ADCRANGE); + int shunt_lsb =3D adcrange ? INA238_SHUNT_LSB_NV_R1 : INA238_SHUNT_LSB= _NV_R0; + int64_t sr, br, tr, cur, pwr; + uint16_t mathof =3D 0; + bool power_fresh =3D bus_en; + + if (!bus_en && !shunt_en && !temp_en) { + return; + } + + if (shunt_en) { + sr =3D s->shunt_nv / shunt_lsb; + sr =3D MAX(INT16_MIN, MIN(INT16_MAX, sr)); + s->shunt_reg =3D (uint16_t)(int16_t)sr; + + if (s->shunt_cal =3D=3D 0) { + cur =3D 0; + } else { + cur =3D (int64_t)(int16_t)s->shunt_reg * INA238_CURRENT_K / + s->shunt_cal; + } + if (cur > INT16_MAX || cur < INT16_MIN) { + mathof =3D 1; + cur =3D MAX(INT16_MIN, MIN(INT16_MAX, cur)); + } + s->current_reg =3D (uint16_t)(int16_t)cur; + } + + if (bus_en) { + br =3D s->bus_uv / INA238_BUS_LSB_UV; + br =3D MAX(0, MIN(INT16_MAX, br)); + s->bus_reg =3D (uint16_t)br; + } + + if (temp_en) { + /* Die temperature: 12-bit signed value stored in bits [15:4] */ + tr =3D s->temp_mc / INA238_TEMP_LSB_MC; + tr =3D MAX(-2048, MIN(2047, tr)); + s->dietemp_reg =3D ((uint16_t)(int16_t)tr << 4) & INA238_TEMP_LIMI= T_MASK; + } + + /* + * In bus-only mode the current register is retained from the last shu= nt + * conversion rather than measured anew, but the power register is sti= ll + * refreshed. + */ + if (bus_en) { + cur =3D (int16_t)s->current_reg; + if (cur < 0) { + cur =3D -cur; + } + pwr =3D cur * (int64_t)s->bus_reg / INA238_POWER_DIV; + if (pwr > INA238_POWER_MAX) { + mathof =3D 1; + pwr =3D INA238_POWER_MAX; + } + s->power_reg =3D (uint32_t)pwr; + } + + /* Without a calibration the device reports neither current nor power.= */ + if (s->shunt_cal =3D=3D 0) { + s->current_reg =3D 0; + s->power_reg =3D 0; + power_fresh =3D true; + } + + s->diag_alrt =3D FIELD_DP16(s->diag_alrt, INA238_DIAG_ALRT, MATHOF, ma= thof); + s->diag_alrt =3D FIELD_DP16(s->diag_alrt, INA238_DIAG_ALRT, CNVRF, 1); + + trace_ina238_convert(s->description, s->shunt_reg, s->bus_reg, + s->dietemp_reg, s->current_reg, s->power_reg); + + ina238_update_alert(s, shunt_en, bus_en, temp_en, power_fresh); +} + +/* + * A physical input, the calibration or the ADC range changed. + * - in continuous mode the device keeps converting and immediately tracks + * the new value + * - in a triggered mode it performs exactly one conversion per trigger + */ +static void ina238_input_update(INA238State *s) +{ + if (FIELD_EX16(s->adc_config, INA238_ADC_CONFIG, MODE) & 0x8) { + ina238_convert(s); + } +} + +static void ina238_reset_regs(INA238State *s) +{ + s->config =3D INA238_CONFIG_POR; + s->adc_config =3D INA238_ADC_CONFIG_POR; + s->shunt_cal =3D INA238_SHUNT_CAL_POR; + s->diag_alrt =3D INA238_DIAG_ALRT_POR; + s->sovl =3D INA238_SOVL_POR; + s->suvl =3D INA238_SUVL_POR; + s->bovl =3D INA238_BOVL_POR; + s->buvl =3D INA238_BUVL_POR; + s->temp_limit =3D INA238_TEMP_LIMIT_POR; + s->pwr_limit =3D INA238_PWR_LIMIT_POR; + + s->ptr =3D 0; + s->len =3D 0; + s->wr_hi =3D 0; + s->rx_byte =3D 0; + s->rx_width =3D 0; + s->rx_val =3D 0; + + /* + * The measurement registers power up at zero and stay zero until the = next + * conversion. The injected physical inputs are retained, but no conve= rsion + * is performed here, so a software reset does not resurrect a previous + * measurement. + */ + s->shunt_reg =3D 0; + s->bus_reg =3D 0; + s->dietemp_reg =3D 0; + s->current_reg =3D 0; + s->power_reg =3D 0; + + ina238_update_alert(s, true, true, true, true); +} + +static uint32_t ina238_read_reg(INA238State *s, uint8_t reg) +{ + uint32_t val; + + switch (reg) { + case INA238_REG_CONFIG: + val =3D s->config; + break; + case INA238_REG_ADC_CONFIG: + val =3D s->adc_config; + break; + case INA238_REG_SHUNT_CAL: + val =3D s->shunt_cal; + break; + case INA238_REG_VSHUNT: + val =3D s->shunt_reg; + break; + case INA238_REG_VBUS: + val =3D s->bus_reg; + break; + case INA238_REG_DIETEMP: + val =3D s->dietemp_reg; + break; + case INA238_REG_CURRENT: + val =3D s->current_reg; + break; + case INA238_REG_POWER: + val =3D s->power_reg; + break; + case INA238_REG_DIAG_ALRT: + val =3D s->diag_alrt; + /* + * A read always clears CNVRF; the latched limit flags clear too, = but + * only in latch mode. + */ + s->diag_alrt &=3D ~R_INA238_DIAG_ALRT_CNVRF_MASK; + if (FIELD_EX16(s->diag_alrt, INA238_DIAG_ALRT, ALATCH)) { + s->diag_alrt &=3D ~INA238_DIAG_LATCH_MASK; + } + ina238_refresh_alert(s); + break; + case INA238_REG_SOVL: + val =3D s->sovl; + break; + case INA238_REG_SUVL: + val =3D s->suvl; + break; + case INA238_REG_BOVL: + val =3D s->bovl; + break; + case INA238_REG_BUVL: + val =3D s->buvl; + break; + case INA238_REG_TEMP_LIMIT: + val =3D s->temp_limit; + break; + case INA238_REG_PWR_LIMIT: + val =3D s->pwr_limit; + break; + case INA238_REG_MANUFACTURER_ID: + val =3D INA238_MANUFACTURER_ID_VAL; + break; + case INA238_REG_DEVICE_ID: + val =3D INA238_DEVICE_ID_VAL; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: read from undefined register 0x%02x\n", + __func__, s->description, reg); + val =3D 0; + break; + } + + trace_ina238_read(s->description, reg, val); + return val; +} + +static void ina238_write_reg(INA238State *s, uint8_t reg, uint16_t val) +{ + trace_ina238_write(s->description, reg, val); + + switch (reg) { + case INA238_REG_CONFIG: + if (val & R_INA238_CONFIG_RST_MASK) { + trace_ina238_reset(s->description, "reg"); + ina238_reset_regs(s); + break; + } + s->config =3D val & INA238_CONFIG_WMASK; + ina238_input_update(s); + break; + case INA238_REG_ADC_CONFIG: + s->adc_config =3D val; + /* Writing the MODE bits (re)starts a conversion: it is the trigge= r. */ + ina238_convert(s); + break; + case INA238_REG_SHUNT_CAL: + s->shunt_cal =3D val & INA238_SHUNT_CAL_MASK; + ina238_input_update(s); + break; + case INA238_REG_DIAG_ALRT: { + uint16_t status =3D s->diag_alrt & INA238_DIAG_STATUS_MASK; + /* + * In latch mode a write clears the latched limit flags and the + * conversion-ready flag. In transparent mode the flags track the = live + * condition and are preserved. The pin is only refreshed, so a cl= eared + * flag re-asserts on the next conversion rather than immediately. + */ + if (FIELD_EX16(s->diag_alrt, INA238_DIAG_ALRT, ALATCH)) { + status &=3D ~(R_INA238_DIAG_ALRT_CNVRF_MASK | INA238_DIAG_LATC= H_MASK); + } + s->diag_alrt =3D (val & INA238_DIAG_CTRL_MASK) | status; + ina238_refresh_alert(s); + break; + } + case INA238_REG_SOVL: + s->sovl =3D val; + ina238_update_alert(s, true, true, true, true); + break; + case INA238_REG_SUVL: + s->suvl =3D val; + ina238_update_alert(s, true, true, true, true); + break; + case INA238_REG_BOVL: + s->bovl =3D val & INA238_BUS_LIMIT_MASK; + ina238_update_alert(s, true, true, true, true); + break; + case INA238_REG_BUVL: + s->buvl =3D val & INA238_BUS_LIMIT_MASK; + ina238_update_alert(s, true, true, true, true); + break; + case INA238_REG_TEMP_LIMIT: + s->temp_limit =3D val & INA238_TEMP_LIMIT_MASK; + ina238_update_alert(s, true, true, true, true); + break; + case INA238_REG_PWR_LIMIT: + s->pwr_limit =3D val; + ina238_update_alert(s, true, true, true, true); + break; + case INA238_REG_VSHUNT: + case INA238_REG_VBUS: + case INA238_REG_DIETEMP: + case INA238_REG_CURRENT: + case INA238_REG_POWER: + case INA238_REG_MANUFACTURER_ID: + case INA238_REG_DEVICE_ID: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: write to read-only register 0x%02x\n", + __func__, s->description, reg); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: write to undefined register 0x%02x\n", + __func__, s->description, reg); + break; + } +} + +static uint8_t ina238_recv(I2CSlave *i2c) +{ + INA238State *s =3D INA238(i2c); + uint8_t byte; + + if (s->rx_byte =3D=3D 0) { + s->rx_val =3D ina238_read_reg(s, s->ptr); + s->rx_width =3D (s->ptr =3D=3D INA238_REG_POWER) ? 3 : 2; + } + + byte =3D (s->rx_val >> (8 * (s->rx_width - 1 - s->rx_byte))) & 0xff; + s->rx_byte++; + if (s->rx_byte >=3D s->rx_width) { + s->rx_byte =3D 0; + } + + return byte; +} + +static int ina238_send(I2CSlave *i2c, uint8_t data) +{ + INA238State *s =3D INA238(i2c); + + if (s->len =3D=3D 0) { + s->ptr =3D data; + } else if ((s->len & 1) =3D=3D 1) { + s->wr_hi =3D data; + } else { + ina238_write_reg(s, s->ptr, ((uint16_t)s->wr_hi << 8) | data); + } + s->len++; + + return 0; +} + +static int ina238_event(I2CSlave *i2c, enum i2c_event event) +{ + INA238State *s =3D INA238(i2c); + + s->len =3D 0; + s->rx_byte =3D 0; + + return 0; +} + +static void ina238_get_shunt(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA238State *s =3D INA238(obj); + int64_t value =3D s->shunt_nv; + + visit_type_int(v, name, &value, errp); +} + +static void ina238_set_shunt(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA238State *s =3D INA238(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < INA238_SHUNT_MIN_NV || value > INA238_SHUNT_MAX_NV) { + error_setg(errp, + "%s: shunt-voltage %" PRId64 " out of range (%d..%d nV)= ", + s->description, value, + INA238_SHUNT_MIN_NV, INA238_SHUNT_MAX_NV); + return; + } + + s->shunt_nv =3D (int32_t)value; + ina238_input_update(s); +} + +static void ina238_get_bus(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA238State *s =3D INA238(obj); + int64_t value =3D s->bus_uv; + + visit_type_int(v, name, &value, errp); +} + +static void ina238_set_bus(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA238State *s =3D INA238(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < 0 || value > INA238_BUS_MAX_UV) { + error_setg(errp, + "%s: bus-voltage %" PRId64 " out of range (0..%d uV)", + s->description, value, INA238_BUS_MAX_UV); + return; + } + + s->bus_uv =3D (uint32_t)value; + ina238_input_update(s); +} + +static void ina238_get_temp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA238State *s =3D INA238(obj); + int64_t value =3D s->temp_mc; + + visit_type_int(v, name, &value, errp); +} + +static void ina238_set_temp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + INA238State *s =3D INA238(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < INA238_TEMP_MIN_MC || value > INA238_TEMP_MAX_MC) { + error_setg(errp, + "%s: die-temperature %" PRId64 + " out of range (%d..%d m-degC)", + s->description, value, + INA238_TEMP_MIN_MC, INA238_TEMP_MAX_MC); + return; + } + + s->temp_mc =3D (int32_t)value; + ina238_input_update(s); +} + +static void ina238_reset_hold(Object *obj, ResetType type) +{ + INA238State *s =3D INA238(obj); + + trace_ina238_reset(s->description, "hw"); + ina238_reset_regs(s); +} + +static int ina238_post_load(void *opaque, int version_id) +{ + INA238State *s =3D opaque; + + ina238_refresh_alert(s); + + return 0; +} + +static const VMStateDescription ina238_vmstate =3D { + .name =3D "INA238", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D ina238_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(ptr, INA238State), + VMSTATE_UINT8(len, INA238State), + VMSTATE_UINT8(wr_hi, INA238State), + VMSTATE_UINT8(rx_byte, INA238State), + VMSTATE_UINT8(rx_width, INA238State), + VMSTATE_UINT32(rx_val, INA238State), + VMSTATE_UINT16(config, INA238State), + VMSTATE_UINT16(adc_config, INA238State), + VMSTATE_UINT16(shunt_cal, INA238State), + VMSTATE_UINT16(diag_alrt, INA238State), + VMSTATE_UINT16(sovl, INA238State), + VMSTATE_UINT16(suvl, INA238State), + VMSTATE_UINT16(bovl, INA238State), + VMSTATE_UINT16(buvl, INA238State), + VMSTATE_UINT16(temp_limit, INA238State), + VMSTATE_UINT16(pwr_limit, INA238State), + VMSTATE_UINT16(shunt_reg, INA238State), + VMSTATE_UINT16(bus_reg, INA238State), + VMSTATE_UINT16(dietemp_reg, INA238State), + VMSTATE_UINT16(current_reg, INA238State), + VMSTATE_UINT32(power_reg, INA238State), + VMSTATE_INT32(shunt_nv, INA238State), + VMSTATE_UINT32(bus_uv, INA238State), + VMSTATE_INT32(temp_mc, INA238State), + VMSTATE_I2C_SLAVE(parent_obj, INA238State), + VMSTATE_END_OF_LIST() + } +}; + +static void ina238_initfn(Object *obj) +{ + object_property_add(obj, "shunt-voltage", "int", ina238_get_shunt, + ina238_set_shunt, NULL, NULL); + object_property_set_description(obj, "shunt-voltage", + "Injected shunt (differential) voltage= , " + "in nanovolts"); + object_property_add(obj, "bus-voltage", "int", ina238_get_bus, + ina238_set_bus, NULL, NULL); + object_property_set_description(obj, "bus-voltage", + "Injected bus voltage, in microvolts"); + object_property_add(obj, "die-temperature", "int", ina238_get_temp, + ina238_set_temp, NULL, NULL); + object_property_set_description(obj, "die-temperature", + "Injected die temperature, " + "in millidegrees Celsius"); +} + +static void ina238_realize(DeviceState *dev, Error **errp) +{ + INA238State *s =3D INA238(dev); + + if (!s->description) { + s->description =3D g_strdup(object_get_typename(OBJECT(dev))); + } + + qdev_init_gpio_out(dev, &s->alert, 1); +} + +static const Property ina238_properties[] =3D { + DEFINE_PROP_STRING("description", INA238State, description), +}; + +static void ina238_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *ic =3D I2C_SLAVE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + ic->event =3D ina238_event; + ic->recv =3D ina238_recv; + ic->send =3D ina238_send; + dc->realize =3D ina238_realize; + rc->phases.hold =3D ina238_reset_hold; + dc->vmsd =3D &ina238_vmstate; + device_class_set_props(dc, ina238_properties); +} + +static const TypeInfo ina238_types[] =3D { + { + .name =3D TYPE_INA238, + .parent =3D TYPE_I2C_SLAVE, + .instance_init =3D ina238_initfn, + .instance_size =3D sizeof(INA238State), + .class_init =3D ina238_class_init, + }, +}; + +DEFINE_TYPES(ina238_types) diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index b81f001fdf..7e6fd64488 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -1,5 +1,6 @@ system_ss.add(when: 'CONFIG_ADC128D818', if_true: files('adc128d818.c')) system_ss.add(when: 'CONFIG_INA230', if_true: files('ina230.c')) +system_ss.add(when: 'CONFIG_INA238', if_true: files('ina238.c')) system_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) system_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) system_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c')) diff --git a/hw/sensor/trace-events b/hw/sensor/trace-events index f809b6b506..98158e37c6 100644 --- a/hw/sensor/trace-events +++ b/hw/sensor/trace-events @@ -15,6 +15,13 @@ ina230_convert(const char *id, uint16_t shunt, uint16_t = bus, uint16_t current, u ina230_alert(const char *id, bool level) "%s level %u" ina230_reset(const char *id, const char *source) "%s %s" =20 +# ina238.c +ina238_read(const char *id, uint8_t reg, uint32_t value) "%s reg 0x%02x va= l 0x%06x" +ina238_write(const char *id, uint8_t reg, uint16_t value) "%s reg 0x%02x v= al 0x%04x" +ina238_convert(const char *id, uint16_t shunt, uint16_t bus, uint16_t diet= emp, uint16_t current, uint32_t power) "%s shunt 0x%04x bus 0x%04x dietemp = 0x%04x current 0x%04x power 0x%06x" +ina238_alert(const char *id, bool level) "%s level %u" +ina238_reset(const char *id, const char *source) "%s %s" + # tmp105.c tmp105_read(uint8_t dev, uint8_t addr) "device: 0x%02x, addr: 0x%02x" tmp105_write(uint8_t dev, uint8_t addr) "device: 0x%02x, addr 0x%02x" diff --git a/include/hw/sensor/ina238.h b/include/hw/sensor/ina238.h new file mode 100644 index 0000000000..3bc3c02073 --- /dev/null +++ b/include/hw/sensor/ina238.h @@ -0,0 +1,14 @@ +/* + * Texas Instruments INA238 current/voltage/power monitor with I2C interfa= ce + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_SENSOR_INA238_H +#define HW_SENSOR_INA238_H + +#define TYPE_INA238 "ina238" + +#endif --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Cover the reset defaults, the software reset, and the Configuration register write mask. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 177 ++++++++++++++++++++++++++++++++++++++++++= ++++ tests/qtest/meson.build | 1 + 2 files changed, 178 insertions(+) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c new file mode 100644 index 0000000000..6e59ed30b5 --- /dev/null +++ b/tests/qtest/ina238-test.c @@ -0,0 +1,177 @@ +/* + * QTest testcase for the INA238 current/voltage/power monitor + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqos/i2c.h" +#include "libqos/qgraph.h" +#include "libqtest-single.h" +#include "qobject/qdict.h" + +#define INA238_TEST_ID "ina238-test" +#define INA238_TEST_ADDR 0x40 + +/* Register pointer addresses */ +#define REG_CONFIG 0x00 +#define REG_ADC_CONFIG 0x01 +#define REG_SHUNT_CAL 0x02 +#define REG_VSHUNT 0x04 +#define REG_VBUS 0x05 +#define REG_DIETEMP 0x06 +#define REG_CURRENT 0x07 +#define REG_POWER 0x08 +#define REG_DIAG_ALRT 0x0B +#define REG_SOVL 0x0C +#define REG_SUVL 0x0D +#define REG_BOVL 0x0E +#define REG_BUVL 0x0F +#define REG_TEMP_LIMIT 0x10 +#define REG_PWR_LIMIT 0x11 +#define REG_MANUFACTURER_ID 0x3E +#define REG_DEVICE_ID 0x3F + +/* Configuration register bits */ +#define CONFIG_RST 0x8000 +#define CONFIG_ADCRANGE 0x0010 + +/* DIAG_ALRT register bits */ +#define DIAG_MEMSTAT 0x0001 +#define DIAG_CNVRF 0x0002 +#define DIAG_POL 0x0004 +#define DIAG_BUSUL 0x0008 +#define DIAG_BUSOL 0x0010 +#define DIAG_SHNTUL 0x0020 +#define DIAG_SHNTOL 0x0040 +#define DIAG_TMPOL 0x0080 +#define DIAG_MATHOF 0x0200 +#define DIAG_APOL 0x1000 +#define DIAG_SLOWALERT 0x2000 +#define DIAG_CNVR 0x4000 +#define DIAG_ALATCH 0x8000 + +/* Reset values */ +#define CONFIG_POR 0x0000 +#define ADC_CONFIG_POR 0xFB68 +#define SHUNT_CAL_POR 0x1000 +#define DIAG_ALRT_POR 0x0001 +#define SOVL_POR 0x7FFF +#define SUVL_POR 0x8000 +#define BOVL_POR 0x7FFF +#define BUVL_POR 0x0000 +#define TEMP_LIMIT_POR 0x7FF0 +#define PWR_LIMIT_POR 0xFFFF +#define MANUFACTURER_ID_VAL 0x5449 +#define DEVICE_ID_VAL 0x2381 + +/* Read the 24-bit POWER register (MSB first) */ +static uint32_t i2c_get24(QI2CDevice *dev, uint8_t reg) +{ + uint8_t resp[3]; + + i2c_read_block(dev, reg, resp, sizeof(resp)); + return (resp[0] << 16) | (resp[1] << 8) | resp[2]; +} + +/* QMP helpers for injecting the physical inputs */ + +static void qmp_ina238_set(const char *property, int value) +{ + QDict *resp; + + resp =3D qmp("{ 'execute': 'qom-set', 'arguments':" + " { 'path': %s, 'property': %s, 'value': %d } }", + INA238_TEST_ID, property, value); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); +} + +/* Power-on-reset default values and the ID registers */ +static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_POR); + g_assert_cmphex(i2c_get16(dev, REG_ADC_CONFIG), =3D=3D, ADC_CONFIG_POR= ); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT_CAL), =3D=3D, SHUNT_CAL_POR); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get24(dev, REG_POWER), =3D=3D, 0x000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT), =3D=3D, DIAG_ALRT_POR); + g_assert_cmphex(i2c_get16(dev, REG_SOVL), =3D=3D, SOVL_POR); + g_assert_cmphex(i2c_get16(dev, REG_SUVL), =3D=3D, SUVL_POR); + g_assert_cmphex(i2c_get16(dev, REG_BOVL), =3D=3D, BOVL_POR); + g_assert_cmphex(i2c_get16(dev, REG_BUVL), =3D=3D, BUVL_POR); + g_assert_cmphex(i2c_get16(dev, REG_TEMP_LIMIT), =3D=3D, TEMP_LIMIT_POR= ); + g_assert_cmphex(i2c_get16(dev, REG_PWR_LIMIT), =3D=3D, PWR_LIMIT_POR); + g_assert_cmphex(i2c_get16(dev, REG_MANUFACTURER_ID), =3D=3D, + MANUFACTURER_ID_VAL); + g_assert_cmphex(i2c_get16(dev, REG_DEVICE_ID), =3D=3D, DEVICE_ID_VAL); +} + +/* Software reset via the Configuration RST bit */ +static void test_soft_reset(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_SHUNT_CAL, 0x1234); + i2c_set16(dev, REG_SOVL, 0x0500); + i2c_set16(dev, REG_TEMP_LIMIT, 0x0A00); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + qmp_ina238_set("die-temperature", 25000); + + g_assert_cmphex(i2c_get16(dev, REG_SHUNT_CAL), =3D=3D, 0x1234); + g_assert_cmphex(i2c_get16(dev, REG_SOVL), =3D=3D, 0x0500); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x4BF0); + g_assert_cmpuint(i2c_get16(dev, REG_CURRENT), !=3D, 0); + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_POR); + g_assert_cmphex(i2c_get16(dev, REG_SHUNT_CAL), =3D=3D, SHUNT_CAL_POR); + g_assert_cmphex(i2c_get16(dev, REG_SOVL), =3D=3D, SOVL_POR); + g_assert_cmphex(i2c_get16(dev, REG_TEMP_LIMIT), =3D=3D, TEMP_LIMIT_POR= ); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT), =3D=3D, DIAG_ALRT_POR); + + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmpuint(i2c_get24(dev, REG_POWER), =3D=3D, 0); +} + +/* CONFIG keeps only the writable ADCRANGE/CONVDLY bits and self-clears RS= T */ +static void test_config_wmask(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_ADCRANGE | 0x0040); + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_ADCRANGE | = 0x0040); + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_POR); +} + +static void ina238_register_nodes(void) +{ + QOSGraphEdgeOptions opts =3D { + .extra_device_opts =3D "id=3D" INA238_TEST_ID ",address=3D0x40" + }; + add_qi2c_address(&opts, &(QI2CAddress) { INA238_TEST_ADDR }); + + qos_node_create_driver("ina238", i2c_device_create); + qos_node_consumes("ina238", "i2c-bus", &opts); + + qos_add_test("defaults", "ina238", test_defaults, NULL); + qos_add_test("soft-reset", "ina238", test_soft_reset, NULL); + qos_add_test("config-wmask", "ina238", test_config_wmask, NULL); +} +libqos_init(ina238_register_nodes); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e413a0cc75..7005509d4d 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -331,6 +331,7 @@ qos_test_ss.add( 'eepro100-test.c', 'es1370-test.c', 'ina230-test.c', + 'ina238-test.c', 'lsm303dlhc-mag-test.c', 'isl_pmbus_vr-test.c', 'max34451-test.c', --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060498; cv=none; d=zohomail.com; s=zohoarc; b=Hq744mg119ZwiEMpJJFP4DDRh4yHLyX62cIR5eGYFGD+Ls7zTJeMsQE0owyTiSr27gRXby5YyOYmWHaXzPmZY16z+BG4Zh4MMsRzGdfbSVVyk7qfQaeNJQNnlW7FKfPfv5XCdoT1PFMmmO1n4S4RVX3LrpQYm5THYyMk1JTXg6g= ARC-Message-Signature: i=1; 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 156 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 156 insertions(+) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c index 6e59ed30b5..693139f988 100644 --- a/tests/qtest/ina238-test.c +++ b/tests/qtest/ina238-test.c @@ -89,6 +89,20 @@ static void qmp_ina238_set(const char *property, int val= ue) qobject_unref(resp); } =20 +static int qmp_ina238_get(const char *property) +{ + QDict *resp; + int ret; + + resp =3D qmp("{ 'execute': 'qom-get', 'arguments':" + " { 'path': %s, 'property': %s } }", + INA238_TEST_ID, property); + g_assert(qdict_haskey(resp, "return")); + ret =3D qdict_get_int(resp, "return"); + qobject_unref(resp); + return ret; +} + /* Power-on-reset default values and the ID registers */ static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) { @@ -160,6 +174,139 @@ static void test_config_wmask(void *obj, void *data, = QGuestAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_CONFIG), =3D=3D, CONFIG_POR); } =20 +/* Shunt voltage register */ +static void test_shunt_injection(void *obj, void *data, QGuestAllocator *a= lloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x4BF0); + + qmp_ina238_set("shunt-voltage", -80000000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0xC180); + + g_assert_cmpint(qmp_ina238_get("shunt-voltage"), =3D=3D, -80000000); +} + +/* Bus voltage register */ +static void test_bus_injection(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("bus-voltage", 48000000); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x3C00); + + qmp_ina238_set("bus-voltage", 12000000); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x0F00); +} + +/* Die temperature register */ +static void test_temp_injection(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("die-temperature", 25000); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0x0C80); + + qmp_ina238_set("die-temperature", -25000); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0xF380); + + g_assert_cmpint(qmp_ina238_get("die-temperature"), =3D=3D, -25000); +} + +/* Calibration-derived current */ +static void test_calibration_current(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + qmp_ina238_set("shunt-voltage", 97200000); + + i2c_set16(dev, REG_SHUNT_CAL, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + + i2c_set16(dev, REG_SHUNT_CAL, 0x0FD2); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x4CCC); +} + +/* Calibration-derived power */ +static void test_power(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + i2c_set16(dev, REG_SHUNT_CAL, 0x0FD2); + + g_assert_cmpuint(i2c_get24(dev, REG_POWER), =3D=3D, 4718400); +} + +/* With SHUNT_CAL =3D=3D 0 the current and power registers stay zero */ +static void test_zero_cal(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SHUNT_CAL, 0x0000); + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmpuint(i2c_get24(dev, REG_POWER), =3D=3D, 0); +} + +/* ADCRANGE changes the shunt LSB, not the current divisor. */ +static void test_adcrange(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0FA0); + + i2c_set16(dev, REG_SHUNT_CAL, 0x0800); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x1F40); + + i2c_set16(dev, REG_CONFIG, CONFIG_ADCRANGE); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x3E80); + + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x7D00); + + i2c_set16(dev, REG_SHUNT_CAL, 0x2000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x1F40); +} + +/* Clamping at full scale and the MATHOF flag */ +static void test_overflow(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + i2c_set16(dev, REG_CONFIG, CONFIG_ADCRANGE); + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x7FFF); + qmp_ina238_set("shunt-voltage", -97200000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x8000); + + i2c_set16(dev, REG_CONFIG, CONFIG_POR); + qmp_ina238_set("shunt-voltage", 163835000); + i2c_set16(dev, REG_SHUNT_CAL, 0x0001); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x7FFF); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_MATHOF, =3D=3D, + DIAG_MATHOF); +} + +/* Shunt over-limit alert (transparent mode) */ static void ina238_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -173,5 +320,14 @@ static void ina238_register_nodes(void) qos_add_test("defaults", "ina238", test_defaults, NULL); qos_add_test("soft-reset", "ina238", test_soft_reset, NULL); qos_add_test("config-wmask", "ina238", test_config_wmask, NULL); + qos_add_test("shunt-injection", "ina238", test_shunt_injection, NULL); + qos_add_test("bus-injection", "ina238", test_bus_injection, NULL); + qos_add_test("temp-injection", "ina238", test_temp_injection, NULL); + qos_add_test("calibration-current", "ina238", test_calibration_current, + NULL); + qos_add_test("power", "ina238", test_power, NULL); + qos_add_test("zero-cal", "ina238", test_zero_cal, NULL); + qos_add_test("adcrange", "ina238", test_adcrange, NULL); + qos_add_test("overflow", "ina238", test_overflow, NULL); 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd99faf3sm59782235e9.14.2026.10.15.03.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:29:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792060145; x=1792664945; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=dLcH89Q+3v52wJ3aHqyuR198A/y0zPJ5UzMGy5C22Zs=; b=rlFTzbjJ63C7I+AqONAVNyu4XgX0xGQKhc5uwdpu8WjneaGAfdmqavmRlDSLQZ3VTE 4c3uCQUjNS9/bS2cpmUpTk3UefzwO9qxWhjeoruziQhFlXIf5ZUFZiHOPZyxXvrTlUT/ gi5mNO8LTnZEvgvfJHT5Mfg34TEzRL/V3/9bw0a3L9R7VATocRpkK2v9fiJqMyMabptR PlPonxy71Ee97dgaF45Hmo997fKmZVpok8SJtAcwe0TASweNUl1jFGJYdgYOqcDA+JPO KkeNr8KXK3Tzd9C63qBPkRGEMEpDz/MNUIEQTcemZOnRtW573+M4b04CiiDF//F74Tq4 atqA== X-Gm-Message-State: AFq9FYKGMw2VSj4AVVvMKgjl4YpT41M+PFSlm5pfSqR/5TcQFSDGMX/w LvVlpN4B/fw8XWClPCdinKT2baxWDyKPOm0xrTBgWHUcQKysK72q4JP0009EIg== X-Gm-Gg: AYBFou1CK5nRK7mizSeQaqa1uvEPdDZQRZWdf4RLn3PW6c02DGAnmFNieIMJ0kDNZ1K tWuk3jD8Qn9BNNydjCuU+rhTKsZsiYYzC4bFNDV0vs3OWPunpPj5DmufAh+vYdJNf0bp3Lnfhu5 K2t55MZNbv45CrATnc7pjJR3NIDg4d/fmrzvydUxyd9AIGl6xm0qFBqZzK3hyt6tdSnDHah/an+ MP2jbXYQ8mg14/fY7nYrJAIyKT1gUB4KDGdDtDZ6puU/xM0v7JxcBz1/gMdoVk/f1+Gyg6152M8 SpXHrtjkF8icFZi9JK7ffx8HGeOGYI+oHDa2aTnsX7FPzBa1clb1jmBP90GbCK1646PlwksHku3 cUBJy7nVxNy2HEJ+qgCjTgs3yMX20B6bUVH6fsYOkXhNguAHWGma4lBMr2oQvn9Ctxs1bT7RZ7+ A+i3xVQ6pFZF5VlcBQRVgaL8VGbxQdSLs3jKLB+lFl8TsPUgFT4+hBoTD+hk3jpfI1GN7SjLCqC cNhR+SMNIbgGqNuiWQvdG4+vs2XWwSelh537MOhLg0HCxV2l7kggGdD X-Received: by 2002:a05:600c:6099:b0:4a0:1feb:de6a with SMTP id 5b1f17b1804b1-4a18e4e7a85mr354418085e9.30.1792060144602; Thu, 15 Oct 2026 03:29:04 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:30 +0200 Subject: [PATCH v3 43/50] tests/qtest: ina238: cover the ALERT path and conversion-ready flag MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-43-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , Glenn Miles X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056477; l=6719; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=ZC7CGjlcMtlHZ+/DXyYJ8lCNdfyQ5Stw/MJqODCAIbA=; b=rHpH4ya7Z9w2z+fyQEoQ6nfz3frhkTmVGa5QBucqGTtLqr+IurQIm8yf67taqNv7yLKf/d2eL Zo+T01lYxI7C5uurS0s/S3I3Uo6/yW27PBDpRv6G9BnnB5RJOHu9if4 X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.47; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f47.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060408617158500 Cover the shunt/bus/temperature/power alert thresholds, the multi-alert OR behaviour, the alert latch, the DIAG_ALRT control bits and the conversion-ready (CNVRF) flag. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 146 ++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 145 insertions(+), 1 deletion(-) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c index 693139f988..08813377c9 100644 --- a/tests/qtest/ina238-test.c +++ b/tests/qtest/ina238-test.c @@ -306,7 +306,143 @@ static void test_overflow(void *obj, void *data, QGue= stAllocator *alloc) DIAG_MATHOF); } =20 -/* Shunt over-limit alert (transparent mode) */ +/* Shunt over-limit alert */ +static void test_alert_shunt(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + + qmp_ina238_set("shunt-voltage", 5000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); + + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + qmp_ina238_set("shunt-voltage", 5000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); +} + +/* Bus over-limit alert */ +static void test_alert_bus(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_BOVL, 0x1000); + + qmp_ina238_set("bus-voltage", 12000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_BUSOL, =3D=3D, 0); + + qmp_ina238_set("bus-voltage", 48000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_BUSOL, =3D=3D, DI= AG_BUSOL); +} + +/* Over-temperature alert */ +static void test_alert_temp(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_TEMP_LIMIT, 0x0A00); + + qmp_ina238_set("die-temperature", 10000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_TMPOL, =3D=3D, 0); + + qmp_ina238_set("die-temperature", 25000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_TMPOL, =3D=3D, DI= AG_TMPOL); +} + +/* Power over-limit alert */ +static void test_alert_power(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + i2c_set16(dev, REG_SHUNT_CAL, 0x0FD2); + + i2c_set16(dev, REG_PWR_LIMIT, 0x0100); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_POL, =3D=3D, DIAG= _POL); + + i2c_set16(dev, REG_PWR_LIMIT, 0x7FFF); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_POL, =3D=3D, 0); +} + +/* Two thresholds crossed at once are reported simultaneously (multi-alert= ) */ +static void test_alert_multi(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t diag; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + i2c_set16(dev, REG_BOVL, 0x1000); + + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + + diag =3D i2c_get16(dev, REG_DIAG_ALRT); + g_assert_cmphex(diag & DIAG_SHNTOL, =3D=3D, DIAG_SHNTOL); + g_assert_cmphex(diag & DIAG_BUSOL, =3D=3D, DIAG_BUSOL); +} + +/* Latch mode holds the flag until the DIAG_ALRT register is read */ +static void test_alert_latch(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("shunt-voltage", 5000000); + + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); +} + +/* DIAG_ALRT control bits are writable; status bits are read-only */ +static void test_diag_control(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t diag; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + i2c_set16(dev, REG_DIAG_ALRT, + DIAG_ALATCH | DIAG_CNVR | DIAG_SLOWALERT | DIAG_APOL); + diag =3D i2c_get16(dev, REG_DIAG_ALRT); + g_assert_cmphex(diag & DIAG_ALATCH, =3D=3D, DIAG_ALATCH); + g_assert_cmphex(diag & DIAG_CNVR, =3D=3D, DIAG_CNVR); + g_assert_cmphex(diag & DIAG_SLOWALERT, =3D=3D, DIAG_SLOWALERT); + g_assert_cmphex(diag & DIAG_APOL, =3D=3D, DIAG_APOL); + /* MEMSTAT stays set */ + g_assert_cmphex(diag & DIAG_MEMSTAT, =3D=3D, DIAG_MEMSTAT); +} + +/* Every DIAG_ALRT read clears CNVRF, whatever the alert-latch mode. */ +static void test_cnvrf(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + qmp_ina238_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, DI= AG_CNVRF); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, 0); + + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + qmp_ina238_set("shunt-voltage", 20000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, DI= AG_CNVRF); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, 0); +} + static void ina238_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -329,5 +465,13 @@ static void ina238_register_nodes(void) qos_add_test("zero-cal", "ina238", test_zero_cal, NULL); qos_add_test("adcrange", "ina238", test_adcrange, NULL); qos_add_test("overflow", "ina238", test_overflow, NULL); + qos_add_test("alert-shunt", "ina238", test_alert_shunt, NULL); + qos_add_test("alert-bus", "ina238", test_alert_bus, NULL); + qos_add_test("alert-temp", "ina238", test_alert_temp, NULL); + qos_add_test("alert-power", "ina238", test_alert_power, NULL); + qos_add_test("alert-multi", "ina238", test_alert_multi, NULL); + qos_add_test("alert-latch", "ina238", test_alert_latch, NULL); + qos_add_test("diag-control", "ina238", test_diag_control, NULL); + qos_add_test("cnvrf", "ina238", test_cnvrf, NULL); } libqos_init(ina238_register_nodes); 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 84 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 84 insertions(+) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c index 08813377c9..74912424c0 100644 --- a/tests/qtest/ina238-test.c +++ b/tests/qtest/ina238-test.c @@ -67,6 +67,13 @@ #define MANUFACTURER_ID_VAL 0x5449 #define DEVICE_ID_VAL 0x2381 =20 +/* Injection-property limits (see ina238.c) */ +#define SHUNT_MIN_NV (-163840000) /* -32768 * 5 uV */ +#define SHUNT_MAX_NV 163835000 /* 32767 * 5 uV */ +#define BUS_MAX_UV 85000000 /* 27200 * 3.125 mV */ +#define TEMP_MIN_MC (-40000) /* -320 * 125 m-degC */ +#define TEMP_MAX_MC 125000 /* 1000 * 125 m-degC */ + /* Read the 24-bit POWER register (MSB first) */ static uint32_t i2c_get24(QI2CDevice *dev, uint8_t reg) { @@ -103,6 +110,18 @@ static int qmp_ina238_get(const char *property) return ret; } =20 +/* A qom-set expected to be rejected (value outside the supported range) */ +static void qmp_ina238_set_fail(const char *property, int64_t value) +{ + QDict *resp; + + resp =3D qmp("{ 'execute': 'qom-set', 'arguments':" + " { 'path': %s, 'property': %s, 'value': %lld } }", + INA238_TEST_ID, property, (long long)value); + g_assert(qdict_haskey(resp, "error")); + qobject_unref(resp); +} + /* Power-on-reset default values and the ID registers */ static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) { @@ -443,6 +462,68 @@ static void test_cnvrf(void *obj, void *data, QGuestAl= locator *alloc) g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, 0); } =20 +/* Shunt-voltage injection limits */ +static void test_shunt_limits(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("shunt-voltage", SHUNT_MAX_NV); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x7FFF); + g_assert_cmpint(qmp_ina238_get("shunt-voltage"), =3D=3D, SHUNT_MAX_NV); + + qmp_ina238_set("shunt-voltage", SHUNT_MIN_NV); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x8000); + g_assert_cmpint(qmp_ina238_get("shunt-voltage"), =3D=3D, SHUNT_MIN_NV); + + qmp_ina238_set_fail("shunt-voltage", (int64_t)SHUNT_MAX_NV + 1); + qmp_ina238_set_fail("shunt-voltage", (int64_t)SHUNT_MIN_NV - 1); + g_assert_cmpint(qmp_ina238_get("shunt-voltage"), =3D=3D, SHUNT_MIN_NV); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x8000); +} + +/* Bus-voltage injection limits */ +static void test_bus_limits(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("bus-voltage", 0); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x0000); + + qmp_ina238_set("bus-voltage", BUS_MAX_UV); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x6A40); + g_assert_cmpint(qmp_ina238_get("bus-voltage"), =3D=3D, BUS_MAX_UV); + + qmp_ina238_set_fail("bus-voltage", (int64_t)BUS_MAX_UV + 1); + qmp_ina238_set_fail("bus-voltage", -1); + g_assert_cmpint(qmp_ina238_get("bus-voltage"), =3D=3D, BUS_MAX_UV); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x6A40); +} + +/* Die-temperature injection limits */ +static void test_temp_limits(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + + qmp_ina238_set("die-temperature", TEMP_MAX_MC); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0x3E80); + g_assert_cmpint(qmp_ina238_get("die-temperature"), =3D=3D, TEMP_MAX_MC= ); + + qmp_ina238_set("die-temperature", TEMP_MIN_MC); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0xEC00); + g_assert_cmpint(qmp_ina238_get("die-temperature"), =3D=3D, TEMP_MIN_MC= ); + + qmp_ina238_set_fail("die-temperature", (int64_t)TEMP_MAX_MC + 1); + qmp_ina238_set_fail("die-temperature", (int64_t)TEMP_MIN_MC - 1); + g_assert_cmpint(qmp_ina238_get("die-temperature"), =3D=3D, TEMP_MIN_MC= ); + g_assert_cmphex(i2c_get16(dev, REG_DIETEMP), =3D=3D, 0xEC00); +} + static void ina238_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -459,6 +540,9 @@ static void ina238_register_nodes(void) qos_add_test("shunt-injection", "ina238", test_shunt_injection, NULL); qos_add_test("bus-injection", "ina238", test_bus_injection, NULL); qos_add_test("temp-injection", "ina238", test_temp_injection, NULL); + qos_add_test("shunt-limits", "ina238", test_shunt_limits, NULL); + qos_add_test("bus-limits", "ina238", test_bus_limits, NULL); + qos_add_test("temp-limits", "ina238", test_temp_limits, NULL); qos_add_test("calibration-current", "ina238", test_calibration_current, NULL); qos_add_test("power", "ina238", test_power, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060605; cv=none; d=zohomail.com; s=zohoarc; b=jJTRqJAAEGBHQyCvTD6erEbmfmNTp41AHiP2Oxmhz1dRh0kLZ21maXvyCVVHVc2eD+9aSIVJBT5bXgS33QLOJulrwtocz/zSFTcNKY7gj1w+BauxfgTciod7SBA5hLERD48Ea3DNFJX9up8hGFj3NOcDcqxF6yArPe43AuUQqLo= ARC-Message-Signature: i=1; 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 70 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c index 74912424c0..fb7bcc265c 100644 --- a/tests/qtest/ina238-test.c +++ b/tests/qtest/ina238-test.c @@ -304,6 +304,73 @@ static void test_adcrange(void *obj, void *data, QGues= tAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x1F40); } =20 +/* Shutdown converts nothing: registers are held, CNVRF stays clear. */ +static void test_mode_shutdown(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SHUNT_CAL, 0x1000); + qmp_ina238_set("shunt-voltage", 20000000); + qmp_ina238_set("bus-voltage", 12000000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0FA0); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x0F00); + + /* Clear CNVRF, then enter shutdown (MODE =3D 0). */ + (void)i2c_get16(dev, REG_DIAG_ALRT); + i2c_set16(dev, REG_ADC_CONFIG, 0x0000); + + /* Injecting while shut down performs no conversion: registers are hel= d. */ + qmp_ina238_set("shunt-voltage", 40000000); + qmp_ina238_set("bus-voltage", 24000000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0FA0); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x0F00); + + /* No conversion completed, so CNVRF stays clear. */ + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, 0); +} + +/* Triggered modes convert once per ADC_CONFIG write. */ +static void test_mode_triggered(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SHUNT_CAL, 0x1000); + qmp_ina238_set("shunt-voltage", 20000000); + + /* Enter triggered bus+shunt+temp mode: one conversion. */ + i2c_set16(dev, REG_ADC_CONFIG, 0x7000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0FA0); + + /* A new input does not convert until the next trigger. */ + qmp_ina238_set("shunt-voltage", 40000000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0FA0); + + /* Re-triggering with another ADC_CONFIG write samples the new input. = */ + i2c_set16(dev, REG_ADC_CONFIG, 0x7000); + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x1F40); +} + +/* A bus-only mode refreshes the bus register alone; the rest are held. */ +static void test_mode_channels(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SHUNT_CAL, 0x1000); + qmp_ina238_set("shunt-voltage", 20000000); + qmp_ina238_set("bus-voltage", 12000000); + + /* Continuous bus-only mode. */ + i2c_set16(dev, REG_ADC_CONFIG, 0x9000); + qmp_ina238_set("shunt-voltage", 40000000); + qmp_ina238_set("bus-voltage", 24000000); + + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x0FA0); + g_assert_cmphex(i2c_get16(dev, REG_VBUS), =3D=3D, 0x1E00); +} + /* Clamping at full scale and the MATHOF flag */ static void test_overflow(void *obj, void *data, QGuestAllocator *alloc) { @@ -548,6 +615,9 @@ static void ina238_register_nodes(void) qos_add_test("power", "ina238", test_power, NULL); qos_add_test("zero-cal", "ina238", test_zero_cal, NULL); qos_add_test("adcrange", "ina238", test_adcrange, NULL); + qos_add_test("mode-shutdown", "ina238", test_mode_shutdown, NULL); + qos_add_test("mode-triggered", "ina238", test_mode_triggered, NULL); + qos_add_test("mode-channels", "ina238", test_mode_channels, NULL); qos_add_test("overflow", "ina238", test_overflow, NULL); qos_add_test("alert-shunt", "ina238", test_alert_shunt, NULL); qos_add_test("alert-bus", "ina238", test_alert_bus, NULL); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060633; cv=none; d=zohomail.com; s=zohoarc; b=Egf7+eMi64UB8P5hyeZSZzPyhXWItNQbqFvlQv+b2656djQ3GWK68TvDTs6OhqONHeE1i2V+nPYDnsV6S54foEeABoCUl7rLOOksdL8eFmlYqeAtJVOt4jhlyOlaeFH+cuz6KShW8/6IdpJqWY9DZ9PeNT77+5BXrGNkPUCWv+Y= ARC-Message-Signature: i=1; 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[89.93.216.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd97ed6asm60537935e9.6.2026.10.15.03.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 03:29:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792060164; x=1792664964; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=c6Lwpzu4bQyFqEheBTwdIlkXZjUIiiE3va3aldXb5fM=; b=MCa5fEtzDq37xOMUhnO25/DrFRIkZYqM63eQQb8MoCRWpV3QUclQN2NSD/G1/3YLQC ZCJxxFPADeCoNYqvqOJZkhRoh0Lhc/LgPIru1eqVRmapyWycWrOO8tI68KZxyHsxNTaI 5hVTYQt+z5Cx9fwm7ii5qmRcyeGylM69jAIXUJSW4clB3QnzGHkARQg8TARHi19B0Alt qjUNB4A6Lp94JimgRhr/Z8scttXxdYIhQ6SMBjcSrYaZmW1Q1Obn5o6BQqPKepmfBqtU 8rIPHiJ/AxM1DiHfbSwxFnf3WH6HurtxWdSgvmNXgwxHejfVTS5JVIW5tqIZX2Vaa/HZ m0mA== X-Gm-Message-State: AFq9FYKQvk7YIMaVC3I9Kme2j4lYuFK2n6sCdwSNFQWZtBzRH9M8j8r1 6Uqo7ERkWBIJaZAlA/+qNNgx/7D9784i3RhcMK4dRaDnrXNljscNG9oXbvIX8Q== X-Gm-Gg: AYBFou0gtcGBNauZ0bRY8WQ+eBtFYcm3NGooYAxbnEOye961AP2mmmLkdb7mBaRdsK9 rq6eYXLLIM95UWO07jebMepiejJqlE39fOjesDfq7rfZ57In0DNUG/J4ayEKzWujNq5TivE+faT kYpfkZCCFvbHNGUf4EEtOGS1eN3ybbbUOgujJcYuZzpMzZZs6DVozR5OeX9Qp62icMgtYFfSSdO XHFEXFvajWWtc2WBouCQeZegiWT+Lws6maL7PL8zfvqbnOL6TM52tFHIV3JZlBuoXng+0dYHnDe LU+eT3UIbEb9jSIbaWQmVDujKZ69ZsSk0CbwKP5WPYnmZuDUTdq+1hDGOeXGSIMVHpSPxAiWN/Q SzteXlZox6233HG9qb47Bv5RVy9Wsg9IE6eI+pjrTlksvg3Oi7pfOOYaVtXr1i2LCyACbeHD5Ly 7RRSvcmIukANzo7TZod6oDNG2GEeHBp8Osh03Mbt9uKkLS+xhSmZ6NGb62aq/maoo42WNmrSbpI +zeq0xNhOACQNtv42SFrlE9EvHe6s7VjtorYjOZtGFHYg== X-Received: by 2002:a05:600c:1909:b0:4a1:722a:d2a3 with SMTP id 5b1f17b1804b1-4a18e4a3f5amr413285845e9.23.1792060163587; Thu, 15 Oct 2026 03:29:23 -0700 (PDT) Date: Thu, 15 Oct 2026 11:28:33 +0200 Subject: [PATCH v3 46/50] tests/qtest: ina238: cover conversion-ready and alert-latch semantics MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261015-bmc-minerva-v3-46-7d50c8a108e5@free.fr> References: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> In-Reply-To: <20261015-bmc-minerva-v3-0-7d50c8a108e5@free.fr> To: qemu-devel@nongnu.org Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , qemu-arm@nongnu.org, Patrick Leis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Emmanuel Blot , Glenn Miles X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792056477; l=6851; i=emmanuel.blot@free.fr; s=20260602; h=from:subject:message-id; bh=RdMmfGACFu+w8i2ytQE/+wzOyY16K5WkLJ6oJOceA5s=; b=ve2uV7WG0dY71mw/JESMZcvZHEfWsfc6Do7QWfX3cZuOjB3b31ZI/QO5FlSbW7XYCMFsaEA8k MEI7OoqMYQ5AXdZLNeMHkhqZ2QHHe7Hq10BhRBervDSBis/BlyIuAsK X-Developer-Key: i=emmanuel.blot@free.fr; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=209.85.128.47; envelope-from=eblot.ml@gmail.com; helo=mail-wm1-f47.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Emmanuel Blot From: Emmanuel Blot via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1792060634879158500 Add coverage for the DIAG_ALRT flag-clearing rules: which of a read and a write clears CNVRF and the limit flags in each alert mode, and that a conversion only re-evaluates the flags of the channels it converted. Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 127 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c index fb7bcc265c..e7dd50a822 100644 --- a/tests/qtest/ina238-test.c +++ b/tests/qtest/ina238-test.c @@ -494,6 +494,106 @@ static void test_alert_latch(void *obj, void *data, Q= GuestAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); } =20 +/* In latch mode a read releases the flag even while the fault persists. */ +static void test_alert_latch_persist(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + + qmp_ina238_set("shunt-voltage", 97200000); + + /* First read shows the latched flag and clears it */ + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + /* Fault still present but no new conversion: the flag stays cleared */ + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); + + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); +} + +/* + * In transparent mode a limit flag follows the live condition: a read lea= ves + * it set while the fault persists. + */ +static void test_alert_transparent_persist(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + /* Repeated reads do not clear the flag while the fault is still prese= nt. */ + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + /* A conversion with the fault gone clears it. */ + qmp_ina238_set("shunt-voltage", 5000000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); +} + +/* A DIAG_ALRT write releases a latched limit flag as a read does. */ +static void test_alert_latch_write_clears(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + /* The read above cleared it; re-latch it with another conversion. */ + qmp_ina238_set("shunt-voltage", 97200000); + + /* A write (keeping latch mode) clears the flag while the fault persis= ts. */ + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); + + /* The next conversion re-asserts the still-present fault. */ + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); +} + +/* + * A conversion only re-evaluates the flags of the channels it converted: = the + * shunt register a bus-only conversion left stale must not resurrect one. + */ +static void test_alert_channel(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SOVL, 0x1000); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + + qmp_ina238_set("shunt-voltage", 97200000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, + DIAG_SHNTOL); + + /* Continuous bus-only mode */ + i2c_set16(dev, REG_ADC_CONFIG, 0x9000); + qmp_ina238_set("bus-voltage", 12000000); + + g_assert_cmphex(i2c_get16(dev, REG_VSHUNT), =3D=3D, 0x4BF0); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_SHNTOL, =3D=3D, 0= ); +} + /* DIAG_ALRT control bits are writable; status bits are read-only */ static void test_diag_control(void *obj, void *data, QGuestAllocator *allo= c) { @@ -529,6 +629,25 @@ static void test_cnvrf(void *obj, void *data, QGuestAl= locator *alloc) g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, 0); } =20 +/* A DIAG_ALRT write clears CNVRF only in latch mode. */ +static void test_cnvrf_write(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + /* Latch mode: a write clears CNVRF. */ + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + qmp_ina238_set("shunt-voltage", 20000000); + i2c_set16(dev, REG_DIAG_ALRT, DIAG_ALATCH); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, 0); + + /* Transparent mode: a write does not clear CNVRF. */ + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + qmp_ina238_set("shunt-voltage", 20000000); + i2c_set16(dev, REG_DIAG_ALRT, 0x0000); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_CNVRF, =3D=3D, DI= AG_CNVRF); +} + /* Shunt-voltage injection limits */ static void test_shunt_limits(void *obj, void *data, QGuestAllocator *allo= c) { @@ -625,7 +744,15 @@ static void ina238_register_nodes(void) qos_add_test("alert-power", "ina238", test_alert_power, NULL); qos_add_test("alert-multi", "ina238", test_alert_multi, NULL); qos_add_test("alert-latch", "ina238", test_alert_latch, NULL); + qos_add_test("alert-latch-persist", "ina238", test_alert_latch_persist, + NULL); + qos_add_test("alert-transparent-persist", "ina238", + test_alert_transparent_persist, NULL); + qos_add_test("alert-latch-write-clears", "ina238", + test_alert_latch_write_clears, NULL); + qos_add_test("alert-channel", "ina238", test_alert_channel, NULL); qos_add_test("diag-control", "ina238", test_diag_control, NULL); qos_add_test("cnvrf", "ina238", test_cnvrf, NULL); + qos_add_test("cnvrf-write", "ina238", test_cnvrf_write, NULL); } libqos_init(ina238_register_nodes); --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Reviewed-by: Glenn Miles Signed-off-by: Emmanuel Blot --- tests/qtest/ina238-test.c | 48 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 48 insertions(+) diff --git a/tests/qtest/ina238-test.c b/tests/qtest/ina238-test.c index e7dd50a822..4e4146461c 100644 --- a/tests/qtest/ina238-test.c +++ b/tests/qtest/ina238-test.c @@ -282,6 +282,30 @@ static void test_zero_cal(void *obj, void *data, QGues= tAllocator *alloc) g_assert_cmpuint(i2c_get24(dev, REG_POWER), =3D=3D, 0); } =20 +/* Clearing SHUNT_CAL zeroes both derived registers in any mode */ +static void test_zero_cal_channels(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + static const uint16_t modes[] =3D { 0x9000, 0xA000, 0xF000 }; + size_t idx; + + for (idx =3D 0; idx < ARRAY_SIZE(modes); idx++) { + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + i2c_set16(dev, REG_SHUNT_CAL, 0x0FD2); + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), !=3D, 0x0000); + g_assert_cmpuint(i2c_get24(dev, REG_POWER), !=3D, 0); + + i2c_set16(dev, REG_ADC_CONFIG, modes[idx]); + i2c_set16(dev, REG_SHUNT_CAL, 0x0000); + + g_assert_cmphex(i2c_get16(dev, REG_CURRENT), =3D=3D, 0x0000); + g_assert_cmpuint(i2c_get24(dev, REG_POWER), =3D=3D, 0); + } +} + /* ADCRANGE changes the shunt LSB, not the current divisor. */ static void test_adcrange(void *obj, void *data, QGuestAllocator *alloc) { @@ -458,6 +482,27 @@ static void test_alert_power(void *obj, void *data, QG= uestAllocator *alloc) g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_POL, =3D=3D, 0); } =20 +/* Clearing SHUNT_CAL drops the power alert with the power reading */ +static void test_alert_power_zero_cal(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set16(dev, REG_CONFIG, CONFIG_RST); + qmp_ina238_set("shunt-voltage", 97200000); + qmp_ina238_set("bus-voltage", 48000000); + i2c_set16(dev, REG_SHUNT_CAL, 0x0FD2); + i2c_set16(dev, REG_PWR_LIMIT, 0x0100); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_POL, =3D=3D, DIAG= _POL); + + /* Continuous shunt-only: the power register is not reconverted. */ + i2c_set16(dev, REG_ADC_CONFIG, 0xA000); + i2c_set16(dev, REG_SHUNT_CAL, 0x0000); + + g_assert_cmpuint(i2c_get24(dev, REG_POWER), =3D=3D, 0); + g_assert_cmphex(i2c_get16(dev, REG_DIAG_ALRT) & DIAG_POL, =3D=3D, 0); +} + /* Two thresholds crossed at once are reported simultaneously (multi-alert= ) */ static void test_alert_multi(void *obj, void *data, QGuestAllocator *alloc) { @@ -733,6 +778,7 @@ static void ina238_register_nodes(void) NULL); qos_add_test("power", "ina238", test_power, NULL); qos_add_test("zero-cal", "ina238", test_zero_cal, NULL); + qos_add_test("zero-cal-channels", "ina238", test_zero_cal_channels, NU= LL); qos_add_test("adcrange", "ina238", test_adcrange, NULL); qos_add_test("mode-shutdown", "ina238", test_mode_shutdown, NULL); qos_add_test("mode-triggered", "ina238", test_mode_triggered, NULL); @@ -742,6 +788,8 @@ static void ina238_register_nodes(void) qos_add_test("alert-bus", "ina238", test_alert_bus, NULL); qos_add_test("alert-temp", "ina238", test_alert_temp, NULL); qos_add_test("alert-power", "ina238", test_alert_power, NULL); + qos_add_test("alert-power-zero-cal", "ina238", test_alert_power_zero_c= al, + NULL); qos_add_test("alert-multi", "ina238", test_alert_multi, NULL); qos_add_test("alert-latch", "ina238", test_alert_latch, NULL); qos_add_test("alert-latch-persist", "ina238", test_alert_latch_persist, --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1792060460; cv=none; d=zohomail.com; s=zohoarc; b=Br9TJTsFERNpdpIaQc3Bk4X0iN221R+fkzDf0o4clv22xLyoihRNSANQdnDx5CKCNH9RTShyEzzJTOZw5jp/d8suFtsRiG9H1ZsnpUM3+JnhIFgS5F1R5BTka3aYVpmFE9qhnltzIvdvBHUxKcyJrqfBX+lf59/6hxb0Qg9vGvU= ARC-Message-Signature: i=1; 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The board uses INA230 and INA238 power monitors, TMP75 temperature sensors, PCA9555 IO expanders, PCA9545 and PCA9548 I2C muxes, AT24C EEPROMs and a DS1339 RTC. Every device the Minerva device tree describes and QEMU already models is instantiated. The remaining ones (LTC4287, XDP710, MAX31790, PCF8563 and IPMB) have no QEMU model and are left documented as comments. Signed-off-by: Emmanuel Blot Reviewed-by: Jamin Lin --- docs/system/arm/aspeed.rst | 1 + hw/arm/aspeed_ast2600_minerva.c | 180 ++++++++++++++++++++++++++++++++++++= ++++ hw/arm/meson.build | 1 + 3 files changed, 182 insertions(+) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index f38f33cbe1..bbd3d9cdf4 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -36,6 +36,7 @@ AST2600 SoC based machines : - ``catalina-bmc`` Facebook Catalina BMC - ``sanmiguel-bmc`` Facebook SanMiguel BMC - ``anacapa-bmc`` Facebook Anacapa BMC +- ``minerva-bmc`` Facebook Minerva BMC - ``gb200nvl-bmc`` Nvidia GB200nvl BMC =20 Supported devices diff --git a/hw/arm/aspeed_ast2600_minerva.c b/hw/arm/aspeed_ast2600_minerv= a.c new file mode 100644 index 0000000000..93abc64770 --- /dev/null +++ b/hw/arm/aspeed_ast2600_minerva.c @@ -0,0 +1,180 @@ +/* + * Facebook Minerva Chassis Management Module + * + * Copyright (c) 2026 Meta Platforms, Inc. and affiliates. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/i2c_mux_pca954x.h" +#include "hw/gpio/pca9552.h" +#include "hw/nvram/eeprom_at24c.h" +#include "hw/rtc/ds1338.h" +#include "hw/sensor/ina230.h" +#include "hw/sensor/ina238.h" +#include "hw/sensor/tmp105.h" + +/* + * Minerva hardware values. + */ +#define MINERVA_BMC_HW_STRAP1 0x00002002 +#define MINERVA_BMC_HW_STRAP2 0x00000800 +#define MINERVA_BMC_RAM_SIZE (2 * GiB) + +/* + * Fan Controller Board (FCB). The Minerva BMC device tree describes six + * identical FCBs, each hanging off one channel of the PCA9548 on i2c2. + */ +static void minerva_fcb_i2c_init(I2CBus *bus) +{ + /* eeprom@50 - atmel,24c128 */ + at24c_eeprom_init(bus, 0x50, 16 * KiB); + /* pwm@5e - maxim,max31790 (no model) */ + /* power-sensor@40/41/44/45 - ti,ina238 */ + i2c_slave_create_simple(bus, TYPE_INA238, 0x40); + i2c_slave_create_simple(bus, TYPE_INA238, 0x41); + i2c_slave_create_simple(bus, TYPE_INA238, 0x44); + i2c_slave_create_simple(bus, TYPE_INA238, 0x45); + /* temperature-sensor@4b - tmp75 */ + i2c_slave_create_simple(bus, TYPE_TMP75, 0x4b); + /* gpio@11/12/13/17 - pca9555 */ + i2c_slave_create_simple(bus, TYPE_PCA9555, 0x11); + i2c_slave_create_simple(bus, TYPE_PCA9555, 0x12); + i2c_slave_create_simple(bus, TYPE_PCA9555, 0x13); + i2c_slave_create_simple(bus, TYPE_PCA9555, 0x17); +} + +static void minerva_pca9545_eeprom_init(I2CBus *bus, uint8_t addr, + unsigned neeprom) +{ + I2CSlave *i2c_mux =3D i2c_slave_create_simple(bus, TYPE_PCA9545, addr); + + for (unsigned idx =3D 0; idx < neeprom; idx++) { + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, idx), 0x50, 8 * KiB= ); + } +} + +static void minerva_bmc_i2c_init(AspeedMachineState *bmc) +{ + /* Reference: aspeed-bmc-facebook-minerva.dts */ + + AspeedSoCState *soc =3D bmc->soc; + I2CBus *i2c[16] =3D {}; + I2CSlave *i2c_mux; + + for (unsigned idx =3D 0; idx < ARRAY_SIZE(i2c); idx++) { + i2c[idx] =3D aspeed_i2c_get_bus(&soc->i2c, idx); + } + + /* &i2c0 */ + /* power-monitor@40/41 - ti,ina230 */ + i2c_slave_create_simple(i2c[0], TYPE_INA230, 0x40); + i2c_slave_create_simple(i2c[0], TYPE_INA230, 0x41); + /* power-monitor@44 - lltc,ltc4287 (no model) */ + /* power-monitor@43 - infineon,xdp710 (no model) */ + /* leds_gpio: gpio@19 - pca9555 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9555, 0x19); + /* gpio@11/12/13 - pca9555 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9555, 0x11); + i2c_slave_create_simple(i2c[0], TYPE_PCA9555, 0x12); + i2c_slave_create_simple(i2c[0], TYPE_PCA9555, 0x13); + + /* &i2c1 */ + /* temperature-sensor@4b/4f - tmp75 */ + i2c_slave_create_simple(i2c[1], TYPE_TMP75, 0x4b); + i2c_slave_create_simple(i2c[1], TYPE_TMP75, 0x4f); + /* eeprom@54 - atmel,24c128 */ + at24c_eeprom_init(i2c[1], 0x54, 16 * KiB); + + /* &i2c2 */ + /* i2c-mux@77 (PCA9548) - six Fan Controller Boards */ + i2c_mux =3D i2c_slave_create_simple(i2c[2], TYPE_PCA9548, 0x77); + /* FCB 1 - imux16 (channel 1) */ + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 1)); + /* FCB 2 - imux17 (channel 0) */ + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 0)); + /* FCB 3 - imux18 (channel 3) */ + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 3)); + /* FCB 4 - imux19 (channel 2) */ + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 2)); + /* FCB 5 - imux20 (channel 4) */ + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 4)); + /* FCB 6 - imux21 (channel 5) */ + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 5)); + /* imux22/imux23 (channels 6/7) - empty */ + + /* &i2c3 */ + /* i2c-mux@72 (PCA9545) - imux24-27, eeprom@50 on each channel */ + minerva_pca9545_eeprom_init(i2c[3], 0x72, 4); + + /* &i2c4 */ + /* i2c-mux@72 (PCA9545) - imux28-31, eeprom@50 on each channel */ + minerva_pca9545_eeprom_init(i2c[4], 0x72, 4); + + /* &i2c5 */ + /* i2c-mux@72 (PCA9545) - imux32-35, eeprom@50 on each channel */ + minerva_pca9545_eeprom_init(i2c[5], 0x72, 4); + + /* &i2c6 */ + /* i2c-mux@72 (PCA9545) - imux36-39, eeprom@50 on each channel */ + minerva_pca9545_eeprom_init(i2c[6], 0x72, 4); + + /* &i2c7 - empty */ + /* &i2c8 - empty */ + + /* &i2c9 */ + /* eeprom@50 - atmel,24c64 */ + at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); + /* rtc@51 - nxp,pcf8563 (no model) */ + /* rtc@68 - dallas,ds1339 */ + i2c_slave_create_simple(i2c[9], TYPE_DS1339, 0x68); + + /* &i2c12 */ + /* i2c-mux@70 (PCA9545) - imux40-42 eeprom@50, imux43 empty */ + minerva_pca9545_eeprom_init(i2c[12], 0x70, 3); + + /* &i2c13 */ + /* i2c-mux@70 (PCA9545) - imux44-46 eeprom@50, imux47 empty */ + minerva_pca9545_eeprom_init(i2c[13], 0x70, 3); + + /* &i2c14 */ + /* ipmb@10 - ipmb-dev (no model) */ + + /* &i2c15 */ + /* eeprom@50 - atmel,24c128 */ + at24c_eeprom_init(i2c[15], 0x50, 16 * KiB); + /* eeprom@56 - atmel,24c64 */ + at24c_eeprom_init(i2c[15], 0x56, 8 * KiB); +} + +static void aspeed_machine_minerva_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Facebook Minerva BMC (Cortex-A7)"; + amc->soc_name =3D "ast2600-a3"; + amc->hw_strap1 =3D MINERVA_BMC_HW_STRAP1; + amc->hw_strap2 =3D MINERVA_BMC_HW_STRAP2; + amc->fmc_model =3D "mx66l1g45g"; + amc->spi_model =3D NULL; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC3_ON; + amc->i2c_init =3D minerva_bmc_i2c_init; + mc->default_ram_size =3D MINERVA_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast2600_minerva_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("minerva-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_minerva_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2600_minerva_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index bcc068de04..a9e8270b85 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -63,6 +63,7 @@ arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: fil= es( 'aspeed_ast2600_fby35.c', 'aspeed_ast2600_fuji.c', 'aspeed_ast2600_gb200nvl.c', + 'aspeed_ast2600_minerva.c', 'aspeed_ast2600_rainier.c', 'aspeed_ast2600_sanmiguel.c', 'aspeed_ast10x0.c', --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Populate them from a sanitized dump read from hardware, so guest firmware can identify the chassis inventory instead of finding blank parts. Reviewed-by: Jamin Lin Signed-off-by: Emmanuel Blot --- hw/arm/aspeed_ast2600_minerva.c | 714 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 695 insertions(+), 19 deletions(-) diff --git a/hw/arm/aspeed_ast2600_minerva.c b/hw/arm/aspeed_ast2600_minerv= a.c index 93abc64770..4b6731e279 100644 --- a/hw/arm/aspeed_ast2600_minerva.c +++ b/hw/arm/aspeed_ast2600_minerva.c @@ -24,14 +24,667 @@ #define MINERVA_BMC_HW_STRAP2 0x00000800 #define MINERVA_BMC_RAM_SIZE (2 * GiB) =20 +/* FRU EEPROM content meaningful size */ +#define MINERVA_FRU_LEN 192 + +/* Motherboards behind each of the four i2c3..i2c6 muxes */ +#define MINERVA_MB_PER_MUX 4 + +/* Minerva CMM PVT */ +static const uint8_t cmm_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x08, 0x11, 0x00, 0x00, 0xe5, 0x01, 0x07, 0x17, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc0, 0xcc, 0x39, 0x30, 0x38, 0x32, 0x43, 0x33, + 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x13, 0x01, 0x09, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, + 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcf, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, + 0x61, 0x20, 0x43, 0x4d, 0x4d, 0x20, 0x50, 0x56, 0x54, 0xce, 0x41, 0x41, + 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x32, + 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, + 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, 0x2e, 0x31, + 0x35, 0xc1, 0x00, 0xef, 0x01, 0x08, 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, + 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, 0x69, 0x6e, 0x65, 0x72, + 0x76, 0x61, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x31, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, 0x41, 0x41, 0x41, 0x30, + 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x33, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x65, +}; + +/* Minerva_CMM_SCM PVT */ +static const uint8_t scm_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd3, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x5f, 0x43, 0x4d, + 0x4d, 0x5f, 0x53, 0x43, 0x4d, 0x20, 0x50, 0x56, 0x54, 0xce, 0x41, 0x41, + 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x34, + 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x32, + 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, 0x2e, 0x31, + 0x30, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x01, 0x08, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, + 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, + 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x33, 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x65, +}; + +/* BMC Storage Module PVT */ +static const uint8_t bsm_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd6, 0x42, 0x4d, 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, + 0x65, 0x20, 0x4d, 0x6f, 0x64, 0x75, 0x6c, 0x65, 0x20, 0x50, 0x56, 0x54, + 0xce, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x35, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, + 0x30, 0x41, 0x33, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, + 0x30, 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x47, 0x01, 0x08, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, + 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, + 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x33, 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x65, +}; + +/* Minerva Fan Board 1 PVT */ +static const uint8_t fcb1_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd5, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, 0x46, 0x61, + 0x6e, 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x50, 0x56, 0x54, 0xce, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x36, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x34, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, + 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x00, 0xa6, 0x01, 0x05, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xc0, 0xc3, 0x50, 0x56, 0x54, 0xc0, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x83, +}; + +/* Minerva Fan Board 2 PVT */ +static const uint8_t fcb2_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd5, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, 0x46, 0x61, + 0x6e, 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x50, 0x56, 0x54, 0xce, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x37, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x34, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, + 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x00, 0xa5, 0x01, 0x05, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xc0, 0xc3, 0x50, 0x56, 0x54, 0xc0, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x83, +}; + +/* Minerva Fan Board 3 PVT */ +static const uint8_t fcb3_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd5, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, 0x46, 0x61, + 0x6e, 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x50, 0x56, 0x54, 0xce, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x38, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x34, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, + 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x00, 0xa4, 0x01, 0x05, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xc0, 0xc3, 0x50, 0x56, 0x54, 0xc0, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x83, +}; + +/* Minerva Fan Board 4 PVT */ +static const uint8_t fcb4_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd5, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, 0x46, 0x61, + 0x6e, 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x50, 0x56, 0x54, 0xce, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x39, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x34, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, + 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x00, 0xa3, 0x01, 0x05, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xc0, 0xc3, 0x50, 0x56, 0x54, 0xc0, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x83, +}; + +/* Minerva Fan Board 5 PVT */ +static const uint8_t fcb5_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd5, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, 0x46, 0x61, + 0x6e, 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x50, 0x56, 0x54, 0xce, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x31, 0x30, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x34, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, + 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x00, 0xab, 0x01, 0x05, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xc0, 0xc3, 0x50, 0x56, 0x54, 0xc0, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x83, +}; + +/* Minerva Fan Board6 PVT */ +static const uint8_t fcb6_eeprom[] =3D { + 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, 0x00, 0xcb, + 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x31, 0xd0, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, + 0x01, 0x0a, 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd5, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, 0x46, 0x61, + 0x6e, 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x50, 0x56, 0x54, 0xce, + 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x31, 0x31, 0xcb, 0x30, 0x41, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x30, 0x34, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, + 0x2e, 0x31, 0x30, 0xc1, 0x00, 0x00, 0x00, 0xaa, 0x01, 0x05, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, + 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0xc0, 0xc3, 0x50, 0x56, 0x54, 0xc0, + 0xc4, 0x51, 0x45, 0x4d, 0x55, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x83, +}; + +/* Harma motherboards, in i2c3/i2c4/i2c5/i2c6 mux channel order */ +static const uint8_t minerva_mb_eeprom[][MINERVA_FRU_LEN] =3D { + { 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, + 0x17, 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, + 0x30, 0x30, 0x31, 0xd0, 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, + 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, + 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x01, 0x0a, + 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd4, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, + 0x48, 0x61, 0x72, 0x6d, 0x61, 0x20, 0x4d, 0x42, 0x20, 0x50, + 0x56, 0x54, 0xce, 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x32, 0xcb, 0x30, 0x41, + 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x41, 0x35, 0xcc, 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0x20, 0x50, + 0x56, 0x54, 0xce, 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x34, 0xcb, 0x30, 0x41, + 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x41, 0x35, 0xcc, + 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, 0x2e, + 0x31, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x01, 0x08, + 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, + 0x32, 0x31, 0x20, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, + 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x41, 0x32, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, 0x41, 0x41, + 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x31, 0x35, 0xc4, 0x51, 0x45, 0x4d, 0x55, 0x00, + 0xc1, 0x21, + }, + { 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, + 0x17, 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, + 0x30, 0x30, 0x31, 0xd0, 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, + 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, + 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x01, 0x0a, + 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd4, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, + 0x48, 0x61, 0x72, 0x6d, 0x61, 0x20, 0x4d, 0x42, 0x20, 0x50, + 0x56, 0x54, 0xce, 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x36, 0xcb, 0x30, 0x41, + 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x41, 0x35, 0xcc, + 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, 0x2e, + 0x31, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x18, 0x01, 0x08, + 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, + 0x32, 0x31, 0x20, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, + 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x41, 0x32, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, 0x41, 0x41, + 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x31, 0x37, 0xc4, 0x51, 0x45, 0x4d, 0x55, 0x00, + 0xc1, 0x1f, + }, + { 0x01, 0x00, 0x01, 0x06, 0x10, 0x00, 0x00, 0xe8, 0x01, 0x05, + 0x17, 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, + 0x30, 0x30, 0x31, 0xd0, 0x41, 0x41, 0x41, 0x41, 0x30, 0x41, + 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, + 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x01, 0x0a, + 0x19, 0xc0, 0xc6, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, + 0x61, 0xd4, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, 0x20, + 0x48, 0x61, 0x72, 0x6d, 0x61, 0x20, 0x4d, 0x42, 0x20, 0x50, + 0x56, 0x54, 0xce, 0x41, 0x41, 0x41, 0x41, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x38, 0xcb, 0x30, 0x41, + 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, 0x41, 0x35, 0xcc, + 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, 0x30, 0x2e, + 0x31, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x16, 0x01, 0x08, + 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, + 0x32, 0x31, 0x20, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, + 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x41, 0x32, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, 0x41, 0x41, + 0x41, 0x30, 0x41, 0x30, 0x41, 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0x20, 0x56, 0x65, 0x72, 0x20, 0x30, 0x2e, + 0x31, 0x31, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x08, + 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x54, + 0x32, 0x31, 0x20, 0x4d, 0x69, 0x6e, 0x65, 0x72, 0x76, 0x61, + 0xcb, 0x30, 0x30, 0x41, 0x30, 0x41, 0x41, 0x41, 0x30, 0x30, + 0x41, 0x32, 0xc3, 0x50, 0x56, 0x54, 0xd1, 0x41, 0x41, 0x41, + 0x41, 0x30, 0x41, 0x30, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x34, 0x33, 0xc4, 0x51, 0x45, 0x4d, 0x55, 0x00, + 0xc1, 0x20, + }, +}; + +/* The four muxes take a quarter of the table each, by hand-written index.= */ +QEMU_BUILD_BUG_ON(ARRAY_SIZE(minerva_mb_eeprom) !=3D 4 * MINERVA_MB_PER_MU= X); + +/* Switch boards on the i2c12 mux */ +static const uint8_t minerva_smb12_eeprom[][MINERVA_FRU_LEN] =3D { + { 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, + 0x19, 0xc0, 0xc6, 0xf0, 0xc9, 0x43, 0x65, 0x6c, 0x65, 0x73, + 0x74, 0x69, 0x63, 0x61, 0xd1, 0x4d, 0x69, 0x6e, 0x65, 0x72, + 0x76, 0x61, 0x20, 0x4a, 0x61, 0x6e, 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0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x34, 0x39, 0xc4, 0x51, 0x45, 0x4d, 0x55, + 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xec, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, + }, +}; + +/* Switch boards on the i2c13 mux */ +static const uint8_t minerva_smb13_eeprom[][MINERVA_FRU_LEN] =3D { + { 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, + 0x19, 0xc0, 0xc6, 0xf0, 0xc9, 0x43, 0x65, 0x6c, 0x65, 0x73, + 0x74, 0x69, 0x63, 0x61, 0xd1, 0x4d, 0x69, 0x6e, 0x65, 0x72, + 0x76, 0x61, 0x20, 0x54, 0x61, 0x68, 0x61, 0x6e, 0x20, 0x53, + 0x4d, 0x42, 0xcd, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x35, 0x30, 0xce, 0x41, 0x30, 0x30, + 0x30, 0x30, 0x2d, 0x41, 0x30, 0x30, 0x30, 0x30, 0x2d, 0x30, + 0x37, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, + 0x30, 0x2e, 0x30, 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0x73, + 0x74, 0x69, 0x63, 0x61, 0xd1, 0x4d, 0x69, 0x6e, 0x65, 0x72, + 0x76, 0x61, 0x20, 0x54, 0x61, 0x68, 0x61, 0x6e, 0x20, 0x53, + 0x4d, 0x42, 0xcd, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x30, 0x35, 0x34, 0xce, 0x41, 0x30, 0x30, + 0x30, 0x30, 0x2d, 0x41, 0x30, 0x30, 0x30, 0x30, 0x2d, 0x30, + 0x37, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72, 0x20, + 0x30, 0x2e, 0x30, 0x32, 0xc1, 0x00, 0x00, 0xbf, 0x01, 0x09, + 0x19, 0xc9, 0x43, 0x65, 0x6c, 0x65, 0x73, 0x74, 0x69, 0x63, + 0x61, 0xcb, 0x54, 0x32, 0x31, 0x20, 0x4d, 0x69, 0x6e, 0x65, + 0x72, 0x76, 0x61, 0xce, 0x41, 0x30, 0x30, 0x30, 0x30, 0x2d, + 0x41, 0x30, 0x30, 0x30, 0x30, 0x2d, 0x41, 0x34, 0xc2, 0x4d, + 0x50, 0xcd, 0x41, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, + 0x30, 0x30, 0x30, 0x35, 0x35, 0xc4, 0x51, 0x45, 0x4d, 0x55, + 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xef, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, + }, +}; + /* * Fan Controller Board (FCB). The Minerva BMC device tree describes six * identical FCBs, each hanging off one channel of the PCA9548 on i2c2. */ -static void minerva_fcb_i2c_init(I2CBus *bus) +static void minerva_fcb_i2c_init(I2CBus *bus, const uint8_t *fru, + uint32_t fru_size) { /* eeprom@50 - atmel,24c128 */ - at24c_eeprom_init(bus, 0x50, 16 * KiB); + at24c_eeprom_init_rom(bus, 0x50, 16 * KiB, fru, fru_size); /* pwm@5e - maxim,max31790 (no model) */ /* power-sensor@40/41/44/45 - ti,ina238 */ i2c_slave_create_simple(bus, TYPE_INA238, 0x40); @@ -48,12 +701,14 @@ static void minerva_fcb_i2c_init(I2CBus *bus) } =20 static void minerva_pca9545_eeprom_init(I2CBus *bus, uint8_t addr, + const uint8_t fru[][MINERVA_FRU_LE= N], unsigned neeprom) { I2CSlave *i2c_mux =3D i2c_slave_create_simple(bus, TYPE_PCA9545, addr); =20 for (unsigned idx =3D 0; idx < neeprom; idx++) { - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, idx), 0x50, 8 * KiB= ); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, idx), 0x50, + 8 * KiB, fru[idx], MINERVA_FRU_LEN); } } =20 @@ -87,46 +742,61 @@ static void minerva_bmc_i2c_init(AspeedMachineState *b= mc) i2c_slave_create_simple(i2c[1], TYPE_TMP75, 0x4b); i2c_slave_create_simple(i2c[1], TYPE_TMP75, 0x4f); /* eeprom@54 - atmel,24c128 */ - at24c_eeprom_init(i2c[1], 0x54, 16 * KiB); + at24c_eeprom_init_rom(i2c[1], 0x54, 16 * KiB, + cmm_eeprom, sizeof(cmm_eeprom)); =20 /* &i2c2 */ /* i2c-mux@77 (PCA9548) - six Fan Controller Boards */ i2c_mux =3D i2c_slave_create_simple(i2c[2], TYPE_PCA9548, 0x77); /* FCB 1 - imux16 (channel 1) */ - minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 1)); + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 1), + fcb1_eeprom, sizeof(fcb1_eeprom)); /* FCB 2 - imux17 (channel 0) */ - minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 0)); + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 0), + fcb2_eeprom, sizeof(fcb2_eeprom)); /* FCB 3 - imux18 (channel 3) */ - minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 3)); + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 3), + fcb3_eeprom, sizeof(fcb3_eeprom)); /* FCB 4 - imux19 (channel 2) */ - minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 2)); + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 2), + fcb4_eeprom, sizeof(fcb4_eeprom)); /* FCB 5 - imux20 (channel 4) */ - minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 4)); + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 4), + fcb5_eeprom, sizeof(fcb5_eeprom)); /* FCB 6 - imux21 (channel 5) */ - minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 5)); + minerva_fcb_i2c_init(pca954x_i2c_get_bus(i2c_mux, 5), + fcb6_eeprom, sizeof(fcb6_eeprom)); /* imux22/imux23 (channels 6/7) - empty */ =20 /* &i2c3 */ /* i2c-mux@72 (PCA9545) - imux24-27, eeprom@50 on each channel */ - minerva_pca9545_eeprom_init(i2c[3], 0x72, 4); + minerva_pca9545_eeprom_init(i2c[3], 0x72, + &minerva_mb_eeprom[0 * MINERVA_MB_PER_MUX], + MINERVA_MB_PER_MUX); =20 /* &i2c4 */ /* i2c-mux@72 (PCA9545) - imux28-31, eeprom@50 on each channel */ - minerva_pca9545_eeprom_init(i2c[4], 0x72, 4); + minerva_pca9545_eeprom_init(i2c[4], 0x72, + &minerva_mb_eeprom[1 * MINERVA_MB_PER_MUX], + MINERVA_MB_PER_MUX); =20 /* &i2c5 */ /* i2c-mux@72 (PCA9545) - imux32-35, eeprom@50 on each channel */ - minerva_pca9545_eeprom_init(i2c[5], 0x72, 4); + minerva_pca9545_eeprom_init(i2c[5], 0x72, + &minerva_mb_eeprom[2 * MINERVA_MB_PER_MUX], + MINERVA_MB_PER_MUX); =20 /* &i2c6 */ /* i2c-mux@72 (PCA9545) - imux36-39, eeprom@50 on each channel */ - minerva_pca9545_eeprom_init(i2c[6], 0x72, 4); + minerva_pca9545_eeprom_init(i2c[6], 0x72, + &minerva_mb_eeprom[3 * MINERVA_MB_PER_MUX], + MINERVA_MB_PER_MUX); =20 /* &i2c7 - empty */ /* &i2c8 - empty */ =20 /* &i2c9 */ - /* eeprom@50 - atmel,24c64 */ + /* eeprom@50 - atmel,24c64 (no FRU data captured) */ at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); /* rtc@51 - nxp,pcf8563 (no model) */ /* rtc@68 - dallas,ds1339 */ @@ -134,20 +804,26 @@ static void minerva_bmc_i2c_init(AspeedMachineState *= bmc) =20 /* &i2c12 */ /* i2c-mux@70 (PCA9545) - imux40-42 eeprom@50, imux43 empty */ - minerva_pca9545_eeprom_init(i2c[12], 0x70, 3); + minerva_pca9545_eeprom_init(i2c[12], 0x70, + minerva_smb12_eeprom, + ARRAY_SIZE(minerva_smb12_eeprom)); =20 /* &i2c13 */ /* i2c-mux@70 (PCA9545) - imux44-46 eeprom@50, imux47 empty */ - minerva_pca9545_eeprom_init(i2c[13], 0x70, 3); + minerva_pca9545_eeprom_init(i2c[13], 0x70, + minerva_smb13_eeprom, + ARRAY_SIZE(minerva_smb13_eeprom)); =20 /* &i2c14 */ /* ipmb@10 - ipmb-dev (no model) */ =20 /* &i2c15 */ /* eeprom@50 - atmel,24c128 */ - at24c_eeprom_init(i2c[15], 0x50, 16 * KiB); + at24c_eeprom_init_rom(i2c[15], 0x50, 16 * KiB, + scm_eeprom, sizeof(scm_eeprom)); /* eeprom@56 - atmel,24c64 */ - at24c_eeprom_init(i2c[15], 0x56, 8 * KiB); + at24c_eeprom_init_rom(i2c[15], 0x56, 8 * KiB, + bsm_eeprom, sizeof(bsm_eeprom)); } =20 static void aspeed_machine_minerva_class_init(ObjectClass *oc, --=20 2.53.0-Meta From nobody Thu Oct 22 19:27:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Note: The boot image currently lives on a personal fork; a TODO in the test notes it should be relocated under legoater/qemu-aspeed-boot before upstreaming. Signed-off-by: Emmanuel Blot Reviewed-by: Jamin Lin --- tests/functional/arm/meson.build | 2 ++ tests/functional/arm/test_aspeed_minerva.py | 30 +++++++++++++++++++++++++= ++++ 2 files changed, 32 insertions(+) diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.= build index 61b00932db..dd1ddf7f6f 100644 --- a/tests/functional/arm/meson.build +++ b/tests/functional/arm/meson.build @@ -16,6 +16,7 @@ test_arm_timeouts =3D { 'aspeed_bletchley' : 480, 'aspeed_catalina' : 480, 'aspeed_gb200nvl_bmc' : 480, + 'aspeed_minerva' : 480, 'aspeed_rainier' : 480, 'bpim2u' : 500, 'collie' : 180, @@ -51,6 +52,7 @@ tests_arm_system_thorough =3D [ 'aspeed_bletchley', 'aspeed_catalina', 'aspeed_gb200nvl_bmc', + 'aspeed_minerva', 'aspeed_rainier', 'bpim2u', 'canona1100', diff --git a/tests/functional/arm/test_aspeed_minerva.py b/tests/functional= /arm/test_aspeed_minerva.py new file mode 100644 index 0000000000..925a82b139 --- /dev/null +++ b/tests/functional/arm/test_aspeed_minerva.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# Copyright (c) 2026 Meta Platforms, Inc. and affiliates. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class MinervaMachine(AspeedTest): + + # TODO: the boot image currently lives on a personal fork; move it und= er + # legoater/qemu-aspeed-boot before upstreaming. + ASSET_MINERVA_FLASH =3D Asset( + 'https://github.com/eblot/qemu-aspeed-boot/raw/refs/heads/minerva-= bmc/images/minerva-bmc/openbmc-20260720025047/' + 'obmc-phosphor-image-minerva-20260720025047.static.mtd.xz', + 'bd713df39d3c09846299a2377315465187a4dcd33c29d3b3d683ef13b59f36bb') + + def test_arm_ast2600_minerva_openbmc(self): + image_path =3D self.uncompress(self.ASSET_MINERVA_FLASH) + + self.do_test_arm_aspeed_openbmc('minerva-bmc', image=3Dimage_path, + uboot=3D'2019.04', cpu_id=3D'0xf00= ', + soc=3D'AST2600 rev A3') + +if __name__ =3D=3D '__main__': + AspeedTest.main() --=20 2.53.0-Meta