From nobody Thu Oct 22 19:22:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1791819918; cv=none; d=zohomail.com; s=zohoarc; b=QPE94ZV9WrlTE8vMDbt3dQbb46SVWcm/zrr7J0nAKUzDAW5ctWwHCMIxfdtPDGd5dbHK8o9pwZ1Ft6NtoEoU59OkWxOFP9fdeCxlKdxABDPD8Us47Xjk5NRct/vi+F5PhSMxUwwC8aTgikZUCRCz4fQ2qFXh8AJFZJbkEanRijU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791819918; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xVZvn5X9JVCVl0mXu+bnJCmFQ+gW0cd4rx7jbHsRzF4=; b=VW5Qup+AAu6IZTXciIvRE2ijlaaDH+T9g4rsXT1VssLln8JwJTXhTJ6bngVB0k3LTRJtGXuVRyIW4l+3AlML8/8OsE6oJJRzSlXD2OQY5uHNgRA7Aiyxwh+3S7qRDUBfTQNxw1eonLX0SRwxehruPKOWqKFSUA3koJnEC859yGY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791819918386954.3093153363855; Mon, 12 Oct 2026 08:45:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xGICx-00072y-SU; Mon, 12 Oct 2026 11:44:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xGICt-00072K-Ex for qemu-devel@nongnu.org; Mon, 12 Oct 2026 11:44:56 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xGICp-0004ao-Nx for qemu-devel@nongnu.org; Mon, 12 Oct 2026 11:44:53 -0400 Received: from laptop.localdomain (unknown [81.196.141.65]) by linux.microsoft.com (Postfix) with ESMTPSA id E053020B7166; Mon, 12 Oct 2026 08:44:45 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com E053020B7166 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1791819887; bh=xVZvn5X9JVCVl0mXu+bnJCmFQ+gW0cd4rx7jbHsRzF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ssk6ZVRVGHf6N1PmWsa4d6xBP/To1uWw2SRQvedHAZl1b/1BMWC7AGXEmso3kPuLh ecz9Tjh8bwbJEQCCDhF4vdZYV5ycym40rYDesdSZjytHUbouOcnspLUxx4iZHgA26F AZI1ErFDdzENeM6G79YuZHojtk3xHhtAX2t29l4E= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , Wei Liu , Magnus Kulke , Magnus Kulke , Zhao Liu , Paolo Bonzini , Wei Liu , =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= Subject: [PATCH 1/2] i386/cpu.c: Adjust minimum xlevel to 0x8000_001E when TOPOEXT is enabled Date: Mon, 12 Oct 2026 18:44:41 +0300 Message-ID: <20261012154442.306511-2-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261012154442.306511-1-dblanzeanu@linux.microsoft.com> References: <20261012154442.306511-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1791819918983158500 This ensures the guests can discover the AMD cache and processor topology l= eaves when TOPOEXT feature is enabled. Signed-off-by: Doru Bl=C3=A2nzeanu --- target/i386/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 74eebeabd7..f1d8a35766 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9879,6 +9879,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); } =20 + /* TOPOEXT requires CPUID[0x8000001D] and CPUID[0x8000001E] */ + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001E); + } + /* SEV requires CPUID[0x8000001F] */ if (sev_enabled()) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); --=20 2.53.0 From nobody Thu Oct 22 19:22:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1791819890; bh=m0/6LBaTSZBurt5DrWgHDAFzsGIP5qxDVOvdE1hOpJI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XItWYoXQ3nyF6XQVC1D1Ztp1jQxrnv7pEjMLaMD5NhHxca2YCqtRLKQIDO4ONEdHs cfPgBqabOBvvFuolJuN5tvqo1MwtyG5Cj4dcv5CbbHMuj3pAEwg/jfpbOfYn8lXuhc xdlZPmJyPJGceG8+8mgYHY3kXIlDqr0Xm8VDhWQA= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , Wei Liu , Magnus Kulke , Magnus Kulke , Zhao Liu , Paolo Bonzini , Wei Liu , =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= Subject: [PATCH 2/2] mshv/mshv-cpu.c: Collect all Intel topology subleaves and AMD cache subleaves Date: Mon, 12 Oct 2026 18:44:42 +0300 Message-ID: <20261012154442.306511-3-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261012154442.306511-1-dblanzeanu@linux.microsoft.com> References: <20261012154442.306511-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1791819931159158500 This fix makes AMD cache overrides subleaf-specific, makes 0x8000_001E apply regardless of ECX (not subleaf specific) and collects Intel topology subleaves (0x0b, 0x1f). Signed-off-by: Doru Bl=C3=A2nzeanu --- target/i386/mshv/mshv-cpu.c | 41 +++++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 4df73bb497..25670667f0 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1093,6 +1093,21 @@ static void collect_cpuid_entries(const CPUState *cp= u, GList **cpuid_entries) /* Collect basic leaves (0x0 to max_basic_leaf) */ for (leaf =3D 0; leaf <=3D max_basic_leaf; leaf++) { bool has_subleaves =3D false; + + if (leaf =3D=3D 0x0b || leaf =3D=3D 0x1f) { + for (subleaf =3D 0; subleaf < max_subleaf; subleaf++) { + cpu_x86_cpuid(env, leaf, subleaf, + &eax, &ebx, &ecx, &edx); + add_cpuid_entry(cpuid_entries, leaf, subleaf, + eax, ebx, ecx, edx); + + if (!(ecx & 0xff00)) { + break; + } + } + continue; + } + for (int i =3D 0; i < n_subleaf_leaves; i++) { if (leaf =3D=3D leaves_with_subleaves[i]) { has_subleaves =3D true; @@ -1150,6 +1165,20 @@ static void collect_cpuid_entries(const CPUState *cp= u, GList **cpuid_entries) =20 /* Collect extended leaves (0x80000000 to max_extended_leaf) */ for (leaf =3D 0x80000000; leaf <=3D max_extended_leaf; leaf++) { + if (leaf =3D=3D 0x8000001d) { + for (subleaf =3D 0; subleaf < max_subleaf; subleaf++) { + cpu_x86_cpuid(env, leaf, subleaf, + &eax, &ebx, &ecx, &edx); + + add_cpuid_entry(cpuid_entries, leaf, subleaf, + eax, ebx, ecx, edx); + if ((eax & 0x1f) =3D=3D 0) { + break; + } + } + continue; + } + cpu_x86_cpuid(env, leaf, 0, &eax, &ebx, &ecx, &edx); add_cpuid_entry(cpuid_entries, leaf, 0, eax, ebx, ecx, edx); } @@ -1229,12 +1258,10 @@ static int register_intercept_result_cpuid(const CP= UState *cpu, * 0xb - Extended Topology Enumeration Leaf * 0x1f - V2 Extended Topology Enumeration Leaf * AMD - * 0x8000_001e - Processor Topology Information * 0x8000_0026 - Extended CPU Topology */ if (entry->function =3D=3D 0xb || entry->function =3D=3D 0x1f || - entry->function =3D=3D 0x8000001e || entry->function =3D=3D 0x80000026) { subleaf_specific =3D 1; always_override =3D 1; @@ -1245,12 +1272,14 @@ static int register_intercept_result_cpuid(const CP= UState *cpu, * 0x0D: Processor Extended State Enumeration * 0x0F: Platform QoS Monitoring * 0x10: Platform QoS Enforcement + * 0x8000_001D: AMD Cache Topology */ } else if (entry->function =3D=3D 0x04 || entry->function =3D=3D 0x07 || entry->function =3D=3D 0x0d || entry->function =3D=3D 0x0f || - entry->function =3D=3D 0x10) { + entry->function =3D=3D 0x10 || + entry->function =3D=3D 0x8000001d) { subleaf_specific =3D 1; always_override =3D 1; /* Basic feature leaves (no subleaves) */ @@ -2339,11 +2368,6 @@ void mshv_arch_init_vcpu(CPUState *cpu) header =3D (X86XSaveHeader *)(env->xsave_buf + sizeof(X86LegacyXSaveAr= ea)); header->xcomp_bv =3D header->xstate_bv | (1ULL << 63); =20 - /* - * TODO: populate topology info: - * X86CPUTopoInfo *topo_info =3D &env->topo_info; - */ - ret =3D init_cpuid2(cpu); assert(ret =3D=3D 0); =20 @@ -2394,6 +2418,7 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uint= 32_t idx, int reg) /* Disable nested virtualization features not yet supported by MSHV */ if (func =3D=3D 0x80000001 && reg =3D=3D R_ECX) { ret &=3D ~CPUID_EXT3_SVM; + ret |=3D CPUID_EXT3_TOPOEXT; } if (func =3D=3D 0x01 && reg =3D=3D R_ECX) { ret &=3D ~CPUID_EXT_VMX; --=20 2.53.0