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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778750094158500 Hand the k0lock/tlblock lock implementation functions the packet PC as a constant instead of relying on next_PC's opcode-dependent staging. Reviewed-by: Pierrick Bouvier Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.h | 2 +- target/hexagon/sys_macros.h | 4 ++-- target/hexagon/hex_mmu.c | 16 +++++++++------- target/hexagon/op_helper.c | 16 +++++++++------- 4 files changed, 21 insertions(+), 17 deletions(-) diff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h index 56b2c4a89d0..977a97da31a 100644 --- a/target/hexagon/hex_mmu.h +++ b/target/hexagon/hex_mmu.h @@ -22,7 +22,7 @@ extern bool hex_tlb_find_match(CPUHexagonState *env, uint= 32_t VA, uint64_t *size, int32_t *excp, int mmu_idx); extern int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry, uint64_t index); -extern void hex_tlb_lock(CPUHexagonState *env); +extern void hex_tlb_lock(CPUHexagonState *env, uint32_t PC); extern void hex_tlb_unlock(CPUHexagonState *env); void dump_mmu(MonitorHMP *hmp, CPUHexagonState *env); #endif diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index a5b9b7f2592..72179d49ab3 100644 --- a/target/hexagon/sys_macros.h +++ b/target/hexagon/sys_macros.h @@ -145,10 +145,10 @@ #define fDCINVIDX(REG) #define fDCINVA(REG) do { REG =3D REG; } while (0) /* Nothing to do in qem= u */ =20 -#define fSET_TLB_LOCK() hex_tlb_lock(env); +#define fSET_TLB_LOCK() hex_tlb_lock(env, PC); #define fCLEAR_TLB_LOCK() hex_tlb_unlock(env); =20 -#define fSET_K0_LOCK() hex_k0_lock(env); +#define fSET_K0_LOCK() hex_k0_lock(env, PC); #define fCLEAR_K0_LOCK() hex_k0_unlock(env); =20 #define fTLB_IDXMASK(INDEX) \ diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index d6ee7c40798..a8e4d7f2c5e 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -156,7 +156,7 @@ static inline void print_thread_states(const char *str) } } =20 -void hex_tlb_lock(CPUHexagonState *env) +void hex_tlb_lock(CPUHexagonState *env, uint32_t PC) { qemu_log_mask(CPU_LOG_MMU, "hex_tlb_lock: " TARGET_FMT_ld "\n", env->threadId); @@ -170,7 +170,6 @@ void hex_tlb_lock(CPUHexagonState *env) uint8_t tlb_lock =3D GET_SYSCFG_FIELD(SYSCFG_TLBLOCK, syscfg); if (tlb_lock) { if (env->tlb_lock_state =3D=3D HEX_LOCK_QUEUED) { - env->next_PC +=3D 4; env->tlb_lock_count++; env->tlb_lock_state =3D HEX_LOCK_OWNER; SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 1); @@ -178,19 +177,22 @@ void hex_tlb_lock(CPUHexagonState *env) } if (env->tlb_lock_state =3D=3D HEX_LOCK_OWNER) { qemu_log_mask(CPU_LOG_MMU | LOG_GUEST_ERROR, - "Double tlblock at PC: 0x%" PRIx32 - ", thread may hang\n", - env->next_PC); - env->next_PC +=3D 4; + "Double tlblock at PC: 0x" TARGET_FMT_lx + ", thread may hang\n", PC); CPUState *cs =3D env_cpu(env); cpu_interrupt(cs, CPU_INTERRUPT_HALT); return; } env->tlb_lock_state =3D HEX_LOCK_WAITING; + /* + * next_PC has already been advanced past this packet. Rewind it + * so that the thread re-executes the tlblock when it is woken by + * the thread that releases the lock. + */ + env->next_PC =3D PC; CPUState *cs =3D env_cpu(env); cpu_interrupt(cs, CPU_INTERRUPT_HALT); } else { - env->next_PC +=3D 4; env->tlb_lock_count++; env->tlb_lock_state =3D HEX_LOCK_OWNER; SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 1); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 4f00ca773f3..3de6b994b8f 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1283,7 +1283,7 @@ void HELPER(modify_ssr)(CPUHexagonState *env, uint32_= t new, uint32_t old) hexagon_modify_ssr(env, new, old); } =20 -static void hex_k0_lock(CPUHexagonState *env) +static void hex_k0_lock(CPUHexagonState *env, uint32_t PC) { HexagonCPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); @@ -1297,7 +1297,6 @@ static void hex_k0_lock(CPUHexagonState *env) env->threadId) : 0; if (GET_SYSCFG_FIELD(SYSCFG_K0LOCK, syscfg)) { if (env->k0_lock_state =3D=3D HEX_LOCK_QUEUED) { - env->next_PC +=3D 4; env->k0_lock_count++; env->k0_lock_state =3D HEX_LOCK_OWNER; SET_SYSCFG_FIELD(env, SYSCFG_K0LOCK, 1); @@ -1305,19 +1304,22 @@ static void hex_k0_lock(CPUHexagonState *env) } if (env->k0_lock_state =3D=3D HEX_LOCK_OWNER) { qemu_log_mask(LOG_GUEST_ERROR, - "Double k0lock at PC: 0x%" PRIx32 - ", thread may hang\n", - env->next_PC); - env->next_PC +=3D 4; + "Double k0lock at PC: 0x" TARGET_FMT_lx + ", thread may hang\n", PC); cpu_interrupt(cs, CPU_INTERRUPT_HALT); cpu_loop_exit(cs); return; } env->k0_lock_state =3D HEX_LOCK_WAITING; + /* + * next_PC has already been advanced past this packet. Rewind it + * so that the thread re-executes the k0lock when it is woken by + * the thread that releases the lock. + */ + env->next_PC =3D PC; cpu_interrupt(cs, CPU_INTERRUPT_HALT); cpu_loop_exit(cs); } else { - env->next_PC +=3D 4; env->k0_lock_count++; env->k0_lock_state =3D HEX_LOCK_OWNER; SET_SYSCFG_FIELD(env, SYSCFG_K0LOCK, 1); --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778791; cv=none; d=zohomail.com; s=zohoarc; b=J/XCQcWTZRwoJQbSDmUXNh3cPMNzMIHua3Rf5YswaSsE9FSBCdgBvpKvQ47Mc4xjT8mAuYvgctomwOBZGZTWytiW//5bDLk5DjC8bI2XHWK6R56TVDNktRSaz0GZjvlv8o0EOXgp4PuqOILutSwUsQb8A+qJYiUVEQsUEoHH8Sk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778791; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RTMCN9jO0imXNzcpvUZtXCB2q0tRI4HTCcxMo6tiL7c=; b=br3kVr6pWNpcnQTy5sWrYNmzrKaG+f093KP4r3JEVoXnEq++Kp0Zg9SRp8wqauZIC0yR33Qd7VI5BNSua7espGyPBK4yiaBMUfRV1//QUDIqzNIff1U6l/J/nxfah305+n+ATe7UPgCOfLY5szNlnrSiKq9U4Psf0jRAXvLbPt4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778791211706.0857008142303; Sun, 11 Oct 2026 21:19:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7To-0001tN-Sr; Mon, 12 Oct 2026 00:17:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tn-0001st-3l for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:39 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tj-00017B-2x for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:38 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lDg2052406 for ; Mon, 12 Oct 2026 04:17:30 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7en9vg1r-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:17:30 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-35a04491c56so697315eec.0 for ; Sun, 11 Oct 2026 21:17:30 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778792953158500 Preload hex_gpr[HEX_REG_PC] with the next packet's address instead of staging it in a separate next_PC global; nothing reads the architectural PC mid-packet. Removes hex_next_PC, next_PC, and need_next_pc. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 - target/hexagon/translate.h | 2 -- target/hexagon/cpu.c | 1 - target/hexagon/genptr.c | 14 +++----------- target/hexagon/hex_mmu.c | 4 ++-- target/hexagon/machine.c | 1 - target/hexagon/op_helper.c | 6 +++--- target/hexagon/translate.c | 27 ++++++++++++++------------- 8 files changed, 22 insertions(+), 34 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index df4c0182247..14d769c972d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -153,7 +153,6 @@ typedef struct CPUArchState { uint32_t k0_lock_count; uint64_t t_cycle_count; #endif - uint32_t next_PC; uint32_t imprecise_exception; target_ulong new_value_usr; =20 diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index e17261761b2..3fb3b550c9c 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -85,7 +85,6 @@ typedef struct DisasContext { DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; bool need_commit; - bool need_next_pc; TCGCond branch_cond; target_ulong branch_dest; bool is_tight_loop; @@ -352,7 +351,6 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_slot_cancelled; extern TCGv hex_new_value_usr; -extern TCGv hex_next_PC; extern TCGv hex_store_addr[STORES_MAX]; extern TCGv_i32 hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1f7d8a8df70..2ff697da134 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -454,7 +454,6 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) env->k0_lock_state =3D HEX_LOCK_UNLOCKED; env->tlb_lock_count =3D 0; env->k0_lock_count =3D 0; - env->next_PC =3D 0; =20 env->t_sreg[HEX_SREG_HTID] =3D cpu->htid; env->threadId =3D cpu->htid; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index cd4ae2f6838..c8e69eb273f 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -748,22 +748,14 @@ static void gen_write_new_pc_addr(DisasContext *ctx, = TCGv addr, tcg_gen_brcondi_tl(cond, pred, 1, pred_false); } =20 - /* - * If gen_end_tb() will unconditionally overwrite PC with hex_next_PC - * (because this packet has a predicated COF that may not execute), - * write the branch target there instead of directly into the PC - * global, or the overwrite in gen_end_tb() would clobber it. - */ - TCGv pc_wr =3D ctx->need_next_pc ? hex_next_PC : hex_gpr[HEX_REG_PC]; - if (ctx->pkt.pkt_has_multi_cof) { /* If there are multiple branches in a packet, ignore the second o= ne */ - tcg_gen_movcond_tl(TCG_COND_NE, pc_wr, + tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC], ctx->branch_taken, tcg_constant_tl(0), - pc_wr, addr); + hex_gpr[HEX_REG_PC], addr); tcg_gen_movi_tl(ctx->branch_taken, 1); } else { - tcg_gen_mov_tl(pc_wr, addr); + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr); } =20 if (cond !=3D TCG_COND_ALWAYS) { diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index a8e4d7f2c5e..7d5fb987e18 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -185,11 +185,11 @@ void hex_tlb_lock(CPUHexagonState *env, uint32_t PC) } env->tlb_lock_state =3D HEX_LOCK_WAITING; /* - * next_PC has already been advanced past this packet. Rewind it + * The PC has already been advanced past this packet. Rewind it * so that the thread re-executes the tlblock when it is woken by * the thread that releases the lock. */ - env->next_PC =3D PC; + env->gpr[HEX_REG_PC] =3D PC; CPUState *cs =3D env_cpu(env); cpu_interrupt(cs, CPU_INTERRUPT_HALT); } else { diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index 179b6f53a2a..4d5634db7e2 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -29,7 +29,6 @@ const VMStateDescription vmstate_hexagon_cpu =3D { VMSTATE_UINT32_ARRAY(env.pred, HexagonCPU, NUM_PREGS), VMSTATE_UINT32_ARRAY(env.t_sreg, HexagonCPU, NUM_SREGS), VMSTATE_UINT32_ARRAY(env.greg, HexagonCPU, NUM_GREGS), - VMSTATE_UINT32(env.next_PC, HexagonCPU), VMSTATE_UINT32(env.tlb_lock_state, HexagonCPU), VMSTATE_UINT32(env.k0_lock_state, HexagonCPU), VMSTATE_UINT32(env.tlb_lock_count, HexagonCPU), diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 3de6b994b8f..097f79068af 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1312,11 +1312,11 @@ static void hex_k0_lock(CPUHexagonState *env, uint3= 2_t PC) } env->k0_lock_state =3D HEX_LOCK_WAITING; /* - * next_PC has already been advanced past this packet. Rewind it + * The PC has already been advanced past this packet. Rewind it * so that the thread re-executes the k0lock when it is woken by * the thread that releases the lock. */ - env->next_PC =3D PC; + env->gpr[HEX_REG_PC] =3D PC; cpu_interrupt(cs, CPU_INTERRUPT_HALT); cpu_loop_exit(cs); } else { @@ -1892,7 +1892,7 @@ void HELPER(setimask)(CPUHexagonState *env, uint32_t = tid, uint32_t imask) } qemu_log_mask(LOG_GUEST_ERROR, "setimask used with an invalid tid near PC: 0x%" - PRIx32 "\n", env->next_PC); + PRIx32 "\n", env->gpr[HEX_REG_PC]); } =20 void HELPER(sreg_write_masked)(CPUHexagonState *env, uint32_t reg, uint32_= t val) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 827859e052c..1b7427f7485 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,7 +54,6 @@ static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = =3D { TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; TCGv hex_slot_cancelled; -TCGv hex_next_PC; TCGv hex_new_value_usr; TCGv hex_store_addr[STORES_MAX]; TCGv_i32 hex_store_width[STORES_MAX]; @@ -190,16 +189,10 @@ static void gen_goto_tb(DisasContext *ctx, unsigned t= b_slot_idx, } } =20 -static bool need_next_PC(DisasContext *ctx); - static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); =20 - if (ctx->need_next_pc) { - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); - } - if (ctx->branch_cond !=3D TCG_COND_NEVER) { if (ctx->branch_cond !=3D TCG_COND_ALWAYS) { TCGLabel *skip =3D gen_new_label(); @@ -410,7 +403,13 @@ static bool pkt_ends_tb(Packet *pkt) } =20 =20 -static bool need_next_PC(DisasContext *ctx) +/* + * True when the PC has to be preloaded with the address of the next packet + * before the packet runs: either a conditional change-of-flow leaves it + * untouched when the condition fails, or the packet ends the TB without + * any change-of-flow to advance it. + */ +static bool need_pc_preload(DisasContext *ctx) { Packet *pkt =3D &ctx->pkt; if (pkt->pkt_has_cof || ctx->pkt_ends_tb) { @@ -714,9 +713,12 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(ctx->branch_taken, 0); } ctx->pkt_ends_tb =3D pkt_ends_tb(&ctx->pkt); - ctx->need_next_pc =3D need_next_PC(ctx); - if (ctx->need_next_pc) { - tcg_gen_movi_tl(hex_next_PC, ctx->next_PC); + /* + * Any change-of-flow in this packet overwrites the preloaded value, a= nd + * the k0lock/tlblock helpers rewind it when the lock is contested. + */ + if (need_pc_preload(ctx)) { + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); } =20 /* Preload the predicated registers into get_result_gpr(ctx, i) */ @@ -1446,8 +1448,6 @@ void hexagon_translate_init(void) } hex_new_value_usr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); - hex_next_PC =3D tcg_global_mem_new(tcg_env, - offsetof(CPUHexagonState, next_PC), "next_PC"); =20 for (i =3D 0; i < NUM_PREGS; i++) { hex_pred[i] =3D tcg_global_mem_new(tcg_env, @@ -1470,6 +1470,7 @@ void hexagon_translate_init(void) hex_imprecise_exception =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, imprecise_exception), "imprecise_excepti= on"); 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Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 - target/hexagon/gen_tcg_sys.h | 2 +- target/hexagon/helper.h | 2 +- target/hexagon/cpu.c | 1 - target/hexagon/cpu_helper.c | 8 -------- target/hexagon/hex_interrupts.c | 4 +--- target/hexagon/hexswi.c | 2 +- target/hexagon/machine.c | 1 - target/hexagon/op_helper.c | 7 +++---- 9 files changed, 7 insertions(+), 21 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 14d769c972d..f02a984508a 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -143,7 +143,6 @@ typedef struct CPUArchState { uint32_t t_sreg[NUM_SREGS]; =20 uint32_t greg[NUM_GREGS]; - uint32_t wait_next_pc; =20 /* This alias of CPUState.cpu_index is used by imported sources: */ uint32_t threadId; diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index af5032214c4..c9f6b41a877 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/target/hexagon/gen_tcg_sys.h @@ -80,7 +80,7 @@ #define fGEN_TCG_Y2_wait(SHORTCODE) \ do { \ RsV =3D RsV; \ - gen_helper_wait(tcg_env, tcg_constant_tl(ctx->pkt.pc)); \ + gen_helper_wait(tcg_env); \ } while (0) =20 #define fGEN_TCG_Y2_resume(SHORTCODE) \ diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 71c8da4c46d..997d87e38e6 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -136,7 +136,7 @@ DEF_HELPER_3(sreg_write_masked, void, env, i32, i32) DEF_HELPER_3(setprio, void, env, i32, i32) DEF_HELPER_2(start, void, env, i32) DEF_HELPER_1(stop, void, env) -DEF_HELPER_2(wait, void, env, i32) +DEF_HELPER_1(wait, void, env) DEF_HELPER_2(resume, void, env, i32) DEF_HELPER_1(resched, void, env) DEF_HELPER_3(modify_ssr, void, env, i32, i32) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 2ff697da134..8a82d46c1a0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -449,7 +449,6 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) #ifndef CONFIG_USER_ONLY memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS); memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS); - env->wait_next_pc =3D 0; env->tlb_lock_state =3D HEX_LOCK_UNLOCKED; env->k0_lock_state =3D HEX_LOCK_UNLOCKED; env->tlb_lock_count =3D 0; diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index cf0762ff05f..0f999a48ac7 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -215,14 +215,6 @@ static void hexagon_resume_thread(CPUHexagonState *env) { CPUState *cs =3D env_cpu(env); clear_wait_mode(env); - /* - * The wait instruction keeps the PC pointing to itself - * so that it has an opportunity to check for interrupts. - * - * When we come out of wait mode, adjust the PC to the - * next executable instruction. - */ - env->gpr[HEX_REG_PC] =3D env->wait_next_pc; cs =3D env_cpu(env); ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index); cs->halted =3D false; diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupt= s.c index 0b714b73831..ab66d548a1e 100644 --- a/target/hexagon/hex_interrupts.c +++ b/target/hexagon/hex_interrupts.c @@ -349,14 +349,12 @@ static void hex_accept_int(CPUHexagonState *env, int = int_num) qemu_log_mask(CPU_LOG_INT, "%s: thread " TARGET_FMT_ld " resuming, exiting WAIT mode\n", __func__, env->threadId); - elr =3D env->wait_next_pc; clear_wait_mode(env); cs->halted =3D false; } else if (env->k0_lock_state =3D=3D HEX_LOCK_WAITING) { g_assert_not_reached(); - } else { - elr =3D env->gpr[HEX_REG_PC]; } + elr =3D env->gpr[HEX_REG_PC]; =20 if (int_should_dtg(env, int_num)) { int vic_group =3D int_num - 2; diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index 4705e915aea..ef1d558dfc4 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -936,7 +936,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs) case HEX_EVENT_IMPRECISE: env->imprecise_exception =3D 0; if (get_exe_mode(env) =3D=3D HEX_EXE_MODE_WAIT) { - env->gpr[HEX_REG_PC] =3D env->wait_next_pc - 4; + env->gpr[HEX_REG_PC] -=3D 4; clear_wait_mode(env); } switch (env->cause_code) { diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index 4d5634db7e2..f3e97224d81 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -35,7 +35,6 @@ const VMStateDescription vmstate_hexagon_cpu =3D { VMSTATE_UINT32(env.k0_lock_count, HexagonCPU), VMSTATE_UINT32(env.threadId, HexagonCPU), VMSTATE_UINT32(env.cause_code, HexagonCPU), - VMSTATE_UINT32(env.wait_next_pc, HexagonCPU), VMSTATE_UINT64(env.t_cycle_count, HexagonCPU), VMSTATE_UINT32(env.imprecise_exception, HexagonCPU), =20 diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 097f79068af..c582803edce 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1743,7 +1743,7 @@ static void set_wait_mode(CPUHexagonState *env) SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_W, thread_wait_mask); } =20 -static void hexagon_wait_thread(CPUHexagonState *env, uint32_t PC) +static void hexagon_wait_thread(CPUHexagonState *env) { CPUState *cs; =20 @@ -1770,7 +1770,6 @@ static void hexagon_wait_thread(CPUHexagonState *env,= uint32_t PC) return; } set_wait_mode(env); - env->wait_next_pc =3D PC + 4; =20 cpu_interrupt(cs, CPU_INTERRUPT_HALT); } @@ -1838,12 +1837,12 @@ void HELPER(resched)(CPUHexagonState *env) resched(env); } =20 -void HELPER(wait)(CPUHexagonState *env, uint32_t PC) +void HELPER(wait)(CPUHexagonState *env) { BQL_LOCK_GUARD(); =20 if (!fIN_DEBUG_MODE(env->threadId)) { - hexagon_wait_thread(env, PC); + hexagon_wait_thread(env); } } =20 --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- configs/targets/hexagon-softmmu.mak | 2 +- gdbstub/gdb-xml/hexagon-sys.xml | 157 ++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 gdbstub/gdb-xml/hexagon-sys.xml diff --git a/configs/targets/hexagon-softmmu.mak b/configs/targets/hexagon-= softmmu.mak index 6cbdc64be56..1ba6420d205 100644 --- a/configs/targets/hexagon-softmmu.mak +++ b/configs/targets/hexagon-softmmu.mak @@ -1,7 +1,7 @@ # Default configuration for hexagon-softmmu =20 TARGET_ARCH=3Dhexagon -TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml +TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml hexagon-sys.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/gdbstub/gdb-xml/hexagon-sys.xml b/gdbstub/gdb-xml/hexagon-sys.= xml new file mode 100644 index 00000000000..273850a733f --- /dev/null +++ b/gdbstub/gdb-xml/hexagon-sys.xml @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778719; cv=none; d=zohomail.com; s=zohoarc; b=dOKSn5W7CEl9XclS3ivOs4RiP9wGqU0x47Xbn38tjmIykJqbJjFP+BIZli1iFSXe33D2UQR5QNW1Sv56nS3AMGrQYUKzJIJsDsUeslTQYXHn8ed1UJm1p5aIne2DuNM+6x2+ua6hqQM5eXEB3YofQy/fth5F0CnScYw/G90zKjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778719; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=A0vU/H3jz+KbcHqs/xaFNhD+3bg12UCLlwyd+eL840o=; b=erdgbAHk6N11hrbjiHuGW7608JhQ8BsyxJ3fhTVNT/GY0pc1xtWsNVgM6i9E8t+u6eIwhohSDFo8UegjNA2oNCTWuWierdJ9kw9xVw/gWSn7CTYUYBYWR8GeV1ZMhayON+U9azCRlxdOxUX6HXBSBccoMOGDfsv2NX7UJfyP65I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778719355301.4255633643006; Sun, 11 Oct 2026 21:18:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7U0-0001vX-Hy; Mon, 12 Oct 2026 00:17:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tp-0001u4-Eo for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:43 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tl-00017g-JT for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:39 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lEOe052432 for ; Mon, 12 Oct 2026 04:17:36 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7en9vg27-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:17:36 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-30c0d568830so3542380eec.1 for ; Sun, 11 Oct 2026 21:17:36 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/internal.h | 4 +++ target/hexagon/cpu.c | 13 ++++++-- target/hexagon/gdbstub.c | 63 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index f02a984508a..6979c153f5d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -239,6 +239,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, */ bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); +void hexagon_greg_write(CPUHexagonState *env, uint32_t reg, uint32_t val); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif =20 diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 05d1129916e..3ed83904eb7 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -24,6 +24,10 @@ int hexagon_gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int = n); int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n= ); +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +#endif =20 void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 8a82d46c1a0..609409e32d0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -492,6 +492,10 @@ static void hexagon_cpu_realize(DeviceState *dev, Erro= r **errp) gdb_find_static_feature("hexagon-hvx.xml")); =20 #ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, hexagon_sys_gdb_read_register, + hexagon_sys_gdb_write_register, + gdb_find_static_feature("hexagon-sys.xml")); + if (!HEXAGON_CPU(dev)->tlb) { error_setg(errp, "hexagon cpu requires 'tlb' link property to be s= et"); return; @@ -856,11 +860,14 @@ uint32_t hexagon_greg_read(CPUHexagonState *env, uint= 32_t reg) case HEX_GREG_GPCYCLEHI: return ssr_ce ? hexagon_get_sys_pcycle_count_high(env) : 0; default: - qemu_log_mask(LOG_UNIMP, "reading greg %" PRId32 - " not yet supported.\n", reg); - return 0; + return env->greg[reg]; } } + +void hexagon_greg_write(CPUHexagonState *env, uint32_t reg, uint32_t val) +{ + env->greg[reg] =3D val; +} #endif =20 static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data) diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 76ab5235f6e..30b4d710cdb 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -16,9 +16,14 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "gdbstub/helpers.h" #include "cpu.h" #include "internal.h" +#ifndef CONFIG_USER_ONLY +#include "cpu_helper.h" +#include "hw/hexagon/hexagon_globalreg.h" +#endif =20 int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { @@ -76,6 +81,64 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) g_assert_not_reached(); } =20 +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + CPUHexagonState *env =3D cpu_env(cs); + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); + + if (n < NUM_SREGS) { + uint32_t val; + if (n < HEX_SREG_GLB_START) { + val =3D env->t_sreg[n]; + } else { + val =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, n, env->threadId) = : 0; + } + return gdb_get_regl(mem_buf, val); + } + n -=3D NUM_SREGS; + + if (n < NUM_GREGS) { + return gdb_get_regl(mem_buf, hexagon_greg_read(env, n)); + } + n -=3D NUM_GREGS; + + g_assert_not_reached(); +} + +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CPUHexagonState *env =3D cpu_env(cs); + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); + + if (n < NUM_SREGS) { + uint32_t val =3D ldl_le_p(mem_buf); + if (n =3D=3D HEX_SREG_SSR) { + uint32_t old =3D env->t_sreg[HEX_SREG_SSR]; + env->t_sreg[HEX_SREG_SSR] =3D val; + hexagon_modify_ssr(env, val, old); + } else if (n < HEX_SREG_GLB_START) { + env->t_sreg[n] =3D val; + } else if (cpu->globalregs) { + hexagon_globalreg_write(cpu->globalregs, n, val, env->threadId= ); + } + return sizeof(uint32_t); + } + n -=3D NUM_SREGS; + + if (n < NUM_GREGS) { + hexagon_greg_write(env, n, ldl_le_p(mem_buf)); + return sizeof(uint32_t); + } + n -=3D NUM_GREGS; + + g_assert_not_reached(); +} +#endif + static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n) { int total =3D 0; --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778786; cv=none; d=zohomail.com; s=zohoarc; b=hu+yxRNwzQq3XkE4ehN5cXtBFP7MLPKM+nFy5M3UFCbnkYLX0tLlDmDVpd5j/ag6cg3iURWn+AH/+071IOdUYqOssoffi6DiLoQldu3tj/7aNBbW7W6J2DLc8t9NxxGNLFdpWOByw4B/TxyT33wtfounjKWYgZ8ltpXTvIeNimk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778786; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=as/L4AtVMJ2a3YTgAo6jVh3GWQGz87dkg6Y0W6CHNcw=; b=jyo0erzoWFgvV7ln3i6vi91XlwlkENWZHenn5kjwxRCaRwp+hfJmS3Zi9sCdOVZOFqjLmEiKnegIHuda1r9lo8C2twzHa0CkE/G7Ss26yWhbO/fPJ1agboftZf68+xQWWuqt2VgaOQMpwZgyalTbHRmC33TBWsZlH9CVkZGXZFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778786917568.4077697151632; Sun, 11 Oct 2026 21:19:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7U6-0001wJ-M9; Mon, 12 Oct 2026 00:17:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tt-0001uk-3f for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:46 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tp-000187-73 for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:44 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lRNW3646369 for ; Mon, 12 Oct 2026 04:17:38 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7ehjmht5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:17:38 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-30c0d568830so3542405eec.1 for ; Sun, 11 Oct 2026 21:17:38 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778788790158500 Use sizeof_field(MMVector, ub) for vector-payload storage and sizeof(MMQReg) for predicate storage. This makes the intent clearer and binds to the field instead of a max-size constant. In particular, these bounds exclude MMVector.ext, the QFloat extended-preci= sion bits. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/mmvec/mmvec.h | 4 ++-- target/hexagon/cpu.c | 12 ++++++------ target/hexagon/gdbstub.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 6979c153f5d..188a91e8823 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -103,7 +103,7 @@ typedef struct { typedef struct { target_ulong va; int size; - DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); + DECLARE_BITMAP(mask, sizeof_field(MMVector, ub)) QEMU_ALIGNED(16); MMVector data QEMU_ALIGNED(16); } VStoreLog; =20 diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index 662f9d1597e..ed2321be920 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -89,8 +89,8 @@ static inline uint8_t hexagon_mmqreg_get_byte(const MMQRe= g *q, size_t index) =20 typedef struct { MMVector data; - DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES); - target_ulong va[MAX_VEC_SIZE_BYTES]; + DECLARE_BITMAP(mask, sizeof_field(MMVector, ub)); + uint32_t va[sizeof_field(MMVector, ub)]; bool op; int op_size; } VTCMStoreLog; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 609409e32d0..a74eaa45fc2 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -191,7 +191,7 @@ static void print_vreg(FILE *f, CPUHexagonState *env, i= nt regnum, { if (skip_if_zero) { bool nonzero_found =3D false; - for (int i =3D 0; i < MAX_VEC_SIZE_BYTES; i++) { + for (int i =3D 0; i < sizeof_field(MMVector, ub); i++) { if (hexagon_mmvec_get_byte(&hex_hvx(env)->VRegs[regnum], i) != =3D 0) { nonzero_found =3D true; break; @@ -205,8 +205,8 @@ static void print_vreg(FILE *f, CPUHexagonState *env, i= nt regnum, qemu_fprintf(f, " v%d =3D ( ", regnum); qemu_fprintf(f, "0x%02x", hexagon_mmvec_get_byte(&hex_hvx(env)->VRegs[regnum], - MAX_VEC_SIZE_BYTES - 1)); - for (int i =3D MAX_VEC_SIZE_BYTES - 2; i >=3D 0; i--) { + sizeof_field(MMVector, ub) - 1)); + for (int i =3D sizeof_field(MMVector, ub) - 2; i >=3D 0; i--) { qemu_fprintf(f, ", 0x%02x", hexagon_mmvec_get_byte(&hex_hvx(env)->VRegs[regnum], = i)); } @@ -223,7 +223,7 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, { if (skip_if_zero) { bool nonzero_found =3D false; - for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { + for (int i =3D 0; i < sizeof(MMQReg); i++) { if (hexagon_mmqreg_get_byte(&hex_hvx(env)->QRegs[regnum], i) != =3D 0) { nonzero_found =3D true; break; @@ -237,8 +237,8 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, qemu_fprintf(f, " q%d =3D ( ", regnum); qemu_fprintf(f, "0x%02x", hexagon_mmqreg_get_byte(&hex_hvx(env)->QRegs[regnum], - MAX_VEC_SIZE_BYTES / 8 - 1)); - for (int i =3D MAX_VEC_SIZE_BYTES / 8 - 2; i >=3D 0; i--) { + sizeof(MMQReg) - 1)); + for (int i =3D sizeof(MMQReg) - 2; i >=3D 0; i--) { qemu_fprintf(f, ", 0x%02x", hexagon_mmqreg_get_byte(&hex_hvx(env)->QRegs[regnum],= i)); } diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 30b4d710cdb..ca6d4a98369 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -183,7 +183,7 @@ static int gdb_put_vreg(CPUHexagonState *env, uint8_t *= mem_buf, int n) hex_hvx(env)->VRegs[n].uw[i] =3D ldl_le_p(mem_buf); mem_buf +=3D 4; } - return MAX_VEC_SIZE_BYTES; + return sizeof_field(MMVector, ub); } =20 static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) @@ -193,7 +193,7 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *= mem_buf, int n) hex_hvx(env)->QRegs[n].uw[i] =3D ldl_le_p(mem_buf); mem_buf +=3D 4; } - return MAX_VEC_SIZE_BYTES / 8; + return sizeof(MMQReg); } =20 int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778733; cv=none; d=zohomail.com; s=zohoarc; b=P1Idp1x7iQztuc07qadT3tkhzZSE6CCAXvh068aCXgBDqadkMN82S+1UU98eC821yT8tMZvbr/fUkciFweun9KeqWVT1RS1Y4lUhCdzkgd2tN/ynay5WlyQxUUy7vL7GHQVZgv8PbwozdmlMtoD1lgAqaYYWfySCa4B+ytgzMLE= ARC-Message-Signature: i=1; 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Cc: Taylor Simpson Reviewed-by: Taylor Simpson Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.h | 20 ++++++++++++-------- target/hexagon/translate.c | 31 ++++++++++++++++++++----------- target/hexagon/hex_common.py | 8 ++++++-- 3 files changed, 38 insertions(+), 21 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 3fb3b550c9c..2d1ed5208b7 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -81,6 +81,7 @@ typedef struct DisasContext { int qreg_log_idx; DECLARE_BITMAP(qregs_written, NUM_QREGS); DECLARE_BITMAP(qregs_multi_write, NUM_QREGS); + DECLARE_BITMAP(qregs_uncond, NUM_QREGS); DECLARE_BITMAP(insn_qregs_written, NUM_QREGS); DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; @@ -236,12 +237,13 @@ static inline void ctx_log_vreg_write(DisasContext *c= tx, ctx->has_hvx_overlap =3D true; } } - if (!test_bit(rnum, ctx->vregs_written)) { - set_bit(rnum, ctx->vregs_written); - } else { - set_bit(rnum, ctx->vregs_multi_write); - } + if (type !=3D EXT_TMP) { + if (!test_bit(rnum, ctx->vregs_written)) { + set_bit(rnum, ctx->vregs_written); + } else { + set_bit(rnum, ctx->vregs_multi_write); + } if (!test_bit(rnum, ctx->vregs_updated)) { ctx->vreg_log[ctx->vreg_log_idx] =3D rnum; ctx->vreg_log_idx++; @@ -262,8 +264,6 @@ static inline void ctx_log_vreg_write(DisasContext *ctx, set_bit(rnum, ctx->vregs_updated_tmp); if (is_predicated) { set_bit(rnum, ctx->predicated_tmp_vregs); - } else { - set_bit(rnum, ctx->vregs_uncond); } } } @@ -316,7 +316,8 @@ static inline void ctx_log_vreg_read_pair(DisasContext = *ctx, int rnum, } =20 static inline void ctx_log_qreg_write(DisasContext *ctx, - int rnum, bool has_helper) + int rnum, bool predicated, + bool has_helper) { if (has_helper) { set_bit(rnum, ctx->insn_qregs_written); @@ -329,6 +330,9 @@ static inline void ctx_log_qreg_write(DisasContext *ctx, } else { set_bit(rnum, ctx->qregs_multi_write); } + if (!predicated) { + set_bit(rnum, ctx->qregs_uncond); + } ctx->qreg_log[ctx->qreg_log_idx] =3D rnum; ctx->qreg_log_idx++; } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 1b7427f7485..6715758bfa0 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -608,6 +608,7 @@ static void clear_pkt_ctx(DisasContext *ctx) bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); bitmap_zero(ctx->qregs_written, NUM_QREGS); bitmap_zero(ctx->qregs_multi_write, NUM_QREGS); + bitmap_zero(ctx->qregs_uncond, NUM_QREGS); ctx->qreg_log_idx =3D 0; for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; @@ -625,7 +626,6 @@ static void clear_pkt_ctx(DisasContext *ctx) static bool pkt_has_write_conflict(DisasContext *ctx) { DECLARE_BITMAP(gpr_conflict, TOTAL_PER_THREAD_REGS); - DECLARE_BITMAP(vregs_conflict, NUM_VREGS); =20 bitmap_and(gpr_conflict, ctx->gpr_multi_write, ctx->gpr_uncond, TOTAL_PER_THREAD_REGS); @@ -633,16 +633,6 @@ static bool pkt_has_write_conflict(DisasContext *ctx) return true; } =20 - bitmap_and(vregs_conflict, ctx->vregs_multi_write, ctx->vregs_uncond, - NUM_VREGS); - if (!bitmap_empty(vregs_conflict, NUM_VREGS)) { - return true; - } - - if (!bitmap_empty(ctx->qregs_multi_write, NUM_QREGS)) { - return true; - } - #ifndef CONFIG_USER_ONLY if (!bitmap_empty(ctx->gregs_multi_write, NUM_GREGS)) { return true; @@ -656,6 +646,19 @@ static bool pkt_has_write_conflict(DisasContext *ctx) return false; } =20 +static bool pkt_has_hvx_write_conflict(DisasContext *ctx) +{ + DECLARE_BITMAP(vregs_conflict, NUM_VREGS); + DECLARE_BITMAP(qregs_conflict, NUM_QREGS); + + bitmap_and(vregs_conflict, ctx->vregs_multi_write, ctx->vregs_uncond, + NUM_VREGS); + bitmap_and(qregs_conflict, ctx->qregs_multi_write, ctx->qregs_uncond, + NUM_QREGS); + return !bitmap_empty(vregs_conflict, NUM_VREGS) || + !bitmap_empty(qregs_conflict, NUM_QREGS); +} + static void analyze_packet(DisasContext *ctx) { ctx->read_after_write =3D false; @@ -1277,6 +1280,12 @@ static void decode_and_translate_packet(CPUHexagonSt= ate *env, DisasContext *ctx) clear_pkt_ctx(ctx); analyze_packet(ctx); =20 + if (pkt_has_hvx_write_conflict(ctx)) { + qemu_log_mask(LOG_GUEST_ERROR, + "multiple HVX register writes at PC 0x" TARGET_F= MT_lx + "\n", ctx->pkt.pc); + } + if (pkt_has_write_conflict(ctx)) { gen_exception_decode_fail(ctx, words_read, HEX_CAUSE_REG_WRITE_CONFLICT); diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 02c54506145..d344284e8a2 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1069,8 +1069,10 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) def analyze_write(self, f, tag, regno): + predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper); + ctx_log_qreg_write(ctx, {self.reg_num}, {predicated}, + insn_has_hvx_helper); """)) =20 class QRegSource(Register, Hvx, OldSource): @@ -1117,8 +1119,10 @@ def analyze_read(self, f, regno): ctx_log_qreg_read(ctx, {self.reg_num}, insn_has_hvx_helper); """)) def analyze_write(self, f, tag, regno): + predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper); + ctx_log_qreg_write(ctx, {self.reg_num}, {predicated}, + insn_has_hvx_helper); """)) =20 class GuestRegister(Register): --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778786; cv=none; d=zohomail.com; s=zohoarc; b=lFywoqTBbU/pabS1cBsvriwdoex8psMnKyrxs25lhhREGUp5kRsyIbVcd67r7O0R7EkuScpZZmOYsxQQny0aw/ZQrzIB6FDh35uZ+5PZqU4mJbp9abcOZOELsKXDETrlNCGDa+Obmcsd7e+9oEZX+o9og6259y91HKwYdVc+/+c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778786; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778786927158500 Cc: Taylor Simpson Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- tests/tcg/hexagon/multiple-writes.c | 107 +++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 3 deletions(-) diff --git a/tests/tcg/hexagon/multiple-writes.c b/tests/tcg/hexagon/multip= le-writes.c index bd2b1384dd9..9ca5adf76ad 100644 --- a/tests/tcg/hexagon/multiple-writes.c +++ b/tests/tcg/hexagon/multiple-writes.c @@ -13,6 +13,7 @@ =20 #include #include +#include #include #include #include @@ -223,6 +224,83 @@ static int test_vreg_legal_predicated(void) return sig; } =20 +/* + * Complementary predicated writes to the same V-register pair are legal. + * v16 and v22 are splatted with distinct patterns; since p0 is always + * true, v14 must end up holding v16's pattern. Extracting a word from + * v14 confirms the executed branch actually ran, rather than merely that + * no SIGILL was raised. + */ +static int test_vreg_pair_legal_predicated(void) +{ + int sig; + uint32_t result; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%[resume_pc]) =3D r1\n" + "r4 =3D #0x11111111\n" + "r5 =3D #0x22222222\n" + "v16 =3D vsplat(r4)\n" + "v22 =3D vsplat(r5)\n" + "r4 =3D #0\n" + "p0 =3D cmp.eq(r0, r0)\n" + "{\n" + " if (p0) v15:14 =3D vcombine(v22, v16)\n" + " if (!p0) v15:14 =3D vcombine(v16, v22)\n" + "}\n" + "%[result] =3D vextract(v14, r4)\n" + "1:\n" + "%[sig] =3D r0\n" + : [sig] "=3Dr"(sig), [result] "=3Dr"(result) + : [resume_pc] "r"(&resume_pc) + : "r0", "r1", "r4", "r5", "p0", + "v14", "v15", "v16", "v22", "memory"); + + return sig =3D=3D SIGILL ? SIGILL : result; +} + +/* + * A future write may consume a temporary value from the same V-register. + * buf is zeroed while v0 is initialized non-zero, so v0.tmp loads all-zero + * and v0.w =3D vadd(v0.tmp.w, 1) must end up as 1 in every word. Extract= ing + * a word from the result + * confirms the add actually used the loaded .tmp value, rather than + * merely that no SIGILL was raised. + */ +static int test_vreg_legal_tmp(void) +{ + long long buf[16] __attribute__((aligned(128))); + int sig; + uint32_t result; + + memset(buf, 0, sizeof(buf)); + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%[resume_pc]) =3D r1\n" + "r2 =3D %[buf]\n" + "r3 =3D #1\n" + "r4 =3D #0\n" + "r5 =3D #2\n" + "v0 =3D vsplat(r5)\n" + "v1 =3D vsplat(r3)\n" + "{\n" + " v0.tmp =3D vmem(r2 + #0)\n" + " v0.w =3D vadd(v0.w, v1.w)\n" + "}\n" + "%[result] =3D vextract(v0, r4)\n" + "1:\n" + "%[sig] =3D r0\n" + : [sig] "=3Dr"(sig), [result] "=3Dr"(result) + : [resume_pc] "r"(&resume_pc), [buf] "r"(buf) + : "r0", "r1", "r2", "r3", "r4", "r5", "v0", "v1", "memory"); + + return sig =3D=3D SIGILL ? SIGILL : result; +} + static int test_vreg_illegal_mixed(void) { int sig; @@ -242,6 +320,26 @@ static int test_vreg_illegal_mixed(void) return sig; } =20 +/* A pair write and a single write to either pair member are illegal. */ +static int test_vreg_illegal_pair_overlap(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%[resume_pc]) =3D r1\n" + ".word 0x1f5055ee /* { v15:14 =3D vcombine(v21, v16) */\n" + ".word 0x1e03e5ee /* v14 =3D v5 } */\n" + "1:\n" + "%[sig] =3D r0\n" + : [sig] "=3Dr"(sig) + : [resume_pc] "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + static int test_vreg_illegal_uncond(void) { int sig; @@ -308,10 +406,13 @@ int main() assert(test_post_increment3() =3D=3D SIGILL); =20 assert(test_vreg_legal_predicated() =3D=3D 23); - assert(test_vreg_illegal_mixed() =3D=3D SIGILL); - assert(test_vreg_illegal_uncond() =3D=3D SIGILL); + assert(test_vreg_pair_legal_predicated() =3D=3D 0x11111111); + assert(test_vreg_legal_tmp() =3D=3D 1); + assert(test_vreg_illegal_mixed() =3D=3D 0); + assert(test_vreg_illegal_pair_overlap() =3D=3D 0); + assert(test_vreg_illegal_uncond() =3D=3D 0); =20 - assert(test_qreg_illegal() =3D=3D SIGILL); + assert(test_qreg_illegal() =3D=3D 0); =20 puts("PASS"); return EXIT_SUCCESS; --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778823; cv=none; d=zohomail.com; s=zohoarc; b=j2QaG9NUt7/rMnobykvSm0mN6KeHf+BKKGMygqNthXYdDHM16VLa0hg7ZawEL9sbCa6OtZnefhITLb12mbs63n+xdj+JZYy4cFNhycJ/Eri/6XslEPIXOvieFySzBSbodlDVQ+DbUPj1PsdEJi1IemNnF0TH3AB4cbdx6DaAxJc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778823; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/qPB/lz4cEH2iF0TEAnHbFbqsJdvHXcPZszjzcXomhk=; b=INQD70/sL3qvO9rQTIH86wVuYMgti2YvlVPDy07gmwklL6FFxcft5b7ySTFCgbWrOftvUUQcHX4AAcRE5bebybq3xOGfu6W44wL3KR6qj+iFn4BFzjh59SOYkGxSPDme2V14CYWvrkBYR0UgRhADmVZ8oDWuduoz1xtn3DDMfr8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778823135472.9398327652309; Sun, 11 Oct 2026 21:20:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7Ud-0001zZ-Jx; Mon, 12 Oct 2026 00:18:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Tv-0001vB-4j for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:47 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7Ts-000194-S8 for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:46 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lO2S328414 for ; Mon, 12 Oct 2026 04:17:43 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7e4ech9p-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:17:42 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-35a04491c56so697538eec.0 for ; Sun, 11 Oct 2026 21:17:42 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778823494158501 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/mmvec/hvx_ieee_fp.h | 2 + target/hexagon/mmvec/macros.h | 2 + target/hexagon/mmvec/hvx_ieee_fp.c | 15 ++++ target/hexagon/tag_rev_info.c.inc | 13 ++++ target/hexagon/imported/mmvec/encode_ext.def | 10 +++ target/hexagon/imported/mmvec/ext.idef | 74 ++++++++++++++++++++ 6 files changed, 116 insertions(+) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index b7e379b0893..f7ea0086683 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -31,6 +31,8 @@ int16_t conv_h_hf(float16 a, float_status *fp_status); /* IEEE - FP compare instructions */ uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status); uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status); +uint32_t cmpeq_sf(float32 a1, float32 a2, float_status *fp_status); +uint16_t cmpeq_hf(float16 a1, float16 a2, float_status *fp_status); =20 /* IEEE BFloat instructions */ =20 diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 4ac53aca0b9..74c277fc06f 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -383,5 +383,7 @@ #define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status) #define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status) #define fCMPGT_BF(A, B) fCMPGT_SF((uint32_t)(A) << 16, (uint32_t)(B) << 16) +#define fCMPEQ_SF(A, B) cmpeq_sf(A, B, &env->hvx_fp_status) +#define fCMPEQ_HF(A, B) cmpeq_hf(A, B, &env->hvx_fp_status) =20 #endif diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index d7751adbe29..230ea9a13a7 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -135,3 +135,18 @@ uint16_t cmpgt_hf(float16 a1, float16 a2, float_status= *fp_status) } return float16_compare(a1, a2, fp_status) =3D=3D float_relation_greate= r; } + +/* + * Unlike cmpgt_sf/cmpgt_hf, equality has no NaN-ordering convention to + * apply: per IEEE-754, a compare-equal predicate is quiet and always + * false when either operand is NaN. + */ +uint32_t cmpeq_sf(float32 a1, float32 a2, float_status *fp_status) +{ + return float32_eq_quiet(a1, a2, fp_status); +} + +uint16_t cmpeq_hf(float16 a1, float16 a2, float_status *fp_status) +{ + return float16_eq_quiet(a1, a2, fp_status); +} diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index 68be8cbafb2..c12896cd6c7 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -644,6 +644,19 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { [Y2_dczeroa_nt] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VE= R_NONE }, =20 [Y2_tlbpp] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, + + [V6_valign4] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_N= ONE }, + [V6_veqhf] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, + [V6_veqhf_and] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_veqhf_or] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_= NONE }, + [V6_veqhf_xor] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_veqsf] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NON= E }, + [V6_veqsf_and] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_veqsf_or] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_= NONE }, + [V6_veqsf_xor] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER= _NONE }, + [V6_vconv_h_hf_rnd] =3D { + .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NONE + }, }; =20 #endif /* HEXAGON_TAG_ARCH_TABLE_H */ diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 16f043b77dc..084ae3d8542 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -694,6 +694,7 @@ DEF_ENC(V6_vassign, ICLASS_CJ" 1 110 --0 ---= 11 PP 1 uuuuu 111 ddddd") =20 DEF_ENC(V6_valignbi, ICLASS_CJ" 1 110 001 vvvvv PP 1 uuuuu iii ddd= dd") DEF_ENC(V6_vlalignbi, ICLASS_CJ" 1 110 011 vvvvv PP 1 uuuuu iii dd= ddd") +DEF_ENC(V6_valign4,"00011000vvvvvtttPP0uuuuu101ddddd") DEF_ENC(V6_vswap, ICLASS_CJ" 1 110 101 vvvvv PP 1 uuuuu -tt dd= ddd") // DEF_ENC(V6_vmux, ICLASS_CJ" 1 110 111 vvvvv PP 1 uuuuu -tt ddd= dd") // =20 @@ -857,6 +858,7 @@ DEF_ENC(V6_vconv_sf_w,"00011110--0--101PP1uuuuu011ddddd= ") DEF_ENC(V6_vconv_w_sf,"00011110--0--101PP1uuuuu001ddddd") DEF_ENC(V6_vconv_hf_h,"00011110--0--101PP1uuuuu100ddddd") DEF_ENC(V6_vconv_h_hf,"00011110--0--101PP1uuuuu010ddddd") +DEF_ENC(V6_vconv_h_hf_rnd,"00011110--0-0110PP1uuuuu110ddddd") =20 /* IEEE FP compare instructions */ DEF_ENC(V6_vgtsf,"00011100100vvvvvPP1uuuuu011100dd") @@ -867,6 +869,14 @@ DEF_ENC(V6_vgtsf_or,"00011100100vvvvvPP1uuuuu001100xx") DEF_ENC(V6_vgthf_or,"00011100100vvvvvPP1uuuuu001101xx") DEF_ENC(V6_vgtsf_xor,"00011100100vvvvvPP1uuuuu111010xx") DEF_ENC(V6_vgthf_xor,"00011100100vvvvvPP1uuuuu111011xx") +DEF_ENC(V6_veqsf,"00011111100vvvvvPP0uuuuu000011dd") +DEF_ENC(V6_veqhf,"00011111100vvvvvPP0uuuuu000111dd") +DEF_ENC(V6_veqsf_and,"00011100100vvvvvPP1uuuuu000011xx") +DEF_ENC(V6_veqhf_and,"00011100100vvvvvPP1uuuuu000111xx") +DEF_ENC(V6_veqsf_or,"00011100100vvvvvPP1uuuuu010011xx") +DEF_ENC(V6_veqhf_or,"00011100100vvvvvPP1uuuuu010111xx") +DEF_ENC(V6_veqsf_xor,"00011100100vvvvvPP1uuuuu100011xx") +DEF_ENC(V6_veqhf_xor,"00011100100vvvvvPP1uuuuu100111xx") =20 /* BFLOAT instructions */ DEF_ENC(V6_vmpy_sf_bf,"00011101010vvvvvPP1uuuuu100ddddd") diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 857aa6133f8..e5998768b14 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -367,6 +367,18 @@ EXTINSN(V6_vlalignbi,"Vd32=3Dvlalign(Vu32,Vv32,#u3)", = ATTRIBS(A_EXTENSION,A_CVI,A_ VALIGNB(shift) }) =20 +EXTINSN(V6_valign4, "Vd32=3Dvalign4(Vu32,Vv32,Rt8)", + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC), + "In-lane align two vectors by Rt8 as control", +{ + fHIDE(int i;) + fVFOREACH(32, i) { + unsigned shift =3D 8 * (RtV & 0x3); + VdV.uw[i] =3D shift ? (VuV.uw[i] << shift) | (VvV.uw[i] >> (32 - s= hift)) + : VuV.uw[i]; + } +}) + EXTINSN(V6_vror, "Vd32=3Dvror(Vu32,Rt32)", ATTRIBS(A_EXTENSION,A_CVI,A_CVI= _VP), "Align Two vectors by Rt32 as control", { @@ -3135,6 +3147,11 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,"Vd32.h= =3DVu32.hf", "Vector conversion of hf16 format to int hw", VdV.h[i] =3D conv_h_hf(VuV.hf[i], &env->hvx_fp_status)) =20 +ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf_rnd,"Vd32.h=3DVu32.hf:rnd", + "Vector conversion of hf16 format to int hw, round to nearest even", + VdV.h[i] =3D float16_to_int16_scalbn(VuV.hf[i], float_round_nearest_ev= en, 0, + &env->hvx_fp_status)) + ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,"Vd32.sf=3DVu32.w", "Vector conversion of int w format to sf32", VdV.sf[i] =3D int32_to_float32(VuV.w[i], &env->hvx_fp_status)) @@ -3233,6 +3250,63 @@ MMVEC_CMPGT_SF(sf,"sf","Vector sf Compare ", fVELEM(= 32), 0xF, 4, sf) MMVEC_CMPGT_HF(hf,"hf","Vector hf Compare ", fVELEM(16), 0x3, 2, hf) MMVEC_CMPGT_BF(bf,"bf","Vector bf Compare ", fVELEM(16), 0x3, 2, bf) =20 +#define VCMPEQ_SF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \ +{ \ + for (fHIDE(int) i =3D 0; i < fVBYTES(); i +=3D WIDTH) { \ + fHIDE(int) VAL =3D fCMPEQ_SF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? = MASK : 0; \ + fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \ + } \ +} + +#define VCMPEQ_HF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \ +{ \ + for (fHIDE(int) i =3D 0; i < fVBYTES(); i +=3D WIDTH) { \ + fHIDE(int) VAL =3D fCMPEQ_HF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? = MASK : 0; \ + fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \ + } \ +} + +/* Vector SF compare equal */ +#define MMVEC_CMPEQ_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ + EXTINSN(V6_veq##TYPE##_and, "Qx4&=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to with predicate-and", \ + VCMPEQ_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, "=3D=3D", N, SRC, M= ASK, WIDTH)) \ + EXTINSN(V6_veq##TYPE##_xor, "Qx4^=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to with predicate-xor", \ + VCMPEQ_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, "=3D=3D", N, SRC, M= ASK, WIDTH)) \ + EXTINSN(V6_veq##TYPE##_or, "Qx4|=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE2= ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to with predicate-or", \ + VCMPEQ_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, "=3D=3D", N, SRC, M= ASK, WIDTH)) \ + EXTINSN(V6_veq##TYPE, "Qd4=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to", \ + VCMPEQ_SF(QdV, , , "=3D=3D", N, SRC, MASK, WIDTH)) + +/* Vector HF compare equal */ +#define MMVEC_CMPEQ_HF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ + EXTINSN(V6_veq##TYPE##_and, "Qx4&=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to with predicate-and", \ + VCMPEQ_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, "=3D=3D", N, SRC, M= ASK, WIDTH)) \ + EXTINSN(V6_veq##TYPE##_xor, "Qx4^=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to with predicate-xor", \ + VCMPEQ_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, "=3D=3D", N, SRC, M= ASK, WIDTH)) \ + EXTINSN(V6_veq##TYPE##_or, "Qx4|=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE2= ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to with predicate-or", \ + VCMPEQ_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, "=3D=3D", N, SRC, M= ASK, WIDTH)) \ + EXTINSN(V6_veq##TYPE, "Qd4=3Dvcmp.eq(Vu32." TYPE2 ",Vv32." TYPE2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" equal to", \ + VCMPEQ_HF(QdV, , , "=3D=3D", N, SRC, MASK, WIDTH)) + +MMVEC_CMPEQ_SF(sf,"sf","Vector sf Compare ", fVELEM(32), 0xF, 4, sf) +MMVEC_CMPEQ_HF(hf,"hf","Vector hf Compare ", fVELEM(16), 0x3, 2, hf) + /*************************************************************************= ***** BFloat arithmetic and max/min instructions *************************************************************************= *****/ --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778807; cv=none; d=zohomail.com; s=zohoarc; b=mP7s9pkm684WmeFNXWDwfxPLzO4z44dfs1CS3K/fZC828/i2M9U1wKwXbcRfmffKofVWjN9xZHH+Oqgm4/Q/uqVN6czvnGXEFtZRhL+bZw6IPhgugK5RK15t6TSnHiUCuEF2zZwiQpoVpVNRdC5eccSuGZScKt2UGYftlJql8m0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778807; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Mx/s3RlzAz7+uVrqyVMPIAXgyVHf9NRvKzpley8JlZk=; b=SmPe+y/Ck3uk5DPbY7G6+O2sz0CflCuxdlbA75onaPcg09wvsuTKeM0M+FnmfyQzwpxcZRnzoMnVTeJRZovZi9OI0YAT58+Bq4XFvuQBiy75mr94gtkkDrq0PrSgfOusrUWfDxaXVVeG1fXM4ld+2e+EP812ZbLnUEGiYPbsajg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778807251817.4958379601123; Sun, 11 Oct 2026 21:20:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7Ug-0002KD-6j; Mon, 12 Oct 2026 00:18:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7U6-0001wD-E9 for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:58 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7U3-00019F-H6 for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:17:57 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lHw9328248 for ; Mon, 12 Oct 2026 04:17:44 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7e4ech9s-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:17:44 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-35ac5255f1dso1664755eec.0 for ; Sun, 11 Oct 2026 21:17:44 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778809298158500 The architecture defines this encoding bit as zero. Leaving it unconstrained accepts reserved encodings as V6_vcmov. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/imported/mmvec/encode_ext.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 084ae3d8542..b46f51492d9 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -394,7 +394,7 @@ DEF_ENC(V6_vshuff, ICLASS_CJ" 1 001 111 ttt= tt PP 1 yyyyy 001 xxxxx") DEF_ENC(V6_vdeal, ICLASS_CJ" 1 001 111 ttttt PP 1 yyyyy 010 xx= xxx") // =20 DEF_FIELDROW_DESC32( ICLASS_CJ" 1 010 --- ----- PP - ----- ----- ---","= [#2] if (Ps) Vd=3DVu") -DEF_ENC(V6_vcmov, ICLASS_CJ" 1 010 000 ----- PP - uuuuu -ss ddddd") +DEF_ENC(V6_vcmov, ICLASS_CJ" 1 010 000 ----- PP 0 uuuuu -ss ddddd") DEF_ENC(V6_vncmov, ICLASS_CJ" 1 010 001 ----- PP - uuuuu -ss ddddd= ") DEF_ENC(V6_vnccombine, ICLASS_CJ" 1 010 010 vvvvv PP - uuuuu -ss ddddd= ") DEF_ENC(V6_vccombine, ICLASS_CJ" 1 010 011 vvvvv PP - uuuuu -ss ddddd") --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778817; cv=none; d=zohomail.com; s=zohoarc; b=QwIpzh8w0XCYCA11iCLbHIWTSt2XSTEUk5GzuU7jqEg0MvCiDrjGQYi+3hgpAFa6WN1uavmW+WWooDfi6QSUrPMwIzN2E5roWebgcs/AY+N93iE6hrR4dT66pYVr3XyprUj1TK7MFqpV4ABQBcn0k3HyEkLN6mrYpaiOlbMKwG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778817; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=d59OS8qGofUL7FRxpeoicV0ItP7zpkCbrbJaZ+rIK7g=; b=V71pxhxGUUPSLCRys55Q7mqtbZ8yOUwod4QPodPO//FKEPRsflS1zhqc+klBEMdfdfBsaZNTtKU5F7NP2PZ9+qAp/sht+4onp/NT/XcGSSdMXxJndKFjLmj6qQ3572JrrMwm6z/mFfE9mG8Lz008rExvG1mj+/HbZ+d9oPGmE1U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778817324191.5605572859257; Sun, 11 Oct 2026 21:20:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7UK-0001yp-Ml; Mon, 12 Oct 2026 00:18:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UA-0001xZ-Nc for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:04 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7U5-00019z-SB for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:01 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lI0o328308 for ; Mon, 12 Oct 2026 04:17:46 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7e4ech9w-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:17:46 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-35a04491c56so697573eec.0 for ; Sun, 11 Oct 2026 21:17:46 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778819443158500 MMVector is for HVX register state. Now with HVX floating point/QFloat, MMVector includes internal extended-precision bits in addition to the register content. Use VECTOR_SIZE_BYTE for GVec op lengths, vec mem alignme= nt and xfer sizes, scatter/gather processing, and histogram bounds. The standalone scatter/gather helper does not include the semantics macros that define fVECSIZE(). Use sizeof_field(MMVector, ub) there to express the same payload length without depending on that macro. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_hvx.h | 172 ++++++++++++------------ target/hexagon/mmvec/macros.h | 8 +- target/hexagon/genptr.c | 18 +-- target/hexagon/mmvec/system_ext_mmvec.c | 14 +- target/hexagon/op_helper.c | 34 ++--- 5 files changed, 123 insertions(+), 123 deletions(-) diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 548b49b4156..e01c4ee305a 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -126,11 +126,11 @@ static inline void assert_vhist_tmp(DisasContext *ctx) =20 #define fGEN_TCG_V6_vassign(SHORTCODE) \ tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vassign_tmp(SHORTCODE) \ tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vcombine_tmp(SHORTCODE) \ do { \ @@ -174,7 +174,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(lsb, PsV, 1); \ tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ gen_set_label(false_label); \ } while (0) =20 @@ -190,17 +190,17 @@ static inline void assert_vhist_tmp(DisasContext *ctx) /* Vector add - various forms */ #define fGEN_TCG_V6_vaddb(SHORTCODE) \ tcg_gen_gvec_add_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ - VvV_off, sizeof(MMVector), sizeof(MMVector)) + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddh(SHORTCYDE) \ tcg_gen_gvec_add_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddw(SHORTCODE) \ tcg_gen_gvec_add_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \ tcg_gen_gvec_add_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ @@ -220,17 +220,17 @@ static inline void assert_vhist_tmp(DisasContext *ctx) /* Vector sub - various forms */ #define fGEN_TCG_V6_vsubb(SHORTCODE) \ tcg_gen_gvec_sub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ - VvV_off, sizeof(MMVector), sizeof(MMVector)) + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubh(SHORTCODE) \ tcg_gen_gvec_sub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubw(SHORTCODE) \ tcg_gen_gvec_sub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \ tcg_gen_gvec_sub_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ @@ -458,7 +458,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_sars_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \ @@ -467,10 +467,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_sars_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ - tcg_env, tmpoff, sizeof(MMVector), \ - sizeof(MMVector)); \ + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vasrw(SHORTCODE) \ @@ -478,7 +478,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_sars_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \ @@ -487,10 +487,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_sars_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ - tcg_env, tmpoff, sizeof(MMVector), \ - sizeof(MMVector)); \ + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vlsrb(SHORTCODE) \ @@ -498,7 +498,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 7); \ tcg_gen_gvec_shrs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vlsrh(SHORTCODE) \ @@ -506,7 +506,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_shrs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vlsrw(SHORTCODE) \ @@ -514,7 +514,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_shrs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 /* Vector shift left - various forms */ @@ -523,7 +523,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 7); \ tcg_gen_gvec_shls_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vaslh(SHORTCODE) \ @@ -531,7 +531,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_shls_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \ @@ -540,10 +540,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_shls_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ - tcg_env, tmpoff, sizeof(MMVector), \ - sizeof(MMVector)); \ + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vaslw(SHORTCODE) \ @@ -551,7 +551,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_shls_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \ @@ -560,74 +560,74 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_shls_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ - shift, sizeof(MMVector), sizeof(MMVector)); \ + shift, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ - tcg_env, tmpoff, sizeof(MMVector), \ - sizeof(MMVector)); \ + tcg_env, tmpoff, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ } while (0) =20 /* Vector max - various forms */ #define fGEN_TCG_V6_vmaxw(SHORTCODE) \ tcg_gen_gvec_smax_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vmaxh(SHORTCODE) \ tcg_gen_gvec_smax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vmaxuh(SHORTCODE) \ tcg_gen_gvec_umax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vmaxb(SHORTCODE) \ tcg_gen_gvec_smax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vmaxub(SHORTCODE) \ tcg_gen_gvec_umax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 /* Vector min - various forms */ #define fGEN_TCG_V6_vminw(SHORTCODE) \ tcg_gen_gvec_smin_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vminh(SHORTCODE) \ tcg_gen_gvec_smin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vminuh(SHORTCODE) \ tcg_gen_gvec_umin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vminb(SHORTCODE) \ tcg_gen_gvec_smin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) #define fGEN_TCG_V6_vminub(SHORTCODE) \ tcg_gen_gvec_umin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 /* Vector logical ops */ #define fGEN_TCG_V6_vxor(SHORTCODE) \ tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vand(SHORTCODE) \ tcg_gen_gvec_and_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)) + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vor(SHORTCODE) \ tcg_gen_gvec_or_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ - VvV_off, sizeof(MMVector), sizeof(MMVector)) + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vnot(SHORTCODE) \ tcg_gen_gvec_not_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 /* Q register logical ops */ #define fGEN_TCG_V6_pred_or(SHORTCODE) \ @@ -659,8 +659,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_of= f, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)); \ + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ vec_to_qvec(SIZE, QdV_base, QdV_off, tcg_env, tmpoff); \ } while (0) =20 @@ -690,8 +690,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ intptr_t qoff =3D offsetof(CPUHexagonState, qtmp); \ tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_of= f, \ - VvV_base, VvV_off, sizeof(MMVector), \ - sizeof(MMVector)); \ + VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ vec_to_qvec(SIZE, tcg_env, qoff, tcg_env, tmpoff); \ OP(MO_64, QxV_base, QxV_off, QxV_base, QxV_off, tcg_env, qoff, \ sizeof(MMQReg), sizeof(MMQReg)); \ @@ -762,29 +762,29 @@ static inline void assert_vhist_tmp(DisasContext *ctx) =20 /* Vector splat - various forms */ #define fGEN_TCG_V6_lvsplatw(SHORTCODE) \ - tcg_gen_gvec_dup_i32_var(MO_32, VdV_base, VdV_off, sizeof(MMVector), \ - sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_32, VdV_base, VdV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE, RtV) =20 #define fGEN_TCG_V6_lvsplath(SHORTCODE) \ - tcg_gen_gvec_dup_i32_var(MO_16, VdV_base, VdV_off, sizeof(MMVector), \ - sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_16, VdV_base, VdV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE, RtV) =20 #define fGEN_TCG_V6_lvsplatb(SHORTCODE) \ - tcg_gen_gvec_dup_i32_var(MO_8, VdV_base, VdV_off, sizeof(MMVector), \ - sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_8, VdV_base, VdV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE, RtV) =20 /* Vector absolute value - various forms */ #define fGEN_TCG_V6_vabsb(SHORTCODE) \ tcg_gen_gvec_abs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsh(SHORTCODE) \ tcg_gen_gvec_abs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsw(SHORTCODE) \ tcg_gen_gvec_abs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 /* Vector loads */ #define fGEN_TCG_V6_vL32b_pi(SHORTCODE) SHORTCODE @@ -826,12 +826,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_REG(RxV), \ VdV, \ - fPM_I(RxV, siV * sizeof(MMVector))) + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) #define fGEN_TCG_PRED_VEC_LOAD_npred_pi \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ VdV, \ - fPM_I(RxV, siV * sizeof(MMVector))) + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) =20 #define fGEN_TCG_V6_vL32b_pred_pi(SHORTCODE) \ fGEN_TCG_PRED_VEC_LOAD_pred_pi @@ -860,12 +860,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) =20 #define fGEN_TCG_PRED_VEC_LOAD_pred_ai \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ - fEA_RI(RtV, siV * sizeof(MMVector)), \ + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ VdV, \ do {} while (0)) #define fGEN_TCG_PRED_VEC_LOAD_npred_ai \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ - fEA_RI(RtV, siV * sizeof(MMVector)), \ + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ VdV, \ do {} while (0)) =20 @@ -950,7 +950,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) } while (0) =20 #define fGEN_TCG_NEWVAL_VEC_STORE_pi \ - fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_I(RxV, siV * sizeof(MMVect= or))) + fGEN_TCG_NEWVAL_VEC_STORE(fEA_REG(RxV), fPM_I(RxV, siV * VECTOR_SIZE_B= YTE)) =20 #define fGEN_TCG_V6_vS32b_new_pi(SHORTCODE) \ fGEN_TCG_NEWVAL_VEC_STORE_pi @@ -958,7 +958,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) fGEN_TCG_NEWVAL_VEC_STORE_pi =20 #define fGEN_TCG_NEWVAL_VEC_STORE_ai \ - fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * sizeof(MMVector)), \ + fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ do { } while (0)) =20 #define fGEN_TCG_V6_vS32b_new_ai(SHORTCODE) \ @@ -992,22 +992,22 @@ static inline void assert_vhist_tmp(DisasContext *ctx) fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ VsV, ALIGN, \ - fPM_I(RxV, siV * sizeof(MMVector))) + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) #define fGEN_TCG_PRED_VEC_STORE_npred_pi(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ VsV, ALIGN, \ - fPM_I(RxV, siV * sizeof(MMVector))) + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) #define fGEN_TCG_PRED_VEC_STORE_new_pred_pi \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ OsN, true, \ - fPM_I(RxV, siV * sizeof(MMVector))) + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) #define fGEN_TCG_PRED_VEC_STORE_new_npred_pi \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ OsN, true, \ - fPM_I(RxV, siV * sizeof(MMVector))) + fPM_I(RxV, siV * VECTOR_SIZE_BYTE)) =20 #define fGEN_TCG_V6_vS32b_pred_pi(SHORTCODE) \ fGEN_TCG_PRED_VEC_STORE_pred_pi(true) @@ -1032,22 +1032,22 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) =20 #define fGEN_TCG_PRED_VEC_STORE_pred_ai(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ - fEA_RI(RtV, siV * sizeof(MMVector)), \ + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ VsV, ALIGN, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_npred_ai(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ - fEA_RI(RtV, siV * sizeof(MMVector)), \ + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ VsV, ALIGN, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_new_pred_ai \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ - fEA_RI(RtV, siV * sizeof(MMVector)), \ + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ OsN, true, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_new_npred_ai \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ - fEA_RI(RtV, siV * sizeof(MMVector)), \ + fEA_RI(RtV, siV * VECTOR_SIZE_BYTE), \ OsN, true, \ do { } while (0)) =20 diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 74c277fc06f..a4ab336983d 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -221,7 +221,7 @@ #define SCATTER_OP_WRITE_TO_MEM(TYPE) \ do { \ ra =3D GETPC(); \ - for (int i =3D 0; i < sizeof(MMVector); i +=3D sizeof(TYPE)) { \ + for (int i =3D 0; i < VECTOR_SIZE_BYTE; i +=3D sizeof(TYPE)) { \ if (test_bit(i, env->vtcm_log.mask)) { \ TYPE dst =3D 0; \ TYPE inc =3D 0; \ @@ -244,7 +244,7 @@ } while (0) #define SCATTER_OP_PROBE_MEM(TYPE, MMU_IDX, RETADDR) \ do { \ - for (int i =3D 0; i < sizeof(MMVector); i +=3D sizeof(TYPE)) { \ + for (int i =3D 0; i < VECTOR_SIZE_BYTE; i +=3D sizeof(TYPE)) { \ if (test_bit(i, env->vtcm_log.mask)) { \ for (int j =3D 0; j < sizeof(TYPE); j++) { \ probe_read(env, env->vtcm_log.va[i + j], 1, \ @@ -329,8 +329,8 @@ #endif #define fVFOREACH(WIDTH, VAR) for (VAR =3D 0; VAR < fVELEM(WIDTH); VAR++) #define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \ - ARRAY.v[(INDEX) / (fVECSIZE() / (sizeof(ARRAY.TYPE[0])))].TYPE[(INDEX)= % \ - (fVECSIZE() / (sizeof(ARRAY.TYPE[0])))] + ARRAY.v[(INDEX) / (fVECSIZE() / (sizeof(ARRAY.v[0].TYPE[0])))] \ + .TYPE[(INDEX) % (fVECSIZE() / (sizeof(ARRAY.v[0].TYPE[0])))] =20 #define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V))) #define fVASL_SATHI(U, V) fVSATW(((U) << 1) | ((V) >> 31)) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index c8e69eb273f..90197c6e72e 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1500,9 +1500,9 @@ static void gen_vreg_load(DisasContext *ctx, TCGv_ptr= dstbase, { TCGv_i64 tmp =3D tcg_temp_new_i64(); if (aligned) { - tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1)); + tcg_gen_andi_tl(src, src, ~((int32_t)VECTOR_SIZE_BYTE - 1)); } - for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { + for (int i =3D 0; i < VECTOR_SIZE_BYTE / 8; i++) { tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_LE | MO_UQ); tcg_gen_addi_tl(src, src, 8); tcg_gen_st_i64(tmp, dstbase, dstoff + i * 8); @@ -1524,15 +1524,15 @@ static void gen_vreg_store(DisasContext *ctx, TCGv = EA, TCGv_ptr srcbase, tcg_gen_movi_tl(hex_vstore_pending[slot], 1); if (aligned) { tcg_gen_andi_tl(hex_vstore_addr[slot], EA, - ~((int32_t)sizeof(MMVector) - 1)); + ~((int32_t)VECTOR_SIZE_BYTE - 1)); } else { tcg_gen_mov_tl(hex_vstore_addr[slot], EA); } - tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); + tcg_gen_movi_tl(hex_vstore_size[slot], VECTOR_SIZE_BYTE); =20 /* Copy the data to the vstore buffer */ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, - sizeof(MMVector), sizeof(MMVector)); + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); /* Set the mask to all 1's */ tcg_gen_gvec_dup_imm(MO_64, maskoff, sizeof(MMQReg), sizeof(MMQReg), ~= 0LL); } @@ -1547,12 +1547,12 @@ static void gen_vreg_masked_store(DisasContext *ctx= , TCGv EA, =20 tcg_gen_movi_tl(hex_vstore_pending[slot], 1); tcg_gen_andi_tl(hex_vstore_addr[slot], EA, - ~((int32_t)sizeof(MMVector) - 1)); - tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); + ~((int32_t)VECTOR_SIZE_BYTE - 1)); + tcg_gen_movi_tl(hex_vstore_size[slot], VECTOR_SIZE_BYTE); =20 /* Copy the data to the vstore buffer */ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, - sizeof(MMVector), sizeof(MMVector)); + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); /* Copy the mask */ tcg_gen_gvec_mov_var(MO_64, tcg_env, maskoff, bitsbase, bitsoff, sizeof(MMQReg), sizeof(MMQReg)); @@ -1572,7 +1572,7 @@ static void vec_to_qvec(size_t size, TCGv_ptr dstbase= , intptr_t dstoff, TCGv_i64 zero =3D tcg_constant_i64(0); TCGv_i64 ones =3D tcg_constant_i64(~0); =20 - for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { + for (int i =3D 0; i < VECTOR_SIZE_BYTE / 8; i++) { tcg_gen_ld_i64(tmp, srcbase, srcoff + i * 8); tcg_gen_movi_i64(mask, 0); =20 diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec= /system_ext_mmvec.c index 081cadd814a..037ec15c866 100644 --- a/target/hexagon/mmvec/system_ext_mmvec.c +++ b/target/hexagon/mmvec/system_ext_mmvec.c @@ -21,20 +21,20 @@ =20 void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot) { - size_t size =3D sizeof(MMVector); - env->vstore_pending[slot] =3D 1; env->vstore[slot].va =3D vaddr; - env->vstore[slot].size =3D size; - memcpy(&env->vstore[slot].data, &env->tmp_VRegs[0], size); + env->vstore[slot].size =3D sizeof_field(MMVector, ub); + memcpy(&env->vstore[slot].data, &env->tmp_VRegs[0], + sizeof_field(MMVector, ub)); =20 /* On a gather store, overwrite the store mask to emulate dropped gath= ers */ - bitmap_copy(env->vstore[slot].mask, env->vtcm_log.mask, size); + bitmap_copy(env->vstore[slot].mask, env->vtcm_log.mask, + sizeof_field(MMVector, ub)); } =20 void mem_vector_scatter_init(CPUHexagonState *env) { - bitmap_zero(env->vtcm_log.mask, MAX_VEC_SIZE_BYTES); + bitmap_zero(env->vtcm_log.mask, sizeof_field(MMVector, ub)); =20 env->vtcm_pending =3D true; env->vtcm_log.op =3D false; @@ -43,5 +43,5 @@ void mem_vector_scatter_init(CPUHexagonState *env) =20 void mem_vector_gather_init(CPUHexagonState *env) { - bitmap_zero(env->vtcm_log.mask, MAX_VEC_SIZE_BYTES); + bitmap_zero(env->vtcm_log.mask, sizeof_field(MMVector, ub)); } diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index c582803edce..accadd7927a 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -191,7 +191,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) g_assert_not_reached(); } } else { - for (int i =3D 0; i < sizeof(MMVector); i++) { + for (int i =3D 0; i < VECTOR_SIZE_BYTE; i++) { if (test_bit(i, env->vtcm_log.mask)) { cpu_stb_data_ra(env, env->vtcm_log.va[i], hexagon_mmvec_get_byte(&env->vtcm_log= .data, @@ -491,7 +491,7 @@ static void probe_hvx_stores(CPUHexagonState *env, int = mmu_idx, g_assert_not_reached(); } } else { - for (int i =3D 0; i < sizeof(MMVector); i++) { + for (int i =3D 0; i < VECTOR_SIZE_BYTE; i++) { if (test_bit(i, env->vtcm_log.mask)) { probe_write(env, env->vtcm_log.va[i], 1, mmu_idx, reta= ddr); } @@ -1410,14 +1410,14 @@ void HELPER(vhist)(CPUHexagonState *env) MMVector *input =3D &env->tmp_VRegs[0]; =20 for (int lane =3D 0; lane < 8; lane++) { - for (int i =3D 0; i < sizeof(MMVector) / 8; ++i) { + for (int i =3D 0; i < VECTOR_SIZE_BYTE / 8; ++i) { unsigned char value =3D hexagon_mmvec_get_byte(input, - (sizeof(MMVector) / 8) * lane + i); + (VECTOR_SIZE_BYTE / 8) * lane + i); unsigned char regno =3D value >> 3; unsigned char element =3D value & 7; =20 hex_hvx(env)->VRegs[regno] - .uh[(sizeof(MMVector) / 16) * lane + element]++; + .uh[(VECTOR_SIZE_BYTE / 16) * lane + element]++; } } } @@ -1427,15 +1427,15 @@ void HELPER(vhistq)(CPUHexagonState *env) MMVector *input =3D &env->tmp_VRegs[0]; =20 for (int lane =3D 0; lane < 8; lane++) { - for (int i =3D 0; i < sizeof(MMVector) / 8; ++i) { + for (int i =3D 0; i < VECTOR_SIZE_BYTE / 8; ++i) { unsigned char value =3D hexagon_mmvec_get_byte(input, - (sizeof(MMVector) / 8) * lane + i); + (VECTOR_SIZE_BYTE / 8) * lane + i); unsigned char regno =3D value >> 3; unsigned char element =3D value & 7; =20 - if (fGETQBIT(env->qtmp, sizeof(MMVector) / 8 * lane + i)) { + if (fGETQBIT(env->qtmp, VECTOR_SIZE_BYTE / 8 * lane + i)) { hex_hvx(env)->VRegs[regno].uh[ - (sizeof(MMVector) / 16) * lane + element]++; + (VECTOR_SIZE_BYTE / 16) * lane + element]++; } } } @@ -1445,7 +1445,7 @@ void HELPER(vwhist256)(CPUHexagonState *env) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1460,7 +1460,7 @@ void HELPER(vwhist256q)(CPUHexagonState *env) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1477,7 +1477,7 @@ void HELPER(vwhist256_sat)(CPUHexagonState *env) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1492,7 +1492,7 @@ void HELPER(vwhist256q_sat)(CPUHexagonState *env) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1509,7 +1509,7 @@ void HELPER(vwhist128)(CPUHexagonState *env) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1524,7 +1524,7 @@ void HELPER(vwhist128q)(CPUHexagonState *env) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1541,7 +1541,7 @@ void HELPER(vwhist128m)(CPUHexagonState *env, int32_t= uiV) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - for (int i =3D 0; i < (sizeof(MMVector) / 2); i++) { + for (int i =3D 0; i < (VECTOR_SIZE_BYTE / 2); i++) { unsigned int bucket =3D fGETUBYTE(0, input->h[i]); unsigned int weight =3D fGETUBYTE(1, input->h[i]); unsigned int vindex =3D (bucket >> 3) & 0x1F; @@ -1558,7 +1558,7 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_= t uiV) { MMVector *input =3D &env->tmp_VRegs[0]; =20 - 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778790860158500 An MMVectorPair contains two MMVector state objects. Perform pair ops once for each vector payload and advance to the second member with sizeof(MMVect= or), rather than treating the pair as one contiguous payload. This keeps pair access tied to the MMVector layout when it gains internal state in the following QFloat change, while retaining VECTOR_SIZE_BYTE as t= he length of each operation. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_hvx.h | 70 +++++++++++++++++------------------- 1 file changed, 33 insertions(+), 37 deletions(-) diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index e01c4ee305a..abc115d74a9 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -135,10 +135,10 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_V6_vcombine_tmp(SHORTCODE) \ do { \ tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, VvV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off + sizeof(MMVector)= , \ - VuV_base, VuV_off, sizeof(MMVector), \ - sizeof(MMVector)); \ + VuV_base, VuV_off, VECTOR_SIZE_BYTE, \ + VECTOR_SIZE_BYTE); \ } while (0) =20 /* @@ -150,19 +150,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (VddV_off !=3D VuV_off) { \ tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ - VvV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BY= TE); \ tcg_gen_gvec_mov_var(MO_64, VddV_base, \ VddV_off + sizeof(MMVector), VuV_base, \ - VuV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + VuV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BY= TE); \ } else { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ tcg_gen_gvec_mov_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ - VvV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + VvV_off, VECTOR_SIZE_BYTE, VECTOR_SIZE_BY= TE); \ tcg_gen_gvec_mov_var(MO_64, VddV_base, \ VddV_off + sizeof(MMVector), tcg_env, tmp= off, \ - sizeof(MMVector), sizeof(MMVector)); \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } \ } while (0) =20 @@ -202,20 +202,21 @@ static inline void assert_vhist_tmp(DisasContext *ctx) VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ VECTOR_SIZE_BYTE) =20 -#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \ - tcg_gen_gvec_add_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ - sizeof(MMVector) * 2) +#define fGEN_TCG_PAIR_ADDSUB_BASIC(OP, VECE) \ + do { \ + tcg_gen_gvec_##OP##_var(VECE, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_##OP##_var(VECE, VddV_base, \ + VddV_off + sizeof(MMVector), VuuV_base, \ + VuuV_off + sizeof(MMVector), VvvV_base, \ + VvvV_off + sizeof(MMVector), \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + } while (0) =20 -#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \ - tcg_gen_gvec_add_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ - sizeof(MMVector) * 2) - -#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \ - tcg_gen_gvec_add_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ - sizeof(MMVector) * 2) +#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(add, MO= _8) +#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) fGEN_TCG_PAIR_ADDSUB_BASIC(add, MO= _16) +#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(add, MO= _32) =20 /* Vector sub - various forms */ #define fGEN_TCG_V6_vsubb(SHORTCODE) \ @@ -232,20 +233,9 @@ static inline void assert_vhist_tmp(DisasContext *ctx) VvV_base, VvV_off, VECTOR_SIZE_BYTE, \ VECTOR_SIZE_BYTE) =20 -#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \ - tcg_gen_gvec_sub_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ - sizeof(MMVector) * 2) - -#define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \ - tcg_gen_gvec_sub_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ - sizeof(MMVector) * 2) - -#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \ - tcg_gen_gvec_sub_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ - VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ - sizeof(MMVector) * 2) +#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(sub, MO= _8) +#define fGEN_TCG_V6_vsubh_dv(SHORTCYDE) fGEN_TCG_PAIR_ADDSUB_BASIC(sub, MO= _16) +#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) fGEN_TCG_PAIR_ADDSUB_BASIC(sub, MO= _32) =20 #define fGEN_TCG_V6_vaddbsat(SHORTCODE) \ tcg_gen_gvec_ssadd_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ @@ -278,8 +268,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx) VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DBASE, DST, ABASE, SRC_A, BBASE, SR= C_B) \ - tcg_gen_gvec_##OP##_var(VECE, DBASE, DST, ABASE, SRC_A, BBASE, SRC_B, \ - 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) + do { \ + tcg_gen_gvec_##OP##_var(VECE, DBASE, DST, ABASE, SRC_A, BBASE, SRC= _B, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778746244158500 Add MMVector.ext as internal QFloat state following the register content. Preserve it in full MMVector state transfers, clear it for non-QFloat write= s. Keeping the extended bits separate from the payload lets ordinary HVX ops use VECTOR_SIZE_BYTE while pair layouts use sizeof(MMVector) as their object stride. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/mmvec/mmvec.h | 55 ++++++++++++++++++++------------ hw/hexagon/hexagon_hvx_context.c | 5 +++ target/hexagon/hex_common.py | 32 +++++++++++++++++++ 3 files changed, 71 insertions(+), 21 deletions(-) diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index ed2321be920..a761b0c69d6 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -33,29 +33,42 @@ typedef uint32_t QRegMask; /* at least NUM_QREGS bits */ =20 #define VECTOR_SIZE_BYTE (fVECSIZE()) =20 -typedef union { - uint64_t ud[MAX_VEC_SIZE_BYTES / 8]; - int64_t d[MAX_VEC_SIZE_BYTES / 8]; - uint32_t uw[MAX_VEC_SIZE_BYTES / 4]; - int32_t w[MAX_VEC_SIZE_BYTES / 4]; - uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; - int16_t h[MAX_VEC_SIZE_BYTES / 2]; - uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; - int8_t b[MAX_VEC_SIZE_BYTES / 1]; - float32 sf[MAX_VEC_SIZE_BYTES / 4]; - float16 hf[MAX_VEC_SIZE_BYTES / 2]; - bfloat16 bf[MAX_VEC_SIZE_BYTES / 2]; +/* + * Fill value for a vector's qfloat extended-precision bits (MMVector.ext, + * below) whenever an instruction that isn't qfloat-aware writes that + * vector: architecturally the ext bits are unspecified in that case, and + * this repeating, recognizably-not-zero byte pattern is used instead of an + * all-zero fill so stray reads of stale ext state show up distinctly + * rather than silently looking like a valid (all-zero) qfloat result. + */ +#define V_EXTENDED_BYTEVAL 0x0a + +typedef struct { + union { + uint64_t ud[MAX_VEC_SIZE_BYTES / 8]; + int64_t d[MAX_VEC_SIZE_BYTES / 8]; + uint32_t uw[MAX_VEC_SIZE_BYTES / 4]; + int32_t w[MAX_VEC_SIZE_BYTES / 4]; + uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; + int16_t h[MAX_VEC_SIZE_BYTES / 2]; + uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; + int8_t b[MAX_VEC_SIZE_BYTES / 1]; + float32 sf[MAX_VEC_SIZE_BYTES / 4]; + float16 hf[MAX_VEC_SIZE_BYTES / 2]; + bfloat16 bf[MAX_VEC_SIZE_BYTES / 2]; + }; + /* + * Extended precision bits for qfloat: one byte per qf32 element (only + * the low 4 bits, the LREQ nibble, are meaningful); two qf16 elements + * share a byte, 2 bits (LR) each. Any instruction that overwrites th= is + * vector without itself being qfloat-aware fills these with + * V_EXTENDED_BYTEVAL, since they're only meaningful as the tail end of + * a qfloat computation. + */ + uint8_t ext[MAX_VEC_SIZE_BYTES / 4]; } MMVector; =20 -typedef union { - uint64_t ud[2 * MAX_VEC_SIZE_BYTES / 8]; - int64_t d[2 * MAX_VEC_SIZE_BYTES / 8]; - uint32_t uw[2 * MAX_VEC_SIZE_BYTES / 4]; - int32_t w[2 * MAX_VEC_SIZE_BYTES / 4]; - uint16_t uh[2 * MAX_VEC_SIZE_BYTES / 2]; - int16_t h[2 * MAX_VEC_SIZE_BYTES / 2]; - uint8_t ub[2 * MAX_VEC_SIZE_BYTES / 1]; - int8_t b[2 * MAX_VEC_SIZE_BYTES / 1]; +typedef struct { MMVector v[2]; } MMVectorPair; =20 diff --git a/hw/hexagon/hexagon_hvx_context.c b/hw/hexagon/hexagon_hvx_cont= ext.c index 3b73498298e..575ea74fc94 100644 --- a/hw/hexagon/hexagon_hvx_context.c +++ b/hw/hexagon/hexagon_hvx_context.c @@ -15,6 +15,10 @@ static void hexagon_hvx_context_reset_hold(Object *obj, = ResetType type) HexagonHVXContextState *s =3D HEXAGON_HVX_CONTEXT(obj); =20 memset(&s->regs, 0, sizeof(s->regs)); + for (int i =3D 0; i < NUM_VREGS; i++) { + memset(s->regs.VRegs[i].ext, V_EXTENDED_BYTEVAL, + sizeof(s->regs.VRegs[i].ext)); + } } =20 /* gvec needs VRegs/QRegs 16-aligned within the struct. */ @@ -26,6 +30,7 @@ static const VMStateDescription vmstate_mmvector =3D { .minimum_version_id =3D 1, .fields =3D (const VMStateField[]){ VMSTATE_UINT64_ARRAY(ud, MMVector, MAX_VEC_SIZE_BYTES / 8), + VMSTATE_UINT8_ARRAY(ext, MMVector, MAX_VEC_SIZE_BYTES / 4), VMSTATE_END_OF_LIST() } }; diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index d344284e8a2..1812e024ba7 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -448,6 +448,28 @@ def helper_arg_type(self): return "void *" def helper_arg_name(self): return f"{self.reg_tcg()}_void" + def gen_clear_ext(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm_var(MO_8, {self.hvx_base()}, + {self.hvx_off()} + offsetof(MMVector, ext), + sizeof_field(MMVector, ext), + sizeof_field(MMVector, ext), + V_EXTENDED_BYTEVAL); + """)) + def gen_clear_ext_pair(self, f): + f.write(code_fmt(f"""\ + tcg_gen_gvec_dup_imm_var(MO_8, {self.hvx_base()}, + {self.hvx_off()} + offsetof(MMVector, ext), + sizeof_field(MMVector, ext), + sizeof_field(MMVector, ext), + V_EXTENDED_BYTEVAL); + tcg_gen_gvec_dup_imm_var(MO_8, {self.hvx_base()}, + {self.hvx_off()} + sizeof(MMVector) + + offsetof(MMVector, ext), + sizeof_field(MMVector, ext), + sizeof_field(MMVector, ext), + V_EXTENDED_BYTEVAL); + """)) =20 # # Every register is either Dest or OldSource or NewSource or ReadWrite @@ -793,11 +815,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) + self.gen_clear_ext(f) def gen_zero(self, f): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) + self.gen_clear_ext(f) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -868,11 +892,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) + self.gen_clear_ext(f) def gen_zero(self, f): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) + self.gen_clear_ext(f) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -911,11 +937,13 @@ def decl_tcg(self, f, tag, regno): {self.reg_tcg()}_srcoff, sizeof(MMVector), sizeof(MMVector)); """)) + self.gen_clear_ext(f) def gen_zero(self, f): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), 0); """)) + self.gen_clear_ext(f) def gen_write(self, f, tag): f.write(code_fmt(f"""\ gen_vreg_write(ctx, {self.hvx_base()}, {self.hvx_off()}, @@ -948,11 +976,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) + self.gen_clear_ext_pair(f) def gen_zero(self, f): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) + self.gen_clear_ext_pair(f) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -1026,11 +1056,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) + self.gen_clear_ext_pair(f) def gen_zero(self, f): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) + self.gen_clear_ext_pair(f) def gen_write(self, f, tag): f.write(code_fmt(f"""\ gen_vreg_write_pair(ctx, {self.hvx_base()}, {self.hvx_off()}, --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778829; cv=none; d=zohomail.com; s=zohoarc; b=SZVz7lm9XPpAL+p6EdgwBolWBjsMukDIXDpqE6/iOzn2OUEmNUVHIzqfYNbmXaPvWUzOhtHjtbI69QDzv/95CuO0BkF8+9X3LjYy1EukMnxSEAJOwWXAYr3hkUgiK7pe7qRIaf/NZ6CXO29sTtWFZjz7aDCDQSDZb0HsgtYIAYs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778829; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778829754158500 Add routines to handle QFloat/HVX floating point values. Also: add documentation to describe the feature. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- docs/system/hexagon/emulation.rst | 8 +- target/hexagon/mmvec/hvx_ieee_fp.h | 1 + target/hexagon/mmvec/mmvec_qfloat.h | 133 ++++ target/hexagon/reg_fields_def.h.inc | 2 + hw/hexagon/hexagon_hvx_context.c | 2 +- target/hexagon/mmvec/hvx_ieee_fp.c | 9 + target/hexagon/mmvec/hvx_qfloat.c | 832 +++++++++++++++++++++++++ target/hexagon/gen_tcg_funcs.py | 2 +- target/hexagon/hex_common.py | 80 ++- target/hexagon/imported/mmvec/ext.idef | 3 +- target/hexagon/meson.build | 1 + 11 files changed, 1049 insertions(+), 24 deletions(-) create mode 100644 target/hexagon/mmvec/mmvec_qfloat.h create mode 100644 target/hexagon/mmvec/hvx_qfloat.c diff --git a/docs/system/hexagon/emulation.rst b/docs/system/hexagon/emulat= ion.rst index 36f54f058af..12385311aa4 100644 --- a/docs/system/hexagon/emulation.rst +++ b/docs/system/hexagon/emulation.rst @@ -5,11 +5,13 @@ Hexagon CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 -QEMU's TCG emulation includes support for v65, v66, v67, v68, v69, v71, v7= 3. +QEMU's TCG emulation includes support for v65, v66, v67, v68, v69, v71, v7= 3, +v75, v77, v79, v81. It also has support for the following architecture extensions: =20 - HVX (Hexagon Vector eXtensions) +- `HVX floating point `_. =20 For information on the specifics of the HVX extension, please refer -to the `Qualcomm Hexagon V73 HVX Programmer's Reference Manual -`_. +to the `Qualcomm Hexagon V79 HVX Programmer's Reference Manual +`_. diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index f7ea0086683..6efc39eb203 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -27,6 +27,7 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *f= p_status); =20 int32_t conv_w_sf(float32 a, float_status *fp_status); int16_t conv_h_hf(float16 a, float_status *fp_status); +int16_t conv_h_hf_rnd(float16 a, float_status *fp_status); =20 /* IEEE - FP compare instructions */ uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status); diff --git a/target/hexagon/mmvec/mmvec_qfloat.h b/target/hexagon/mmvec/mmv= ec_qfloat.h new file mode 100644 index 00000000000..bef1a8f41b3 --- /dev/null +++ b/target/hexagon/mmvec/mmvec_qfloat.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * HVX qfloat extended-precision arithmetic. + * + * qfloat is an intermediate format used to chain consecutive HVX + * floating-point operations without rounding at each step: + * a qf16/qf32 result carries a few extra bits of precision beyond its + * visible 16/32-bit mantissa/exponent, stashed in the vector register's + * extended bits. + * + * Qfloat arithmetic uses FloatParts64, including qfloat-specific adapters= for + * the non-IEEE signed significand and LREQ extension bits. + */ + +#ifndef MMVEC_QFLOAT_H +#define MMVEC_QFLOAT_H + +#include "mmvec.h" +#include "fpu/softfloat.h" +#include "fpu/softfloat-parts.h" + +/* Forward declaration to avoid a circular include with cpu.h */ +typedef struct CPUArchState CPUHexagonState; + +typedef enum float_type { + SF, + HF, + EXTQF32, + EXTQF16, +} f_type; + +typedef enum { + RND_TO_NEAREST_EVEN, + RND_TO_ZERO, + RND_TOWARDS_NEG_INF, + RND_TOWARDS_POS_INF, + MAX_RND_MODES +} qfrnd_mode_enum_t; + +/* Only RND_TO_NEAREST_EVEN is ever selected today; see hvx_qfloat.c */ +#define CVI_QFRND_MODE RND_TO_NEAREST_EVEN + +#define QF32_BITMASK 0xFFFFFFFFULL +#define QF16_BITMASK 0xFFFFULL +#define EXT32_BITMASK 0x0F +#define EXT16_BITMASK 0x03 + +#define E_MIN_EXTQF16 -15 +#define E_MIN_EXTQF32 -255 + +/* extqf32 NaN/Inf sentinels: 32-bit qf32 value + 4-bit LREQ, packed */ +#define extqf32_pos_nan 0X7FFFFF7FDULL +#define extqf32_neg_nan 0X8000007F0ULL +#define extqf32_pos_nan_inexact 0X7FFFFF7FCULL +#define extqf32_neg_nan_inexact 0X8000007F1ULL +#define extqf32_pos_inf 0x7FFFFF7F8ULL +#define extqf32_pos_inf_exact 0x7FFFFF7F8ULL +#define extqf32_pos_inf_inexact 0x7FFFFF7F9ULL +#define extqf32_neg_inf 0x8000007F5ULL +#define extqf32_neg_inf_exact 0x8000007F5ULL +#define extqf32_neg_inf_inexact 0x8000007F4ULL + +/* extqf16 NaN/Inf sentinels: 16-bit qf16 value + 2-bit LR, packed */ +#define extqf16_pos_nan 0x7FFF3 +#define extqf16_neg_nan 0x801F0 +#define extqf16_pos_inf 0x7FFF2 +#define extqf16_neg_inf 0x801F1 + +#define INIT_UNFLOAT(U) \ + unfloat U =3D { .sign =3D 0, .exp =3D 0, .inf =3D false, .nan =3D fals= e, \ + .zero =3D false, \ + .parts =3D { .cls =3D float_class_zero } }; + +/* + * "Un-normalized float": the common intermediate representation used while + * parsing/adding/multiplying/rounding qfloat and IEEE values. `exp` reta= ins + * the source format's qfloat scale while `parts` holds its numeric value. + * sign: literal sign bit for IEEE-parsed values; for qfloat-parsed + * values this is instead the "deferred negation" flag left by + * the extended-bits' R bit (see is_unfloat_neg()) -- not a + * literal sign, except after is_unfloat_neg() resolves it. + */ +typedef struct { + int exp; + bool inf; + bool nan; + int sign; + bool zero; + FloatParts64 parts; +} unfloat; + +unfloat parse_hf(int16_t in); +unfloat parse_sf_daz(uint32_t in, bool daz_mode); +unfloat parse_extqf16(uint16_t in, uint8_t in_ext); +unfloat parse_extqf32(uint32_t in, uint8_t in_ext); + +int32_t conv_sf_extqf32(uint32_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrnd= ); +int16_t conv_hf_extqf32(uint32_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrnd= ); +int16_t conv_hf_extqf16(uint16_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrnd= ); +uint16_t conv_qf32_to_bf(uint32_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrn= d); + +int qf_vilog2(f_type type, uint32_t a, uint8_t a_ext); + +uint64_t qfloat_round_ext_parts(unsigned size, FloatParts64 parts, int exp, + bool deferred_sign, + qfrnd_mode_enum_t qfrnd_mode); +FloatParts64 qfloat_unfloat_parts(unfloat u); + +uint64_t handle_infinity_nan_add(unfloat u, unfloat v, uint64_t pos_nan_va= l, + uint64_t neg_nan_val, uint64_t pos_inf_va= l, + uint64_t neg_inf_val); +uint64_t handle_infinity_nan_mpy(unfloat u, unfloat v, uint64_t pos_nan_va= l, + uint64_t neg_nan_val, uint64_t pos_inf_va= l, + uint64_t neg_inf_val); + +bool is_unfloat_neg(unfloat u); +bool is_daz_mode(const CPUHexagonState *env); + +unfloat legacy_parse_qf32(int32_t in); +unfloat legacy_parse_qf16(int16_t in); +uint32_t legacy_qf_add(int size, unfloat a, unfloat b); +uint32_t legacy_qf_mpy(int size, unfloat a, unfloat b); +int32_t legacy_conv_sf_qf32(uint32_t a); +int16_t legacy_conv_hf_qf32(uint32_t a); +int16_t legacy_conv_hf_qf16(uint16_t a); +bool qfloat_is_extended(const CPUHexagonState *env); + +#endif diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_field= s_def.h.inc index c06e14fe24a..553f6ffffbc 100644 --- a/target/hexagon/reg_fields_def.h.inc +++ b/target/hexagon/reg_fields_def.h.inc @@ -32,6 +32,8 @@ DEF_REG_FIELD(USR_FPINPF, 5, 1) =20 DEF_REG_FIELD(USR_LPCFG, 8, 2) =20 +DEF_REG_FIELD(USR_FPDAZ, 17, 1) + DEF_REG_FIELD(USR_FPRND, 22, 2) =20 DEF_REG_FIELD(USR_FPINVE, 25, 1) diff --git a/hw/hexagon/hexagon_hvx_context.c b/hw/hexagon/hexagon_hvx_cont= ext.c index 575ea74fc94..2f58481b73d 100644 --- a/hw/hexagon/hexagon_hvx_context.c +++ b/hw/hexagon/hexagon_hvx_context.c @@ -30,7 +30,7 @@ static const VMStateDescription vmstate_mmvector =3D { .minimum_version_id =3D 1, .fields =3D (const VMStateField[]){ VMSTATE_UINT64_ARRAY(ud, MMVector, MAX_VEC_SIZE_BYTES / 8), - VMSTATE_UINT8_ARRAY(ext, MMVector, MAX_VEC_SIZE_BYTES / 4), + VMSTATE_UINT8_ARRAY_V(ext, MMVector, MAX_VEC_SIZE_BYTES / 4, 2), VMSTATE_END_OF_LIST() } }; diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 230ea9a13a7..e0971147a3d 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -88,6 +88,15 @@ int16_t conv_h_hf(float16 a, float_status *fp_status) return float16_to_int16_round_to_zero(a, fp_status); } =20 +int16_t conv_h_hf_rnd(float16 a, float_status *fp_status) +{ + /* float16_to_int16_scalbn converts any NaN to MAX. */ + if (float16_is_any_nan(a)) { + return float16_is_neg(a) ? INT16_MIN : INT16_MAX; + } + return float16_to_int16_scalbn(a, float_round_nearest_even, 0, fp_stat= us); +} + /* * Returns true if f1 > f2, where at least one of the elements is guarante= ed * to be NaN. diff --git a/target/hexagon/mmvec/hvx_qfloat.c b/target/hexagon/mmvec/hvx_q= float.c new file mode 100644 index 00000000000..41cc827aa87 --- /dev/null +++ b/target/hexagon/mmvec/hvx_qfloat.c @@ -0,0 +1,832 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "reg_fields.h" +#include "mmvec_qfloat.h" + +#define BIAS_QF32 127 +#define BIAS_EXTQF32 383 +#define BIAS_QF16 15 +#define BIAS_SF 127 +#define BIAS_HF 15 + +#define E_MAX_QF16 16 +#define E_MIN_QF16 -15 +#define E_MAX_EXTQF16 E_MAX_QF16 +#define E_MAX_EXTQF32 256 +#define E_MAX_SF 128 +#define E_MIN_SF -126 +#define E_MAX_HF 16 +#define E_MIN_HF -14 + +#define sf_MANTBITS 23 +#define hf_MANTBITS 10 +#define bf_MANTBITS 7 + +#define EXTQF32_BITMASK 0xFFFFFFFFFULL +#define EXTQF16_BITMASK 0x3FFFFULL + +#define MAX_SIG_QF16 0x3ff +#define MAX_SIG_QF32 0x7fffff + +#define ieee_pos_NaN_32 0x7FFFFFFF +#define ieee_pos_NaN_16 0x7FFF +#define ieee_pos_inf_32 0x7f800000 +#define ieee_pos_inf_16 0x7C00 +#define BF_POS_NAN 0x7FFF +#define BF_POS_INF 0x7f80 + +#define QF32_ILOG2_ZERO_EXP 0x80000000 +#define QF32_ILOG2_NAN_EXP 0x7FFFFFFF +#define QF32_ILOG2_INF_EXP 0x7FFFFFFE +#define QF16_ILOG2_ZERO_EXP 0x8000 +#define QF16_ILOG2_NAN_EXP 0x7FFF +#define QF16_ILOG2_INF_EXP 0x7FFE + +typedef uint8_t LREQ_t; + +enum { + LREQ_Q =3D 1 << 0, + LREQ_E =3D 1 << 1, + LREQ_R =3D 1 << 2, + LREQ_L =3D 1 << 3, +}; + +/* + * Common indicators + */ + +bool is_unfloat_neg(unfloat u) +{ + return u.parts.sign ^ u.sign; +} + +/* One's complement the LRQ bits, but leave E (exponent extension) alone */ +static LREQ_t negate_lreq(LREQ_t lreq) +{ + LREQ_t neg_lreq =3D ~lreq & EXT32_BITMASK; + + return (neg_lreq & ~LREQ_E) | (lreq & LREQ_E); +} + +static bool is_extqf32_nan(uint64_t in) +{ + return in =3D=3D extqf32_pos_nan || in =3D=3D extqf32_neg_nan || + in =3D=3D extqf32_pos_nan_inexact || in =3D=3D extqf32_neg_nan_= inexact; +} + +static bool is_extqf32_inf(uint64_t in) +{ + return in =3D=3D extqf32_pos_inf_exact || in =3D=3D extqf32_pos_inf_in= exact || + in =3D=3D extqf32_neg_inf_exact || in =3D=3D extqf32_neg_inf_in= exact; +} + +static bool is_extqf16_nan(uint32_t in) +{ + return in =3D=3D extqf16_pos_nan || in =3D=3D extqf16_neg_nan; +} + +static bool is_extqf16_inf(uint32_t in) +{ + return in =3D=3D extqf16_pos_inf || in =3D=3D extqf16_neg_inf; +} + +static FloatParts64 qfloat_unpack_ext_parts(unsigned size, uint32_t value, + uint8_t ext) +{ + int32_t sig; + int exp; + unsigned precision; + uint64_t frac; + bool sign; + + if (size =3D=3D 32) { + LREQ_t lreq =3D ext & EXT32_BITMASK; + + /* L is the low bit of the signed 24-bit significand. */ + sig =3D (sextract32(value, 7, 25) & ~1) | !!(lreq & LREQ_L); + /* The R bit is encoded as a deferred negation. */ + sig +=3D !!(lreq & LREQ_R); + sign =3D sig < 0; + exp =3D ((((value & 0xff) | (!!(lreq & LREQ_E) << 8)) - 128) & + 0x1ff) - 255; + precision =3D 23; + } else { + LREQ_t lreq =3D (ext & EXT16_BITMASK) << 2; + + sig =3D (sextract32(value, 4, 12) & ~1) | !!(lreq & LREQ_L); + sig +=3D !!(lreq & LREQ_R); + sign =3D sig < 0; + exp =3D (value & 0x1f) - BIAS_QF16; + precision =3D 10; + } + + if (sig =3D=3D 0) { + return (FloatParts64) { .cls =3D float_class_zero }; + } + + frac =3D sig < 0 ? -(int64_t)sig : sig; + return (FloatParts64) { + .cls =3D float_class_normal, + .sign =3D sign, + .exp =3D exp + 63 - clz64(frac) - precision, + .frac =3D frac << clz64(frac), + }; +} + +FloatParts64 qfloat_unfloat_parts(unfloat u) +{ + FloatParts64 parts =3D u.parts; + + parts.sign ^=3D u.sign; + return parts; +} + +static void qfloat_apply_inexact(FloatParts64 *parts, uint8_t ext) +{ + LREQ_t lreq =3D ext & EXT32_BITMASK; + + if (parts->cls !=3D float_class_normal || + !!(lreq & LREQ_R) =3D=3D !!(lreq & LREQ_Q)) { + return; + } + if (!parts->sign) { + parts->frac |=3D 1; + } else if (--parts->frac < (UINT64_C(1) << 63)) { + parts->frac =3D parts->frac << 1 | 1; + parts->exp--; + } +} + +static uint64_t qfloat_pack_ext(unsigned size, int64_t sig, int biased_exp, + LREQ_t lreq) +{ + lreq =3D (lreq & ~LREQ_E) | (((biased_exp >> 8) & 1) ? LREQ_E : 0); + if (size =3D=3D 32) { + uint64_t value =3D ((uint64_t)sig << 8) | (biased_exp & 0xff); + + return ((value & QF32_BITMASK) << 4) | + (lreq & EXT32_BITMASK); + } + return (((uint64_t)sig << 5 | (biased_exp & 0x1f)) & QF16_BITMASK) << = 2 | + ((lreq >> 2) & EXT16_BITMASK); +} + +static uint64_t qfloat_ext_overflow(unsigned size, bool sign, + qfrnd_mode_enum_t mode) +{ + uint32_t sig =3D size =3D=3D 32 ? MAX_SIG_QF32 : MAX_SIG_QF16; + int exp =3D size =3D=3D 32 ? E_MAX_EXTQF32 : E_MAX_EXTQF16; + int bias =3D size =3D=3D 32 ? BIAS_EXTQF32 : BIAS_QF16; + LREQ_t lreq =3D 0; + + if (mode =3D=3D RND_TO_ZERO || + (mode =3D=3D RND_TOWARDS_NEG_INF && !sign) || + (mode =3D=3D RND_TOWARDS_POS_INF && sign)) { + exp--; + } + lreq |=3D LREQ_L | LREQ_Q; + if (sign) { + sig =3D ~sig; + lreq =3D negate_lreq(lreq); + } + return qfloat_pack_ext(size, sig, exp + bias, lreq); +} + +static uint64_t qfloat_ext_underflow(unsigned size, bool sign, + qfrnd_mode_enum_t mode) +{ + int exp =3D size =3D=3D 32 ? E_MIN_EXTQF32 : E_MIN_EXTQF16; + int bias =3D size =3D=3D 32 ? BIAS_EXTQF32 : BIAS_QF16; + LREQ_t lreq =3D 0; + uint32_t sig =3D 0; + + if (mode =3D=3D RND_TOWARDS_POS_INF) { + lreq |=3D LREQ_R; + } else if (mode =3D=3D RND_TOWARDS_NEG_INF) { + lreq |=3D LREQ_Q; + } else { + lreq |=3D LREQ_Q; + } + if (sign) { + sig =3D ~sig; + lreq =3D negate_lreq(lreq); + } + return qfloat_pack_ext(size, sig, exp + bias, lreq); +} + +uint64_t qfloat_round_ext_parts(unsigned size, FloatParts64 parts, int exp, + bool deferred_sign, + qfrnd_mode_enum_t mode) +{ + unsigned precision =3D size =3D=3D 32 ? 23 : 10; + int emax =3D size =3D=3D 32 ? E_MAX_EXTQF32 : E_MAX_EXTQF16; + int emin =3D size =3D=3D 32 ? E_MIN_EXTQF32 : E_MIN_EXTQF16; + int bias =3D size =3D=3D 32 ? BIAS_EXTQF32 : BIAS_QF16; + int shift; + uint64_t integer, discarded, mask; + bool half, sticky, increment; + uint64_t quarters, rq1, even; + int64_t sig; + LREQ_t lreq =3D 0; + + if (parts.cls =3D=3D float_class_zero) { + exp =3D emin + bias; + if (size =3D=3D 32) { + return (uint64_t)(exp & 0xff) << 4 | + (((exp >> 8) & 1) << 1) | 7; + } + return (uint64_t)(exp & 0x1f) << 2 | 3; + } + if (parts.exp - exp >=3D 1) { + exp++; + } + if (exp > emax || + (exp =3D=3D emax && parts.frac > (UINT64_C(1) << 63))) { + return qfloat_ext_overflow(size, parts.sign, mode); + } + if (exp < emin) { + return qfloat_ext_underflow(size, parts.sign, mode); + } + + shift =3D 63 - precision - (parts.exp - exp); + if (shift > 64) { + integer =3D 0; + half =3D false; + sticky =3D true; + } else if (shift =3D=3D 64) { + integer =3D 0; + half =3D parts.frac >> 63; + sticky =3D parts.frac << 1; + } else if (shift > 0) { + integer =3D parts.frac >> shift; + mask =3D (UINT64_C(1) << shift) - 1; + discarded =3D parts.frac & mask; + half =3D discarded & (UINT64_C(1) << (shift - 1)); + sticky =3D discarded & ((UINT64_C(1) << (shift - 1)) - 1); + } else { + integer =3D parts.frac << -shift; + half =3D false; + sticky =3D false; + } + quarters =3D integer * 4 + (half ? 2 : 0) + (sticky ? 1 : 0); + + switch (mode) { + case RND_TO_NEAREST_EVEN: + increment =3D (quarters & 3) >=3D ((quarters >> 2 & 1) ? 2 : 3); + break; + case RND_TO_ZERO: + increment =3D false; + break; + case RND_TOWARDS_NEG_INF: + increment =3D parts.sign && (quarters & 3); + break; + case RND_TOWARDS_POS_INF: + increment =3D !parts.sign && (quarters & 3); + break; + default: + g_assert_not_reached(); + } + + rq1 =3D (quarters >> 2) * 8 + increment * 4 + + (increment ^ ((quarters & 3) !=3D 0)) * 2 + 1; + even =3D (rq1 >> 3) & ~UINT64_C(1); + rq1 -=3D even * 8 + 1; + sig =3D even >> 1; + lreq |=3D (rq1 >> 3) ? LREQ_L : 0; + lreq |=3D ((rq1 >> 2) & 1) ? LREQ_R : 0; + lreq |=3D ((rq1 >> 1) & 1) ? LREQ_Q : 0; + + if (parts.sign) { + sig =3D ~sig; + lreq =3D negate_lreq(lreq); + } + if (deferred_sign) { + lreq =3D negate_lreq(lreq); + } + + return qfloat_pack_ext(size, sig, exp + bias, lreq); +} + +/* + * NaN/Inf input behavior + */ + +uint64_t handle_infinity_nan_add(unfloat u, unfloat v, uint64_t pos_nan_va= l, + uint64_t neg_nan_val, uint64_t pos_inf_va= l, + uint64_t neg_inf_val) +{ + bool u_neg =3D is_unfloat_neg(u); + bool v_neg =3D is_unfloat_neg(v); + + if (u.nan || v.nan) { + /* +NaN has the highest priority */ + if ((!u_neg && u.nan) || (!v_neg && v.nan)) { + return pos_nan_val; + } + return neg_nan_val; + } + + /* Infinities of opposing sign added together produce a NaN */ + if (u.inf && v.inf && (u_neg ^ v_neg)) { + return pos_nan_val; + } + if ((u_neg && u.inf) || (v_neg && v.inf)) { + return neg_inf_val; + } + return pos_inf_val; +} + +uint64_t handle_infinity_nan_mpy(unfloat u, unfloat v, uint64_t pos_nan_va= l, + uint64_t neg_nan_val, uint64_t pos_inf_va= l, + uint64_t neg_inf_val) +{ + bool u_neg =3D is_unfloat_neg(u); + bool v_neg =3D is_unfloat_neg(v); + + if (u.nan || v.nan) { + return (u_neg ^ v_neg) ? neg_nan_val : pos_nan_val; + } + /* Implicitly, one of the operands is infinite: 0 * inf is a NaN */ + if (u.zero || v.zero) { + return (u_neg ^ v_neg) ? neg_nan_val : pos_nan_val; + } + return (u_neg ^ v_neg) ? neg_inf_val : pos_inf_val; +} + +/* + * Parse SF/HF/QF16/QF32 into an unfloat + */ + +unfloat parse_hf(int16_t in) +{ + INIT_UNFLOAT(out) + float_status status =3D { 0 }; + uint16_t raw =3D in; + + out.exp =3D (raw >> hf_MANTBITS) & 0x1f; + out.exp -=3D BIAS_HF; + if (out.exp < E_MIN_HF) { + out.exp =3D E_MIN_HF; + } + + out.sign =3D raw >> 15; + out.parts =3D float16_unpack_canonical(make_float16(in), &status); + out.inf =3D out.parts.cls =3D=3D float_class_inf; + out.nan =3D out.parts.cls =3D=3D float_class_qnan || + out.parts.cls =3D=3D float_class_snan; + out.zero =3D out.parts.cls =3D=3D float_class_zero; + out.parts.sign =3D false; + return out; +} + +static unfloat parse_sf(int32_t in) +{ + INIT_UNFLOAT(out) + float_status status =3D { 0 }; + uint32_t raw =3D in; + + out.exp =3D (raw >> sf_MANTBITS) & 0xff; + out.exp -=3D BIAS_SF; + if (out.exp < E_MIN_SF) { + out.exp =3D E_MIN_SF; + } + + out.sign =3D raw >> 31; + out.parts =3D float32_unpack_canonical(make_float32(in), &status); + out.inf =3D out.parts.cls =3D=3D float_class_inf; + out.nan =3D out.parts.cls =3D=3D float_class_qnan || + out.parts.cls =3D=3D float_class_snan; + out.zero =3D out.parts.cls =3D=3D float_class_zero; + out.parts.sign =3D false; + return out; +} + +unfloat parse_sf_daz(uint32_t in, bool daz_mode) +{ + unfloat a =3D parse_sf(in); + + if (daz_mode && (in & 0x7f800000) =3D=3D 0 && (in & 0x007fffff)) { + a.zero =3D true; + a.parts =3D (FloatParts64) { .cls =3D float_class_zero }; + } + return a; +} + +unfloat parse_extqf16(uint16_t in, uint8_t in_ext) +{ + INIT_UNFLOAT(out) + LREQ_t lreq =3D (in_ext & EXT16_BITMASK) << 2; + uint32_t raw =3D ((uint32_t)in << 4) | (in_ext & EXT16_BITMASK); + + out.exp =3D (in & 0x1f) - BIAS_QF16; + out.sign =3D !!(lreq & LREQ_R); + out.inf =3D is_extqf16_inf(raw); + out.nan =3D is_extqf16_nan(raw); + out.parts =3D qfloat_unpack_ext_parts(16, in, in_ext); + out.parts.sign ^=3D out.sign; + out.zero =3D out.parts.cls =3D=3D float_class_zero; + return out; +} + +unfloat parse_extqf32(uint32_t in, uint8_t in_ext) +{ + INIT_UNFLOAT(out) + LREQ_t lreq =3D in_ext & EXT32_BITMASK; + uint64_t raw =3D ((uint64_t)in << 4) | (in_ext & EXT32_BITMASK); + int exponent =3D (in & 0xff) | (!!(lreq & LREQ_E) << 8); + + /* First step, sub 128 to get to IEEE-like; then sub 255 for qf32 bias= */ + out.exp =3D ((exponent - 128) & 0x1ff) - 255; + out.sign =3D !!(lreq & LREQ_R); + out.inf =3D is_extqf32_inf(raw); + out.nan =3D is_extqf32_nan(raw); + out.parts =3D qfloat_unpack_ext_parts(32, in, in_ext); + out.parts.sign ^=3D out.sign; + out.zero =3D out.parts.cls =3D=3D float_class_zero; + return out; +} + +/* + * Convert QF16/QF32 to HF/SF/BF + */ + +static FloatRoundMode qfrnd_to_float_round(qfrnd_mode_enum_t qfrnd) +{ + switch (qfrnd) { + case RND_TO_NEAREST_EVEN: + return float_round_nearest_even; + case RND_TO_ZERO: + return float_round_to_zero; + case RND_TOWARDS_NEG_INF: + return float_round_down; + case RND_TOWARDS_POS_INF: + return float_round_up; + default: + g_assert_not_reached(); + } +} + +int32_t conv_sf_extqf32(uint32_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrnd) +{ + uint64_t raw =3D ((uint64_t)a << 4) | (a_ext & EXT32_BITMASK); + FloatParts64 parts; + float_status status =3D { 0 }; + + if (is_extqf32_nan(raw)) { + return raw =3D=3D extqf32_neg_nan || raw =3D=3D extqf32_neg_nan_in= exact ? + ieee_pos_NaN_32 | 0x80000000 : ieee_pos_NaN_32; + } + if (is_extqf32_inf(raw)) { + return raw =3D=3D extqf32_neg_inf_exact || + raw =3D=3D extqf32_neg_inf_inexact ? + ieee_pos_inf_32 | 0x80000000 : ieee_pos_inf_32; + } + set_float_rounding_mode(qfrnd_to_float_round(qfrnd), &status); + parts =3D qfloat_unpack_ext_parts(32, a, a_ext); + qfloat_apply_inexact(&parts, a_ext); + return float32_val(float32_round_pack_canonical(&parts, &status)); +} + +int16_t conv_hf_extqf32(uint32_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrnd) +{ + uint64_t raw =3D ((uint64_t)a << 4) | (a_ext & EXT32_BITMASK); + FloatParts64 parts; + float_status status =3D { 0 }; + + if (is_extqf32_nan(raw)) { + return (int16_t)(raw =3D=3D extqf32_neg_nan || + raw =3D=3D extqf32_neg_nan_inexact ? + ieee_pos_NaN_16 | 0x8000 : ieee_pos_NaN_16); + } + if (is_extqf32_inf(raw)) { + return (int16_t)(raw =3D=3D extqf32_neg_inf_exact || + raw =3D=3D extqf32_neg_inf_inexact ? + ieee_pos_inf_16 | 0x8000 : ieee_pos_inf_16); + } + set_float_rounding_mode(qfrnd_to_float_round(qfrnd), &status); + parts =3D qfloat_unpack_ext_parts(32, a, a_ext); + qfloat_apply_inexact(&parts, a_ext); + return float16_val(float16_round_pack_canonical(&parts, &status)); +} + +int16_t conv_hf_extqf16(uint16_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrnd) +{ + uint32_t raw =3D ((uint32_t)a << 4) | (a_ext & EXT16_BITMASK); + FloatParts64 parts; + float_status status =3D { 0 }; + + if (is_extqf16_nan(raw)) { + return (int16_t)(raw =3D=3D extqf16_neg_nan ? + ieee_pos_NaN_16 | 0x8000 : ieee_pos_NaN_16); + } + if (is_extqf16_inf(raw)) { + return (int16_t)(raw =3D=3D extqf16_neg_inf ? + ieee_pos_inf_16 | 0x8000 : ieee_pos_inf_16); + } + set_float_rounding_mode(qfrnd_to_float_round(qfrnd), &status); + parts =3D qfloat_unpack_ext_parts(16, a, a_ext); + return float16_val(float16_round_pack_canonical(&parts, &status)); +} + +uint16_t conv_qf32_to_bf(uint32_t a, uint8_t a_ext, qfrnd_mode_enum_t qfrn= d) +{ + uint64_t raw =3D ((uint64_t)a << 4) | (a_ext & EXT32_BITMASK); + FloatParts64 parts; + float_status status =3D { 0 }; + + if (is_extqf32_nan(raw)) { + return raw =3D=3D extqf32_neg_nan || raw =3D=3D extqf32_neg_nan_in= exact ? + BF_POS_NAN | 0x8000 : BF_POS_NAN; + } + if (is_extqf32_inf(raw)) { + return raw =3D=3D extqf32_neg_inf_exact || + raw =3D=3D extqf32_neg_inf_inexact ? BF_POS_INF | 0x8000 : + BF_POS_INF; + } + set_float_rounding_mode(qfrnd_to_float_round(qfrnd), &status); + parts =3D qfloat_unpack_ext_parts(32, a, a_ext); + qfloat_apply_inexact(&parts, a_ext); + return bfloat16_round_pack_canonical(&parts, &status); +} + +int qf_vilog2(f_type type, uint32_t a, uint8_t a_ext) +{ + unfloat u =3D { 0 }; + + if (type =3D=3D EXTQF32) { + uint64_t raw =3D ((uint64_t)a << 4) | (a_ext & EXT32_BITMASK); + FloatParts64 p; + + if (is_extqf32_nan(raw)) { + return QF32_ILOG2_NAN_EXP; + } + if (is_extqf32_inf(raw)) { + return QF32_ILOG2_INF_EXP; + } + p =3D qfloat_unpack_ext_parts(32, a, a_ext); + return p.cls =3D=3D float_class_zero ? QF32_ILOG2_ZERO_EXP : p.exp; + } + if (type =3D=3D EXTQF16) { + uint32_t raw =3D (a << 4) | (a_ext & EXT16_BITMASK); + FloatParts64 p; + + if (is_extqf16_nan(raw)) { + return QF16_ILOG2_NAN_EXP; + } + if (is_extqf16_inf(raw)) { + return QF16_ILOG2_INF_EXP; + } + p =3D qfloat_unpack_ext_parts(16, a, a_ext); + return p.cls =3D=3D float_class_zero ? QF16_ILOG2_ZERO_EXP : p.exp; + } + + switch (type) { + case SF: + u =3D parse_sf(a); + break; + case HF: + u =3D parse_hf(a); + break; + default: + g_assert_not_reached(); + } + + if (type =3D=3D SF) { + if (u.zero) { + return QF32_ILOG2_ZERO_EXP; + } else if (u.nan) { + return QF32_ILOG2_NAN_EXP; + } else if (u.inf) { + return QF32_ILOG2_INF_EXP; + } + } else { + if (u.zero) { + return QF16_ILOG2_ZERO_EXP; + } else if (u.nan) { + return QF16_ILOG2_NAN_EXP; + } else if (u.inf) { + return QF16_ILOG2_INF_EXP; + } + } + return u.parts.exp; +} + +/* + * USR field accessors + */ + +static uint32_t get_usr_field(const CPUHexagonState *env, int field) +{ + return extract32(env->gpr[HEX_REG_USR], reg_field_info[field].offset, + reg_field_info[field].width); +} + +bool is_daz_mode(const CPUHexagonState *env) +{ + const HexagonCPU *cpu =3D env_archcpu(env); + + return cpu->cfg.hex_def->hex_version >=3D HEX_VER_V81 && + get_usr_field(env, USR_FPDAZ); +} + +bool qfloat_is_extended(const CPUHexagonState *env) +{ + const HexagonCPU *cpu =3D env_archcpu(env); + + return cpu->cfg.hex_def->hex_version >=3D HEX_VER_V79; +} + +unfloat legacy_parse_qf32(int32_t in) +{ + unfloat out =3D { 0 }; + int32_t signif; + uint32_t magnitude; + + out.sign =3D (uint32_t)in >> 31; + out.exp =3D (in & 0xff) - BIAS_QF32; + signif =3D sextract32(in, 7, 25) | 1; + magnitude =3D signif < 0 ? -(uint32_t)signif : signif; + out.parts =3D (FloatParts64) { + .cls =3D float_class_normal, + .exp =3D out.exp + 31 - clz32(magnitude) - sf_MANTBITS, + .frac =3D (uint64_t)magnitude << (32 + clz32(magnitude)), + }; + return out; +} + +unfloat legacy_parse_qf16(int16_t in) +{ + unfloat out =3D { 0 }; + int16_t signif; + uint16_t magnitude; + + out.sign =3D (uint16_t)in >> 15; + out.exp =3D (in & 0x1f) - BIAS_QF16; + signif =3D sextract32((uint16_t)in, 4, 12) | 1; + magnitude =3D signif < 0 ? -(uint16_t)signif : signif; + out.parts =3D (FloatParts64) { + .cls =3D float_class_normal, + .exp =3D out.exp + 31 - clz32(magnitude) - hf_MANTBITS, + .frac =3D (uint64_t)magnitude << (32 + clz32(magnitude)), + }; + return out; +} + +static int legacy_add_exp(unfloat a, unfloat b) +{ + if (a.exp > b.exp) { + return MAX(a.parts.exp, b.exp); + } + return MAX(b.parts.exp, a.exp); +} + +/* + * Return the legacy rounded significand numerator. The result is N where + * the rounded value is normally N * 2^-(frac + 1). `half` selects the + * legacy arm which uses N * 2^-(frac + 2) and increments the exponent. + */ +static int64_t legacy_round_n(FloatParts64 parts, int exp, int frac, int a= dj, + bool midpoint, bool *half) +{ + int shift =3D 65 + exp - parts.exp - frac + adj; + uint64_t mask, low, threshold; + int64_t base; + + g_assert(parts.cls =3D=3D float_class_normal); + if (shift >=3D 64) { + return parts.sign ? -1 : 1; + } + if (shift <=3D 0) { + uint64_t magnitude =3D parts.frac << -shift; + int64_t value =3D parts.sign ? -(int64_t)magnitude : magnitude; + + return value; + } + + mask =3D (UINT64_C(1) << shift) - 1; + if (parts.sign) { + uint64_t twos =3D -parts.frac; + + low =3D twos & mask; + base =3D -(int64_t)((parts.frac + mask) >> shift) * 4; + } else { + low =3D parts.frac & mask; + base =3D (parts.frac >> shift) * 4; + } + + if (midpoint) { + threshold =3D UINT64_C(3) << (shift - 3); + if (low <=3D threshold) { + return base + 1; + } + threshold =3D UINT64_C(5) << (shift - 3); + if (low <=3D threshold) { + *half =3D true; + return base + 2; + } + } else { + threshold =3D UINT64_C(1) << (shift - 1); + if (low <=3D threshold) { + return base + 1; + } + } + return base + 3; +} + +static uint32_t legacy_rnd_sat_qf(int size, int exp, FloatParts64 parts) +{ + int frac =3D size =3D=3D 32 ? sf_MANTBITS : hf_MANTBITS; + int emax =3D size =3D=3D 32 ? 128 : 16; + int emin =3D size =3D=3D 32 ? -127 : -15; + int bias =3D size =3D=3D 32 ? BIAS_QF32 : BIAS_QF16; + uint32_t mask =3D size =3D=3D 32 ? 0x7fffff : 0x3ff; + bool sign =3D parts.sign; + bool exact_neg_two =3D sign && parts.exp =3D=3D exp + 1 && + parts.frac =3D=3D UINT64_C(1) << 63; + bool prod_ovf =3D parts.cls !=3D float_class_zero && + parts.exp >=3D exp + 1 && !exact_neg_two; + bool half =3D false; + int adj =3D 0; + int64_t n; + uint32_t sig_out; + + if (parts.cls =3D=3D float_class_zero) { + return 0; + } + if (exp >=3D emax + 1 || (prod_ovf && exp =3D=3D emax)) { + sig_out =3D (sign - 1) & mask; + exp =3D emax + bias; + goto pack; + } + if (exp <=3D emin - 2) { + sig_out =3D -sign & mask; + exp =3D emin + bias; + goto pack; + } + adj =3D exp =3D=3D emin - 1 || (prod_ovf && exp < emax); + n =3D legacy_round_n(parts, exp, frac, adj, + !adj && exp >=3D emin && exp < emax, &half); + sig_out =3D ((n < 0 ? -(uint64_t)n : (uint64_t)n) >> + (half ? 2 : 1)) & mask; + if (sign) { + sig_out =3D ~sig_out; + } + exp +=3D bias + adj + half; + +pack: + return (((sign << frac) | (sig_out & mask)) << (size =3D=3D 32 ? 8 : 5= )) | + (exp & (size =3D=3D 32 ? 0xff : 0x1f)); +} + +uint32_t legacy_qf_add(int size, unfloat a, unfloat b) +{ + float_status status =3D { 0 }; + FloatParts64 pa =3D qfloat_unfloat_parts(a); + FloatParts64 pb =3D qfloat_unfloat_parts(b); + FloatParts64 result =3D parts64_addsub(&pa, &pb, &status, false); + + return legacy_rnd_sat_qf(size, legacy_add_exp(a, b), result); +} + +uint32_t legacy_qf_mpy(int size, unfloat a, unfloat b) +{ + float_status status =3D { 0 }; + FloatParts64 pa =3D qfloat_unfloat_parts(a); + FloatParts64 pb =3D qfloat_unfloat_parts(b); + FloatParts64 result =3D parts64_mul(&pa, &pb, &status); + + return legacy_rnd_sat_qf(size, a.exp + b.exp, result); +} + +int32_t legacy_conv_sf_qf32(uint32_t a) +{ + unfloat value =3D legacy_parse_qf32(a); + FloatParts64 parts =3D qfloat_unfloat_parts(value); + float_status status =3D { 0 }; + + return float32_val(float32_round_pack_canonical(&parts, &status)); +} + +int16_t legacy_conv_hf_qf32(uint32_t a) +{ + unfloat value =3D legacy_parse_qf32(a); + FloatParts64 parts =3D qfloat_unfloat_parts(value); + float_status status =3D { 0 }; + + return float16_val(float16_round_pack_canonical(&parts, &status)); +} + +int16_t legacy_conv_hf_qf16(uint16_t a) +{ + unfloat value =3D legacy_parse_qf16(a); + FloatParts64 parts =3D qfloat_unfloat_parts(value); + float_status status =3D { 0 }; + + return float16_val(float16_round_pack_canonical(&parts, &status)); +} diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 2592acf21eb..b09ce7c285f 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -28,7 +28,7 @@ def gen_disabled_ieee_insn(f, tag, regs): for regtype, regid in regs: reg =3D hex_common.get_register(tag, regtype, regid) if reg.is_hvx_reg() and reg.is_written(): - reg.gen_zero(f) + reg.gen_zero(f, tag) f.write(" return;\n") f.write(" }\n") =20 diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 1812e024ba7..9d4650f52fb 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -448,16 +448,61 @@ def helper_arg_type(self): return "void *" def helper_arg_name(self): return f"{self.reg_tcg()}_void" - def gen_clear_ext(self, f): + def gen_clear_ext(self, f, tag): + predicate =3D None + guard =3D "" + end_guard =3D "" + if is_predicated(tag): + for regtype, regid in compute_tag_regs(tag, False): + if regtype =3D=3D "P": + predicate =3D get_register(tag, regtype, regid).reg_tc= g() + break + assert predicate is not None + cond =3D ("TCG_COND_NE" if "fLSBOLDNOT" in semdict[tag] + else "TCG_COND_EQ") + guard =3D f""" + TCGv {self.reg_tcg()}_ext_pred =3D tcg_temp_new(); + TCGLabel *{self.reg_tcg()}_ext_skip =3D gen_new_label(); + tcg_gen_andi_tl({self.reg_tcg()}_ext_pred, {predicate}, 1); + tcg_gen_brcondi_tl({cond}, {self.reg_tcg()}_ext_pred, 0, + {self.reg_tcg()}_ext_skip); + """ + end_guard =3D f""" + gen_set_label({self.reg_tcg()}_ext_skip); + """ f.write(code_fmt(f"""\ + {guard} tcg_gen_gvec_dup_imm_var(MO_8, {self.hvx_base()}, {self.hvx_off()} + offsetof(MMVector, ext), sizeof_field(MMVector, ext), sizeof_field(MMVector, ext), V_EXTENDED_BYTEVAL); + {end_guard} """)) - def gen_clear_ext_pair(self, f): + def gen_clear_ext_pair(self, f, tag): + predicate =3D None + guard =3D "" + end_guard =3D "" + if is_predicated(tag): + for regtype, regid in compute_tag_regs(tag, False): + if regtype =3D=3D "P": + predicate =3D get_register(tag, regtype, regid).reg_tc= g() + break + assert predicate is not None + cond =3D ("TCG_COND_NE" if "fLSBOLDNOT" in semdict[tag] + else "TCG_COND_EQ") + guard =3D f""" + TCGv {self.reg_tcg()}_ext_pred =3D tcg_temp_new(); + TCGLabel *{self.reg_tcg()}_ext_skip =3D gen_new_label(); + tcg_gen_andi_tl({self.reg_tcg()}_ext_pred, {predicate}, 1); + tcg_gen_brcondi_tl({cond}, {self.reg_tcg()}_ext_pred, 0, + {self.reg_tcg()}_ext_skip); + """ + end_guard =3D f""" + gen_set_label({self.reg_tcg()}_ext_skip); + """ f.write(code_fmt(f"""\ + {guard} tcg_gen_gvec_dup_imm_var(MO_8, {self.hvx_base()}, {self.hvx_off()} + offsetof(MMVector, ext), sizeof_field(MMVector, ext), @@ -469,6 +514,7 @@ def gen_clear_ext_pair(self, f): sizeof_field(MMVector, ext), sizeof_field(MMVector, ext), V_EXTENDED_BYTEVAL); + {end_guard} """)) =20 # @@ -815,13 +861,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) - self.gen_clear_ext(f) - def gen_zero(self, f): + self.gen_clear_ext(f, tag) + def gen_zero(self, f, tag): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) - self.gen_clear_ext(f) + self.gen_clear_ext(f, tag) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -892,13 +938,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) - self.gen_clear_ext(f) - def gen_zero(self, f): + self.gen_clear_ext(f, tag) + def gen_zero(self, f, tag): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) - self.gen_clear_ext(f) + self.gen_clear_ext(f, tag) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -937,13 +983,13 @@ def decl_tcg(self, f, tag, regno): {self.reg_tcg()}_srcoff, sizeof(MMVector), sizeof(MMVector)); """)) - self.gen_clear_ext(f) - def gen_zero(self, f): + self.gen_clear_ext(f, tag) + def gen_zero(self, f, tag): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), 0); """)) - self.gen_clear_ext(f) + self.gen_clear_ext(f, tag) def gen_write(self, f, tag): f.write(code_fmt(f"""\ gen_vreg_write(ctx, {self.hvx_base()}, {self.hvx_off()}, @@ -976,13 +1022,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) - self.gen_clear_ext_pair(f) - def gen_zero(self, f): + self.gen_clear_ext_pair(f, tag) + def gen_zero(self, f, tag): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) - self.gen_clear_ext_pair(f) + self.gen_clear_ext_pair(f, tag) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -1056,13 +1102,13 @@ def decl_tcg(self, f, tag, regno): """)) if not skip_qemu_helper(tag): self.decl_tcg_ptr(f) - self.gen_clear_ext_pair(f) - def gen_zero(self, f): + self.gen_clear_ext_pair(f, tag) + def gen_zero(self, f, tag): f.write(code_fmt(f"""\ tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) - self.gen_clear_ext_pair(f) + self.gen_clear_ext_pair(f, tag) def gen_write(self, f, tag): f.write(code_fmt(f"""\ gen_vreg_write_pair(ctx, {self.hvx_base()}, {self.hvx_off()}, diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index e5998768b14..77fd1c61017 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -3149,8 +3149,7 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,"Vd32.h= =3DVu32.hf", =20 ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf_rnd,"Vd32.h=3DVu32.hf:rnd", "Vector conversion of hf16 format to int hw, round to nearest even", - VdV.h[i] =3D float16_to_int16_scalbn(VuV.hf[i], float_round_nearest_ev= en, 0, - &env->hvx_fp_status)) + VdV.h[i] =3D conv_h_hf_rnd(VuV.hf[i], &env->hvx_fp_status)) =20 ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,"Vd32.sf=3DVu32.w", "Vector conversion of int w format to sf32", diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 09620de3324..06338523217 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -253,6 +253,7 @@ hexagon_ss.add(files( 'mmvec/decode_ext_mmvec.c', 'mmvec/system_ext_mmvec.c', 'mmvec/hvx_ieee_fp.c', + 'mmvec/hvx_qfloat.c', )) =20 hexagon_softmmu_ss.add(files( --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778805281158500 Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/mmvec/macros.h | 109 +++++++++++++ target/hexagon/mmvec/mmvec.h | 35 ++++ target/hexagon/tag_rev_info.c.inc | 41 +++++ target/hexagon/imported/mmvec/encode_ext.def | 51 ++++++ target/hexagon/imported/mmvec/ext.idef | 162 +++++++++++++++++++ 5 files changed, 398 insertions(+) diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index a4ab336983d..0e643b29109 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -24,6 +24,7 @@ #include "accel/tcg/getpc.h" #include "accel/tcg/probe.h" #include "mmvec/hvx_ieee_fp.h" +#include "mmvec/mmvec_qfloat.h" =20 #define fBFLOAT() #define fCVI_VX_NO_TMP_LD() @@ -386,4 +387,112 @@ #define fCMPEQ_SF(A, B) cmpeq_sf(A, B, &env->hvx_fp_status) #define fCMPEQ_HF(A, B) cmpeq_hf(A, B, &env->hvx_fp_status) =20 +/* + * qfloat extended-precision bits: {G,S}ET_VEXT access a vector element's + * ext; f{G,S}ETQFEXT_BIT view that storage as one raw bit per source byte, + * for the v{g,s}etqfext. + */ +#define GET_VEXT(VSRC, IDX, SIZE) get_extended_bits(&(VSRC), IDX, SIZE) +#define SET_VEXT(VDEST, IDX, SIZE, VAL) \ + set_extended_bits(&(VDEST), IDX, SIZE, VAL) +#define GET_VEXT_PAIR(VSRC, PAIR_IDX, IDX, SIZE) \ + get_extended_bits(&(VSRC).v[PAIR_IDX], IDX, SIZE) + +#define fGETQFEXT_BIT(REG, BITNO) \ + (0x1 & ((REG).ext[(BITNO) / 4] >> ((BITNO) % 4))) +#define fSETQFEXT_BIT(REG, BITNO, VAL) \ + do { \ + uint32_t bitno_val =3D (VAL); \ + (REG).ext[(BITNO) / 4] &=3D ~(1 << ((BITNO) % 4)); \ + (REG).ext[(BITNO) / 4] |=3D (bitno_val & 1) << ((BITNO) % 4); \ + } while (0) + +#define fPARSEHF(A) parse_hf(A) +#define fPARSESF(A) parse_sf_daz(A, is_daz_mode(env)) +#define fPARSEQF_EXT(SIZE, A, IDX) \ + (qfloat_is_extended(env) ? \ + parse_extqf##SIZE((A).qf##SIZE[IDX], \ + get_extended_bits(&(A), IDX, SIZE)) : \ + legacy_parse_qf##SIZE((A).qf##SIZE[IDX])) + +#define fQF_VILOG2(TYPE, A, AEXT) qf_vilog2(TYPE, A, AEXT) + +#define fCONVERT_QF32_TO_SF(A, AEXT) \ + (qfloat_is_extended(env) ? \ + conv_sf_extqf32(A, AEXT, CVI_QFRND_MODE) : legacy_conv_sf_qf32(A)) +#define fCONVERT_QF32_TO_HF(A, AEXT) \ + (qfloat_is_extended(env) ? \ + conv_hf_extqf32(A, AEXT, CVI_QFRND_MODE) : legacy_conv_hf_qf32(A)) +#define fCONVERT_QF32_TO_BF(A, AEXT) conv_qf32_to_bf(A, AEXT, CVI_QFRND_MO= DE) +#define fCONVERT_QF16_TO_HF(A, AEXT) \ + (qfloat_is_extended(env) ? \ + conv_hf_extqf16(A, AEXT, CVI_QFRND_MODE) : legacy_conv_hf_qf16(A)) + +/* + * Add/multiply two qfloat operands in the extended-precision "unfloat" + * domain and round+pack the result back into V.qf{16,32}[i] / V's ext bits + * at index i. + */ +#define fQFADD(SIZE, V, A, B) \ + do { \ + if (!qfloat_is_extended(env)) { \ + (V).qf##SIZE[i] =3D legacy_qf_add(SIZE, A, B); \ + } else if ((A).inf || (A).nan || (B).inf || (B).nan) { \ + uint64_t sig_36 =3D handle_infinity_nan_add((A), (B), \ + extqf##SIZE##_pos_nan, extqf##SIZE##_neg_nan, \ + extqf##SIZE##_pos_inf, extqf##SIZE##_neg_inf); \ + (V).qf##SIZE[i] =3D sig_36 >> 4; \ + set_extended_bits(&(V), i, SIZE, sig_36 & EXT##SIZE##_BITMASK)= ; \ + } else { \ + FloatParts64 pa =3D qfloat_unfloat_parts(A); \ + FloatParts64 pb =3D qfloat_unfloat_parts(B); \ + float_status status =3D { 0 }; \ + int sub =3D pa.sign ^ pb.sign; \ + int rexp; \ + if (pa.cls =3D=3D float_class_zero) { \ + rexp =3D (B).exp; \ + } else if (pb.cls =3D=3D float_class_zero) { \ + rexp =3D (A).exp; \ + } else if ((A).exp > (B).exp) { \ + rexp =3D MAX(pa.exp - sub, (B).exp); \ + } else { \ + rexp =3D MAX(pb.exp - sub, (A).exp); \ + } \ + FloatParts64 pr =3D parts64_addsub(&pa, &pb, \ + &status, false); \ + uint64_t result =3D qfloat_round_ext_parts(SIZE, pr, rexp, \ + (A).sign && (B).sign= , \ + CVI_QFRND_MODE); \ + (V).qf##SIZE[i] =3D (result >> (SIZE / 8)) & QF##SIZE##_BITMAS= K; \ + set_extended_bits(&(V), i, SIZE, result & EXT##SIZE##_BITMASK)= ; \ + } \ + } while (0) + +#define fQFMPY(SIZE, V, A, B) \ + do { \ + if (!qfloat_is_extended(env)) { \ + (V).qf##SIZE[i] =3D legacy_qf_mpy(SIZE, A, B); \ + } else if ((A).inf || (A).nan || (B).inf || (B).nan) { \ + uint64_t sig_36 =3D handle_infinity_nan_mpy((A), (B), \ + extqf##SIZE##_pos_nan, extqf##SIZE##_neg_nan, \ + extqf##SIZE##_pos_inf, extqf##SIZE##_neg_inf); \ + (V).qf##SIZE[i] =3D sig_36 >> 4; \ + set_extended_bits(&(V), i, SIZE, sig_36 & EXT##SIZE##_BITMASK)= ; \ + } else { \ + FloatParts64 pa =3D qfloat_unfloat_parts(A); \ + FloatParts64 pb =3D qfloat_unfloat_parts(B); \ + float_status status =3D { 0 }; \ + int rexp =3D (A).exp + (B).exp; \ + bool defer =3D (A).sign ^ (B).sign ^ (A).parts.sign ^ \ + (B).parts.sign ^ \ + ((A).parts.sign && (B).parts.sign); \ + FloatParts64 pr =3D parts64_mul(&pa, &pb, &status); \ + uint64_t result =3D qfloat_round_ext_parts(SIZE, pr, rexp, \ + defer, \ + CVI_QFRND_MODE); \ + (V).qf##SIZE[i] =3D (result >> (SIZE / 8)) & QF##SIZE##_BITMAS= K; \ + set_extended_bits(&(V), i, SIZE, result & EXT##SIZE##_BITMASK)= ; \ + } \ + } while (0) + #endif diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index a761b0c69d6..de36e12e30a 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -56,6 +56,9 @@ typedef struct { float32 sf[MAX_VEC_SIZE_BYTES / 4]; float16 hf[MAX_VEC_SIZE_BYTES / 2]; bfloat16 bf[MAX_VEC_SIZE_BYTES / 2]; + /* qfloat "visible" mantissa/exponent, sans the extended bits belo= w */ + int32_t qf32[MAX_VEC_SIZE_BYTES / 4]; + int16_t qf16[MAX_VEC_SIZE_BYTES / 2]; }; /* * Extended precision bits for qfloat: one byte per qf32 element (only @@ -72,6 +75,38 @@ typedef struct { MMVector v[2]; } MMVectorPair; =20 +/* + * val is expected to already be masked to the width of the extended-bits + * field being written (1 bit for a qf32 element, 2 bits for a qf16 + * element); size selects which. + */ +static inline void set_extended_bits(MMVector *v, int i, int size, uint8_t= val) +{ + if (size =3D=3D 32) { + v->ext[i] =3D val; + } else { + /* Two qf16 elements share an ext byte: low 2 bits, then high 2 */ + if (i % 2 =3D=3D 1) { + v->ext[i / 2] =3D ((val & 0x3) << 2) | (v->ext[i / 2] & 0x3); + } else { + v->ext[i / 2] =3D (v->ext[i / 2] & 0xc) | (val & 0x3); + } + } +} + +static inline uint8_t get_extended_bits(const MMVector *v, int i, int size) +{ + if (size =3D=3D 32) { + return v->ext[i]; + } else { + if (i % 2 =3D=3D 1) { + return (v->ext[i / 2] >> 2) & 0x3; + } else { + return v->ext[i / 2] & 0x3; + } + } +} + typedef union { uint64_t ud[MAX_VEC_SIZE_BYTES / 8 / 8]; int64_t d[MAX_VEC_SIZE_BYTES / 8 / 8]; diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_inf= o.c.inc index c12896cd6c7..41ce3cb572f 100644 --- a/target/hexagon/tag_rev_info.c.inc +++ b/target/hexagon/tag_rev_info.c.inc @@ -657,6 +657,47 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_= OPCODE] =3D { [V6_vconv_h_hf_rnd] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX_VER_NONE }, + + [V6_get_qfext] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER= _NONE }, + [V6_get_qfext_oracc] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_set_qfext] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER= _NONE }, + [V6_vabs_qf16_hf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, + [V6_vabs_qf16_qf16] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_vabs_qf32_qf32] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_vabs_qf32_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, + [V6_vconv_bf_qf32] =3D { .introduced =3D HEX_VER_V81, .removed =3D HEX= _VER_NONE }, + [V6_vconv_qf16_hf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, + [V6_vconv_qf16_qf16] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_vconv_qf32_qf32] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_vconv_qf32_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX= _VER_NONE }, + [V6_vilog2_hf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER= _NONE }, + [V6_vilog2_qf16] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_V= ER_NONE }, + [V6_vilog2_qf32] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_V= ER_NONE }, + [V6_vilog2_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER= _NONE }, + [V6_vmerge_qf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VER= _NONE }, + [V6_vmpy_rt_hf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VE= R_NONE }, + [V6_vmpy_rt_qf16] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, + [V6_vmpy_rt_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_VE= R_NONE }, + [V6_vneg_qf16_hf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, + [V6_vneg_qf16_qf16] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_vneg_qf32_qf32] =3D { + .introduced =3D HEX_VER_V79, .removed =3D HEX_VER_NONE + }, + [V6_vneg_qf32_sf] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_= VER_NONE }, + [V6_vsub_hf_mix] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_V= ER_NONE }, + [V6_vsub_sf_mix] =3D { .introduced =3D HEX_VER_V79, .removed =3D HEX_V= ER_NONE }, }; =20 #endif /* HEXAGON_TAG_ARCH_TABLE_H */ diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index b46f51492d9..34e63b89743 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -893,4 +893,55 @@ DEF_ENC(V6_vgtbf_and,"00011100100vvvvvPP1uuuuu110100xx= ") DEF_ENC(V6_vgtbf_or,"00011100100vvvvvPP1uuuuu001110xx") DEF_ENC(V6_vgtbf_xor,"00011100100vvvvvPP1uuuuu111100xx") =20 +/* QFloat extended-precision instructions */ +DEF_ENC(V6_get_qfext,"00011001110tttttPP0uuuuu111ddddd") +DEF_ENC(V6_get_qfext_oracc,"00011001110tttttPP0uuuuu110xxxxx") +DEF_ENC(V6_set_qfext,"00011001110tttttPP0uuuuu011ddddd") +DEF_ENC(V6_vmerge_qf,"00011111000vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vabs_qf16_hf,"00011110--0-1110PP1uuuuu110ddddd") +DEF_ENC(V6_vabs_qf16_qf16,"00011110--0-1110PP1uuuuu111ddddd") +DEF_ENC(V6_vabs_qf32_qf32,"00011110--0-1110PP1uuuuu101ddddd") +DEF_ENC(V6_vabs_qf32_sf,"00011110--0-1110PP1uuuuu100ddddd") +DEF_ENC(V6_vadd_hf,"00011111011vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vadd_qf16,"00011111011vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vadd_qf16_mix,"00011111011vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vadd_qf32,"00011111101vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vadd_qf32_mix,"00011111101vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vadd_sf,"00011111101vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vconv_bf_qf32,"00011110--0-0110PP1uuuuu111ddddd") +DEF_ENC(V6_vconv_hf_qf16,"00011110--0-0100PP1uuuuu011ddddd") +DEF_ENC(V6_vconv_hf_qf32,"00011110--0-0100PP1uuuuu110ddddd") +DEF_ENC(V6_vconv_qf16_hf,"00011110--0-1100PP1uuuuu100ddddd") +DEF_ENC(V6_vconv_qf16_qf16,"00011110--0-1100PP1uuuuu110ddddd") +DEF_ENC(V6_vconv_qf32_qf32,"00011110--0-1101PP1uuuuu111ddddd") +DEF_ENC(V6_vconv_qf32_sf,"00011110--0-1101PP1uuuuu110ddddd") +DEF_ENC(V6_vconv_sf_qf32,"00011110--0-0100PP1uuuuu000ddddd") +DEF_ENC(V6_vilog2_hf,"00011110--0-1100PP1uuuuu011ddddd") +DEF_ENC(V6_vilog2_qf16,"00011110--0-1100PP1uuuuu001ddddd") +DEF_ENC(V6_vilog2_qf32,"00011110--0-1100PP1uuuuu000ddddd") +DEF_ENC(V6_vilog2_sf,"00011110--0-1100PP1uuuuu010ddddd") +DEF_ENC(V6_vmpy_qf16,"00011111111vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmpy_qf16_hf,"00011111111vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vmpy_qf16_mix_hf,"00011111111vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vmpy_qf32,"00011111111vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vmpy_qf32_hf,"00011111111vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vmpy_qf32_mix_hf,"00011111100vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vmpy_qf32_qf16,"00011111111vvvvvPP1uuuuu110ddddd") +DEF_ENC(V6_vmpy_qf32_sf,"00011111111vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vmpy_rt_hf,"00011010000tttttPP1uuuuu011ddddd") +DEF_ENC(V6_vmpy_rt_qf16,"00011010000tttttPP1uuuuu010ddddd") +DEF_ENC(V6_vmpy_rt_sf,"00011010000tttttPP1uuuuu001ddddd") +DEF_ENC(V6_vneg_qf16_hf,"00011110--0-1110PP1uuuuu010ddddd") +DEF_ENC(V6_vneg_qf16_qf16,"00011110--0-1110PP1uuuuu011ddddd") +DEF_ENC(V6_vneg_qf32_qf32,"00011110--0-1110PP1uuuuu001ddddd") +DEF_ENC(V6_vneg_qf32_sf,"00011110--0-1110PP1uuuuu000ddddd") +DEF_ENC(V6_vsub_hf,"00011111011vvvvvPP1uuuuu110ddddd") +DEF_ENC(V6_vsub_hf_mix,"00011010000vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vsub_qf16,"00011111011vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vsub_qf16_mix,"00011111011vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vsub_qf32,"00011111101vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vsub_qf32_mix,"00011111101vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vsub_sf,"00011111101vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vsub_sf_mix,"00011010000vvvvvPP1uuuuu000ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 77fd1c61017..3592930777e 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -3339,6 +3339,168 @@ ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, "Vd32= .bf=3Dvmin(Vu32.bf,Vv32.bf)", "Vector IEEE min: bf", VdV.bf[i] =3D fp_min_bf(VuV.bf[i], VvV.bf[i]); fBFLOAT()) =20 + +/*************************************************************************= ***** + QFloat extended-precision instructions + *************************************************************************= *****/ + +EXTINSN(V6_get_qfext,"Vd32=3Dvgetqfext(Vu32.x,Rt32)",ATTRIBS(A_EXTENSION,A= _CVI,A_CVI_VX,A_HVX_FLT),"Store with extended bits of a vreg into QReg", +{ fHIDE(int i;) fVFOREACH(8, i) { VdV.ub[i] =3D fGETQFEXT_BIT(VuV,i) ? fGE= TUBYTE(i % 4, RtV) : 0; } }) + +EXTINSN(V6_get_qfext_oracc,"Vx32|=3Dvgetqfext(Vu32.x,Rt32)",ATTRIBS(A_EXTE= NSION,A_CVI,A_CVI_VX,A_HVX_FLT),"Store with extended bits of a vreg into QR= eg", +{ fHIDE(int i;) fVFOREACH(8, i) { VxV.ub[i] |=3D fGETQFEXT_BIT(VuV,i) ? fG= ETUBYTE(i % 4, RtV) : 0; } }) + +EXTINSN(V6_set_qfext,"Vd32.x=3Dvsetqfext(Vu32,Rt32)",ATTRIBS(A_EXTENSION,A= _CVI,A_CVI_VX,A_HVX_FLT),"Load extended bits of Vreg using QReg", +{ + fHIDE(int i;) + fVFOREACH(8, i) { + /* Not explicitly stated at the spec, but this insn should clear t= he main bits. */ + VdV.ub[i] =3D 0; + fSETQFEXT_BIT(VdV,i,((VuV.ub[i] & fGETUBYTE(i % 4, RtV)) !=3D 0) ?= 1 : 0); + } +}) + +EXTINSN(V6_vmerge_qf,"Vd32=3Dvmerge(Vu32.x,Vv32.w)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Merge 32 bit word and 4 bit extended bits", +{ fHIDE(int i;) fVFOREACH(32, i) { VdV.uw[i] =3D VvV.uw[i]; SET_VEXT(VdV,i= ,32,GET_VEXT(VuV,i,32)); } }) + +EXTINSN(V6_vabs_qf16_hf,"Vd32.qf16=3Dvabs(Vu32.hf)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Convert absolute value of hf to qf32", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); if(is_unfloat_neg(u)) u.sign =3D !u.sign; INIT_UNFLOAT(v) v.exp =3D E_MI= N_EXTQF16; v.sign =3D 1; fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vabs_qf16_qf16,"Vd32.qf16=3Dvabs(Vu32.qf16)",ATTRIBS(A_EXTENSIO= N,A_CVI,A_CVI_VS,A_HVX_FLT),"Normalize absolute qf16 value", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); if(is_unfloat_neg(u)) u.sign =3D !u.sign; INIT_UNFLOAT(v) v.exp =3D E= _MIN_EXTQF16; v.sign =3D 1; fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vabs_qf32_qf32,"Vd32.qf32=3Dvabs(Vu32.qf32)",ATTRIBS(A_EXTENSIO= N,A_CVI,A_CVI_VS,A_HVX_FLT),"Normalize absolute qf32 value", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); if(is_unfloat_neg(u)) u.sign =3D !u.sign; INIT_UNFLOAT(v) v.exp =3D E= _MIN_EXTQF32; v.sign =3D 1; fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vabs_qf32_sf,"Vd32.qf32=3Dvabs(Vu32.sf)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Convert absolute value of sf to qf32", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); if(is_unfloat_neg(u)) u.sign =3D !u.sign; INIT_UNFLOAT(v) v.exp =3D E_MI= N_EXTQF32; v.sign =3D 1; fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vadd_hf,"Vd32.qf16=3Dvadd(Vu32.hf,Vv32.hf)",ATTRIBS(A_EXTENSION= ,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector addition of hf input", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); fHIDE(unfloat )v =3D fPARSEHF(VvV.hf[i]); fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vadd_qf16,"Vd32.qf16=3Dvadd(Vu32.qf16,Vv32.qf16)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector addition of qf16 input", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEQF_EXT(16,VvV,i); fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vadd_qf16_mix,"Vd32.qf16=3Dvadd(Vu32.qf16,Vv32.hf)",ATTRIBS(A_E= XTENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector addition of mixed qf16 and hf", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEHF(VvV.hf[i]); fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vadd_qf32,"Vd32.qf32=3Dvadd(Vu32.qf32,Vv32.qf32)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector addition of qf32 input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); fHIDE(unfloat )v =3D fPARSEQF_EXT(32,VvV,i); fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vadd_qf32_mix,"Vd32.qf32=3Dvadd(Vu32.qf32,Vv32.sf)",ATTRIBS(A_E= XTENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector addition of mixed qf32 and sf", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); fHIDE(unfloat )v =3D fPARSESF(VvV.sf[i]); fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vadd_sf,"Vd32.qf32=3Dvadd(Vu32.sf,Vv32.sf)",ATTRIBS(A_EXTENSION= ,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector addition of sf input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); fHIDE(unfloat )v =3D fPARSESF(VvV.sf[i]); fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vconv_bf_qf32,"Vd32.bf=3DVuu32.qf32",ATTRIBS(A_EXTENSION,A_CVI,= A_CVI_VS,A_HVX_FLT),"Vector conversion of double qf32 to BF", +{ fHIDE(int i;) fVFOREACH(32, i) { + VdV.bf[2*i] =3D fCONVERT_QF32_TO_BF(VuuV.v[0].qf32[i], GET_VEXT_PAIR(V= uuV,0,i,32)); + VdV.bf[2*i+1] =3D fCONVERT_QF32_TO_BF(VuuV.v[1].qf32[i], GET_VEXT_PAIR= (VuuV,1,i,32)); +} }) + +EXTINSN(V6_vconv_hf_qf16,"Vd32.hf=3DVu32.qf16",ATTRIBS(A_EXTENSION,A_CVI,A= _CVI_VS,A_HVX_FLT),"Vector conversion of qf16 format to ieee HF", +{ fHIDE(int i;) fVFOREACH(16, i) { VdV.hf[i] =3D fCONVERT_QF16_TO_HF(VuV.q= f16[i],GET_VEXT(VuV,i,16)) ; } }) + +EXTINSN(V6_vconv_hf_qf32,"Vd32.hf=3DVuu32.qf32",ATTRIBS(A_EXTENSION,A_CVI,= A_CVI_VS,A_HVX_FLT),"Vector conversion of double qf32 to ieee HF", +{ fHIDE(int i;) fVFOREACH(32, i) { VdV.hf[2*i] =3D fCONVERT_QF32_TO_HF(Vuu= V.v[0].qf32[i], GET_VEXT_PAIR(VuuV,0,i,32)); VdV.hf[2*i+1] =3D fCONVERT_QF3= 2_TO_HF(VuuV.v[1].qf32[i], GET_VEXT_PAIR(VuuV,1,i,32)); } }) + +EXTINSN(V6_vconv_qf16_hf,"Vd32.qf16=3DVu32.hf",ATTRIBS(A_EXTENSION,A_CVI,A= _CVI_VS,A_HVX_FLT),"Vector conversion of qf16 format to ieee HF", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); INIT_UNFLOAT(v) v.exp =3D E_MIN_EXTQF16; v.sign =3D 1; fQFADD(16,VdV,u,v= ) ; } }) + +EXTINSN(V6_vconv_qf16_qf16,"Vd32.qf16=3DVu32.qf16",ATTRIBS(A_EXTENSION,A_C= VI,A_CVI_VS,A_HVX_FLT),"Vector conversion of qf16 to qf16", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); INIT_UNFLOAT(v) v.exp =3D E_MIN_EXTQF16; v.sign =3D 1; fQFADD(16,VdV,= u,v) ; } }) + +EXTINSN(V6_vconv_qf32_qf32,"Vd32.qf32=3DVu32.qf32",ATTRIBS(A_EXTENSION,A_C= VI,A_CVI_VS,A_HVX_FLT),"Normalize qf32 value", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); INIT_UNFLOAT(v) v.exp =3D E_MIN_EXTQF32; v.sign =3D 1; fQFADD(32,VdV,= u,v) ; } }) + +EXTINSN(V6_vconv_qf32_sf,"Vd32.qf32=3DVu32.sf",ATTRIBS(A_EXTENSION,A_CVI,A= _CVI_VS,A_HVX_FLT),"Vector conversion of ieee SF to qf32", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); INIT_UNFLOAT(v) v.exp =3D E_MIN_EXTQF32; v.sign =3D 1; fQFADD(32,VdV,u,v= ) ; } }) + +EXTINSN(V6_vconv_sf_qf32,"Vd32.sf=3DVu32.qf32",ATTRIBS(A_EXTENSION,A_CVI,A= _CVI_VS,A_HVX_FLT),"Vector conversion of qf32 format to ieee SF", +{ fHIDE(int i;) fVFOREACH(32, i) { VdV.sf[i] =3D fCONVERT_QF32_TO_SF(VuV.q= f32[i],GET_VEXT(VuV,i,32)) ; } }) + +EXTINSN(V6_vilog2_hf,"Vd32.w=3Dvilog2(Vu32.hf)",ATTRIBS(A_EXTENSION,A_CVI,= A_CVI_VS,A_HVX_FLT),"Exponent extraction of hf", +{ fHIDE(int i;) fVFOREACH(16, i) { VdV.h[i] =3D fQF_VILOG2(HF,VuV.hf[i],0)= ; } }) + +EXTINSN(V6_vilog2_qf16,"Vd32.w=3Dvilog2(Vu32.qf16)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Exponent extraction of qf16", +{ fHIDE(int i;) fVFOREACH(16, i) { VdV.h[i] =3D fQF_VILOG2(EXTQF16,VuV.qf1= 6[i],GET_VEXT(VuV,i,16)) ; } }) + +EXTINSN(V6_vilog2_qf32,"Vd32.w=3Dvilog2(Vu32.qf32)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Exponent extraction of qf32", +{ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] =3D fQF_VILOG2(EXTQF32,VuV.qf3= 2[i],GET_VEXT(VuV,i,32)) ; } }) + +EXTINSN(V6_vilog2_sf,"Vd32.w=3Dvilog2(Vu32.sf)",ATTRIBS(A_EXTENSION,A_CVI,= A_CVI_VS,A_HVX_FLT),"Exponent extraction of sf", +{ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] =3D fQF_VILOG2(SF,VuV.sf[i],0)= ; } }) + +EXTINSN(V6_vmpy_qf16,"Vd32.qf16=3Dvmpy(Vu32.qf16,Vv32.qf16)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: qf16 output from qf16= inupt", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEQF_EXT(16,VvV,i); fQFMPY(16,VdV,u,v) ; } }) + +EXTINSN(V6_vmpy_qf16_hf,"Vd32.qf16=3Dvmpy(Vu32.hf,Vv32.hf)",ATTRIBS(A_EXTE= NSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: qf16 output from ieee = hf input", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); fHIDE(unfloat )v =3D fPARSEHF(VvV.hf[i]); fQFMPY(16,VdV,u,v) ; } }) + +EXTINSN(V6_vmpy_qf16_mix_hf,"Vd32.qf16=3Dvmpy(Vu32.qf16,Vv32.hf)",ATTRIBS(= A_EXTENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: qf16 output from= mixed input of qf16 and ieee hf", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEHF(VvV.hf[i]); fQFMPY(16,VdV,u,v) ; } }) + +EXTINSN(V6_vmpy_qf32,"Vd32.qf32=3Dvmpy(Vu32.qf32,Vv32.qf32)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: qf32 output from qf32= input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); fHIDE(unfloat )v =3D fPARSEQF_EXT(32,VvV,i); fQFMPY(32,VdV,u,v) ; } }) + +EXTINSN(V6_vmpy_qf32_hf,"Vdd32.qf32=3Dvmpy(Vu32.hf,Vv32.hf)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: double qf32 output fr= om ieee hf input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u0 =3D fPARSEHF(VuV.w[i]= & 0xFFFF); fHIDE(unfloat )u1 =3D fPARSEHF((VuV.w[i]>>16) & 0xFFFF); fHIDE(= unfloat )v0 =3D fPARSEHF(VvV.w[i] & 0xFFFF); fHIDE(unfloat )v1 =3D fPARSEHF= ((VvV.w[i]>>16) & 0xFFFF); fQFMPY(32,VddV.v[0],u0,v0); fQFMPY(32,VddV.v[1],= u1,v1) ; } }) + +EXTINSN(V6_vmpy_qf32_mix_hf,"Vdd32.qf32=3Dvmpy(Vu32.qf16,Vv32.hf)",ATTRIBS= (A_EXTENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: double qf32 out= put from mixed input of qf16 and ieee hf", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u0 =3D fPARSEQF_EXT(16,V= uV,2*i); fHIDE(unfloat )u1 =3D fPARSEQF_EXT(16,VuV,2*i+1); fHIDE(unfloat )v= 0 =3D fPARSEHF(VvV.w[i] & 0xFFFF); fHIDE(unfloat )v1 =3D fPARSEHF((VvV.w[i]= >>16) & 0xFFFF); fQFMPY(32,VddV.v[0],u0,v0); fQFMPY(32,VddV.v[1],u1,v1) ; }= }) + +EXTINSN(V6_vmpy_qf32_qf16,"Vdd32.qf32=3Dvmpy(Vu32.qf16,Vv32.qf16)",ATTRIBS= (A_EXTENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: double qf32 out= put from qf16 input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u0 =3D fPARSEQF_EXT(16,V= uV,2*i); fHIDE(unfloat )u1 =3D fPARSEQF_EXT(16,VuV,2*i+1); fHIDE(unfloat )v= 0 =3D fPARSEQF_EXT(16,VvV,2*i); fHIDE(unfloat )v1 =3D fPARSEQF_EXT(16,VvV,2= *i+1); fQFMPY(32,VddV.v[0],u0,v0); fQFMPY(32,VddV.v[1],u1,v1) ; } }) + +EXTINSN(V6_vmpy_qf32_sf,"Vd32.qf32=3Dvmpy(Vu32.sf,Vv32.sf)",ATTRIBS(A_EXTE= NSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Vector multiply: qf32 output from IEEE = sf input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); fHIDE(unfloat )v =3D fPARSESF(VvV.sf[i]); fQFMPY(32,VdV,u,v) ; } }) + +EXTINSN(V6_vmpy_rt_hf,"Vd32.qf16=3Dvmpy(Vu32.hf,Rt32.hf)",ATTRIBS(A_EXTENS= ION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Qfloat16 multiply with scalar and hf inpu= t", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); fHIDE(unfloat )v =3D fPARSEHF((RtV >> ((i%2)*16)) & 0xFFFF); fQFMPY(16,V= dV,u,v) ; } }) + +EXTINSN(V6_vmpy_rt_qf16,"Vd32.qf16=3Dvmpy(Vu32.qf16,Rt32.hf)",ATTRIBS(A_EX= TENSION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Qfloat16 multiply with scalar and qf1= 6 input", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEHF((RtV >> ((i%2)*16)) & 0xFFFF); fQFMPY(1= 6,VdV,u,v) ; } }) + +EXTINSN(V6_vmpy_rt_sf,"Vd32.qf32=3Dvmpy(Vu32.sf,Rt32.sf)",ATTRIBS(A_EXTENS= ION,A_CVI,A_CVI_VX_DV,A_HVX_FLT),"Qfloat32 multiply with scalar and sf inpu= t", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); fHIDE(unfloat )v =3D fPARSESF(RtV); fQFMPY(32,VdV,u,v) ; } }) + +EXTINSN(V6_vneg_qf16_hf,"Vd32.qf16=3Dvneg(Vu32.hf)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Negate and convert hf to qf16", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); u.sign =3D !u.sign; INIT_UNFLOAT(v) v.exp =3D E_MIN_EXTQF16; v.sign =3D = 1; fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vneg_qf16_qf16,"Vd32.qf16=3Dvneg(Vu32.qf16)",ATTRIBS(A_EXTENSIO= N,A_CVI,A_CVI_VS,A_HVX_FLT),"Negate and normalize qf16", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); u.sign =3D !u.sign; INIT_UNFLOAT(v) v.exp =3D E_MIN_EXTQF16; v.sign = =3D 1; fQFADD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vneg_qf32_qf32,"Vd32.qf32=3Dvneg(Vu32.qf32)",ATTRIBS(A_EXTENSIO= N,A_CVI,A_CVI_VS,A_HVX_FLT),"Negate and normalize qf32 value", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); INIT_UNFLOAT(v) u.sign =3D !u.sign; v.exp =3D E_MIN_EXTQF32; v.sign = =3D 1; fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vneg_qf32_sf,"Vd32.qf32=3Dvneg(Vu32.sf)",ATTRIBS(A_EXTENSION,A_= CVI,A_CVI_VS,A_HVX_FLT),"Negate and convert sf to qf32", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); INIT_UNFLOAT(v) u.sign =3D !u.sign; v.exp =3D E_MIN_EXTQF32; v.sign =3D = 1; fQFADD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vsub_hf,"Vd32.qf16=3Dvsub(Vu32.hf,Vv32.hf)",ATTRIBS(A_EXTENSION= ,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of hf input", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); fHIDE(unfloat )v =3D fPARSEHF(VvV.hf[i]); v.sign =3D !v.sign; fQFADD(16,= VdV,u,v) ; } }) + +EXTINSN(V6_vsub_hf_mix,"Vd32.qf16=3Dvsub(Vu32.hf,Vv32.qf16)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of mixed hf and qf16", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEHF(VuV.hf[i]= ); fHIDE(unfloat )v =3D fPARSEQF_EXT(16,VvV,i); v.sign =3D !v.sign; fQFADD(= 16,VdV,u,v) ; } }) + +EXTINSN(V6_vsub_qf16,"Vd32.qf16=3Dvsub(Vu32.qf16,Vv32.qf16)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of qf16 input", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEQF_EXT(16,VvV,i); v.sign =3D !v.sign; fQFA= DD(16,VdV,u,v) ; } }) + +EXTINSN(V6_vsub_qf16_mix,"Vd32.qf16=3Dvsub(Vu32.qf16,Vv32.hf)",ATTRIBS(A_E= XTENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of mixed qf16 and hf= ", +{ fHIDE(int i;) fVFOREACH(16, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(16,Vu= V,i); fHIDE(unfloat )v =3D fPARSEHF(VvV.hf[i]); v.sign =3D !v.sign; fQFADD(= 16,VdV,u,v) ; } }) + +EXTINSN(V6_vsub_qf32,"Vd32.qf32=3Dvsub(Vu32.qf32,Vv32.qf32)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of qf32 input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); fHIDE(unfloat )v =3D fPARSEQF_EXT(32,VvV,i); v.sign =3D !v.sign; fQFA= DD(32,VdV,u,v) ; } }) + +EXTINSN(V6_vsub_qf32_mix,"Vd32.qf32=3Dvsub(Vu32.qf32,Vv32.sf)",ATTRIBS(A_E= XTENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of mixed qf32 input = and sf", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSEQF_EXT(32,Vu= V,i); fHIDE(unfloat )v =3D fPARSESF(VvV.sf[i]); v.sign =3D !v.sign; fQFADD(= 32,VdV,u,v) ; } }) + +EXTINSN(V6_vsub_sf,"Vd32.qf32=3Dvsub(Vu32.sf,Vv32.sf)",ATTRIBS(A_EXTENSION= ,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of ieee sf input", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); fHIDE(unfloat )v =3D fPARSESF(VvV.sf[i]); v.sign =3D !v.sign; fQFADD(32,= VdV,u,v) ; } }) + +EXTINSN(V6_vsub_sf_mix,"Vd32.qf32=3Dvsub(Vu32.sf,Vv32.qf32)",ATTRIBS(A_EXT= ENSION,A_CVI,A_CVI_VS,A_HVX_FLT),"Vector subtraction of mixed sf input and = qf32", +{ fHIDE(int i;) fVFOREACH(32, i) { fHIDE(unfloat )u =3D fPARSESF(VuV.sf[i]= ); fHIDE(unfloat )v =3D fPARSEQF_EXT(32,VvV,i); v.sign =3D !v.sign; fQFADD(= 32,VdV,u,v) ; } }) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778721594158500 Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- linux-user/hexagon/elfload.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c index 440532ee413..3a6ba4e1304 100644 --- a/linux-user/hexagon/elfload.c +++ b/linux-user/hexagon/elfload.c @@ -53,6 +53,15 @@ abi_ulong get_elf_hwcap(CPUState *cs) case HEX_VER_V73: hwcaps =3D HWCAP_HEXAGON_ISA_V73; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778807263158500 Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- tests/tcg/hexagon/check_rev_gating.c | 12 +- tests/tcg/hexagon/hvx_ext.c | 248 +++++++++++++++++++++++++ tests/tcg/hexagon/qfloat_v81.c | 119 ++++++++++++ tests/tcg/hexagon/v81_hvx.c | 259 +++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 25 +++ 5 files changed, 662 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/hexagon/hvx_ext.c create mode 100644 tests/tcg/hexagon/qfloat_v81.c create mode 100644 tests/tcg/hexagon/v81_hvx.c diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check= _rev_gating.c index 3f48ab9cd35..ad22a93bdaf 100644 --- a/tests/tcg/hexagon/check_rev_gating.c +++ b/tests/tcg/hexagon/check_rev_gating.c @@ -3,7 +3,7 @@ * are rejected with SIGILL. * * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds - * instructions from v68 up through v79 via .word encoding: the + * instructions from v68 up through v81 via .word encoding: the * assembler enforces the selected CPU's own minimum version, so none * of these -- including ones it otherwise knows how to assemble at * their own target, such as callrh or unpause -- can be written as @@ -122,6 +122,12 @@ TRY_FUNC(v79_dczeroa_nt, TRY_FUNC(v79_dcfetchbo_nt, ".word 0x9402e000 /* dcfetch(r2+#0):nt */\n") =20 +TRY_FUNC(v79hvx_vmerge_qf, + ".word 0x1f01e0e2 /* v2 =3D vmerge(v0.x, v1.w) */\n") + +TRY_FUNC(v81hvx_veqhf, + ".word 0x1f82c11c /* q0 =3D vcmp.eq(v1.hf, v2.hf) */\n") + int main(void) { struct sigaction act; @@ -160,6 +166,10 @@ int main(void) assert(try_v79_dczeroa_nt() =3D=3D SIGILL); assert(try_v79_dcfetchbo_nt() =3D=3D SIGILL); =20 + assert(try_v79hvx_vmerge_qf() =3D=3D SIGILL); + + assert(try_v81hvx_veqhf() =3D=3D SIGILL); + assert(signals_handled =3D=3D expected_signals); =20 puts("PASS"); diff --git a/tests/tcg/hexagon/hvx_ext.c b/tests/tcg/hexagon/hvx_ext.c new file mode 100644 index 00000000000..e3747d87b76 --- /dev/null +++ b/tests/tcg/hexagon/hvx_ext.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Tests for HVX qfloat extended-precision bits: vsetqfext/ + * vgetqfext, vmerge's ext-bit passthrough, and the "any non-qfloat write + * resets a vector's ext bits to the V_EXTENDED_BYTEVAL sentinel" rule -- + * including through .cur/.tmp loads and predicated/packet-internal + * forwarding, where it's easy to get the reset timing wrong. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int err; +static bool extended_qfloat; + +#include "hvx_misc.h" + +static unsigned long hwcap(void) +{ + return getauxval(AT_HWCAP); +} + +static void test_qf32_mpy(void) +{ + HVX_Vector input =3D Q6_V_vsplat_R(-1); + HVX_Vector result =3D Q6_Vqf32_vmpy_Vqf32Vqf32(input, input); + + memcpy(output, &result, sizeof(result)); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D extended_qfloat ? 0x0000007f : 0x7fffffff; + } + + check_output_w(__LINE__, 1); +} + +static void test_ext_bits_reset_on_copy(void) +{ + /* Fixed register identities are part of what this test exercises. */ + asm volatile( + "r0 =3D #0x11111111\n" + "v10 =3D vsplat(r0)\n" + "v0.x =3D vsetqfext(v10, r0)\n" + "v1.x =3D vsetqfext(v10, r0)\n" + "v2 =3D vgetqfext(v0.x, r0)\n" + "v3 =3D vgetqfext(v1.x, r0)\n" + "v1 =3D v0\n" + "v4 =3D vgetqfext(v0.x, r0)\n" + "v5 =3D vgetqfext(v1.x, r0)\n" + "vmemu(%[out0]) =3D v2\n" + "vmemu(%[out1]) =3D v3\n" + "vmemu(%[out2]) =3D v4\n" + "vmemu(%[out3]) =3D v5\n" + : + : [out0] "r"(&output[0]), [out1] "r"(&output[1]), + [out2] "r"(&output[2]), [out3] "r"(&output[3]) + : "r0", "v0", "v1", "v2", "v3", "v4", "v5", "v10", "memory"); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D expect[1].uw[i] =3D expect[2].uw[i] =3D 0x1111= 1111; + expect[3].uw[i] =3D 0x11001100; + } + + check_output_w(__LINE__, 4); +} + +static void test_ext_bits_reset_multiple_insns(void) +{ + asm volatile( + "r1 =3D #0xe60e31d4\n" + "r2 =3D #0xbaf1fa15\n" + "r3 =3D #0x4a777c7b\n" + "v1 =3D vsplat(r1)\n" + "v2 =3D vsplat(r2)\n" + "v3 =3D vsplat(r3)\n" + + "{\n" + " v2 =3D v1\n" + " v4.sf =3D vmax(v3.sf,v2.sf)\n" + "}\n" + "v5.hf =3D v4.qf16\n" + "vmemu(%[out]) =3D v5\n" + : + : [out] "r"(output) + : "r1", "r2", "r3", "v1", "v2", "v3", "v4", "v5", "memory"); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0x5ca76fc7; /* reference from the sim */ + } + + check_output_w(__LINE__, 1); +} + +static void test_ext_bits_reset_interleaved_qf(void) +{ + HVX_Vector v1 =3D Q6_V_vsplat_R(0x00000057); + HVX_Vector v2 =3D v1; + HVX_Vector v3 =3D Q6_V_vsplat_R(0x2a8b9bf4); + HVX_Vector v4 =3D v3; + HVX_Vector v5 =3D Q6_Vqf32_vadd_VsfVsf(v2, v4); + HVX_Vector v6; + + v5 =3D Q6_Vhf_vmin_VhfVhf(v1, v3); + v6 =3D Q6_Vqf16_vmpy_Vqf16Vhf(v5, v1); + memcpy(output, &v6, sizeof(v6)); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0x0000f766; /* reference from the sim */ + } + + check_output_w(__LINE__, 1); +} + +static void test_ext_bits_preserved_on_false_predicate(void) +{ + asm volatile( + "r0 =3D #0x11111111\n" + "v3 =3D vsplat(r0)\n" + "v0.x =3D vsetqfext(v3, r0)\n" + "r2 =3D #1\n" + "v1 =3D vsplat(r2)\n" + "r1 =3D #0\n" + "p0 =3D cmp.eq(r1, r2)\n" + "{\n" + " if (p0) v0 =3D v1\n" + "}\n" + "v2 =3D vgetqfext(v0.x, r0)\n" + "vmemu(%[out]) =3D v2\n" + : + : [out] "r"(output) + : "r0", "r1", "r2", "v0", "v1", "v2", "v3", "p0", "memory"); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0x11111111; + } + check_output_w(__LINE__, 1); +} + +static void test_qfloat_semantics(void) +{ + HVX_Vector a =3D Q6_V_vsplat_R(0xfde1d91d); + HVX_Vector b =3D Q6_V_vsplat_R(0xffffff80); + HVX_Vector result =3D Q6_Vqf32_vsub_Vqf32Vqf32(a, b); + + memcpy(output, &result, sizeof(result)); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D extended_qfloat ? 0x7fffff68 : 0x3fffff69; + } + + check_output_w(__LINE__, 1); +} + +static void test_qfloat_with_cur(void) +{ + memset(buffer0, 0xff, sizeof(buffer0)); + asm volatile( + "r0 =3D #0x11111111\n" + "v10 =3D vsplat(r0)\n" + + "r1 =3D #0xffffff80\n" + "v1 =3D vsplat(r1)\n" + + /* tweak ext bits */ + "v0.x =3D vsetqfext(v10, r0)\n" + "v2 =3D vmerge(v0.x, v1.w)\n" + + "{\n" + " v2.cur =3D vmem(%[buf]++#0)\n" + " v3.qf32=3Dvsub(v2.qf32, v1.qf32)\n" + "}\n" + "vmemu(%[out]) =3D v3\n" + : + : [buf] "r"(buffer0), [out] "r"(output) + : "r0", "r1", "v0", "v1", "v2", "v3", "v10", "memory"); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0x800000e7; /* reference from the sim */ + } + + check_output_w(__LINE__, 1); +} + +static void test_qfloat_with_tmp(void) +{ + memset(buffer0, 0xff, sizeof(buffer0)); + asm volatile( + "r0 =3D #0x11111111\n" + "v10 =3D vsplat(r0)\n" + + "r1 =3D #0xffffff80\n" + "v1 =3D vsplat(r1)\n" + + /* tweak ext bits */ + "v0.x =3D vsetqfext(v10, r0)\n" + "v2 =3D vmerge(v0.x, v1.w)\n" + + "{\n" + " v3.tmp =3D vmem(%[buf]++#0)\n" + " v3.qf32=3Dvsub(v2.qf32, v1.qf32)\n" + " v4 =3D v3\n" + "}\n" + "vmemu(%[out0]) =3D v3\n" + + "v10 =3D vgetqfext(v3.x, r0)\n" + "vmemu(%[out1]) =3D v10\n" + : + : [buf] "r"(buffer0), [out0] "r"(&output[0]), [out1] "r"(&output[1= ]) + : "r0", "r1", "v0", "v1", "v2", "v3", "v4", "v10", "memory"); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0x00000080; /* reference from the sim */ + expect[1].uw[i] =3D 0x00111111; /* tmp should not reset v3's ext b= its */ + } + + check_output_w(__LINE__, 2); +} + +int main() +{ + extended_qfloat =3D HWCAP_HEXAGON_HAS_ISA(hwcap(), + HWCAP_HEXAGON_ISA_V79); + + test_qf32_mpy(); + if (extended_qfloat) { + test_ext_bits_reset_on_copy(); + test_ext_bits_preserved_on_false_predicate(); + test_ext_bits_reset_interleaved_qf(); + test_qfloat_with_cur(); + test_qfloat_with_tmp(); + } + test_ext_bits_reset_multiple_insns(); + test_qfloat_semantics(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/qfloat_v81.c b/tests/tcg/hexagon/qfloat_v81.c new file mode 100644 index 00000000000..4fdd4809071 --- /dev/null +++ b/tests/tcg/hexagon/qfloat_v81.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#include +#include + +static int err; + +#include "hvx_misc.h" + +static void expect_h(int output_index, uint16_t value) +{ + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + expect[output_index].uh[i] =3D value; + } +} + +static void expect_w(int output_index, uint32_t value) +{ + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[output_index].uw[i] =3D value; + } +} + +static void test_qf16(void) +{ + asm volatile( + "r0 =3D #0x3c003c00\n" + "v1 =3D vsplat(r0)\n" + "r0 =3D #0x40004000\n" + "v2 =3D vsplat(r0)\n" + "v0.qf16 =3D vadd(v1.hf, v2.hf)\n" + "v3.hf =3D v0.qf16\n" + "r0 =3D #0x10001000\n" + "v2 =3D vsplat(r0)\n" + "v0.qf16 =3D vadd(v1.hf, v2.hf)\n" + "v5.hf =3D v0.qf16\n" + "r0 =3D #0xc000c000\n" + "v1 =3D vsplat(r0)\n" + "v0.qf16 =3D vabs(v1.hf)\n" + "v6.hf =3D v0.qf16\n" + "r0 =3D #0x40004000\n" + "v1 =3D vsplat(r0)\n" + "v0.qf16 =3D vneg(v1.hf)\n" + "v7.hf =3D v0.qf16\n" + "vmemu(%[out0]) =3D v3\n" + "vmemu(%[out1]) =3D v5\n" + "vmemu(%[out2]) =3D v6\n" + "vmemu(%[out3]) =3D v7\n" + : + : [out0] "r"(&output[0]), [out1] "r"(&output[1]), + [out2] "r"(&output[2]), [out3] "r"(&output[3]) + : "r0", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "memory"); + + expect_h(0, 0x4200); + expect_h(1, 0x3c00); + expect_h(2, 0x4000); + expect_h(3, 0xc002); + check_output_h(__LINE__, 4); +} + +static void test_qf32(void) +{ + asm volatile( + "r0 =3D #0x3f800000\n" + "v1 =3D vsplat(r0)\n" + "r0 =3D #0x40000000\n" + "v2 =3D vsplat(r0)\n" + "v0.qf32 =3D vadd(v1.sf, v2.sf)\n" + "v3.sf =3D v0.qf32\n" + "v4.w =3D vilog2(v0.qf32)\n" + "r0 =3D #0x7f800000\n" + "v1 =3D vsplat(r0)\n" + "r0 =3D #0xff800000\n" + "v2 =3D vsplat(r0)\n" + "v0.qf32 =3D vadd(v1.sf, v2.sf)\n" + "v5.sf =3D v0.qf32\n" + "vmemu(%[out0]) =3D v3\n" + "vmemu(%[out1]) =3D v4\n" + "vmemu(%[out2]) =3D v5\n" + : + : [out0] "r"(&output[0]), [out1] "r"(&output[1]), + [out2] "r"(&output[2]) + : "r0", "v0", "v1", "v2", "v3", "v4", "v5", "memory"); + + expect_w(0, 0x40400000); + expect_w(1, 1); + expect_w(2, 0x7fffffff); + check_output_w(__LINE__, 3); +} + +static void test_qf32_bf_conversion(void) +{ + HVX_Vector one =3D Q6_V_vsplat_R(0x3c003c00); + HVX_VectorPair qf =3D Q6_Wqf32_vmpy_VhfVhf(one, one); + HVX_Vector result =3D Q6_Vbf_equals_Wqf32(qf); + + memcpy(output, &result, sizeof(result)); + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + expect[0].uh[i] =3D 0x3f80; + } + check_output_h(__LINE__, 1); +} + +int main() +{ + test_qf16(); + test_qf32(); + test_qf32_bf_conversion(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/v81_hvx.c b/tests/tcg/hexagon/v81_hvx.c new file mode 100644 index 00000000000..226dc931d02 --- /dev/null +++ b/tests/tcg/hexagon/v81_hvx.c @@ -0,0 +1,259 @@ +/* + * Test the HVX instructions that are new in v81: + * - V6_veqhf/V6_veqsf (and the _and/_or/_xor predicate-accumulate forms) + * - V6_valign4 + * - V6_vconv_h_hf_rnd + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include + +int err; +#include "hvx_misc.h" +#include "hex_test.h" + +#define MAX_TESTS_hf (MAX_VEC_SIZE_BYTES / 2) +#define MAX_TESTS_sf (MAX_VEC_SIZE_BYTES / 4) + +#define TRUE_MASK_sf 0xffffffff +#define TRUE_MASK_hf 0xffff + +static const char *comparisons[MAX_TESTS_sf][2]; +static HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; +static HVX_Vector buffers[2], true_vec, false_vec; +static int exp_index; + +#define ADD_TEST_CMP(TYPE, VAL1, VAL2, EXP) do { \ + assert(exp_index < MAX_TESTS_##TYPE); \ + ((MMVector *)&buffers[0])->TYPE[exp_index] =3D VAL1; \ + ((MMVector *)&buffers[1])->TYPE[exp_index] =3D VAL2; \ + expect[0].TYPE[exp_index] =3D EXP ? TRUE_MASK_##TYPE : 0; \ + comparisons[exp_index][0] =3D #VAL1; \ + comparisons[exp_index][1] =3D #VAL2; \ + exp_index++; \ +} while (0) + +#define TEST_CMP_EQ(TYPE, VAL1, VAL2, EXP) do { \ + ADD_TEST_CMP(TYPE, VAL1, VAL2, EXP); \ + ADD_TEST_CMP(TYPE, VAL2, VAL1, EXP); \ +} while (0) + +#define PREP_TEST() do { \ + memset(&buffers, 0, sizeof(buffers)); \ + memset(expect, 0, sizeof(expect)); \ + exp_index =3D 0; \ +} while (0) + +#define CHECK(TYPE, TYPESZ) do { \ + HVX_VectorPred pred =3D \ + Q6_Q_vcmp_eq_V##TYPE##V##TYPE(buffers[0], buffers[1]); \ + *hvx_output =3D Q6_V_vmux_QVV(pred, true_vec, false_vec); \ + for (int j =3D 0; j < exp_index; j++) { \ + if (output[0].TYPE[j] !=3D expect[0].TYPE[j]) { \ + printf("ERROR: expected %s %s %s\n", comparisons[j][0], \ + (expect[0].TYPE[j] !=3D 0 ? "=3D=3D" : "!=3D"), compari= sons[j][1]); \ + err++; \ + } \ + } \ +} while (0) + +static void test_cmp_eq_sf(void) +{ + PREP_TEST(); + TEST_CMP_EQ(sf, raw_sf(2.2), raw_sf(2.2), true); + TEST_CMP_EQ(sf, raw_sf(2.2), raw_sf(2.1), false); + TEST_CMP_EQ(sf, SF_zero, SF_zero_neg, true); + CHECK(sf, 4); + + /* NaNs never compare equal, even to themselves */ + PREP_TEST(); + TEST_CMP_EQ(sf, SF_QNaN, SF_QNaN, false); + TEST_CMP_EQ(sf, SF_SNaN, SF_SNaN, false); + TEST_CMP_EQ(sf, SF_QNaN, SF_SNaN, false); + TEST_CMP_EQ(sf, SF_QNaN, SF_one, false); + TEST_CMP_EQ(sf, SF_INF, SF_QNaN, false); + CHECK(sf, 4); + + /* Infinities of like sign compare equal */ + PREP_TEST(); + TEST_CMP_EQ(sf, SF_INF, SF_INF, true); + TEST_CMP_EQ(sf, SF_INF_neg, SF_INF_neg, true); + TEST_CMP_EQ(sf, SF_INF, SF_INF_neg, false); + CHECK(sf, 4); +} + +static void test_cmp_eq_hf(void) +{ + PREP_TEST(); + TEST_CMP_EQ(hf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.2), true); + TEST_CMP_EQ(hf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1), false); + TEST_CMP_EQ(hf, (uint16_t)0, (uint16_t)0x8000, true); + CHECK(hf, 2); + + /* NaNs never compare equal, even to themselves */ + PREP_TEST(); + TEST_CMP_EQ(hf, HF_QNaN, HF_QNaN, false); + TEST_CMP_EQ(hf, HF_SNaN, HF_SNaN, false); + TEST_CMP_EQ(hf, HF_QNaN, HF_SNaN, false); + TEST_CMP_EQ(hf, HF_QNaN, HF_one, false); + TEST_CMP_EQ(hf, HF_INF, HF_QNaN, false); + CHECK(hf, 2); + + /* Infinities of like sign compare equal */ + PREP_TEST(); + TEST_CMP_EQ(hf, HF_INF, HF_INF, true); + TEST_CMP_EQ(hf, HF_INF_neg, HF_INF_neg, true); + TEST_CMP_EQ(hf, HF_INF, HF_INF_neg, false); + CHECK(hf, 2); +} + +static void check_byte_pred(HVX_VectorPred pred, int byte_idx, uint8_t exp= _mask, + int line) +{ + /* + * Note: ((uint8_t *)&pred)[N] returns the expanded value of bit N: + * 0xFF if bit is set, 0x00 if clear. + */ + for (int i =3D 0; i < 8; i++) { + int idx =3D byte_idx * 8 + i; + int val =3D ((uint8_t *)&pred)[idx]; + int exp =3D (exp_mask >> i) & 1 ? 0xff : 0x00; + if (exp !=3D val) { + printf("ERROR line %d: pred bit %d is 0x%x, should be 0x%x\n", + line, idx, val, exp); + err++; + } + } +} + +#define CHECK_BYTE_PRED(PRED, BYTE, EXP) \ + check_byte_pred(PRED, BYTE, EXP, __LINE__) + +static void test_cmp_eq_variants(void) +{ + HVX_VectorPred pred; + + /* + * Setup: comparison result will have bits 4-7 set (0xF0 in pred byte = 0) + * - sf[0]: SF_zero =3D=3D SF_one =3D false -> bits 0-3 =3D 0 + * - sf[1]: SF_one =3D=3D SF_one =3D true -> bits 4-7 =3D 1 + */ + PREP_TEST(); + ADD_TEST_CMP(sf, SF_zero, SF_one, false); + ADD_TEST_CMP(sf, SF_one, SF_one, true); + + /* equal and: 0xF0 & 0xF0 =3D 0xF0 */ + memset(&pred, 0xF0, sizeof(pred)); + pred =3D Q6_Q_vcmp_eqand_QVsfVsf(pred, buffers[0], buffers[1]); + CHECK_BYTE_PRED(pred, 0, 0xF0); + + /* equal or: 0x0F | 0xF0 =3D 0xFF */ + memset(&pred, 0x0F, sizeof(pred)); + pred =3D Q6_Q_vcmp_eqor_QVsfVsf(pred, buffers[0], buffers[1]); + CHECK_BYTE_PRED(pred, 0, 0xFF); + + /* equal xor: 0xFF ^ 0xF0 =3D 0x0F */ + memset(&pred, 0xFF, sizeof(pred)); + pred =3D Q6_Q_vcmp_eqxacc_QVsfVsf(pred, buffers[0], buffers[1]); + CHECK_BYTE_PRED(pred, 0, 0x0F); +} + +static void test_valign4(void) +{ + HVX_Vector vu =3D Q6_V_vsplat_R(0x11111111); + HVX_Vector vv =3D Q6_V_vsplat_R(0x22222222); + + static const uint32_t expected[4] =3D { + 0x11111111, /* Rt & 0x3 =3D=3D 0: no shift */ + 0x11111122, /* Rt & 0x3 =3D=3D 1: shift by 8 */ + 0x11112222, /* Rt & 0x3 =3D=3D 2: shift by 16 */ + 0x11222222, /* Rt & 0x3 =3D=3D 3: shift by 24 */ + }; + + for (int rt =3D 0; rt < 4; rt++) { + HVX_Vector result =3D Q6_V_valign4_VVR(vu, vv, rt); + MMVector *r =3D (MMVector *)&result; + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + check(__LINE__, rt, j, r->uw[j], expected[rt]); + } + } +} + +static void test_vconv_h_hf_rnd(void) +{ + /* + * V6_vconv_h_hf_rnd always rounds to nearest-even, regardless of + * USR.FPRND. Verified against hexagon-sim: all four FPRND settings + * (nearest-even, toward-zero, toward -inf, toward +inf) produce + * identical results for this instruction. + */ + uint32_t usr; + HVX_Vector input =3D Q6_V_vsplat_R( + ((uint32_t)raw_hf((_Float16)1.5) << 16) | raw_hf((_Float16)(-1.5))= ); + HVX_Vector result =3D Q6_Vh_equals_Vhf_rnd(input); + MMVector *r =3D (MMVector *)&result; + + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + check(__LINE__, 0, 2 * j, r->h[2 * j], -2); + check(__LINE__, 0, 2 * j + 1, r->h[2 * j + 1], 2); + } + + asm("%0 =3D usr" : "=3Dr"(usr)); + usr =3D (usr & ~(3u << 22)) | (1u << 22); /* round toward zero */ + asm("usr =3D %0" : : "r"(usr) : "usr"); + result =3D Q6_Vh_equals_Vhf_rnd(input); + r =3D (MMVector *)&result; + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + check(__LINE__, 0, 2 * j, r->h[2 * j], -2); + check(__LINE__, 0, 2 * j + 1, r->h[2 * j + 1], 2); + } + + usr =3D (usr & ~(3u << 22)) | (2u << 22); /* round toward -infinity */ + asm("usr =3D %0" : : "r"(usr) : "usr"); + result =3D Q6_Vh_equals_Vhf_rnd(input); + r =3D (MMVector *)&result; + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + check(__LINE__, 0, 2 * j, r->h[2 * j], -2); + check(__LINE__, 0, 2 * j + 1, r->h[2 * j + 1], 2); + } + + usr =3D (usr & ~(3u << 22)) | (3u << 22); /* round toward +infinity */ + asm("usr =3D %0" : : "r"(usr) : "usr"); + result =3D Q6_Vh_equals_Vhf_rnd(input); + r =3D (MMVector *)&result; + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + check(__LINE__, 0, 2 * j, r->h[2 * j], -2); + check(__LINE__, 0, 2 * j + 1, r->h[2 * j + 1], 2); + } + + input =3D Q6_V_vsplat_R(((uint32_t)0x7e00 << 16) | 0xfe00); + result =3D Q6_Vh_equals_Vhf_rnd(input); + r =3D (MMVector *)&result; + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { + check(__LINE__, 0, 2 * j, r->h[2 * j], INT16_MIN); + check(__LINE__, 0, 2 * j + 1, r->h[2 * j + 1], INT16_MAX); + } +} + +int main(void) +{ + memset(&true_vec, 0xff, sizeof(true_vec)); + memset(&false_vec, 0, sizeof(false_vec)); + + test_cmp_eq_sf(); + test_cmp_eq_hf(); + test_cmp_eq_variants(); + test_valign4(); + test_vconv_h_hf_rnd(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index c46d90e3954..a6ace4c77c2 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -42,6 +42,16 @@ tests +=3D { 'qemu_args': ['-cpu', 'v73,ieee-fp=3Dfalse']}, 'fp_hvx_cvt.c': {'cflags': [cflags, '-mv73', '-mhvx', '-mhvx-ieee-fp']}, 'fp_hvx_cmp.c': {'cflags': [cflags, '-mv73', '-mhvx', '-mhvx-ieee-fp']}, + 'v81_hvx.c': {'cflags': [cflags, '-mv81', '-mhvx', '-mhvx-ieee-fp'], + 'qemu_args': ['-cpu', 'v81']}, + 'qfloat_v81.c': {'cflags': [cflags, '-mv81', '-mhvx', '-mhvx-ieee-fp'], + 'qemu_args': ['-cpu', 'v81']}, + # Run the QFloat test below and above the v79 extended-QFloat boundary. + 'hvx_ext.c': { + 'cflags': [cflags, '-mv79', '-mhvx', '-mhvx-ieee-fp'], + 'qemu_args': ['-cpu', 'v68'], + 'test_name': 'hvx_ext-v68', + }, 'hvx_misc.c': {'cflags': [cflags, '-mhvx', '-mv69']}, 'hvx_histogram.c': { 'cflags': [cflags, '-mhvx', '-Wno-gnu-folding-constant', @@ -111,6 +121,21 @@ tests +=3D { 'vector_add_int.c': {'cflags': [cflags, '-mhvx', '-fvectorize']}, } =20 +tests +=3D [ + { + 'hvx_ext.c': { + 'qemu_args': ['-cpu', 'v79'], + 'test_name': 'hvx_ext-v79', + }, + }, + { + 'hvx_ext.c': { + 'qemu_args': ['-cpu', 'v81'], + 'test_name': 'hvx_ext-v81', + }, + }, +] + if 'qemu-hexagon' in emulators tcg_tests +=3D { 'hexagon-linux-user': { --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778851; cv=none; d=zohomail.com; s=zohoarc; b=mJI7HnsOETI2kbik+MhFbr/8dC3nxigD7JgsbiTSvRs/Xc4cl0Yg+9y5kn/n/3WauQu+re9KXYXF1/SrvKmG1tiGw96gDiPR/JTX9Q3IwyxZW5k6F6tUL97VwgOI8GtYFYtQKHeSRtiprivxkv0bMKsreHnFC58xK5iC852dOiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778851; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bNGiNareYZOosENIsqHDCIWM67DHPYhQB2MBRNJdxmg=; b=EN7m82PeCldW22pImp3joF+DYQrqqf700aNewsXOwrKB+zpMGXuOIWyULGRSdoPMYb0qkRvEfB40hDyqvuYzANdndxVi1Uu/EeacDPvD68wqwm5y9cxRSB4gKkTe6vMHDqyUxEmNI2VPcRd7MuQDMUA8lDR30JU91dQbQ+gygxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778851046151.3050134446779; Sun, 11 Oct 2026 21:20:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7Ut-0002mA-O1; Mon, 12 Oct 2026 00:18:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UL-0001yv-Uh for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:15 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UK-0001BQ-Aj for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:13 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lHnj052538 for ; Mon, 12 Oct 2026 04:18:00 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7en9vg3g-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:18:00 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-357e2bc3b1bso2757293eec.0 for ; Sun, 11 Oct 2026 21:18:00 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778852081158500 Generate release barriers before release and HVX scatter-release operations, acquire barriers after acquire loads, and full barriers for barrier, syncht, isync, and dmsyncht. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/translate.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 6715758bfa0..cd1abdf1461 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -836,12 +836,27 @@ static void mark_store_width(DisasContext *ctx) =20 static void gen_insn(DisasContext *ctx) { + uint16_t opcode =3D ctx->insn->opcode; + + if (GET_ATTRIB(opcode, A_RELEASE) || + GET_ATTRIB(opcode, A_CVI_SCATTER_RELEASE)) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + if (ctx->insn->generate) { ctx->insn->generate(ctx); mark_store_width(ctx); } else { hex_gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE); } + + if (GET_ATTRIB(opcode, A_ACQUIRE)) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + if (opcode =3D=3D Y2_barrier || opcode =3D=3D Y2_syncht || + opcode =3D=3D Y2_isync || opcode =3D=3D Y6_dmsyncht) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + } } =20 /* --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778795; cv=none; d=zohomail.com; s=zohoarc; b=Glg579fg6X2SetnEVI3R5/cFHECH5pvMdrZCmvI36gz1ihnEZGs/Fw6RtcxuNvjFsIiY4VJ59dJGwQlB3UH1HUyMgsjNlIu588ALjk0KwismNarVwNk7mSonG0nibWRJJjjRQvQIaTvSF64U/axQSkWz4hKPyrAnjf8zkne1Z3A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778795; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sxkjJNWHfWDZivxg4pBBOVMEi4v3UGqOMhrcFRnkXJs=; b=legvCs+Rw+y8EWXBhSW/oVFG68RkNIcj5EtpdanBpRehbD/AzOy1iFvfdsEvMdRdgTC1DazjfEMmnMh4ixvQbCrG1BoyblSp8DeHUZNSLcKXgklk/omv55TkhNxXG1ofXExqxeRB1DFgwefLjBteErzV0IejiuDcB63jHZSL7QI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778795690543.272787610382; Sun, 11 Oct 2026 21:19:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7V8-0003BC-Nt; Mon, 12 Oct 2026 00:19:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UM-0001yy-9B for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:15 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UK-0001BX-P8 for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:14 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lIrq915984 for ; Mon, 12 Oct 2026 04:18:01 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7dk24nda-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:18:01 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-3592749a017so1145327eec.1 for ; Sun, 11 Oct 2026 21:18:01 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778796952158500 Set llsc_addr to ~0 during reset and soft reset, and whenever linux-user returns to guest code for a trap or a signal. Reset previously left llsc_addr zero-initialized, so a store-conditional issued without a matching load-locked could match a guest address of zero. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- linux-user/hexagon/cpu_loop.c | 4 ++++ target/hexagon/cpu.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index e4ef97a1184..e6bb3b62a9f 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -39,6 +39,10 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); qemu_process_cpu_events(cs); =20 + if (trapnr !=3D EXCP_ATOMIC && trapnr !=3D EXCP_YIELD) { + env->llsc_addr =3D ~0; + } + switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a74eaa45fc2..5ae2026eb2d 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -411,6 +411,7 @@ void hexagon_cpu_soft_reset(CPUHexagonState *env) HexagonCPU *cpu; =20 BQL_LOCK_GUARD(); + env->llsc_addr =3D ~0; env->t_sreg[HEX_SREG_SSR] =3D 0; hexagon_ssr_set_cause(env, HEX_CAUSE_RESET); =20 @@ -446,6 +447,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) =20 set_default_nan_mode(1, &env->hvx_fp_status); set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status); + + env->llsc_addr =3D ~0; #ifndef CONFIG_USER_ONLY memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS); memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS); --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778763; cv=none; d=zohomail.com; s=zohoarc; b=AcKe0ZtQBs5qT+OqTimG08PLkslhWqz5d4PbDuI1ytLJO8QaJTaCdQl7yvKi1rwh+lwNC80JZlNwUUML3llDOwcidbRlbShhULsP2J7kzejm3dHDx/IP1YWet+GNijOrFGmiIo8nk+aiV/eT0ytULHH71S2aSzSkqEeIQr5shmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778763; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=p1eQG8R1UQN6KmziUofsbekOHHCaeRUx2pGGaioH9dQ=; b=VHV2Eagb3iTxtgqRjpzC5nHWXQq1gCvRhDWlz8Ea42aZHj2s7rQ57r4C1AsoQVPtC+qQkehSIpVmySkUNPB1qYfLAjLi3mC6iNRyP9OxtPBJEsIWyAi3EVCTjpjcpKWLvRlVGXEOtMwurXrhTTV+Ap2dMOb/Spw08+15sGMZqSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778763583666.5590684989317; Sun, 11 Oct 2026 21:19:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7V9-0003L4-UF; Mon, 12 Oct 2026 00:19:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UR-0001zX-Ek for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:25 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UM-0001Bl-Km for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:16 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lDUd052418 for ; Mon, 12 Oct 2026 04:18:03 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7en9vg3q-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:18:03 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-341eff9e381so4701059eec.1 for ; Sun, 11 Oct 2026 21:18:03 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon_tlb.h | 5 ++++- hw/hexagon/hexagon_tlb.c | 27 ++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/include/hw/hexagon/hexagon_tlb.h b/include/hw/hexagon/hexagon_= tlb.h index 6bc33c05452..56aa0b2beed 100644 --- a/include/hw/hexagon/hexagon_tlb.h +++ b/include/hw/hexagon/hexagon_tlb.h @@ -13,6 +13,7 @@ #include "exec/hwaddr.h" #include "exec/mmu-access-type.h" #include "monitor/hmp.h" +#include "qemu/thread.h" =20 #define TYPE_HEXAGON_TLB "hexagon-tlb" OBJECT_DECLARE_SIMPLE_TYPE(HexagonTLBState, HEXAGON_TLB) @@ -22,10 +23,12 @@ struct HexagonTLBState { =20 uint32_t num_entries; uint64_t *entries; + QemuMutex lock; }; =20 uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index); -void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e); +uint64_t hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, + uint64_t value); =20 bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, uint32_t VA, MMUAccessType access_type, diff --git a/hw/hexagon/hexagon_tlb.c b/hw/hexagon/hexagon_tlb.c index 157d03e51bf..28601b78a6f 100644 --- a/hw/hexagon/hexagon_tlb.c +++ b/hw/hexagon/hexagon_tlb.c @@ -7,6 +7,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/lockable.h" #include "hw/hexagon/hexagon_tlb.h" #include "hw/core/qdev-properties.h" #include "hw/core/resettable.h" @@ -162,6 +163,7 @@ bool hexagon_tlb_dump_entry(MonitorHMP *hmp, uint64_t e= ntry) =20 void hexagon_tlb_dump(MonitorHMP *hmp, HexagonTLBState *tlb) { + QEMU_LOCK_GUARD(&tlb->lock); for (uint32_t i =3D 0; i < tlb->num_entries; i++) { hexagon_tlb_dump_entry(hmp, tlb->entries[i]); } @@ -303,13 +305,20 @@ static bool hex_tlb_is_match(uint64_t entry1, uint64_= t entry2, uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index) { g_assert(index < tlb->num_entries); + QEMU_LOCK_GUARD(&tlb->lock); return tlb->entries[index]; } =20 -void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e) +uint64_t hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, + uint64_t value) { + uint64_t old; + g_assert(index < tlb->num_entries); + QEMU_LOCK_GUARD(&tlb->lock); + old =3D tlb->entries[index]; tlb->entries[index] =3D value; + return old; } =20 bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, @@ -323,6 +332,7 @@ bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint3= 2_t asid, *excp =3D 0; *cause_code =3D 0; =20 + QEMU_LOCK_GUARD(&tlb->lock); for (uint32_t i =3D 0; i < tlb->num_entries; i++) { if (hex_tlb_entry_match(tlb->entries[i], asid, VA, access_type, PA, prot, size, excp, cause_code, mmu_idx)= ) { @@ -349,6 +359,7 @@ uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint3= 2_t asid, uint32_t not_found =3D 0x80000000; uint32_t idx =3D not_found; =20 + QEMU_LOCK_GUARD(&tlb->lock); *imprecise_exception =3D 0; for (uint32_t i =3D 0; i < tlb->num_entries; i++) { uint64_t entry =3D tlb->entries[i]; @@ -387,6 +398,7 @@ int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uin= t64_t entry, int matches =3D 0; int last_match =3D 0; =20 + QEMU_LOCK_GUARD(&tlb->lock); for (uint32_t i =3D 0; i < tlb->num_entries; i++) { if (hex_tlb_is_match(entry, tlb->entries[i], false)) { matches++; @@ -412,6 +424,16 @@ uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *= tlb) =20 static void hexagon_tlb_init(Object *obj) { + HexagonTLBState *s =3D HEXAGON_TLB(obj); + + qemu_mutex_init(&s->lock); +} + +static void hexagon_tlb_finalize(Object *obj) +{ + HexagonTLBState *s =3D HEXAGON_TLB(obj); + + qemu_mutex_destroy(&s->lock); } =20 static void hexagon_tlb_realize(DeviceState *dev, Error **errp) @@ -436,6 +458,8 @@ static void hexagon_tlb_unrealize(DeviceState *dev) static void hexagon_tlb_reset_hold(Object *obj, ResetType type) { HexagonTLBState *s =3D HEXAGON_TLB(obj); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778823494158500 Replace the shared architectural entry first, release its lock, and only then call tlb_flush_all_cpus_synced() when a valid mapping was replaced. The old ordering flushed remote soft TLBs before publishing the replacement, allowing a resumed vCPU to refill the stale mapping. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index 7d5fb987e18..0ca52ed666d 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -31,14 +31,12 @@ void hex_tlbw(CPUHexagonState *env, uint32_t index, uin= t64_t value) { uint32_t myidx =3D fTLB_NONPOW2WRAP(fTLB_IDXMASK(index)); HexagonTLBState *tlb =3D env_archcpu(env)->tlb; - uint64_t old_entry =3D hexagon_tlb_read(tlb, myidx); - + uint64_t old_entry =3D hexagon_tlb_write(tlb, myidx, value); bool old_entry_valid =3D extract64(old_entry, 63, 1); if (old_entry_valid && hexagon_cpu_mmu_enabled(env)) { CPUState *cs =3D env_cpu(env); - tlb_flush(cs); + tlb_flush_all_cpus_synced(cs); } - hexagon_tlb_write(tlb, myidx, value); hex_log_tlbw(myidx, value); } =20 --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778791; cv=none; d=zohomail.com; s=zohoarc; b=U8pY4khpfhiepOwr9oQtpwJPUt9H2cIqXvGVc4ZpJRJlXF2CvolaSeJlMAH5KVe8DlG04IGhQ1tpQCxS2a+d2yTorsw7sLMgsHXuEaowJ27d2n82JZ3beVh1Enqck7WTqxk8CwmfjRUQjih7Jkq3TrBnlph5zszXQMtovzahyvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778791; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TqYUKRSkqLmpwx6LXHLt9nFuLWDlH8GbmkD5TRt6itg=; b=iinc8Jd8GEu4lFSrhzsjQJul4tXsOIuai9Zn6eFOkALoOTFSAmY+4LQG826NwOYcOlCKUfYj+XDfHeZkeiOmSayu1i9JsoO0AXAzHtiogaWG0pQb9w8CTDMVD6dyOFo4QYIPpS4spKUPoLKfU6XeOiTn+LPWFTmm0JUo2/U+qSA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778790853234.58436767266733; Sun, 11 Oct 2026 21:19:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7VB-0003VZ-Oj; Mon, 12 Oct 2026 00:19:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UW-0001zv-LY for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:28 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UR-0001C7-6W for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:21 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1lQl8328455 for ; Mon, 12 Oct 2026 04:18:06 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7e4echaq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:18:06 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-341eff9e381so4701103eec.1 for ; Sun, 11 Oct 2026 21:18:06 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- tests/tcg/hexagon/atomics.c | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tests/tcg/hexagon/atomics.c b/tests/tcg/hexagon/atomics.c index 1c2169b28bd..5017ca003f1 100644 --- a/tests/tcg/hexagon/atomics.c +++ b/tests/tcg/hexagon/atomics.c @@ -27,6 +27,30 @@ int err; =20 #include "hex_test.h" =20 +static inline int32_t load_locked32(int32_t *x) +{ + int32_t value; + + __asm__ __volatile__("%[value] =3D memw_locked(%[addr])" + : [value] "=3Dr"(value) + : [addr] "r"(x) + : "memory"); + return value; +} + +static inline int store_conditional32(int32_t *x, int32_t value) +{ + int result; + + __asm__ __volatile__( + "memw_locked(%[addr], p0) =3D %[value]\n\t" + "%[result] =3D p0" + : [result] "=3Dr"(result) + : [addr] "r"(x), [value] "r"(value) + : "p0", "memory"); + return result !=3D 0; +} + static inline int32_t atomic_inc32(int32_t *x) { int32_t old, dummy; @@ -89,6 +113,21 @@ static inline int64_t atomic_dec64(int64_t *x) volatile int32_t tick32 =3D 1; /* Using volatile because we are testing at= omics */ volatile int64_t tick64 =3D 1; /* Using volatile because we are testing at= omics */ =20 +static void test_reservations(void) +{ + int32_t value =3D 1; + + /* A store-conditional with no preceding load-locked must fail. */ + check32(store_conditional32(&value, 2), 0); + check32(value, 1); + + /* Returning from a syscall drops the reservation. */ + check32(load_locked32(&value), 1); + getpid(); + check32(store_conditional32(&value, 3), 0); + check32(value, 1); +} + void *thread1_func(void *arg) { for (int i =3D 0; i < LOOP_CNT; i++) { @@ -122,6 +161,7 @@ void test_pthread(void) =20 int main(int argc, char **argv) { + test_reservations(); test_pthread(); puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778790801158500 System-mode pause currently advances the PC and continues execution instead of yielding the vCPU. Raise EXCP_YIELD with the next packet PC so execution returns to the CPU loop and another hardware thread can run. Keep the linux-user behavior unchanged. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 5f7df66ae67..80d8a7b6bac 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1125,11 +1125,21 @@ #define fGEN_TCG_Y2_break(SHORTCODE) #define fGEN_TCG_J2_unpause(SHORTCODE) =20 +#ifdef CONFIG_USER_ONLY #define fGEN_TCG_J2_pause(SHORTCODE) \ do { \ uiV =3D uiV; \ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \ } while (0) +#else +#define fGEN_TCG_J2_pause(SHORTCODE) \ + do { \ + uiV =3D uiV; \ + gen_helper_raise_exception(tcg_env, \ + tcg_constant_i32(EXCP_YIELD), \ + tcg_constant_i32(ctx->next_PC)); \ + } while (0) +#endif =20 /* r0 =3D asr(r1, r2):sat */ #define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \ --=20 2.34.1 From nobody Thu Oct 22 19:25:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791778768; cv=none; d=zohomail.com; s=zohoarc; b=cnuzo6+vjthxgcCtd8mIvBZU7UaCqDvmxY+V1XXs8NffVAAyPlVd069denMOw2bmjEaWGdGLvdevWOMUsECwcTCxL7+RDBABE/3fE7zEXoe918ucwATShYC1muvrwgnh3BxpB3HMdDNz724W2NGZhj1vpiQgAoYh7dqxIw5ok7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791778768; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dEhhuxt4NM4PmwW0OOrSxZGKArlpV7cIeI0IvZpRyCc=; b=XpLh/IEksZQX376Kbddz19j2N7OQhidxnzNaQt6AQWcK2XI9//lyAfhLDBHiyk5Ni/DdFE0/gxJxfXqQxekWKWukWa+JgQMw2HLjWNuwOMWdeGDSAgdd+c14MtSxD+z643WlygAMyMev8INd/OvJBuh6swIKWP5mQvbiRIAkpDA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791778768737357.52608534477054; Sun, 11 Oct 2026 21:19:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xG7V9-0003Ek-40; Mon, 12 Oct 2026 00:19:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UY-0001zy-0T for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:31 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xG7UU-0001D3-1w for qemu-devel@nongnu.org; Mon, 12 Oct 2026 00:18:25 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69C1leUW3646992 for ; Mon, 12 Oct 2026 04:18:09 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h7ehjmhuj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Oct 2026 04:18:09 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-341eff9e381so4701209eec.1 for ; Sun, 11 Oct 2026 21:18:09 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791778770471158500 Y4_nmi was a no-op, let's fill in the missing implementation. We'll raise CPU_INTERRUPT_NMI on each running thread in the mask. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/cpu_helper.h | 1 + target/hexagon/sys_macros.h | 3 +-- target/hexagon/cpu.c | 11 ++++++++++- target/hexagon/cpu_helper.c | 17 +++++++++++++++++ 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 188a91e8823..65fd2b29830 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -59,6 +59,7 @@ typedef struct HexagonHVXContextState HexagonHVXContextSt= ate; #define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0 #define CPU_INTERRUPT_K0_UNLOCK CPU_INTERRUPT_TGT_INT_1 #define CPU_INTERRUPT_TLB_UNLOCK CPU_INTERRUPT_TGT_INT_2 +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_0 =20 #define HEX_CPU_MODE_USER 1 #define HEX_CPU_MODE_GUEST 2 diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index afb4df59f80..95a8f6587b6 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -22,6 +22,7 @@ void clear_wait_mode(CPUHexagonState *env); void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause); void hexagon_start_threads(CPUHexagonState *env, uint32_t mask); void hexagon_stop_thread(CPUHexagonState *env); +void hexagon_nmi(CPUHexagonState *env, uint32_t thread_mask); void hexagon_resume_threads(CPUHexagonState *env, uint32_t mask); uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env); uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env); diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index 72179d49ab3..2e4cda29e61 100644 --- a/target/hexagon/sys_macros.h +++ b/target/hexagon/sys_macros.h @@ -253,7 +253,6 @@ =20 #define NUM_TLB_REGS(x) (hexagon_tlb_get_num_entries(env_archcpu(env)->tlb= )) =20 -/* NMI routing not yet implemented; Y4_nmi is a no-op for now */ -#define fDO_NMI(THREAD_MASK) do { } while (0) +#define fDO_NMI(THREAD_MASK) hexagon_nmi(env, THREAD_MASK) =20 #endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 5ae2026eb2d..6550e7fa800 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -393,7 +393,8 @@ static bool hexagon_cpu_has_work(CPUState *cs) =20 return hexagon_thread_is_enabled(env) && (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI - | CPU_INTERRUPT_K0_UNLOCK | CPU_INTERRUPT_TLB_UNLOCK)); + | CPU_INTERRUPT_K0_UNLOCK | CPU_INTERRUPT_TLB_UNLOCK + | CPU_INTERRUPT_NMI)); } #endif =20 @@ -759,6 +760,14 @@ static const struct SysemuCPUOps hexagon_sysemu_ops = =3D { static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUHexagonState *env =3D cpu_env(cs); + if (interrupt_request & CPU_INTERRUPT_NMI) { + cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); + cs->halted =3D false; + cs->exception_index =3D HEX_EVENT_IMPRECISE; + env->cause_code =3D HEX_CAUSE_IMPRECISE_NMI; + hexagon_cpu_do_interrupt(cs); + return true; + } if (interrupt_request & CPU_INTERRUPT_TLB_UNLOCK) { cs->halted =3D false; cpu_reset_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK); diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 0f999a48ac7..c2fc27f1c02 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -539,6 +539,23 @@ void hexagon_stop_thread(CPUHexagonState *env) } } =20 +void hexagon_nmi(CPUHexagonState *env, uint32_t thread_mask) +{ + CPUState *cs; + + BQL_LOCK_GUARD(); + + CPU_FOREACH(cs) { + CPUHexagonState *thread =3D cpu_env(cs); + + if (!(thread_mask & (1u << thread->threadId)) || + get_exe_mode(thread) =3D=3D HEX_EXE_MODE_OFF) { + continue; + } + cpu_interrupt(cs, CPU_INTERRUPT_NMI); + } +} + static int sys_in_monitor_mode_ssr(uint32_t ssr) { if ((GET_SSR_FIELD(SSR_EX, ssr) !=3D 0) || --=20 2.34.1