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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639465; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cv1mnVaaa2py2bLoOqax63rfmn2rgM5Tmv6Vdfg/Z40=; b=Iw4jGazI/52HM67xrYhRusZvqNIbg/TIqIIh4idlfvESLJ79rviGq/pgwYr/kCV96b0ZKX Q2oA0+8QvZbZdOGKfrNdHsAkJdeG48PM13tgdIG1x+Uv/PTRtVBWQYiyYjlF9W7+enqpDI KP0o6sXmjy9Ocj69UOE9eVDsFz2EjXc= X-MC-Unique: AyibHwLoMQ63QlWei9-4Tw-1 X-Mimecast-MFC-AGG-ID: AyibHwLoMQ63QlWei9-4Tw_1791639460 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 01/26] target/arm: Move REVIDR into isar.idregs[] storage Date: Sat, 10 Oct 2026 15:36:05 +0200 Message-ID: <20261010133725.642498-2-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Move REVIDR into the isar.idregs[] array as other ID registers. This will allow to overwrite it as others. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 - target/arm/cpu-sysregs.h.inc | 1 + hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu-max.c | 2 +- target/arm/cpu64.c | 2 +- target/arm/helper.c | 2 +- target/arm/tcg/cpu-v7m.c | 4 ++-- target/arm/tcg/cpu32.c | 4 ++-- target/arm/tcg/cpu64.c | 20 ++++++++++---------- 9 files changed, 19 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 06ebed4a8f..b2af36a8c3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1124,7 +1124,6 @@ struct ArchCPU { uint64_t idregs[NUM_ID_IDX]; } isar; uint64_t midr; - uint32_t revidr; uint32_t reset_fpsid; uint64_t ctr; uint32_t reset_sctlr; diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index b5c7970971..580d88d1f4 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -44,3 +44,4 @@ DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 6bc392b0e3..1f56fff046 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1051,7 +1051,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { goto bad_offset; } - return cpu->revidr; + return GET_IDREG(isar, REVIDR); case 0xd00: /* CPUID Base. */ return cpu->midr; case 0xd04: /* Interrupt Control State (ICSR) */ diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 2ed1cfef9b..b4e57a167d 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -37,7 +37,7 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enab= led) cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; } cpu->midr =3D 0x411fd070; - cpu->revidr =3D 0x00000000; + SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x41034070; cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x12111111; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dcd0d698b3..80c9c9e5b3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -717,7 +717,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->midr =3D 0x410fd034; - cpu->revidr =3D 0x00000100; + SET_IDREG(isar, REVIDR, 0x00000100); cpu->reset_fpsid =3D 0x41034070; cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x12111111; diff --git a/target/arm/helper.c b/target/arm/helper.c index ff0b766b73..41c0d0df12 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7415,7 +7415,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_tid1, .fgt =3D FGT_REVIDR_EL1, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, + .type =3D ARM_CP_CONST, .resetvalue =3D GET_IDREG(&cpu->isar= , REVIDR) }, }; ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST | ARM_= CP_NO_GDB, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 48b31d5eac..e7c61d3c31 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -211,7 +211,7 @@ static void cortex_m55_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x410fd221; /* r0p1 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; /* These are the MVFR* values for the FPU + full MVE configuration */ @@ -249,7 +249,7 @@ static void cortex_m85_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x411fd231; /* r1p1 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; /* These are the MVFR* values for the FPU + full MVE configuration */ diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index f95051458d..c02b737fc0 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -456,7 +456,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); /* r4p0 cpu, not requiring expensive tlb flush errata */ cpu->midr =3D 0x414fc0f0; - cpu->revidr =3D 0x0; + SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x410430f0; cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x11111111; @@ -647,7 +647,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr =3D 0x411fd133; /* r1p3 */ - cpu->revidr =3D 0x00000000; + SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x41034023; cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x12111111; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 59692dddcf..ac1dace1e4 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -48,7 +48,7 @@ static void aarch64_a35_initfn(Object *obj) =20 /* From B2.2 AArch64 identification registers. */ cpu->midr =3D 0x411fd040; - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); cpu->ctr =3D 0x84448004; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); @@ -248,7 +248,7 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x412FD050; /* r2p0 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); =20 /* From B2.23 CCSIDR_EL1 */ /* 32KB L1 dcache */ @@ -292,7 +292,7 @@ static void aarch64_a72_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x410fd083; - cpu->revidr =3D 0x00000000; + SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x41034080; cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x12111111; @@ -383,7 +383,7 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0b1; /* r4p1 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); =20 /* From B2.18 CCSIDR_EL1 */ /* 64KB L1 dcache */ @@ -456,7 +456,7 @@ static void aarch64_a78ae_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x410fd423; /* r0p3 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); =20 /* From 3.2.33 CCSIDR_EL1 */ /* 64KB L1 dcache */ @@ -501,7 +501,7 @@ static void aarch64_a64fx_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x461f0010; - cpu->revidr =3D 0x00000000; + SET_IDREG(isar, REVIDR, 0); cpu->ctr =3D 0x86668006; cpu->reset_sctlr =3D 0x30000180; SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ @@ -707,7 +707,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0c1; /* r4p1 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); =20 /* From B2.23 CCSIDR_EL1 */ /* 64KB L1 dcache */ @@ -787,7 +787,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x411FD402; /* r1p2 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); =20 /* * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, @@ -984,7 +984,7 @@ static void aarch64_a710_initfn(Object *obj) =20 /* Ordered by Section B.4: AArch64 registers */ cpu->midr =3D 0x412FD471; /* r2p1 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); @@ -1087,7 +1087,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) =20 /* Ordered by Section B.5: AArch64 ID registers */ cpu->midr =3D 0x410FD493; /* r0p3 */ - cpu->revidr =3D 0; + SET_IDREG(isar, REVIDR, 0); SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639505; cv=none; d=zohomail.com; s=zohoarc; b=m8TIno82q5dptCal27ai9X92Lv0eso4I1ZcU1M3fwTNfkm8SEJ8Ko5uXbLEYXPPgOKIr4dLl5o7jlz11SYpMy4bF8HMYySbKnnwpgxiCt0bx9dgzlYuaiJOgzQ2WOkPPehRfyWRbAmweq8PkUQJGud00QJTYX0EAh7etX/OTJRs= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639508844158500 Content-Type: text/plain; charset="utf-8" Move MIDR into the isar.idregs[] array as other ID registers. This will allow to overwrite it as others. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 - target/arm/cpu-sysregs.h.inc | 1 + hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu-max.c | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 2 +- target/arm/helper.c | 13 +++++++------ target/arm/hvf/hvf.c | 4 ++-- target/arm/tcg/cpu-v7m.c | 14 +++++++------- target/arm/tcg/cpu32.c | 33 +++++++++++++++++---------------- target/arm/tcg/cpu64.c | 22 +++++++++++----------- target/arm/whpx/whpx-all.c | 4 ++-- 12 files changed, 51 insertions(+), 49 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b2af36a8c3..dcdd4eb18e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1123,7 +1123,6 @@ struct ArchCPU { uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; } isar; - uint64_t midr; uint32_t reset_fpsid; uint64_t ctr; uint32_t reset_sctlr; diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 580d88d1f4..709dc8fc97 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -41,6 +41,7 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) +DEF(MIDR_EL1, 3, 0, 0, 0, 0) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1f56fff046..1f7209f6b6 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1053,7 +1053,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return GET_IDREG(isar, REVIDR); case 0xd00: /* CPUID Base. */ - return cpu->midr; + return GET_IDREG(isar, MIDR); case 0xd04: /* Interrupt Control State (ICSR) */ /* VECTACTIVE */ val =3D cpu->env.v7m.exception; diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index b4e57a167d..c47db5251d 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -36,7 +36,7 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enab= led) if (kvm_enabled()) { cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A57; } - cpu->midr =3D 0x411fd070; + SET_IDREG(isar, MIDR, 0x411fd070); SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x41034070; cpu->isar.mvfr0 =3D 0x10110222; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10ac6c9831..2f545482bc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2501,7 +2501,7 @@ static ObjectClass *arm_cpu_class_by_name(const char = *cpu_model) } =20 static const Property arm_cpu_properties[] =3D { - DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), + DEFINE_PROP_UINT64("midr", ARMCPU, isar.idregs[MIDR_EL1_IDX], 0), DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 80c9c9e5b3..64103df0a7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -716,7 +716,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; - cpu->midr =3D 0x410fd034; + SET_IDREG(isar, MIDR, 0x410fd034); SET_IDREG(isar, REVIDR, 0x00000100); cpu->reset_fpsid =3D 0x41034070; cpu->isar.mvfr0 =3D 0x10110222; diff --git a/target/arm/helper.c b/target/arm/helper.c index 41c0d0df12..dfd71f1b51 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7153,12 +7153,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D cpu->midr, + .resetvalue =3D GET_IDREG(&cpu->isar, MIDR), .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL2_RW, .resetvalue =3D cpu->midr, + .access =3D PL2_RW, .resetvalue =3D GET_IDREG(&cpu->isar, MI= DR), .type =3D ARM_CP_EL3_NO_EL2_C_NZ, .nv2_redirect_offset =3D 0x88, .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, @@ -7377,7 +7377,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ { .name =3D "MIDR", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .resetvalue =3D cpu->midr, + .access =3D PL1_R, .resetvalue =3D GET_IDREG(&cpu->isar, MID= R), .writefn =3D arm_cp_write_ignore, .raw_writefn =3D raw_write, .readfn =3D midr_read, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), @@ -7402,14 +7402,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + .resetvalue =3D GET_IDREG(&cpu->isar, MIDR), .fgt =3D FGT_MIDR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o= f MIDR */ { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, + .access =3D PL1_R, .resetvalue =3D GET_IDREG(&cpu->isar, MID= R) }, { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, .access =3D PL1_R, @@ -7420,7 +7421,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST | ARM_= CP_NO_GDB, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr + .access =3D PL1_R, .resetvalue =3D GET_IDREG(&cpu->isar, MIDR) }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b00a7e1a84..f9f3d22014 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1295,7 +1295,7 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; cpu->isar =3D arm_host_cpu_features.isar; cpu->env.features =3D arm_host_cpu_features.features; - cpu->midr =3D arm_host_cpu_features.midr; + SET_IDREG(&cpu->isar, MIDR, arm_host_cpu_features.midr); cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; cpu->sme_vq.supported =3D arm_host_cpu_features.sme_vq_supported; } @@ -1472,7 +1472,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* Set CP_NO_RAW system registers on init */ ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, - arm_cpu->midr); + GET_IDREG(&arm_cpu->isar, MIDR)); assert_hvf_ok(ret); =20 ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index e7c61d3c31..20d40f176d 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -49,7 +49,7 @@ static void cortex_m0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_M); =20 - cpu->midr =3D 0x410cc200; + SET_IDREG(isar, MIDR, 0x410cc200); =20 /* * These ID register values are not guest visible, because @@ -83,7 +83,7 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; + SET_IDREG(isar, MIDR, 0x410fc231); cpu->pmsav7_dregion =3D 8; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); @@ -111,7 +111,7 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fc240; /* r0p0 */ + SET_IDREG(isar, MIDR, 0x410fc240); /* r0p0 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; @@ -142,7 +142,7 @@ static void cortex_m7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x411fc272; /* r1p2 */ + SET_IDREG(isar, MIDR, 0x411fc272); /* r1p2 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; @@ -174,7 +174,7 @@ static void cortex_m33_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fd213; /* r0p3 */ + SET_IDREG(isar, MIDR, 0x410fd213); /* r0p3 */ cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; cpu->isar.mvfr0 =3D 0x10110021; @@ -210,7 +210,7 @@ static void cortex_m55_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fd221; /* r0p1 */ + SET_IDREG(isar, MIDR, 0x410fd221); /* r0p1 */ SET_IDREG(isar, REVIDR, 0); cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; @@ -248,7 +248,7 @@ static void cortex_m85_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x411fd231; /* r1p1 */ + SET_IDREG(isar, MIDR, 0x411fd231); /* r1p1 */ SET_IDREG(isar, REVIDR, 0); cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index c02b737fc0..faeeeff4ea 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -27,7 +27,8 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr =3D 0x41069265; + SET_IDREG(&cpu->isar, MIDR, 0x41069265); + cpu->reset_fpsid =3D 0x41011090; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; @@ -54,7 +55,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x41059461; + SET_IDREG(&cpu->isar, MIDR, 0x41059461); cpu->ctr =3D 0x0f004006; cpu->reset_sctlr =3D 0x00000078; } @@ -68,7 +69,7 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr =3D 0x4106a262; + SET_IDREG(&cpu->isar, MIDR, 0x4106a262); cpu->reset_fpsid =3D 0x410110a0; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; @@ -117,7 +118,7 @@ static void arm1136_r2_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr =3D 0x4107b362; + SET_IDREG(isar, MIDR, 0x4107b362); cpu->reset_fpsid =3D 0x410120b4; cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; @@ -149,7 +150,7 @@ static void arm1136_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr =3D 0x4117b363; + SET_IDREG(isar, MIDR, 0x4117b363); cpu->reset_fpsid =3D 0x410120b4; cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; @@ -182,7 +183,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr =3D 0x410fb767; + SET_IDREG(isar, MIDR, 0x410fb767); cpu->reset_fpsid =3D 0x410120b5; cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; @@ -213,7 +214,7 @@ static void arm11mpcore_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_MPIDR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x410fb022; + SET_IDREG(isar, MIDR, 0x410fb022); cpu->reset_fpsid =3D 0x410120b4; cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; @@ -257,7 +258,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x410fc080; + SET_IDREG(isar, MIDR, 0x410fc080); cpu->reset_fpsid =3D 0x410330c0; cpu->isar.mvfr0 =3D 0x11110222; cpu->isar.mvfr1 =3D 0x00011111; @@ -335,7 +336,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_CBAR); set_feature(&cpu->env, ARM_FEATURE_D32DIS); - cpu->midr =3D 0x410fc090; + SET_IDREG(isar, MIDR, 0x410fc090); cpu->reset_fpsid =3D 0x41033090; cpu->isar.mvfr0 =3D 0x11110222; cpu->isar.mvfr1 =3D 0x01111111; @@ -403,7 +404,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); set_feature(&cpu->env, ARM_FEATURE_D32DIS); - cpu->midr =3D 0x410fc075; + SET_IDREG(isar, MIDR, 0x410fc075); cpu->reset_fpsid =3D 0x41023075; cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x11111111; @@ -455,7 +456,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); /* r4p0 cpu, not requiring expensive tlb flush errata */ - cpu->midr =3D 0x414fc0f0; + SET_IDREG(isar, MIDR, 0x414fc0f0); SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x410430f0; cpu->isar.mvfr0 =3D 0x10110222; @@ -505,7 +506,7 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x411fc153; /* r1p3 */ + SET_IDREG(isar, MIDR, 0x411fc153); /* r1p3 */ SET_IDREG(isar, ID_PFR0, 0x0131); SET_IDREG(isar, ID_PFR1, 0x001); SET_IDREG(isar, ID_DFR0, 0x010400); @@ -646,7 +647,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_AUXCR); - cpu->midr =3D 0x411fd133; /* r1p3 */ + SET_IDREG(isar, MIDR, 0x411fd133); /* r1p3 */ SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x41034023; cpu->isar.mvfr0 =3D 0x10110222; @@ -694,7 +695,7 @@ static void ti925t_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_V4T); set_feature(&cpu->env, ARM_FEATURE_OMAPCP); - cpu->midr =3D ARM_CPUID_TI925T; + SET_IDREG(&cpu->isar, MIDR, ARM_CPUID_TI925T); cpu->ctr =3D 0x5109149; cpu->reset_sctlr =3D 0x00000070; } @@ -706,7 +707,7 @@ static void sa1100_initfn(Object *obj) cpu->dtb_compatible =3D "intel,sa1100"; set_feature(&cpu->env, ARM_FEATURE_STRONGARM); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x4401A11B; + SET_IDREG(&cpu->isar, MIDR, 0x4401A11B); cpu->reset_sctlr =3D 0x00000070; } =20 @@ -715,7 +716,7 @@ static void sa1110_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_STRONGARM); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x6901B119; + SET_IDREG(&cpu->isar, MIDR, 0x6901B119); cpu->reset_sctlr =3D 0x00000070; } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ac1dace1e4..d73d792ad9 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -47,7 +47,7 @@ static void aarch64_a35_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* From B2.2 AArch64 identification registers. */ - cpu->midr =3D 0x411fd040; + SET_IDREG(isar, MIDR, 0x411fd040); SET_IDREG(isar, REVIDR, 0); cpu->ctr =3D 0x84448004; SET_IDREG(isar, ID_PFR0, 0x00000131); @@ -247,7 +247,7 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_PFR2, 0x00000011); - cpu->midr =3D 0x412FD050; /* r2p0 */ + SET_IDREG(isar, MIDR, 0x412FD050); /* r2p0 */ SET_IDREG(isar, REVIDR, 0); =20 /* From B2.23 CCSIDR_EL1 */ @@ -291,7 +291,7 @@ static void aarch64_a72_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x410fd083; + SET_IDREG(isar, MIDR, 0x410fd083); SET_IDREG(isar, REVIDR, 0); cpu->reset_fpsid =3D 0x41034080; cpu->isar.mvfr0 =3D 0x10110222; @@ -382,7 +382,7 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); - cpu->midr =3D 0x414fd0b1; /* r4p1 */ + SET_IDREG(isar, MIDR, 0x414fd0b1); /* r4p1 */ SET_IDREG(isar, REVIDR, 0); =20 /* From B2.18 CCSIDR_EL1 */ @@ -455,7 +455,7 @@ static void aarch64_a78ae_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); - cpu->midr =3D 0x410fd423; /* r0p3 */ + SET_IDREG(isar, MIDR, 0x410fd423); /* r0p3 */ SET_IDREG(isar, REVIDR, 0); =20 /* From 3.2.33 CCSIDR_EL1 */ @@ -500,7 +500,7 @@ static void aarch64_a64fx_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x461f0010; + SET_IDREG(isar, MIDR, 0x461f0010); SET_IDREG(isar, REVIDR, 0); cpu->ctr =3D 0x86668006; cpu->reset_sctlr =3D 0x30000180; @@ -706,7 +706,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); - cpu->midr =3D 0x414fd0c1; /* r4p1 */ + SET_IDREG(isar, MIDR, 0x414fd0c1); /* r4p1 */ SET_IDREG(isar, REVIDR, 0); =20 /* From B2.23 CCSIDR_EL1 */ @@ -786,7 +786,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); - cpu->midr =3D 0x411FD402; /* r1p2 */ + SET_IDREG(isar, MIDR, 0x411FD402); /* r1p2 */ SET_IDREG(isar, REVIDR, 0); =20 /* @@ -983,7 +983,7 @@ static void aarch64_a710_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* Ordered by Section B.4: AArch64 registers */ - cpu->midr =3D 0x412FD471; /* r2p1 */ + SET_IDREG(isar, MIDR, 0x412FD471); /* r2p1 */ SET_IDREG(isar, REVIDR, 0); SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ @@ -1086,7 +1086,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* Ordered by Section B.5: AArch64 ID registers */ - cpu->midr =3D 0x410FD493; /* r0p3 */ + SET_IDREG(isar, MIDR, 0x410FD493); /* r0p3 */ SET_IDREG(isar, REVIDR, 0); SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ @@ -1214,7 +1214,7 @@ void aarch64_max_v8_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr =3D t; + SET_IDREG(isar, MIDR, t); =20 /* * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,= LoUIS} diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 46f0b9524e..18009d6c8d 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -775,7 +775,7 @@ void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; cpu->isar =3D arm_host_cpu_features.isar; cpu->env.features =3D arm_host_cpu_features.features; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639712711158500 Content-Type: text/plain; charset="utf-8" At the moment MPIDR_EL1 has no real storage. Instead cpu mp_affinity field stores the Aff0-Aff2 bits only and the ID register is reconstructed when needed. There is also an mp-affinity property used for TCG only. Keep the mp-affinity property and its associated storage while making sure the MPIDR_EL1 full register is stored in cpu->isar.idregs[] as other ID registers. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 +++++++- target/arm/cpu-sysregs.h.inc | 1 + target/arm/cpu.c | 17 +++++++++++++++++ target/arm/helper.c | 14 +------------- target/arm/hvf/hvf.c | 2 +- target/arm/kvm.c | 1 + target/arm/whpx/whpx-all.c | 2 +- 7 files changed, 29 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dcdd4eb18e..639be0713e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1128,7 +1128,13 @@ struct ArchCPU { uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; - uint64_t mp_affinity; /* MP ID without feature bits */ + /* + * MP ID without feature bits, ie. Aff0..Aff3 only + * used to store the corresponding property value for TCG vcpus. + * The MPIDR_EL1 value (affinity + feature bits) is stored in a + * consistent manner in isar.idregs[MPIDR_EL1_IDX]. + */ + uint64_t mp_affinity; uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 709dc8fc97..f148f6f565 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -42,6 +42,7 @@ DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(MIDR_EL1, 3, 0, 0, 0, 0) +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2f545482bc..bee74c0f94 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2174,6 +2174,23 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) ARM_DEFAULT_CPUS_PER_CLUS= TER); } =20 + /* Consistently update MPIDR_EL1 in isar.idregs[] by adding feature bi= ts */ + { + uint64_t mpidr =3D cpu->mp_affinity; + + if (arm_feature(env, ARM_FEATURE_V7MP)) { + mpidr |=3D (1U << 31); + /* + * Uniprocessor (non-coherent) cores that still implement the = MP + * extensions set U (bit 30), e.g. Cortex-R5. + */ + if (cpu->mp_is_up) { + mpidr |=3D (1u << 30); + } + } + SET_IDREG(&cpu->isar, MPIDR, mpidr); + } + if (cpu->reset_hivecs) { cpu->reset_sctlr |=3D (1 << 13); } diff --git a/target/arm/helper.c b/target/arm/helper.c index dfd71f1b51..36e8119f79 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3176,20 +3176,8 @@ static uint64_t midr_read(CPUARMState *env, const AR= MCPRegInfo *ri) static uint64_t mpidr_read_val(CPUARMState *env) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t mpidr =3D cpu->mp_affinity; =20 - if (arm_feature(env, ARM_FEATURE_V7MP)) { - mpidr |=3D (1U << 31); - /* - * Cores which are uniprocessor (non-coherent) - * but still implement the MP extensions set - * bit 30. (For instance, Cortex-R5). - */ - if (cpu->mp_is_up) { - mpidr |=3D (1u << 30); - } - } - return mpidr; + return GET_IDREG(&cpu->isar, MPIDR); } =20 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f9f3d22014..4b947e9ba5 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1476,7 +1476,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) assert_hvf_ok(ret); =20 ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, - arm_cpu->mp_affinity); + GET_IDREG(&arm_cpu->isar, MPIDR)); assert_hvf_ok(ret); =20 pfr =3D GET_IDREG(&arm_cpu->isar, ID_AA64PFR0); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 3d905f8565..9d68801c26 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2096,6 +2096,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (ret) { return ret; } + SET_IDREG(&cpu->isar, MPIDR, mpidr); cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 return kvm_arm_init_cpreg_list(cpu); diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 18009d6c8d..024d18df04 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -842,7 +842,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 clean_whv_register_value(&val); =20 - val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); + val.Reg64 =3D GET_IDREG(&arm_cpu->isar, MPIDR); whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639546; cv=none; d=zohomail.com; s=zohoarc; b=ca2y4zK35tQK1+V+XXUz9h428lScOlt5Ljr9wevj1Sgj0KJQrDFzF3TEzZfd2DnIUyAjzfX3TZ0dQwzg1zTWaQnkISDl5A2FohdMBG8wDvBGxj9po7bpWG8UIYuSkr1wi3m40iQ2CbCBYUZbqYYFshsSpl9I4XPwydK78gvycyM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639546; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sat, 10 Oct 2026 13:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8zMymiCc6qFGUfLZrmpJjxZKSMoCg+G0Tr++d0qjFL0=; b=HQYq4i+UEefc1hKIH/d6yN8K/8mfwVCtQfcre+G6uAgc++RKhwGcfTrSzDiiXC2HjC1Lxr 0e/bRSYup+MMstzXazsPD+2Vl/4bRUQUPPgdltGCLXP+ckOZlgfyYLJmq1mTPe7abK4Hwc qWtRzTyai012zM2muvLwhOA1Y+7LpWc= X-MC-Unique: Z4dtRfjRNQq8KefrgrrSvQ-1 X-Mimecast-MFC-AGG-ID: Z4dtRfjRNQq8KefrgrrSvQ_1791639475 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 04/26] target/arm/cpu-sysregs.h.inc: Update with automatic generation Date: Sat, 10 Oct 2026 15:36:08 +0200 Message-ID: <20261010133725.642498-5-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639547346158501 Content-Type: text/plain; charset="utf-8" Introduce scripts/update-aarch64-cpu-sysregs-header.py that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc under the form of DEF(, , , , , ) or DEF_MUX(, , , , , , ) We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] As we plan to reuse get_opcode() and extract_idregs_from_registers_json() functions in another script, put them in a separate module. Update target/arm/cpu-sysregs.h.inc with the script. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v9 -> v10: - squashed 3 patches: main script, module and generated file - improve the comment related to skipped registers. Move is_demux in the loop. Fix indent. - sort by reg name inside the helper - add support for DEMUX register --- target/arm/cpu-sysregs.h.inc | 10 ++ scripts/aarch64_sysreg_helpers.py | 118 +++++++++++++++++++ scripts/update-aarch64-cpu-sysregs-header.py | 59 ++++++++++ 3 files changed, 187 insertions(+) create mode 100644 scripts/aarch64_sysreg_helpers.py create mode 100755 scripts/update-aarch64-cpu-sysregs-header.py diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index f148f6f565..c15ce8fc7e 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,12 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file is autogenerated by scripts/update-aarch64-cpu-sysregs-header= .py */ +/* DEF(, , , , , ) */ +/* DEF_MUX(, , , , , , ) */ + +DEF(AIDR_EL1, 3, 1, 0, 0, 7) +DEF_MUX(CCSIDR2_EL1, 3, 1, 0, 0, 2, 16) DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(CTR_EL0, 3, 3, 0, 0, 1) DEF(DCZID_EL0, 3, 3, 0, 0, 7) +DEF(GMID_EL1, 3, 1, 0, 0, 4) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) @@ -47,3 +56,4 @@ DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) DEF(REVIDR_EL1, 3, 0, 0, 0, 6) +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) diff --git a/scripts/aarch64_sysreg_helpers.py b/scripts/aarch64_sysreg_hel= pers.py new file mode 100644 index 0000000000..53ca0eecbf --- /dev/null +++ b/scripts/aarch64_sysreg_helpers.py @@ -0,0 +1,118 @@ +#!/usr/bin/env python3 + +# Helpers used in aarch64 sysreg definition generation +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import json +import os + +# Some regs have op code values like 000x, 001x. skip them explicitly +# as they are not needed anyway. Also, although VMPIDR_EL2 and VPIDR_EL2 +# have opcodes outside of the ID reg scope, they have MPIDR_EL1/MIDR_EL1 +# accessors because if EL2 is not implemented, reads of those register +# return the value of MPIDR_EL1/MIDR_EL1. Skip them too. + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', 'VMPIDR_EL2', 'VPIDR_E= L2'] + +# return a tuple containing whether a register is a demux register and if = yes +# we also output its length. Currently we only handle CCSIDR. + +def get_demux_register_info(r): + name =3D r.get('name', '') + if not isinstance(r, dict): + return False, 0 + + if name.startswith("CCSIDR"): + return True, 16 + + return False, 0 + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers into + idregs[] dictionary whose key is the name of the register and + the value a string containing the opcodes. + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [ + r for r in register_data + if isinstance(r, dict) + and r.get('_type') =3D=3D 'Register' + ] + + idregs =3D {} + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and op1 in (0, 1, 3) and \ + crn =3D=3D 0 and (0 <=3D crm <=3D 7) and (0= <=3D op2 <=3D 7): + is_demux, demux_length =3D get_demux_regis= ter_info(register) + idregs[reg_name] =3D { + "encoding": encoding_str, + "is_demux": is_demux, + "demux_length": demux_length + } + + # sort by register name + return dict(sorted(idregs.items())) diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py new file mode 100755 index 0000000000..669314384b --- /dev/null +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc +# under the form of DEF(, , , , , ) or +# DEF_MUX(, , , , , , ) +# +# Copyright (C) 2027 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import json +import os +import sys + +from aarch64_sysreg_helpers import extract_idregs_from_registers_json + +if __name__ =3D=3D "__main__": + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysregs-header.py " + "") + sys.exit(1) + else: + json_file_path =3D sys.argv[1] + + extracted_registers =3D extract_idregs_from_registers_json(json_file_p= ath) + + if extracted_registers: + idregs =3D extracted_registers.items() + + # format lines as DEF(, , , , , ) + final_output =3D "" + for reg_name, info in idregs: + reformatted_encoding =3D info["encoding"].replace(" ", ", ") + is_demux =3D info.get("is_demux", False) + demux_length =3D info.get("demux_length", 0) + + if is_demux: + final_output +=3D ( + f"DEF_MUX({reg_name}, {reformatted_encoding}, " + f"{demux_length})\n" + ) + else: + final_output +=3D f"DEF({reg_name}, {reformatted_encoding}= )\n" + + with open("target/arm/cpu-sysregs.h.inc", 'w') as f: + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* This file is autogenerated by ") + f.write("scripts/update-aarch64-cpu-sysregs-header.py */\n") + f.write("/* DEF(, , , , , ) */\= n") + f.write("/* DEF_MUX(, , , , , ,= " + ") */\n\n") + f.write(final_output) + print("updated target/arm/cpu-sysregs.h.inc") --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Introduce an infrastructure to store the definition of all ID regs: This include their name, index array of named fields and enum values if any. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Co-authored-by: Khushit Shah Signed-off-by: Khushit Shah --- v9 -> v10: - commit description and comment slight rewording - store RangeValues instead of Values v7 -> v8: - remove typedef struct ArmIdRegArchVal v5 -> v6: - add ArmIdRegArchVal --- target/arm/cpu-idregs.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 target/arm/cpu-idregs.h diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h new file mode 100644 index 0000000000..e0399e251b --- /dev/null +++ b/target/arm/cpu-idregs.h @@ -0,0 +1,41 @@ +/* + * ID registers and their field definition + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef TARGET_ARM_CPU_IDREGS_H +#define TARGET_ARM_CPU_IDREGS_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegArchValueRange { + uint64_t lo; + uint64_t hi; +} ARM64SysRegArchValueRange; + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */ + int shift; /* lsb of the field in the register */ + int length; /* highest bit number */ + const ARM64SysRegArchValueRange *arch_value_ranges; + uint32_t arch_value_ranges_count; +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */ + struct ARM64SysRegField *fields; + uint32_t fields_count; + uint64_t writable_mask; +} ARM64SysReg; + +/* + * List of exposed ID regs (automatically populated from AARCHMRS Register= s.json) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +#endif --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=+7jpCnNWVONGrKduSQUm6TViuxQeMzjvlgr015jgBRY=; b=cz1vCIJHRoyYUtOLeN/zEBXUq/5LEV8NG5Inab3P+mU7wH7+YFNWJM36GOKAX6OAVoP9mE gDa9wkxp3O6iFQMRGL/lr7tahbsp/SfHrdOg+I5clMYzP9NPHU9T6XQOUPXOvrzS84/Wrf /5w1utgZBqUE90JUFSjW/ubZvt1NvVY= X-MC-Unique: pPR30kTvOl6fypfLPmiVBg-1 X-Mimecast-MFC-AGG-ID: pPR30kTvOl6fypfLPmiVBg_1791639485 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 06/26] target/arm/cpu-idregs.h.inc: Generate with script Date: Sat, 10 Oct 2026 15:36:10 +0200 Message-ID: <20261010133725.642498-7-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and automates the generation of system register properties definitions. generates target/arm/cpu-idregs.h.inc containing definitions for feature ID registers. Current generation is based on AARCHMRS_OPENSOURCE_A_profile_FAT-2026-03. We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Generate ID reg definitions with the scripts/update-aarch64-cpu-sysreg-prop= erties.py based on AARCHMRS_OPENSOURCE_A_profile_FAT-2026-03 Registers.json Each register and fields are described with this pattern: IDREG_START(REG) IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) ... IDREG_END(REG) Signed-off-by: Eric Auger Suggested-by: Khushit Shah Suggested-by: Shaju Abraham --- v9 -> v10: - squashed the script and the generated header. - improved comments - some minor code rework like sorting inside the helper v5 -> v6 - add ident --- target/arm/cpu-idregs.h.inc | 617 ++++++++++++++++++ .../update-aarch64-cpu-sysreg-properties.py | 165 +++++ 2 files changed, 782 insertions(+) create mode 100644 target/arm/cpu-idregs.h.inc create mode 100644 scripts/update-aarch64-cpu-sysreg-properties.py diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc new file mode 100644 index 0000000000..a10d750123 --- /dev/null +++ b/target/arm/cpu-idregs.h.inc @@ -0,0 +1,617 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* IDREG_START(REG) */ +/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ +/* ... */ +/* IDREG_END(REG) */ + +IDREG_START(AIDR_EL1) +IDREG_END(AIDR_EL1) + +IDREG_START(CCSIDR2_EL1) + IDREG_FIELD(CCSIDR2_EL1, NumSets, 0, 24) +IDREG_END(CCSIDR2_EL1) + +IDREG_START(CCSIDR_EL1) + IDREG_FIELD(CCSIDR_EL1, NumSets, 32, 24) + IDREG_FIELD(CCSIDR_EL1, Associativity, 3, 21) + IDREG_FIELD(CCSIDR_EL1, LineSize, 0, 3) +IDREG_END(CCSIDR_EL1) + +IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) + IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) + IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) + IDREG_FIELD(CLIDR_EL1, Ttype4, 39, 2) + IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) + IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) + IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) + IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) + IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) + IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) + IDREG_FIELD(CLIDR_EL1, Ctype7, 18, 3) + IDREG_FIELD(CLIDR_EL1, Ctype6, 15, 3) + IDREG_FIELD(CLIDR_EL1, Ctype5, 12, 3) + IDREG_FIELD(CLIDR_EL1, Ctype4, 9, 3) + IDREG_FIELD(CLIDR_EL1, Ctype3, 6, 3) + IDREG_FIELD(CLIDR_EL1, Ctype2, 3, 3) + IDREG_FIELD(CLIDR_EL1, Ctype1, 0, 3) +IDREG_END(CLIDR_EL1) + +IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, DIC, 29, 1) + IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD(CTR_EL0, CWG, 24, 4) + IDREG_FIELD(CTR_EL0, ERG, 20, 4) + IDREG_FIELD(CTR_EL0, DminLine, 16, 4) + IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD(CTR_EL0, IminLine, 0, 4) +IDREG_END(CTR_EL0) + +IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, TBS, 5, 4) + IDREG_FIELD(DCZID_EL0, DZP, 4, 1) + IDREG_FIELD(DCZID_EL0, BS, 0, 4) +IDREG_END(DCZID_EL0) + +IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, BS, 0, 4) +IDREG_END(GMID_EL1) + +IDREG_START(ID_AA64AFR0_EL1) +IDREG_END(ID_AA64AFR0_EL1) + +IDREG_START(ID_AA64AFR1_EL1) +IDREG_END(ID_AA64AFR1_EL1) + +IDREG_START(ID_AA64DFR0_EL1) + IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) +IDREG_END(ID_AA64DFR0_EL1) + +IDREG_START(ID_AA64DFR1_EL1) + IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) +IDREG_END(ID_AA64DFR1_EL1) + +IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) +IDREG_END(ID_AA64DFR2_EL1) + +IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) +IDREG_END(ID_AA64FPFR0_EL1) + +IDREG_START(ID_AA64ISAR0_EL1) + IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) +IDREG_END(ID_AA64ISAR0_EL1) + +IDREG_START(ID_AA64ISAR1_EL1) + IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) +IDREG_END(ID_AA64ISAR1_EL1) + +IDREG_START(ID_AA64ISAR2_EL1) + IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) +IDREG_END(ID_AA64ISAR2_EL1) + +IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) +IDREG_END(ID_AA64ISAR3_EL1) + +IDREG_START(ID_AA64MMFR0_EL1) + IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) +IDREG_END(ID_AA64MMFR0_EL1) + +IDREG_START(ID_AA64MMFR1_EL1) + IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) +IDREG_END(ID_AA64MMFR1_EL1) + +IDREG_START(ID_AA64MMFR2_EL1) + IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) +IDREG_END(ID_AA64MMFR2_EL1) + +IDREG_START(ID_AA64MMFR3_EL1) + IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) +IDREG_END(ID_AA64MMFR3_EL1) + +IDREG_START(ID_AA64MMFR4_EL1) + IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) +IDREG_END(ID_AA64MMFR4_EL1) + +IDREG_START(ID_AA64PFR0_EL1) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) +IDREG_END(ID_AA64PFR0_EL1) + +IDREG_START(ID_AA64PFR1_EL1) + IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) +IDREG_END(ID_AA64PFR1_EL1) + +IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) +IDREG_END(ID_AA64PFR2_EL1) + +IDREG_START(ID_AA64SMFR0_EL1) + IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) +IDREG_END(ID_AA64SMFR0_EL1) + +IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) +IDREG_END(ID_AA64ZFR0_EL1) + +IDREG_START(ID_AFR0_EL1) +IDREG_END(ID_AFR0_EL1) + +IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) + IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) + IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) + IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) + IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) +IDREG_END(ID_DFR0_EL1) + +IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) + IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) +IDREG_END(ID_DFR1_EL1) + +IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) + IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) + IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) + IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) + IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) +IDREG_END(ID_ISAR0_EL1) + +IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) + IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) + IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) + IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) + IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) + IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) +IDREG_END(ID_ISAR1_EL1) + +IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) + IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) + IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) + IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) + IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) +IDREG_END(ID_ISAR2_EL1) + +IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) + IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) + IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) + IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) + IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) + IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) + IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) + IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) +IDREG_END(ID_ISAR3_EL1) + +IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) + IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) + IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) + IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) + IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) + IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) + IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) +IDREG_END(ID_ISAR4_EL1) + +IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) + IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) + IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) + IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) +IDREG_END(ID_ISAR5_EL1) + +IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) + IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) + IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) + IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) + IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) + IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) + IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) +IDREG_END(ID_ISAR6_EL1) + +IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) + IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) + IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) + IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) + IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) + IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) + IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) + IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) +IDREG_END(ID_MMFR0_EL1) + +IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) +IDREG_END(ID_MMFR1_EL1) + +IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) + IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) + IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) + IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) +IDREG_END(ID_MMFR2_EL1) + +IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) + IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) + IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) + IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) + IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) +IDREG_END(ID_MMFR3_EL1) + +IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) + IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) + IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) + IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) + IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) + IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) + IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) + IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) +IDREG_END(ID_MMFR4_EL1) + +IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) + IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) +IDREG_END(ID_MMFR5_EL1) + +IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) + IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) + IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) + IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) + IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) + IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) + IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) +IDREG_END(ID_PFR0_EL1) + +IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) + IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) + IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) + IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) + IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) + IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) + IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) + IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) +IDREG_END(ID_PFR1_EL1) + +IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) + IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) +IDREG_END(ID_PFR2_EL1) + +IDREG_START(MIDR_EL1) + IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(MIDR_EL1, Variant, 20, 4) + IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) + IDREG_FIELD(MIDR_EL1, Revision, 0, 4) +IDREG_END(MIDR_EL1) + +IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, U, 30, 1) + IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) + IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) + IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) +IDREG_END(MPIDR_EL1) + +IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) + IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) + IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) + IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) + IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) + IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) + IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) + IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) +IDREG_END(MVFR0_EL1) + +IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) + IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) + IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) + IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) + IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) + IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) + IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) + IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) +IDREG_END(MVFR1_EL1) + +IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) + IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) +IDREG_END(MVFR2_EL1) + +IDREG_START(REVIDR_EL1) +IDREG_END(REVIDR_EL1) + +IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) + IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) + IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) + IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) + IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) +IDREG_END(SMIDR_EL1) + diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py new file mode 100644 index 0000000000..436e36ef58 --- /dev/null +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -0,0 +1,165 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs target/arm/cpu-idregs.h.inc content. +# ID regs are defined using this pattern: +# +# IDREG_START(REG) +# IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) +# ... +# IDREG_END(REG) +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys +from aarch64_sysreg_helpers import extract_idregs_from_registers_json + +# look for all the fields belonging to a register fieldset +# this is a recursive parser where bit_offset is used to convey +# bit positions from the parent container if any +def collect_fields(fieldset, bit_offset=3D0): + fields =3D [] + if not isinstance(fieldset, dict): + return fields + + _type =3D fieldset.get('_type', '') + + # Leaf array type (for example CLIDR_EL1 Ctype, Ttype) + if _type =3D=3D 'Fields.Array': + name_template =3D fieldset.get('name') or fieldset.get('label', '') + index_info =3D fieldset.get('indexes', [{}])[0] + start_idx =3D index_info.get('start', 0) + count =3D index_info.get('width', 0) + + full_range =3D fieldset.get('rangeset', [{}])[0] + bit_start =3D full_range.get('start', 0) + bit_offset + elem_width =3D full_range.get('width', 0) // count if count else 0 + + for i in range(count): + idx =3D start_idx + i + # Append the actual index to the field by replacing + field_name =3D name_template.replace('', str(idx)) + fields.append({ + 'name': field_name, + 'rangeset': [{ + 'start': bit_start + (i * elem_width), + 'width': elem_width + }], + '_type': 'Fields.Field' + }) + return fields + + # Conditional field which depend on specific FEAT_* + # like ID_AA64ZFR0_EL1_SVEver or ID_AA64MMFR4_EL1_E2H0 + elif _type =3D=3D 'Fields.ConditionalField': + container_bit_offset =3D bit_offset + if fieldset.get('rangeset'): + # Parent container defines the absolute start bit + container_bit_offset =3D fieldset['rangeset'][0].get('start', = bit_offset) + + for entry in fieldset.get('fields', []): + inner =3D entry.get('field') + if inner: + fields.extend(collect_fields(inner, container_bit_offset)) + return fields + + # Field Types + leaf_types =3D ['Fields.Field', 'Fields.ConstantField', + 'Fields.EnumeratedField', 'Fields.Bitfield'] + if _type in leaf_types: + field_copy =3D fieldset.copy() + if field_copy.get('rangeset'): + new_ranges =3D [] + for r in field_copy['rangeset']: + nr =3D r.copy() + nr['start'] =3D r.get('start', 0) + bit_offset + new_ranges.append(nr) + field_copy['rangeset'] =3D new_ranges + fields.append(field_copy) + return fields + + # Traverse the hierarchy for other cases + for key in ['fields', 'values', 'fieldsets']: + for nested in fieldset.get(key, []): + fields.extend(collect_fields(nested, bit_offset)) + + return fields + +def generate_sysreg_properties_from_registers_json(idregs, raw_json_path): + with open(raw_json_path, 'r') as f: + register_data =3D json.load(f) + + regs =3D {r.get('name'): r for r in register_data if r.get('_type') = =3D=3D 'Register'} + + final_output =3D "" + + for reg_name in idregs: + register =3D regs.get(reg_name) + if not register: + print(f"Error: Inconsistency when analyzing registers!", file= =3Dsys.stderr) + sys.exit(1) + + final_output +=3D f"IDREG_START({reg_name})\n" + + unique_fields =3D {} + for fieldset in register.get('fieldsets', []): + candidates =3D collect_fields(fieldset) + for val in candidates: + name =3D (val.get('name') or val.get('label', '')).strip() + if not name or "RESERVED" in name.upper(): + continue + for r in val.get('rangeset', []): + lsb =3D int(r.get('start')) + width =3D r.get('width') + msb =3D lsb + int(width) - 1 + + # In json, some idregs may have multiple fielsets, dep= ending + # on some architecture configurations. If this happens= , pick + # up a single one with the largest msb (known one is C= CSIDR + # which is currently skipped) + if name not in unique_fields or msb > unique_fields[na= me]['msb']: + unique_fields[name] =3D {'lsb': lsb, 'msb': msb, 'w= idth': width} + + # Sort by decreasing lsbs + sorted_fields =3D sorted(unique_fields.items(), + key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) + + for name, bits in sorted_fields: + line =3D (f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") + final_output +=3D line + final_output +=3D f"IDREG_END({reg_name})\n" + final_output +=3D "\n" + + os.makedirs("target/arm", exist_ok=3DTrue) + with open("target/arm/cpu-idregs.h.inc", 'w') as f: + f.write("/* AUTOMATICALLY GENERATED, DO NOT MODIFY */\n\n") + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* IDREG_START(REG) */\n") + f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* ... */\n") + f.write("/* IDREG_END(REG) */\n\n") + f.write(final_output) + +if __name__ =3D=3D "__main__": + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysreg-properties.= py " + "") + else: + json_path =3D sys.argv[1] + + idregs =3D extract_idregs_from_registers_json(json_path) + + if idregs: + generate_sysreg_properties_from_registers_json(idregs, json_pa= th) + print("Generated target/arm/cpu-idregs.h.inc") --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639499; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Jf9jQ24GLNfwsDnLqGMcnvrZtdOI5xfNIHnxJfzQckg=; b=GdUBbCP0hrw3R2+aMuYLOipeT/4Dl8FZoiUtj92TPQPYl3o9lKr+v8W1zEyoCV/jCzJY3M BNTlE08CpjunQzb/qAKfgpWLI7eBKmzE5WYSqMchtI99J8YlvChh9FiuWESuUDx/anOUEX Pwwv32aNATcqwVR4wp2QOKdiXEzj0fo= X-MC-Unique: IKFkFqlSN8-Rr1PdkftcGA-1 X-Mimecast-MFC-AGG-ID: IKFkFqlSN8-Rr1PdkftcGA_1791639490 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 07/26] target/arm/cpu-idregs.h.inc: Generate enum values Date: Sat, 10 Oct 2026 15:36:11 +0200 Message-ID: <20261010133725.642498-8-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_75_100=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639770040158500 Modify the python script so that enum values are also extracted from Registers.json. Single Values and ValueRange are wrapped as IDREG_FIELD_ENUM(REG, FIELD, SHIFT, LENGTH, IDREG_ARCH_VALUE_RANGE(LO, HI), ...). Consecutive values are merged. Using ranges even for single values produces a more compact header, which generally have at least 2 values and brings the benefice to have direct compact support for ValueRange. Signed-off-by: Eric Auger --- target/arm/cpu-idregs.h.inc | 1685 +++++++++++++---- .../update-aarch64-cpu-sysreg-properties.py | 125 +- 2 files changed, 1395 insertions(+), 415 deletions(-) diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc index a10d750123..be3540d41b 100644 --- a/target/arm/cpu-idregs.h.inc +++ b/target/arm/cpu-idregs.h.inc @@ -4,7 +4,9 @@ =20 /* IDREG_START(REG) */ /* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ -/* ... */ +/* or for fields with enum / ValueRange constraints */ +/* IDREG_FIELD_ENUM(REG, FIELD, SHIFT, LENGTH, */ +/* IDREG_ARCH_VALUE_RANGE(LO, HI), ...) */ /* IDREG_END(REG) */ =20 IDREG_START(AIDR_EL1) @@ -28,7 +30,9 @@ IDREG_START(CLIDR_EL1) IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) - IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD_ENUM(CLIDR_EL1, ICB, 30, 3, + IDREG_ARCH_VALUE_RANGE(0, 7) + ) IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) @@ -43,18 +47,26 @@ IDREG_END(CLIDR_EL1) =20 IDREG_START(CTR_EL0) IDREG_FIELD(CTR_EL0, TminLine, 32, 6) - IDREG_FIELD(CTR_EL0, DIC, 29, 1) - IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD_ENUM(CTR_EL0, DIC, 29, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(CTR_EL0, IDC, 28, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_FIELD(CTR_EL0, CWG, 24, 4) IDREG_FIELD(CTR_EL0, ERG, 20, 4) IDREG_FIELD(CTR_EL0, DminLine, 16, 4) - IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD_ENUM(CTR_EL0, L1Ip, 14, 2, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) IDREG_FIELD(CTR_EL0, IminLine, 0, 4) IDREG_END(CTR_EL0) =20 IDREG_START(DCZID_EL0) IDREG_FIELD(DCZID_EL0, TBS, 5, 4) - IDREG_FIELD(DCZID_EL0, DZP, 4, 1) + IDREG_FIELD_ENUM(DCZID_EL0, DZP, 4, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_FIELD(DCZID_EL0, BS, 0, 4) IDREG_END(DCZID_EL0) =20 @@ -69,549 +81,1404 @@ IDREG_START(ID_AA64AFR1_EL1) IDREG_END(ID_AA64AFR1_EL1) =20 IDREG_START(ID_AA64DFR0_EL1) - IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, HPMN0, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, BRBE, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, MTPMU, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, TraceBuffer, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, TraceFilt, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, DoubleLock, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, PMSVer, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 6) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 15) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, WRPs, 20, 4, + IDREG_ARCH_VALUE_RANGE(1, 15) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, PMSS, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, BRPs, 12, 4, + IDREG_ARCH_VALUE_RANGE(1, 15) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, PMUVer, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(4, 9), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, TraceVer, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, DebugVer, 0, 4, + IDREG_ARCH_VALUE_RANGE(6, 11) + ) IDREG_END(ID_AA64DFR0_EL1) =20 IDREG_START(ID_AA64DFR1_EL1) - IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8, + IDREG_ARCH_VALUE_RANGE(0, 63) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, DPFZS, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, EBEP, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, ITE, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, ABLE, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, PMICNTR, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, SPMU, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8, + IDREG_ARCH_VALUE_RANGE(0, 63) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, WRPs, 16, 8, + IDREG_ARCH_VALUE_RANGE(0, 63) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, BRPs, 8, 8, + IDREG_ARCH_VALUE_RANGE(0, 63) + ) + IDREG_FIELD_ENUM(ID_AA64DFR1_EL1, SYSPMUID, 0, 8, + IDREG_ARCH_VALUE_RANGE(0, 31) + ) IDREG_END(ID_AA64DFR1_EL1) =20 IDREG_START(ID_AA64DFR2_EL1) - IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) + IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, SPE_nVM, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, SPE_EXC, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, BWE, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, STEP, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64DFR2_EL1) =20 IDREG_START(ID_AA64FPFR0_EL1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8CVT, 31, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8FMA, 30, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8DP4, 29, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8DP2, 28, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8MM8, 27, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8MM4, 26, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F16MM2, 15, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8E4M3, 1, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8E5M2, 0, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64FPFR0_EL1) =20 IDREG_START(ID_AA64ISAR0_EL1) - IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, RNDR, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, TLB, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, TS, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, FHM, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, DP, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, SM4, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, SM3, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, SHA3, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, RDM, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, Atomic, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(2, 3) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, CRC32, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, SHA2, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, SHA1, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, AES, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_AA64ISAR0_EL1) =20 IDREG_START(ID_AA64ISAR1_EL1) - IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, LS64, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, XS, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, I8MM, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, DGH, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, BF16, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, SPECRES, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, SB, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, FRINTTS, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, GPI, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, GPA, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, LRCPC, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, FCMA, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, JSCVT, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, API, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 6) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, APA, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 6) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR1_EL1, DPB, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_AA64ISAR1_EL1) =20 IDREG_START(ID_AA64ISAR2_EL1) - IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, ATS1A, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, LUT, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, CSSC, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, RPRFM, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, CLRBHB, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, PAC_frac, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, BC, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, MOPS, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, APA3, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 6) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, GPA3, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, RPRES, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR2_EL1, WFxT, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(2, 2) + ) IDREG_END(ID_AA64ISAR2_EL1) =20 IDREG_START(ID_AA64ISAR3_EL1) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, LSCP, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, MTETC, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, FPRCVT, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, LSUI, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, OCCMO, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, LSFE, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, PACM, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, TLBIW, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, CPA, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_AA64ISAR3_EL1) =20 IDREG_START(ID_AA64MMFR0_EL1) - IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, ECV, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, FGT, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, ExS, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, TGran4_2, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, TGran64_2, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, TGran16_2, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, TGran4, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, TGran64, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, TGran16, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, SNSMem, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, BigEnd, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, ASIDBits, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(2, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, PARange, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 7) + ) IDREG_END(ID_AA64MMFR0_EL1) =20 IDREG_START(ID_AA64MMFR1_EL1) - IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, ECBHB, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, CMOW, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, TIDCP1, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, nTLBPA, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, AFP, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, HCX, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, ETS, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, TWED, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, XNX, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, SpecSEI, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, PAN, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, LO, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, HPDS, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, VH, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, VMIDBits, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(2, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR1_EL1, HAFDBS, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) IDREG_END(ID_AA64MMFR1_EL1) =20 IDREG_START(ID_AA64MMFR2_EL1) - IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, E0PD, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, EVT, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, BBM, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, TTL, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, FWB, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, IDS, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, AT, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, ST, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, NV, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, CCIDX, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, VARange, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, IESB, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, LSM, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, UAO, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, CnP, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64MMFR2_EL1) =20 IDREG_START(ID_AA64MMFR3_EL1) - IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, ADERR, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, SDERR, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, ANERR, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, SNERR, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, D128_2, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, D128, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, MEC, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, AIE, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, S2POE, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, S1POE, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, S2PIE, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, S1PIE, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, SCTLRX, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, TCRX, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64MMFR3_EL1) =20 IDREG_START(ID_AA64MMFR4_EL1) - IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, MTEFGT, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, SCRX, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, TEV, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, TPS, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, SRMASK, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, TLBID, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, E3DSE, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, EAESR, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, RMEGDI, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, E2H0, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(14, 15) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, NV_frac, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, FGWTE3, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, HACDBS, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, ASID2, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, EIESB, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 3), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64MMFR4_EL1, PoPS, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64MMFR4_EL1) =20 IDREG_START(ID_AA64PFR0_EL1) - IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, CSV3, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, CSV2, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, RME, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, DIT, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, AMU, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, MPAM, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, SEL2, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, SVE, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, RAS, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, GIC, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(3, 3) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, AdvSIMD, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, FP, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, EL3, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, EL2, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, EL1, 4, 4, + IDREG_ARCH_VALUE_RANGE(1, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR0_EL1, EL0, 0, 4, + IDREG_ARCH_VALUE_RANGE(1, 2) + ) IDREG_END(ID_AA64PFR0_EL1) =20 IDREG_START(ID_AA64PFR1_EL1) - IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, PFAR, 60, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, DF2, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, MTEX, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, THE, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, GCS, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, MTE_frac, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, NMI, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, CSV2_frac, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, RNDR_trap, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, SME, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, MPAM_frac, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, RAS_frac, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, MTE, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, SSBS, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, BT, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_AA64PFR1_EL1) =20 IDREG_START(ID_AA64PFR2_EL1) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, VMTETCL, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, VMTETC, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, VMTE, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, FPMR, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, MPAM2, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, FGDT, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, MTEEIRG, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, UINJ, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, GCIE, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, MTEFAR, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, MTEPERM, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64PFR2_EL1) =20 IDREG_START(ID_AA64SMFR0_EL1) - IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, FA64, 63, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, LUT6, 61, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, LUTv2, 60, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SMEver, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, I16I64, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F64F64, 48, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, I16I32, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(5, 5) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, B16B16, 43, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F16F16, 42, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F8F16, 41, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F8F32, 40, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, I8I32, 36, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F16F32, 35, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, B16F32, 34, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, BI32I32, 33, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F32F32, 32, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SF8FMA, 30, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SF8DP4, 29, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SF8DP2, 28, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SBitPerm, 25, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, AES, 24, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SFEXPA, 23, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, STMOP, 16, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SMOP4, 0, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_AA64SMFR0_EL1) =20 IDREG_START(ID_AA64ZFR0_EL1) - IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, F64MM, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, F32MM, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, F16MM, 48, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, I8MM, 44, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, SM4, 40, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, SHA3, 32, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, B16B16, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, BF16, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, BitPerm, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, EltPerm, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, AES, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, SVEver, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) IDREG_END(ID_AA64ZFR0_EL1) =20 IDREG_START(ID_AFR0_EL1) IDREG_END(ID_AFR0_EL1) =20 IDREG_START(ID_DFR0_EL1) - IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) - IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) - IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) - IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) - IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) - IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD_ENUM(ID_DFR0_EL1, TraceFilt, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_DFR0_EL1, PerfMon, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 9), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_DFR0_EL1, MProfDbg, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_DFR0_EL1, MMapTrc, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_DFR0_EL1, CopTrc, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_DFR0_EL1, MMapDbg, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(4, 5) + ) IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) - IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) + IDREG_FIELD_ENUM(ID_DFR0_EL1, CopDbg, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(2, 11) + ) IDREG_END(ID_DFR0_EL1) =20 IDREG_START(ID_DFR1_EL1) - IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) - IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) + IDREG_FIELD_ENUM(ID_DFR1_EL1, HPMN0, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_DFR1_EL1, MTPMU, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) IDREG_END(ID_DFR1_EL1) =20 IDREG_START(ID_ISAR0_EL1) - IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) - IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) - IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) - IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) - IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) - IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) - IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, Divide, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, Debug, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, Coproc, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, CmpBranch, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, BitField, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, BitCount, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR0_EL1, Swap, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_ISAR0_EL1) =20 IDREG_START(ID_ISAR1_EL1) - IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) - IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) - IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) - IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) - IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) - IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) - IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) - IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Jazelle, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Interwork, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Immediate, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, IfThen, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Extend, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Except_AR, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Except, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR1_EL1, Endian, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_ISAR1_EL1) =20 IDREG_START(ID_ISAR2_EL1) - IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) - IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) - IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) - IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) - IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, Reversal, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, PSR_AR, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, MultU, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, MultS, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, Mult, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, MultiAccessInt, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, MemHint, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) + IDREG_FIELD_ENUM(ID_ISAR2_EL1, LoadStore, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_ISAR2_EL1) =20 IDREG_START(ID_ISAR3_EL1) - IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) - IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) - IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) - IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) - IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) - IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) - IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) - IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, T32EE, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, TrueNOP, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, T32Copy, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, TabBranch, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, SynchPrim, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, SVC, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, SIMD, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(3, 3) + ) + IDREG_FIELD_ENUM(ID_ISAR3_EL1, Saturate, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_ISAR3_EL1) =20 IDREG_START(ID_ISAR4_EL1) - IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) - IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) - IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) - IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) - IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) - IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) - IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) - IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, SWP_frac, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, PSR_M, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, SynchPrim_frac, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(3, 3) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, Barrier, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, SMC, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, Writeback, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, WithShifts, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(3, 4) + ) + IDREG_FIELD_ENUM(ID_ISAR4_EL1, Unpriv, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_ISAR4_EL1) =20 IDREG_START(ID_ISAR5_EL1) - IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) - IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) - IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) - IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) - IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) - IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) - IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, VCMA, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, RDM, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, CRC32, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, SHA2, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, SHA1, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, AES, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR5_EL1, SEVL, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_ISAR5_EL1) =20 IDREG_START(ID_ISAR6_EL1) - IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) - IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) - IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) - IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) - IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) - IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) - IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) - IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, CLRBHB, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, I8MM, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, BF16, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, SPECRES, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, SB, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, FHM, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, DP, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_ISAR6_EL1, JSCVT, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_ISAR6_EL1) =20 IDREG_START(ID_MMFR0_EL1) - IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) - IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) - IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) - IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) - IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) - IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) - IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) - IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, InnerShr, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, FCSE, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, AuxReg, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, TCM, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, ShareLvl, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, OuterShr, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, PMSA, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_MMFR0_EL1, VMSA, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 5) + ) IDREG_END(ID_MMFR0_EL1) =20 IDREG_START(ID_MMFR1_EL1) - IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, BPred, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1TstCln, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1Uni, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1Hvd, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1UniSW, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1HvdSW, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1UniVA, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR1_EL1, L1HvdVA, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(ID_MMFR1_EL1) =20 IDREG_START(ID_MMFR2_EL1) - IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) - IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) - IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) - IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, HWAccFlg, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, WFIStall, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, MemBarr, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, UniTLB, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 6) + ) IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, L1HvdRng, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, L1HvdBG, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR2_EL1, L1HvdFG, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_MMFR2_EL1) =20 IDREG_START(ID_MMFR3_EL1) - IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) - IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) - IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) - IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) - IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, Supersec, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, CMemSz, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, CohWalk, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, PAN, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, MaintBcst, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, BPMaint, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, CMaintSW, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR3_EL1, CMaintVA, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_MMFR3_EL1) =20 IDREG_START(ID_MMFR4_EL1) - IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) - IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) - IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) - IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) - IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) - IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) - IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) - IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, EVT, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, CCIDX, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, LSM, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, HPDS, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, CnP, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, XNX, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, AC2, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR4_EL1, SpecSEI, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_MMFR4_EL1) =20 IDREG_START(ID_MMFR5_EL1) - IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) - IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) + IDREG_FIELD_ENUM(ID_MMFR5_EL1, nTLBPA, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_MMFR5_EL1, ETS, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) IDREG_END(ID_MMFR5_EL1) =20 IDREG_START(ID_PFR0_EL1) - IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) - IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) - IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) - IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) - IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) - IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) - IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) - IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) + IDREG_FIELD_ENUM(ID_PFR0_EL1, RAS, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, DIT, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, AMU, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, CSV2, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, State3, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, State2, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, State1, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(3, 3) + ) + IDREG_FIELD_ENUM(ID_PFR0_EL1, State0, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_PFR0_EL1) =20 IDREG_START(ID_PFR1_EL1) - IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) - IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) - IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) - IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) - IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) - IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) - IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) - IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) + IDREG_FIELD_ENUM(ID_PFR1_EL1, GIC, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1), + IDREG_ARCH_VALUE_RANGE(3, 3) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, Virt_frac, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, Sec_frac, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, GenTimer, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, Virtualization, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, MProgMod, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(2, 2) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, Security, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(ID_PFR1_EL1, ProgMod, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_PFR1_EL1) =20 IDREG_START(ID_PFR2_EL1) - IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) - IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) - IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) + IDREG_FIELD_ENUM(ID_PFR2_EL1, RAS_frac, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_PFR2_EL1, SSBS, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(ID_PFR2_EL1, CSV3, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(ID_PFR2_EL1) =20 IDREG_START(MIDR_EL1) - IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_ENUM(MIDR_EL1, Implementer, 24, 8, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(65, 68), + IDREG_ARCH_VALUE_RANGE(70, 70), + IDREG_ARCH_VALUE_RANGE(73, 73), + IDREG_ARCH_VALUE_RANGE(77, 78), + IDREG_ARCH_VALUE_RANGE(80, 81), + IDREG_ARCH_VALUE_RANGE(86, 86), + IDREG_ARCH_VALUE_RANGE(105, 105), + IDREG_ARCH_VALUE_RANGE(192, 192) + ) IDREG_FIELD(MIDR_EL1, Variant, 20, 4) - IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD_ENUM(MIDR_EL1, Architecture, 16, 4, + IDREG_ARCH_VALUE_RANGE(1, 7), + IDREG_ARCH_VALUE_RANGE(15, 15) + ) IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) IDREG_FIELD(MIDR_EL1, Revision, 0, 4) IDREG_END(MIDR_EL1) =20 IDREG_START(MPIDR_EL1) IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) - IDREG_FIELD(MPIDR_EL1, U, 30, 1) - IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD_ENUM(MPIDR_EL1, U, 30, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MPIDR_EL1, MT, 24, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) IDREG_END(MPIDR_EL1) =20 IDREG_START(MVFR0_EL1) - IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) - IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) - IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) - IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) - IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) - IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) - IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) - IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) + IDREG_FIELD_ENUM(MVFR0_EL1, FPRound, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, FPShVec, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, FPSqrt, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, FPDivide, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, FPTrap, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, FPDP, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, FPSP, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(MVFR0_EL1, SIMDReg, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) IDREG_END(MVFR0_EL1) =20 IDREG_START(MVFR1_EL1) - IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) - IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) - IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) - IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) - IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) - IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) - IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) - IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) + IDREG_FIELD_ENUM(MVFR1_EL1, SIMDFMAC, 28, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, FPHP, 24, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, SIMDHP, 20, 4, + IDREG_ARCH_VALUE_RANGE(0, 2) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, SIMDSP, 16, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, SIMDInt, 12, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, SIMDLS, 8, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, FPDNaN, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(MVFR1_EL1, FPFtZ, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) IDREG_END(MVFR1_EL1) =20 IDREG_START(MVFR2_EL1) - IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) - IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) + IDREG_FIELD_ENUM(MVFR2_EL1, FPMisc, 4, 4, + IDREG_ARCH_VALUE_RANGE(0, 4) + ) + IDREG_FIELD_ENUM(MVFR2_EL1, SIMDMisc, 0, 4, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) IDREG_END(MVFR2_EL1) =20 IDREG_START(REVIDR_EL1) IDREG_END(REVIDR_EL1) =20 IDREG_START(SMIDR_EL1) - IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) - IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD_ENUM(SMIDR_EL1, NSMC, 56, 4, + IDREG_ARCH_VALUE_RANGE(0, 15) + ) + IDREG_FIELD_ENUM(SMIDR_EL1, HIP, 52, 4, + IDREG_ARCH_VALUE_RANGE(0, 15) + ) IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) - IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_ENUM(SMIDR_EL1, Implementer, 24, 8, + IDREG_ARCH_VALUE_RANGE(0, 0), + IDREG_ARCH_VALUE_RANGE(65, 68), + IDREG_ARCH_VALUE_RANGE(70, 70), + IDREG_ARCH_VALUE_RANGE(73, 73), + IDREG_ARCH_VALUE_RANGE(77, 78), + IDREG_ARCH_VALUE_RANGE(80, 81), + IDREG_ARCH_VALUE_RANGE(86, 86), + IDREG_ARCH_VALUE_RANGE(105, 105), + IDREG_ARCH_VALUE_RANGE(192, 192) + ) IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) - IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) - IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD_ENUM(SMIDR_EL1, SMPS, 15, 1, + IDREG_ARCH_VALUE_RANGE(0, 1) + ) + IDREG_FIELD_ENUM(SMIDR_EL1, SH, 13, 2, + IDREG_ARCH_VALUE_RANGE(0, 3) + ) IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) IDREG_END(SMIDR_EL1) =20 diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py index 436e36ef58..b4b548a6e2 100644 --- a/scripts/update-aarch64-cpu-sysreg-properties.py +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -9,7 +9,10 @@ # # IDREG_START(REG) # IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) -# ... +# or for fields with enum / ValueRange constraints +# IDREG_FIELD_ENUM(REG, FIELD, SHIFT, LENGTH, +# IDREG_ARCH_VALUE_RANGE(LO, HI), ...) +# ../.. # IDREG_END(REG) # # Copyright (C) 2026 Red Hat, Inc. @@ -95,6 +98,102 @@ def collect_fields(fieldset, bit_offset=3D0): =20 return fields =20 +# Helper to unwrap integer values from strings and interpret +# the value as a binary or a decimal. example: "'0011'" +def parse_value(val_obj): + if isinstance(val_obj, dict): + val_obj =3D val_obj.get("value") + + if val_obj is None: + return None + + # remove ' + clean_str =3D str(val_obj).strip().replace("'", "") + try: + # try binary extraction + return int(clean_str, 2) + except ValueError: + try: + # fall back to decimal extraction + return int(clean_str, 0) + except ValueError: + return None + +def process_value_container(node, enums): + if not isinstance(node, dict): + return + + entry_type =3D node.get("_type", "") + + if entry_type =3D=3D "Values.ValueRange": + s =3D parse_value(node.get("start")) + e =3D parse_value(node.get("end")) + if s is not None and e is not None: + enums.append({'lo': s, 'hi': e}) + return + + # Leaf single value (Values.Value) =E2=86=92 singleton range + int_val =3D parse_value(node) + if int_val is not None: + enums.append({'lo': int_val, 'hi': int_val}) + return + + # Non leaf elements (ImplementationDefined, ConditionalValue, etc.) + for key in ["constraints", "values", "value", "then", "else", "items"]: + sub =3D node.get(key) + if isinstance(sub, list): + # list of values + for item in sub: + process_value_container(item, enums) + elif isinstance(sub, dict): + process_value_container(sub, enums) + +def extract_field_enums(field): + enums =3D [] + if not isinstance(field, dict): + return enums + + if "value" in field and isinstance(field["value"], dict): + process_value_container(field["value"], enums) + elif "values" in field: + process_value_container(field["values"], enums) + + # Deduplicate identical (lo, hi) pairs while preserving order. + already_collected =3D set() + unique_enums =3D [] + for item in enums: + key =3D (item['lo'], item['hi']) + if key not in already_collected: + already_collected.add(key) + unique_enums.append(item) + + return unique_enums + +def merge_enum_ranges(ranges): + if not ranges: + return [] + ordered =3D sorted(ranges, key=3Dlambda r: (r['lo'], r['hi'])) + merged =3D [{'lo': ordered[0]['lo'], 'hi': ordered[0]['hi']}] + for item in ordered[1:]: + cur =3D merged[-1] + if item['lo'] <=3D cur['hi'] + 1: + cur['hi'] =3D max(cur['hi'], item['hi']) + else: + merged.append({'lo': item['lo'], 'hi': item['hi']}) + return merged + +def format_field_enum(reg_name, field_name, lsb, width, ranges): + """IDREG_FIELD_ENUM(..., IDREG_ARCH_VALUE_RANGE(...), ...).""" + lines =3D [ + f" IDREG_FIELD_ENUM({reg_name}, {field_name}, {lsb}, {width},\n" + ] + for i, item in enumerate(ranges): + lo, hi =3D item['lo'], item['hi'] + comma =3D "," if i + 1 < len(ranges) else "" + lines.append(f" IDREG_ARCH_VALUE_RANGE({lo}, {hi})= {comma}\n") + lines.append(" )\n") + return "".join(lines) + def generate_sysreg_properties_from_registers_json(idregs, raw_json_path): with open(raw_json_path, 'r') as f: register_data =3D json.load(f) @@ -128,16 +227,28 @@ def generate_sysreg_properties_from_registers_json(id= regs, raw_json_path): # up a single one with the largest msb (known one is C= CSIDR # which is currently skipped) if name not in unique_fields or msb > unique_fields[na= me]['msb']: - unique_fields[name] =3D {'lsb': lsb, 'msb': msb, 'w= idth': width} + # extract enum values if any + enums =3D extract_field_enums(val) + unique_fields[name] =3D \ + {'lsb': lsb, 'msb': msb, 'width': width, 'enum= s': enums} =20 # Sort by decreasing lsbs sorted_fields =3D sorted(unique_fields.items(), key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) =20 for name, bits in sorted_fields: - line =3D (f" IDREG_FIELD({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") - final_output +=3D line + enums_list =3D bits.get('enums', []) + + if enums_list: + final_output +=3D format_field_enum( + reg_name, name, bits['lsb'], bits['width'], + merge_enum_ranges(enums_list)) + else: + final_output +=3D ( + f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n" + ) + final_output +=3D f"IDREG_END({reg_name})\n" final_output +=3D "\n" =20 @@ -147,7 +258,9 @@ def generate_sysreg_properties_from_registers_json(idre= gs, raw_json_path): f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") f.write("/* IDREG_START(REG) */\n") f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") - f.write("/* ... */\n") + f.write("/* or for fields with enum / ValueRange constraints *= /\n") + f.write("/* IDREG_FIELD_ENUM(REG, FIELD, SHIFT, LENGTH, */\n") + f.write("/* IDREG_ARCH_VALUE_RANGE(LO, HI), .= ..) */\n") f.write("/* IDREG_END(REG) */\n\n") f.write(final_output) =20 --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639689; cv=none; d=zohomail.com; s=zohoarc; b=JUj3BuPzSUIUeSXNNrGJ5Icvpxt+5lWgMj7Yvm/k3G3BLA9DjhgKKesdXOuS+P5wY8NcabmIhA+cBrgQ79Jh6ra3jTS7wL1ZXSeeoHlkuks/C2el9n2QQwgzyyrv7ARV/KMND8C53XEOfRWn7xnpF5V9nEd/m27TamYwzw5Inao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639689; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 08/26] target/arm/cpu-idregs.h.inc: Generate reserved fields Date: Sat, 10 Oct 2026 15:36:12 +0200 Message-ID: <20261010133725.642498-9-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639690361158500 Content-Type: text/plain; charset="utf-8" Extract reserved fields: RES0, RES1, RAZ, ... The extra complexity comes from the fact several reserved fields may exist in the register, as opposed to named fields. Signed-off-by: Eric Auger --- v7 -> v8: - fix WithShifts issue --- target/arm/cpu-idregs.h.inc | 65 ++++++++++++++ .../update-aarch64-cpu-sysreg-properties.py | 85 +++++++++++++++---- 2 files changed, 134 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc index be3540d41b..b9beda484b 100644 --- a/target/arm/cpu-idregs.h.inc +++ b/target/arm/cpu-idregs.h.inc @@ -13,16 +13,20 @@ IDREG_START(AIDR_EL1) IDREG_END(AIDR_EL1) =20 IDREG_START(CCSIDR2_EL1) + IDREG_FIELD(CCSIDR2_EL1, RES0, 24, 40) IDREG_FIELD(CCSIDR2_EL1, NumSets, 0, 24) IDREG_END(CCSIDR2_EL1) =20 IDREG_START(CCSIDR_EL1) + IDREG_FIELD(CCSIDR_EL1, RES0, 56, 8) IDREG_FIELD(CCSIDR_EL1, NumSets, 32, 24) + IDREG_FIELD(CCSIDR_EL1, RES0, 24, 8) IDREG_FIELD(CCSIDR_EL1, Associativity, 3, 21) IDREG_FIELD(CCSIDR_EL1, LineSize, 0, 3) IDREG_END(CCSIDR_EL1) =20 IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, RES0, 47, 17) IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) @@ -46,7 +50,10 @@ IDREG_START(CLIDR_EL1) IDREG_END(CLIDR_EL1) =20 IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, RES0, 38, 26) IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, RES1, 31, 1) + IDREG_FIELD(CTR_EL0, RES0, 30, 1) IDREG_FIELD_ENUM(CTR_EL0, DIC, 29, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -59,10 +66,12 @@ IDREG_START(CTR_EL0) IDREG_FIELD_ENUM(CTR_EL0, L1Ip, 14, 2, IDREG_ARCH_VALUE_RANGE(0, 3) ) + IDREG_FIELD(CTR_EL0, RES0, 4, 10) IDREG_FIELD(CTR_EL0, IminLine, 0, 4) IDREG_END(CTR_EL0) =20 IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, RES0, 9, 55) IDREG_FIELD(DCZID_EL0, TBS, 5, 4) IDREG_FIELD_ENUM(DCZID_EL0, DZP, 4, 1, IDREG_ARCH_VALUE_RANGE(0, 1) @@ -71,13 +80,16 @@ IDREG_START(DCZID_EL0) IDREG_END(DCZID_EL0) =20 IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, RES0, 4, 60) IDREG_FIELD(GMID_EL1, BS, 0, 4) IDREG_END(GMID_EL1) =20 IDREG_START(ID_AA64AFR0_EL1) + IDREG_FIELD(ID_AA64AFR0_EL1, RES0, 32, 32) IDREG_END(ID_AA64AFR0_EL1) =20 IDREG_START(ID_AA64AFR1_EL1) + IDREG_FIELD(ID_AA64AFR1_EL1, RES0, 0, 64) IDREG_END(ID_AA64AFR1_EL1) =20 IDREG_START(ID_AA64DFR0_EL1) @@ -110,6 +122,7 @@ IDREG_START(ID_AA64DFR0_EL1) IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 15) ) + IDREG_FIELD(ID_AA64DFR0_EL1, RES0, 24, 4) IDREG_FIELD_ENUM(ID_AA64DFR0_EL1, WRPs, 20, 4, IDREG_ARCH_VALUE_RANGE(1, 15) ) @@ -169,6 +182,7 @@ IDREG_START(ID_AA64DFR1_EL1) IDREG_END(ID_AA64DFR1_EL1) =20 IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, RES0, 28, 36) IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -178,6 +192,7 @@ IDREG_START(ID_AA64DFR2_EL1) IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, SPE_EXC, 16, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64DFR2_EL1, RES0, 8, 8) IDREG_FIELD_ENUM(ID_AA64DFR2_EL1, BWE, 4, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) @@ -187,6 +202,7 @@ IDREG_START(ID_AA64DFR2_EL1) IDREG_END(ID_AA64DFR2_EL1) =20 IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8CVT, 31, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -205,9 +221,12 @@ IDREG_START(ID_AA64FPFR0_EL1) IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8MM4, 26, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 16, 10) IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F16MM2, 15, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 8, 7) + IDREG_FIELD(ID_AA64FPFR0_EL1, RAZ, 2, 6) IDREG_FIELD_ENUM(ID_AA64FPFR0_EL1, F8E4M3, 1, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -244,6 +263,7 @@ IDREG_START(ID_AA64ISAR0_EL1) IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, RDM, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64ISAR0_EL1, RES0, 24, 4) IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, Atomic, 20, 4, IDREG_ARCH_VALUE_RANGE(0, 0), IDREG_ARCH_VALUE_RANGE(2, 3) @@ -260,6 +280,7 @@ IDREG_START(ID_AA64ISAR0_EL1) IDREG_FIELD_ENUM(ID_AA64ISAR0_EL1, AES, 4, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) + IDREG_FIELD(ID_AA64ISAR0_EL1, RES0, 0, 4) IDREG_END(ID_AA64ISAR0_EL1) =20 IDREG_START(ID_AA64ISAR1_EL1) @@ -366,6 +387,7 @@ IDREG_START(ID_AA64ISAR2_EL1) IDREG_END(ID_AA64ISAR2_EL1) =20 IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, RES0, 48, 16) IDREG_FIELD_ENUM(ID_AA64ISAR3_EL1, LSCP, 44, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -411,6 +433,7 @@ IDREG_START(ID_AA64MMFR0_EL1) IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, FGT, 56, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) + IDREG_FIELD(ID_AA64MMFR0_EL1, RES0, 48, 8) IDREG_FIELD_ENUM(ID_AA64MMFR0_EL1, ExS, 44, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -517,6 +540,7 @@ IDREG_START(ID_AA64MMFR2_EL1) IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, TTL, 48, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64MMFR2_EL1, RES0, 44, 4) IDREG_FIELD_ENUM(ID_AA64MMFR2_EL1, FWB, 40, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -562,6 +586,7 @@ IDREG_START(ID_AA64MMFR3_EL1) IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, SDERR, 52, 4, IDREG_ARCH_VALUE_RANGE(0, 3) ) + IDREG_FIELD(ID_AA64MMFR3_EL1, RES0, 48, 4) IDREG_FIELD_ENUM(ID_AA64MMFR3_EL1, ANERR, 44, 4, IDREG_ARCH_VALUE_RANGE(0, 3) ) @@ -739,6 +764,7 @@ IDREG_START(ID_AA64PFR1_EL1) IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, SME, 24, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) + IDREG_FIELD(ID_AA64PFR1_EL1, RES0, 20, 4) IDREG_FIELD_ENUM(ID_AA64PFR1_EL1, MPAM_frac, 16, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -757,6 +783,7 @@ IDREG_START(ID_AA64PFR1_EL1) IDREG_END(ID_AA64PFR1_EL1) =20 IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, RES0, 48, 16) IDREG_FIELD_ENUM(ID_AA64PFR2_EL1, VMTETCL, 44, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -799,6 +826,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, FA64, 63, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 62, 1) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, LUT6, 61, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -812,6 +840,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_ARCH_VALUE_RANGE(0, 0), IDREG_ARCH_VALUE_RANGE(15, 15) ) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 49, 3) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F64F64, 48, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -847,6 +876,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, F32F32, 32, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 31, 1) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SF8FMA, 30, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -856,6 +886,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SF8DP2, 28, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 26, 2) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SBitPerm, 25, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -865,15 +896,18 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SFEXPA, 23, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 17, 6) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, STMOP, 16, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 1, 15) IDREG_FIELD_ENUM(ID_AA64SMFR0_EL1, SMOP4, 0, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) IDREG_END(ID_AA64SMFR0_EL1) =20 IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 60, 4) IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, F64MM, 56, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -889,9 +923,11 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, SM4, 40, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 36, 4) IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, SHA3, 32, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 28, 4) IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, B16B16, 24, 4, IDREG_ARCH_VALUE_RANGE(0, 3) ) @@ -904,6 +940,7 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, EltPerm, 12, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 8, 4) IDREG_FIELD_ENUM(ID_AA64ZFR0_EL1, AES, 4, 4, IDREG_ARCH_VALUE_RANGE(0, 3) ) @@ -913,9 +950,11 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_END(ID_AA64ZFR0_EL1) =20 IDREG_START(ID_AFR0_EL1) + IDREG_FIELD(ID_AFR0_EL1, RES0, 0, 64) IDREG_END(ID_AFR0_EL1) =20 IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_DFR0_EL1, TraceFilt, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -944,6 +983,7 @@ IDREG_START(ID_DFR0_EL1) IDREG_END(ID_DFR0_EL1) =20 IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, RES0, 8, 56) IDREG_FIELD_ENUM(ID_DFR1_EL1, HPMN0, 4, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -954,6 +994,7 @@ IDREG_START(ID_DFR1_EL1) IDREG_END(ID_DFR1_EL1) =20 IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, RES0, 28, 36) IDREG_FIELD_ENUM(ID_ISAR0_EL1, Divide, 24, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) @@ -978,6 +1019,7 @@ IDREG_START(ID_ISAR0_EL1) IDREG_END(ID_ISAR0_EL1) =20 IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_ISAR1_EL1, Jazelle, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1005,6 +1047,7 @@ IDREG_START(ID_ISAR1_EL1) IDREG_END(ID_ISAR1_EL1) =20 IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_ISAR2_EL1, Reversal, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) @@ -1032,6 +1075,7 @@ IDREG_START(ID_ISAR2_EL1) IDREG_END(ID_ISAR2_EL1) =20 IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_ISAR3_EL1, T32EE, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1060,6 +1104,7 @@ IDREG_START(ID_ISAR3_EL1) IDREG_END(ID_ISAR3_EL1) =20 IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_ISAR4_EL1, SWP_frac, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1089,12 +1134,14 @@ IDREG_START(ID_ISAR4_EL1) IDREG_END(ID_ISAR4_EL1) =20 IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_ISAR5_EL1, VCMA, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) IDREG_FIELD_ENUM(ID_ISAR5_EL1, RDM, 24, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(ID_ISAR5_EL1, RES0, 20, 4) IDREG_FIELD_ENUM(ID_ISAR5_EL1, CRC32, 16, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1113,6 +1160,7 @@ IDREG_START(ID_ISAR5_EL1) IDREG_END(ID_ISAR5_EL1) =20 IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_ISAR6_EL1, CLRBHB, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1140,6 +1188,7 @@ IDREG_START(ID_ISAR6_EL1) IDREG_END(ID_ISAR6_EL1) =20 IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_MMFR0_EL1, InnerShr, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1), IDREG_ARCH_VALUE_RANGE(15, 15) @@ -1169,6 +1218,7 @@ IDREG_START(ID_MMFR0_EL1) IDREG_END(ID_MMFR0_EL1) =20 IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_MMFR1_EL1, BPred, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 4) ) @@ -1196,6 +1246,7 @@ IDREG_START(ID_MMFR1_EL1) IDREG_END(ID_MMFR1_EL1) =20 IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_MMFR2_EL1, HWAccFlg, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1221,6 +1272,7 @@ IDREG_START(ID_MMFR2_EL1) IDREG_END(ID_MMFR2_EL1) =20 IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_MMFR3_EL1, Supersec, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 0), IDREG_ARCH_VALUE_RANGE(15, 15) @@ -1249,6 +1301,7 @@ IDREG_START(ID_MMFR3_EL1) IDREG_END(ID_MMFR3_EL1) =20 IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_MMFR4_EL1, EVT, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 2) ) @@ -1276,6 +1329,7 @@ IDREG_START(ID_MMFR4_EL1) IDREG_END(ID_MMFR4_EL1) =20 IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, RES0, 8, 56) IDREG_FIELD_ENUM(ID_MMFR5_EL1, nTLBPA, 4, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1285,6 +1339,7 @@ IDREG_START(ID_MMFR5_EL1) IDREG_END(ID_MMFR5_EL1) =20 IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_PFR0_EL1, RAS, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 3) ) @@ -1313,6 +1368,7 @@ IDREG_START(ID_PFR0_EL1) IDREG_END(ID_PFR0_EL1) =20 IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(ID_PFR1_EL1, GIC, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1), IDREG_ARCH_VALUE_RANGE(3, 3) @@ -1342,6 +1398,7 @@ IDREG_START(ID_PFR1_EL1) IDREG_END(ID_PFR1_EL1) =20 IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RES0, 12, 52) IDREG_FIELD_ENUM(ID_PFR2_EL1, RAS_frac, 8, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1375,10 +1432,13 @@ IDREG_START(MIDR_EL1) IDREG_END(MIDR_EL1) =20 IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, RES0, 40, 24) IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, RES1, 31, 1) IDREG_FIELD_ENUM(MPIDR_EL1, U, 30, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) + IDREG_FIELD(MPIDR_EL1, RES0, 25, 5) IDREG_FIELD_ENUM(MPIDR_EL1, MT, 24, 1, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1388,6 +1448,7 @@ IDREG_START(MPIDR_EL1) IDREG_END(MPIDR_EL1) =20 IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(MVFR0_EL1, FPRound, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1415,6 +1476,7 @@ IDREG_START(MVFR0_EL1) IDREG_END(MVFR0_EL1) =20 IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, RES0, 32, 32) IDREG_FIELD_ENUM(MVFR1_EL1, SIMDFMAC, 28, 4, IDREG_ARCH_VALUE_RANGE(0, 1) ) @@ -1442,6 +1504,7 @@ IDREG_START(MVFR1_EL1) IDREG_END(MVFR1_EL1) =20 IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, RES0, 8, 56) IDREG_FIELD_ENUM(MVFR2_EL1, FPMisc, 4, 4, IDREG_ARCH_VALUE_RANGE(0, 4) ) @@ -1454,6 +1517,7 @@ IDREG_START(REVIDR_EL1) IDREG_END(REVIDR_EL1) =20 IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, RES0, 60, 4) IDREG_FIELD_ENUM(SMIDR_EL1, NSMC, 56, 4, IDREG_ARCH_VALUE_RANGE(0, 15) ) @@ -1479,6 +1543,7 @@ IDREG_START(SMIDR_EL1) IDREG_FIELD_ENUM(SMIDR_EL1, SH, 13, 2, IDREG_ARCH_VALUE_RANGE(0, 3) ) + IDREG_FIELD(SMIDR_EL1, RES0, 12, 1) IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) IDREG_END(SMIDR_EL1) =20 diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py index b4b548a6e2..86a2d2db84 100644 --- a/scripts/update-aarch64-cpu-sysreg-properties.py +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -78,9 +78,13 @@ def collect_fields(fieldset, bit_offset=3D0): =20 # Field Types leaf_types =3D ['Fields.Field', 'Fields.ConstantField', - 'Fields.EnumeratedField', 'Fields.Bitfield'] + 'Fields.EnumeratedField', 'Fields.Bitfield', 'Fields.Res= erved'] if _type in leaf_types: field_copy =3D fieldset.copy() + + if _type =3D=3D 'Fields.Reserved' and not field_copy.get('name'): + field_copy['name'] =3D fieldset.get('value', 'RES0') + if field_copy.get('rangeset'): new_ranges =3D [] for r in field_copy['rangeset']: @@ -92,7 +96,7 @@ def collect_fields(fieldset, bit_offset=3D0): return fields =20 # Traverse the hierarchy for other cases - for key in ['fields', 'values', 'fieldsets']: + for key in ['fields', 'values', 'fieldsets', 'constants']: for nested in fieldset.get(key, []): fields.extend(collect_fields(nested, bit_offset)) =20 @@ -210,43 +214,92 @@ def generate_sysreg_properties_from_registers_json(id= regs, raw_json_path): =20 final_output +=3D f"IDREG_START({reg_name})\n" =20 - unique_fields =3D {} + fieldset_variants =3D [] + for fieldset in register.get('fieldsets', []): + current_fieldset_fields =3D {} candidates =3D collect_fields(fieldset) + for val in candidates: - name =3D (val.get('name') or val.get('label', '')).strip() - if not name or "RESERVED" in name.upper(): + # reserved fields may leave the 'name' empty or set to Non= e and use + # value or label instead. Last '' garantees we fall back t= o an empty + # string and prevent the next line from cashing + raw_name =3D val.get('name') or val.get('label') or val.ge= t('value') or '' + name =3D raw_name.strip() + if not name: continue + + name_upper =3D name.upper() + + base_reserved =3D None + for r_type in ["RES0", "RES1", "RAZ", "RAO", "WI", "UNKNOW= N"]: + if r_type =3D=3D name_upper: + # Turn UNKNOWN to RES0 + base_reserved =3D "RES0" if r_type =3D=3D "UNKNOWN= " else r_type + break + + if base_reserved: + name =3D base_reserved + elif "RESERVED" in name_upper: + continue + for r in val.get('rangeset', []): lsb =3D int(r.get('start')) width =3D r.get('width') msb =3D lsb + int(width) - 1 =20 - # In json, some idregs may have multiple fielsets, dep= ending - # on some architecture configurations. If this happens= , pick - # up a single one with the largest msb (known one is C= CSIDR - # which is currently skipped) - if name not in unique_fields or msb > unique_fields[na= me]['msb']: - # extract enum values if any + if base_reserved: + # reserved fields have same name so append their l= sb + # to prevent fields from overriding each other + unique_key =3D f"{name}_{lsb}" + else: + unique_key =3D name + + # within the same fieldset we can have fields with the + # same name and different msbs. Keep the largest. + if unique_key not in current_fieldset_fields or \ + msb > current_fieldset_fields[unique_key]['msb']: enums =3D extract_field_enums(val) - unique_fields[name] =3D \ - {'lsb': lsb, 'msb': msb, 'width': width, 'enum= s': enums} + current_fieldset_fields[unique_key] =3D { + 'raw_name': name, + 'lsb': lsb, + 'msb': msb, + 'width': width, + 'enums': enums + } + + if current_fieldset_fields: + fieldset_variants.append(current_fieldset_fields) + + best_fieldset =3D {} + max_total_width =3D -1 + + # among several variants of a fieldset keep the largest one + for variant in fieldset_variants: + total_width =3D sum(f['width'] for f in variant.values()) + + if total_width > max_total_width: + max_total_width =3D total_width + best_fieldset =3D variant + + unique_fields =3D best_fieldset =20 # Sort by decreasing lsbs sorted_fields =3D sorted(unique_fields.items(), key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) =20 - for name, bits in sorted_fields: + for unique_key, bits in sorted_fields: enums_list =3D bits.get('enums', []) + clean_name =3D bits.get('raw_name', unique_key) =20 if enums_list: final_output +=3D format_field_enum( - reg_name, name, bits['lsb'], bits['width'], + reg_name, clean_name, bits['lsb'], bits['width'], merge_enum_ranges(enums_list)) else: final_output +=3D ( f" IDREG_FIELD({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n" + f"{clean_name}, {bits['lsb']}, {bits['width']})\n" ) =20 final_output +=3D f"IDREG_END({reg_name})\n" --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639506; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ILTUNRi9n3hKTKcl3Z/fNaw1glWurmvLUwAogbRUuz8=; b=g5pfwbwO9MG5Uh++Nb41WjHGB1lBHTK5Guoou2gF8uCPEBMa4SpoivQy+wnugHnEKjpwR5 Y2eHm46kIgmmZX71cHOhjc8LzfYfj5ZEMviHJIy3Cmu1juPyBKr/j4S0Se/yIYKzDhe/Ra ovdVuzi72xwD4Jle22M8cZzu92R4lYE= X-MC-Unique: 0mZ0OzNXPluz2j2HDN613Q-1 X-Mimecast-MFC-AGG-ID: 0mZ0OzNXPluz2j2HDN613Q_1791639501 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 09/26] target/arm/cpu_idregs: Generate tables for Arm64 ID registers and fields Date: Sat, 10 Oct 2026 15:36:13 +0200 Message-ID: <20261010133725.642498-10-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639704676158500 Content-Type: text/plain; charset="utf-8" From: Shaju Abraham Include cpu-idregs.h.inc multiple times with different definitions for the X-macros. This will generate tables for all Arm64 ID registers and their fields. Additionally, initialize the tables with all architecturally defined values. These tables will be consumed by the property layer in future patches. Co-authored-by: Khushit Shah Signed-off-by: Khushit Shah Signed-off-by: Shaju Abraham Signed-off-by: Eric Auger --- v9 -> v10 - fix tabs - initialize writable_mask - Use ValueRange instead of Value v7 -> v8 Adaptation after removal of struct ArmIdRegArchVal v5 -> v6 - restored support of enum values --- target/arm/cpu-idregs.c | 93 +++++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 2 files changed, 94 insertions(+) create mode 100644 target/arm/cpu-idregs.c diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c new file mode 100644 index 0000000000..122ef9c82d --- /dev/null +++ b/target/arm/cpu-idregs.c @@ -0,0 +1,93 @@ +/* + * ARM ID register field table. + * + * Builds the per-id-register field descriptor arrays and the global + * arm_idregs[] table. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu-idregs.h" + +/* + * Generate an array of architecturally defined value ranges for each field + * that has enum / ValueRange constraints. + */ + +#define IDREG_ARCH_VALUE_RANGE(_lo, _hi) { .lo =3D (_lo), .hi =3D (_hi) } + +#define IDREG_START(reg) +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_ENUM(reg, field, shift, length, ...) \ + static const ARM64SysRegArchValueRange reg##_##field##_arch_value_rang= es[] =3D { \ + __VA_ARGS__ = \ + }; + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_ENUM +#undef IDREG_ARCH_VALUE_RANGE + +/* generate an array of per-register ArmIdRegField[] descriptors */ + +#define IDREG_START(reg) \ + static ARM64SysRegField reg##_fields[] =3D { + +#define IDREG_END(reg) \ + }; + +#define IDREG_ARCH_VALUE_RANGE(_lo, _hi) + +#define IDREG_FIELD_ENUM(reg, field, _shift, _length, ...) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + .arch_value_ranges =3D reg##_##field##_arch_value_ranges, \ + .arch_value_ranges_count =3D \ + ARRAY_SIZE(reg##_##field##_arch_value_ranges), \ + }, + +#define IDREG_FIELD(reg, field, _shift, _length) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + }, + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_ENUM +#undef IDREG_ARCH_VALUE_RANGE + +/* generate an array of top level ID registers */ + +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_ENUM(reg, field, shift, length, ...) +#define IDREG_ARCH_VALUE_RANGE(_lo, _hi) + +#define IDREG_START(reg) \ + [reg##_IDX] =3D { \ + .name =3D #reg, \ + .index =3D reg##_IDX, \ + .fields =3D reg##_fields, \ + .fields_count =3D ARRAY_SIZE(reg##_fields), \ + .writable_mask =3D 0ULL, \ + }, + +ARM64SysReg arm64_id_regs[NUM_ID_IDX] =3D { +#include "cpu-idregs.h.inc" +}; diff --git a/target/arm/meson.build b/target/arm/meson.build index 0369f96b4c..384d90c530 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -30,6 +30,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_= true: files( =20 arm_common_system_ss.add(files( 'arm-qmp-cmds.c', + 'cpu-idregs.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639574; cv=none; d=zohomail.com; s=zohoarc; b=VWO3I/BHOivBugJZNhF907D1KP1YgMtJBFpM3eApl2E4ZgOuyO54xdlWi4aKMrEmknfBbUmFq41kGKNro7C7QezE7o+WZPWNkegidWPPDL+GeLCwGX609nO0ikDOBnfSvLVqitXSn9iZIoitvjMqed+6uMA56RoCV1lxOrKSoLQ= ARC-Message-Signature: i=1; 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Sat, 10 Oct 2026 13:38:26 +0000 (UTC) Received: from laptop.redhat.corp (headnet03.pony-001.prod.iad2.dc.redhat.com [10.2.32.114]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4422230000E5; Sat, 10 Oct 2026 13:38:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JIONCANj+MKk7AafgcfEQAY6C/fPP7uZSDIuv7Ano6A=; b=RLLcjWaa6xQPsnfqvHo1zSJZqsI/8HBehd7mk6mCAAlHwRrrBsigcEmpdAOBSNUcyiTHJH 95kUwMyRcARnfxqIsOQheXHgDJS271Z38PlIoIHQG/ktP4VopCe2EkFlOY/NNtyudGCRw6 VcZlmZ3qwW1Fe4kNci6lrA3IhTkEbk0= X-MC-Unique: t-MKfQVdMCGq7EYO8RpJwg-1 X-Mimecast-MFC-AGG-ID: t-MKfQVdMCGq7EYO8RpJwg_1791639506 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 10/26] target/arm/kvm: Retrieve writable ID reg map Date: Sat, 10 Oct 2026 15:36:14 +0200 Message-ID: <20261010133725.642498-11-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639575883158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Add a helper to retrieve the writable id reg bitmask. then retrieve the writable_mask array and dispatch it in the writable_map field of arm64_id_regs[] elements. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v9 -> v10: - removed if (idx < 0 || idx > ARRAY_SIZE(arm64_id_regs)) check - commit description cleanup v7 -> v8 - added kvm_enabled() v5 -> v6 - use arm64_id_regs[].writable_map - squashed 2 commits (helper + user) - removed stub --- target/arm/kvm.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9d68801c26..2e68130611 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -28,6 +28,7 @@ #include "kvm_arm.h" #include "cpu.h" #include "cpu-sysregs.h" +#include "cpu-idregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -51,6 +52,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = =3D { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; +static bool writable_map_dispatched; =20 /** * ARMHostCPUFeatures: information about the host CPU (identified @@ -312,6 +314,21 @@ static uint32_t kvm_arm_sve_get_vls(int fd) return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); } =20 +static int kvm_feature_idx_to_idregs_idx(int kidx) +{ + int op1, crm, op2; + ARMSysRegs sysreg; + + op1 =3D kidx / 64; + if (op1 =3D=3D 2) { + op1 =3D 3; + } + crm =3D (kidx % 64) / 8; + op2 =3D kidx % 8; + sysreg =3D ENCODE_ID_REG(3, op1, 0, crm, op2); + return get_sysreg_idx(sysreg); +} + static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -523,9 +540,47 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) ahcf->features =3D features; } =20 +static int kvm_arm_get_writable_id_regs(uint64_t *idregmap) +{ + int cap_writable_id_regs; + struct reg_mask_range range =3D { + .range =3D KVM_ARM_FEATURE_ID_RANGE, + .reserved =3D {0}, + .addr =3D (uint64_t)idregmap, + }; + + cap_writable_id_regs =3D + kvm_check_extension(kvm_state, KVM_CAP_ARM_SUPPORTED_REG_MASK_RANG= ES); + + if (!cap_writable_id_regs || + !(cap_writable_id_regs & (1 << KVM_ARM_FEATURE_ID_RANGE))) { + return -ENOSYS; + } + + return kvm_vm_ioctl(kvm_state, KVM_ARM_GET_REG_WRITABLE_MASKS, &range); +} + void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; + uint64_t *writable_map; + + writable_map =3D g_new(uint64_t, KVM_ARM_FEATURE_ID_RANGE_SIZE); + + if (kvm_enabled() && !writable_map_dispatched && + !kvm_arm_get_writable_id_regs(writable_map)) { + for (int i =3D 0; i < KVM_ARM_FEATURE_ID_RANGE_SIZE; i++) { + uint64_t mask =3D writable_map[i]; + + if (mask) { + int idx =3D kvm_feature_idx_to_idregs_idx(i); + + arm64_id_regs[idx].writable_mask =3D mask; + } + } + writable_map_dispatched =3D true; + } + g_free(writable_map); =20 if (!arm_host_cpu_features.dtb_compatible) { kvm_arm_get_host_cpu_features(&arm_host_cpu_features); --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=vbBNwYmdqWnLEJ+d5lcNwGr8+ZO1ZyY8BY+i6F3iv7s=; b=YWpnpqovq5MA8qFcL0XcqaBF5xCdKI81bpA4B65LFPmx/24Xnj9k8DkcwcV8kqPzhdHD6z 74upmcfHx9cZN9BgTsayhtbG8ghirZJe6lgBvL6UOqlkBI5pw5mL2kNuGqlO9DuDNeo3dY e5roAofjTzUEh5CqVjR0bKH0fcvyg7s= X-MC-Unique: uB2iRn8UPheDRXe62kqzeA-1 X-Mimecast-MFC-AGG-ID: uB2iRn8UPheDRXe62kqzeA_1791639511 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 11/26] hw/arm/virt: Make sure virt_get_caches() keeps on reading CLIDR_EL1 as 0 Date: Sat, 10 Oct 2026 15:36:15 +0200 Message-ID: <20261010133725.642498-12-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639541353158500 Content-Type: text/plain; charset="utf-8" In KVM mode, virt_get_caches() currently gets a zero value for the CLIDR_EL1 register. This is due to the fact CLIDR is never read from host. This is a bug. Soon we will initialize all writable isar.idreg[] from host and this includes CLIDR_EL1. However we cannot directly fix the initialization, first because it would change the way the guest is exposed caches in DT/ACPI descriptions and because some host values would be rejected by the current QEMU code, expecially in the case host has a unified L1 cache which is currently not supported and triggers the following errod: "Unified type is not implemented at level 1" error. So this issue will be fixed separately. Signed-off-by: Eric Auger Reviewed-by: Khushit Shah --- v9 -> v10 - add a comment explaining why we oveeride the clidr value --- hw/arm/virt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9d192515d8..f9a7beb584 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -338,6 +338,17 @@ unsigned int virt_get_caches(const VirtMachineState *v= ms, CPUCoreCaches *caches) ARMISARegisters *isar =3D &armcpu->isar; uint32_t clidr =3D GET_IDREG(isar, CLIDR); =20 + /* + * Commit f669de70011 ("hw/arm/virt: add cache hierarchy to device tre= e") + * read the CLIDR value from the isar array but in KVM mode, this index + * was never initialized from host. Now we want to initialize all ID + * registers * from host and until this gets fixed, we need to override + * clidr to 0 to keep the compatibility. + */ + if (kvm_enabled()) { + clidr =3D 0; + } + for (int cache_level =3D 1; cache_level <=3D CLIDR_CTYPE_MAX_CACHE_LEV= EL; cache_level++) { uint8_t ctype =3D --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639727; cv=none; d=zohomail.com; s=zohoarc; b=HIL+UrTb9ucmkT2joknWNnThxTfIipeckWHBE4/XbjfU+DkaF/AutyeLQX1atHHcEq8ImKRsVslMdpx00sYA+2nToJZPhbyJw8YpEOpx2omaWkgmwUwPT05dfJFKCgu8RFXZM4gtMbrnx1QtHzvQm7hLL+0nJenP8ByggiLDsBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639727; 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Sat, 10 Oct 2026 13:38:35 +0000 (UTC) Received: from laptop.redhat.corp (headnet03.pony-001.prod.iad2.dc.redhat.com [10.2.32.114]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4D61230000E5; Sat, 10 Oct 2026 13:38:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639521; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=InNpy/fUH23ypsNkCh7xC1ndZPiRh9XsgEv/1J5P96c=; b=G2oxcbgqMYN9AkqcKv+XKBMO4jp5PuRIGq75A7apGTYcl99/YnTiiTyjjGdGwcTz9c3T+H bnWFC4zxOGR9pknbUgYfjEQ7J3ADv8f0pAp4s5e3wKm8vpRpFJlIazuvm5RqkIQSmUeLoS sJyWm8uH4kxUbNyEmue5WGcKmnViwZ4= X-MC-Unique: DUR5OHDDMySzgg9fJ2vOaw-1 X-Mimecast-MFC-AGG-ID: DUR5OHDDMySzgg9fJ2vOaw_1791639515 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 12/26] arm/kvm: Initialize isar.idregs[] with all writable host ID regs Date: Sat, 10 Oct 2026 15:36:16 +0200 Message-ID: <20261010133725.642498-13-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639729050158500 Content-Type: text/plain; charset="utf-8" kvm_arm_get_host_cpu_features() already retrieves the values of some host id registers to analyze the available vcpu features. Eventually we want to be able to allow the user to change the value of writable ID reg fields. So we need to store the initial value of all writable ID regs into isar.idregs[]. Introduce a new get_host_cpu_idregs() helper that populates isar.idregs[] and call it from kvm_arm_get_host_cpu_features. This patch has no impact on cpreg values. isar.idregs[] is only used as a temporary storage for register values to be updated in place later. Also it does not handle the writeback of isar.idregs[] into cpreg value list after user update. This will be handled separately. Note the host values are retrieved from the scratch vcpu initialized with all the available capabilities exposed by KVM, independently on the final vcpu features made by the user through the legacy composite options such as sve, pauth, virtualization, ... At the moment, the only caller sets writable to true. Named vcpu models will use the writable=3Dfalse mode. Note this will require some extra handling for ID regs that cannot be read from KVM. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v9 -> v10: - get rid of spurious kvm_arm_writable_idregs_to_cpreg_list trace point - add a writable parameter to get_host_cpu_idregs - some code cleanup v8 -> v9: - improve the commit msg. Only initialize in this patch and move the write back to cpreg value list in a different patch. - Do not hack CLIDR here. The correct way to fix that temporarily is to do that in the machine instead. v7 -> v8 - fix indent and added Khushit's R-b v6 -> v7 - remove vcpu from prototypes (Khushit) v5 -> v6 - do not check writable_map anymore --- target/arm/kvm.c | 44 ++++++++++++++++++++++++++++++++++++++++- target/arm/trace-events | 1 + 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2e68130611..ac4f307276 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -43,6 +43,7 @@ #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" #include "migration/blocker.h" +#include "cpu-idregs.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_INFO(DEVICE_CTRL), @@ -329,7 +330,45 @@ static int kvm_feature_idx_to_idregs_idx(int kidx) return get_sysreg_idx(sysreg); } =20 -static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +/* + * get_host_cpu_idregs: Read all the ID register values from KVM + * vcpu fd and populate @ahcf->isar.idregs[] with those values + * + * Need to be called once the writable mask has been populated + * if @writable is set + * + * @fd: vcpu fd + * @ahcf: ARMHostCPUFeatures whose @ahcf->isar.idregs[] will be + * populated + * @writable: if set, only writable ID regs are read + */ +static int get_host_cpu_idregs(int fd, ARMHostCPUFeatures *ahcf, bool writ= able) +{ + for (int i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D id_register_sysreg[i]; + uint64_t *reg; + int ret; + + if (writable && !sysregdesc->writable_mask) { + continue; + } + + reg =3D &ahcf->isar.idregs[i]; + ret =3D read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + return ret; + } + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + } + return 0; +} + +static void +kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -415,6 +454,9 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64= only */ err =3D 0; } else { + /* Make sure all writable ID reg values are initialized */ + err |=3D get_host_cpu_idregs(fd, ahcf, true); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); diff --git a/target/arm/trace-events b/target/arm/trace-events index 8502fb3265..8c7faf57c7 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639524; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hsy8Wb76UKgAIrb0kzSti5SOHbp3tE79r/MLWon3/vk=; b=L+KTcLpXRd/nwNV+jYi75WOrgYKtbweBUivoOVegoDdayZDurmUegYa2IXOvcwYa4wgSyw H5PSvmRXPYMzduRyjWtusu9HdJaYoqBcSjSxbvU4PHb5f3UdaU6QC+57/KEk+7WCRgPj/6 eeZerA2sAQLza+PpbF1LtENyWairofw= X-MC-Unique: PTvbiei3Nfir4CnuhCL_GA-1 X-Mimecast-MFC-AGG-ID: PTvbiei3Nfir4CnuhCL_GA_1791639520 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 13/26] target/arm/cpu64: Add properties for writable IDReg fields Date: Sat, 10 Oct 2026 15:36:17 +0200 Message-ID: <20261010133725.642498-14-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639724985158501 For KVM vcpu models, we add properties for all writable ID reg fields. This relies on the idreg writable mask retrieved from KVM, which is matched aginst the register description found in target/arm/cpu-idregs.h.inc. The code is prepared to extend this capability to all ID register fields independently on their writability. This will be needed for named vcpu models which may want to relax some values to the host supported one. REVIDR_EL1 and AIDR_EL1 are writable but they do not expose any field. So they will need to be handled separately. The setter and getter are not yet implemented and currently return an error. Note in the future, other acceleration types may benefit from those properties. Signed-off-by: Eric Auger --- v9 -> v10 - instead of parsing the writable mask, scroll through the fields but still do some sanity checks. Add the writable param - move the code to cpu64.c Do not pass any ARM64SysReg handle anymore. Rename the functions v7 -> v8 - scratch the '!' in the error_setg - addapt to the removal of struct ArmIdRegArchVal v5 -> v6 - for enum values, check against value value when setting the prop - do not check writable_map flag anymore v4 -> v5: - free prop_name - check cpu->writable_map as a preamble in kvm_arm_expose_idreg_properties --- target/arm/cpu64.c | 113 ++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 6 +++ 2 files changed, 119 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 64103df0a7..b1738c9be3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -37,6 +37,8 @@ #include "hw/core/qdev-properties.h" #include "internals.h" #include "cpu-features.h" +#include "cpu-idregs.h" +#include "trace.h" =20 /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -798,6 +800,116 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *= cpu) arm_register_cpreg_mig_tolerance(cpu, KVM_REG_ARM_FW_FEAT_BMAP_REG(3), UINT64_MAX, 0, ToleranceOnlySrcTestVa= lue); } + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + error_setg(errp, "%s setter not yet implemented", name); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + error_setg(errp, "%s getter not yet implemented", name); +} + +/** + * aarch64_add_idreg_properties: Add SYSREG__ properties + * for named fields of an ID register + * + * @obj: CPU object + * @reg: Description of the sysreg + * @writable_only: if set, add a property only for writable fields, + * otherwise, add properties unconditionnally + * + * Independently on @writable_only, always check the consistency between + * writable_mask and register fields description: if a field is writable + * make sure all its bits are writable. Also make sure only named fields + * are writable. + */ +static int +aarch64_add_one_idreg_properties(Object *obj, ARM64SysReg *reg, + bool writable_only) +{ + uint64_t map =3D reg->writable_mask; + int nb_sysreg_props =3D 0; + + for (int i =3D 0; i < reg->fields_count; i++) { + ARM64SysRegField *field =3D ®->fields[i]; + int lower =3D field->shift; + int length =3D field->length; + int upper =3D lower + length - 1; + uint64_t field_writable_mask =3D extract64(map, lower, length); + uint64_t field_mask =3D MAKE_64BIT_MASK(lower, length); + char *prop_name; + + /* skip reserved fields, but still account them in writable_mask */ + if (g_str_equal(field->name, "RES0") || + g_str_equal(field->name, "RES1") || + g_str_equal(field->name, "RAZ")) { + map &=3D ~field_mask; + continue; + } + + if (field_writable_mask && + field_writable_mask !=3D MAKE_64BIT_MASK(0, length)) { + /* only a part of the field is writable, this should never hap= pen */ + error_report("field %s is not fully writable! (0x%"PRIx64")", + field->name, field_writable_mask); + } + map =3D map & ~field_mask; + + if (writable_only && !field_writable_mask) { + continue; + } + + prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + trace_add_idreg_property(prop_name, lower, upper, field_writable_m= ask); + g_free(prop_name); + nb_sysreg_props++; + } + if (map) { + error_report("%s has writable bits which do not match " + "any named field! (0x%" PRIx64")", reg->name, map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + + +/** + * aarch64_add_idreg_properties: + * + * Add SYSREG__ properties for every IDReg fields + * + * @cpu: cpu the properties are attached to + *=C2=A0@writable_only: if set, properties are added only if the field is + * writable. Otherwise, added unconditionnally + */ +static void aarch64_add_idreg_properties(Object *obj, bool writable_only) +{ + for (int i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + + if (writable_only && !sysregdesc->writable_mask) { + continue; + } + /* + * special case REVIDR_EL1 and AIDR_EL1 which are writable but + * do not expose named fields. They will need to be handled + * separately + */ + if (!strcmp(sysregdesc->name, "REVIDR_EL1") || + !strcmp(sysregdesc->name, "AIDR_EL1")) { + continue; + } + aarch64_add_one_idreg_properties(obj, sysregdesc, true); + } +} #endif =20 void aarch64_host_initfn(Object *obj) @@ -815,6 +927,7 @@ void aarch64_host_initfn(Object *obj) kvm_arm_set_cpreg_mig_tolerances(cpu); kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); + aarch64_add_idreg_properties(obj, true); #elif defined(CONFIG_HVF) hvf_arm_set_cpu_features_from_host(cpu); #elif defined(CONFIG_WHPX) diff --git a/target/arm/trace-events b/target/arm/trace-events index 8c7faf57c7..ddc79eb666 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -19,6 +19,12 @@ get_host_cpu_idregs(const char *name, uint64_t value) "s= cratch vcpu host value f arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 arm_emulate_firmware_reset(uint64_t mp_aff, unsigned target_el) "cpu %" PR= Iu64 " @EL%u" =20 +# cpu64.c +add_idreg_property(const char* name, int lower, int upper, bool writable) = "%s [%d:%d] writable=3D%d" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" + # arm-powerctl.c arm_powerctl_set_cpu_on(uint64_t mp_aff, unsigned target_el, const char *m= ode, uint64_t entry, uint64_t context_id) "cpu %" PRIu64 " (EL %u, %s) @ 0x= %" PRIx64 " with R0 =3D 0x%" PRIx64 arm_powerctl_set_cpu_on_and_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639714; cv=none; d=zohomail.com; s=zohoarc; b=k2NMSxQnog6x70l3SlrdfuWwFCKWW6YfzQR3LgveSTtce2yANMniEgaPgyUiLcsxT/mDqeaGnvgPLIQ1Dj1b71Mw1QxM/5C+s1UgxjujB4Vh3WX8XQvB3o+4tQ7BRs3wV0NNqRREeGqX9OVvQTeyXUbAD7okiTiOtHRm+PkQORE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639714; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3fgklMGCKXzzfl+Y/I7jaLT7gfuLtYlF+j5mQXWNrTY=; b=Re84iIHStWOm12LTG5t0f2v0M2NnstnkzyQlJlzpglFuUeYgKh2KNIxbZJ2JLV5Jvz/c5mjmmlQYgp26KKhR1Pb3l3vO6cQWJrXHnHm9C594AoSYXUQJ49HXL/q+4MqeNpl0itCSKoTX5LLJ6rK+IsXrn3vVAd+GxGqpbOO4a5Y= ARC-Authentication-Results: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639530; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3fgklMGCKXzzfl+Y/I7jaLT7gfuLtYlF+j5mQXWNrTY=; b=UzxAUyFp/qqqpdtk7H17sZvDODL6aki+F+UF2UIw4MhLUTRg68jUqpy2PSaAiEQkoP8fWP RVcppzjRalTY2/F356F09dJx4+8ZvwZ0Qocd94dzLKx6tSQDQOVPnllcGWCnNPq4Sd3Hme YRsyvG03VxlN3kRPM0XDPYhzS9tQ0c8= X-MC-Unique: rTx9SFtgPb2e8k1qIShEPQ-1 X-Mimecast-MFC-AGG-ID: rTx9SFtgPb2e8k1qIShEPQ_1791639525 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 14/26] target/arm/kvm: Implement SYSREG property setter and getter Date: Sat, 10 Oct 2026 15:36:18 +0200 Message-ID: <20261010133725.642498-15-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639714741158500 Content-Type: text/plain; charset="utf-8" When the setter is called, the final vcpu is not created yet. Applying the override on vcpu.isar initialized with the max scratch vcpu would not be correct because the final vcpu may have some features turned off (for instance virtualization) while the scratch vcpu features all available ones. So we need to postpone the actual override until the final vcpu has been initialized. Set values are recorded in a hash table and will be applied to the guest in a subsequent patch. At this point the only checks that can be done on the input value are checking against field length and arch enum value if any. With regards to the getter, if the sysreg prop was set, we return the set value, otherwise, we return the value in cpu->isar.idregs[]. Signed-off-by: Eric Auger Reviewed-by: Khushit Shah --- v9 -> v10: - renamed MAKE_IDREG_KEY into IDREG_FIELD_KEY - rebase on new implementation in cpu64.c --- target/arm/cpu.h | 2 ++ target/arm/cpu.c | 5 ++-- target/arm/cpu64.c | 65 ++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 68 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 639be0713e..bef100c02c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -968,6 +968,8 @@ struct ArchCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; =20 + GHashTable *sysreg_props; + DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; DynamicGDBFeatureInfo dyn_smereg_feature; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bee74c0f94..d2755d77ca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1238,8 +1238,8 @@ static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 - cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, - NULL, g_free); + cpu->cp_regs =3D g_hash_table_new(g_direct_hash, g_direct_equal); + cpu->sysreg_props =3D g_hash_table_new(g_direct_hash, g_direct_equal); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); @@ -1739,6 +1739,7 @@ static void arm_cpu_finalizefn(Object *obj) ARMCPRegMigTolerance *t, *n; =20 g_hash_table_destroy(cpu->cp_regs); + g_hash_table_destroy(cpu->sysreg_props); =20 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { QLIST_REMOVE(hook, node); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b1738c9be3..9662608675 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -801,18 +801,79 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *= cpu) UINT64_MAX, 0, ToleranceOnlySrcTestVa= lue); } =20 +#define IDREG_FIELD_KEY(reg_idx, field_shift) \ + (((uint64_t)(reg_idx) << 8) | ((uint64_t)(field_shift) & 0xFF)) + static void set_sysreg_prop(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - error_setg(errp, "%s setter not yet implemented", name); + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + int index =3D field->index; + int lower =3D field->shift; + int length =3D field->length; + uint64_t key, value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1ULL << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%" PRIx64 ") exceeds length of " + "field (%d)!", name, value, length); + return; + } + + if (field->arch_vals) { + /* this field has some enum values */ + for (int i =3D 0; i < field->arch_vals_count; i++) { + if (value =3D=3D field->arch_vals[i]) { + goto valid; + } + } + error_setg(errp, + "idreg %s set value (0x%" PRIx64 ") does not match any " + "arch valid enum value", name, value); + return; + } + +valid: + + key =3D IDREG_FIELD_KEY(index, lower); + g_hash_table_insert(cpu->sysreg_props, GUINT_TO_POINTER(key), + GUINT_TO_POINTER(value)); } =20 static void get_sysreg_prop(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - error_setg(errp, "%s getter not yet implemented", name); + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + int index =3D field->index; + int lower =3D field->shift; + int length =3D field->length; + gpointer value_ptr; + uint64_t value; + uint64_t key =3D IDREG_FIELD_KEY(index, lower); + gboolean exists; + + exists =3D g_hash_table_lookup_extended(cpu->sysreg_props, + GUINT_TO_POINTER(key), NULL, + &value_ptr); + if (exists) { + value =3D GPOINTER_TO_UINT(value_ptr); + } else { + uint64_t mask =3D MAKE_64BIT_MASK(lower, length); + uint64_t *idregs =3D cpu->isar.idregs; + + value =3D (idregs[index] & mask) >> lower; + } + + visit_type_uint64(v, name, &value, errp); + trace_get_sysreg_prop(name, value); } =20 /** --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Sat, 10 Oct 2026 13:38:50 +0000 (UTC) Received: from laptop.redhat.corp (headnet03.pony-001.prod.iad2.dc.redhat.com [10.2.32.114]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 00FCD30000E5; Sat, 10 Oct 2026 13:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639536; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rJJ9866SG6H+ss4j/yi5NJRaRLchsKWeX66gkZZoSAY=; b=SPKubFUoL9IGmXtEzCEtIKYxqDzAb1GmgOPmiiAIN6W2A3ybadjr2rGoigeJFV7wD/kJDh u5LsJFA85gj+ioqLn1R9ADr+vQGAxO6cA9pS0aJns0YDATeNYRgXeAAS6ap6zPFNqpBk+j zXdvDjK3ZNzHz9nIuYsl/N+aGxc1HxM= X-MC-Unique: IlDwscnDO6S4RsQQdcxOeA-1 X-Mimecast-MFC-AGG-ID: IlDwscnDO6S4RsQQdcxOeA_1791639530 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 15/26] target/arm/kvm: Let kvm_arm_init_cpreg_list propagate an error handle Date: Sat, 10 Oct 2026 15:36:19 +0200 Message-ID: <20261010133725.642498-16-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639808850158500 Content-Type: text/plain; charset="utf-8" Subsequent patch will add an error handle to kvm_arch_init_vcpu(). So all errors must come with an error handle. kvm_arm_init_cpreg_list does not propogate any, add this capability. Signed-off-by: Eric Auger --- target/arm/kvm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ac4f307276..f2b79c0a34 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -962,6 +962,7 @@ static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t r= egidx) /** * kvm_arm_init_cpreg_list: * @cpu: ARMCPU + * @errp: pointer to Error* for error reporting * * Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away @@ -969,22 +970,27 @@ static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t= regidx) * * Returns: 0 if success, else < 0 error code */ -static int kvm_arm_init_cpreg_list(ARMCPU *cpu) +static int kvm_arm_init_cpreg_list(ARMCPU *cpu, Error **errp) { struct kvm_reg_list rl; - struct kvm_reg_list *rlp; + struct kvm_reg_list *rlp =3D NULL; int i, ret, arraylen; CPUState *cs =3D CPU(cpu); =20 rl.n =3D 0; ret =3D kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); if (ret !=3D -E2BIG) { + if (ret < 0) { + error_setg_errno(errp, -ret, + "failed to get KVM register list size"); + } return ret; } rlp =3D g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)= ); rlp->n =3D rl.n; ret =3D kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); if (ret) { + error_setg_errno(errp, -ret, "failed to get KVM register list"); goto out; } /* Sort the list we get back from the kernel, since cpreg_tuples @@ -1001,7 +1007,7 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu) case KVM_REG_SIZE_U64: break; default: - fprintf(stderr, "Can't handle size of register in kernel list\= n"); + error_setg(errp, "Can't handle size of register in kernel list= "); ret =3D -EINVAL; goto out; } @@ -1027,7 +1033,7 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu) /* Shouldn't happen unless kernel is inconsistent about * what registers exist. */ - fprintf(stderr, "Initial read of kernel register state failed\n"); + error_setg(errp, "Initial read of kernel register state failed"); ret =3D -EINVAL; goto out; } @@ -2196,7 +2202,7 @@ int kvm_arch_init_vcpu(CPUState *cs) SET_IDREG(&cpu->isar, MPIDR, mpidr); cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - return kvm_arm_init_cpreg_list(cpu); + return kvm_arm_init_cpreg_list(cpu, errp); } =20 int kvm_arch_destroy_vcpu(CPUState *cs) --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639642; cv=none; d=zohomail.com; s=zohoarc; b=jTdbMMM2uTz0xP7GhByqz8Cv3LivAd2CP8y8+T/5MncKQMUoKKGDkC3AnHL2H0ZRNEibbgiG0J9tnbYQEUXMZ4vFXknG+vVqVxzDDo0NopXEguqAWqasSluwRg1iJ77ANTxG+nwikEH602ItqskRP01Bx4xiVc5vIGMYYsVDzZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639642; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sat, 10 Oct 2026 13:38:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CK2GlJKkJbYvE/Gn79cZJFY9O5WDQZCgKh0S+ObHI8s=; b=cgcSrjHmKaV5YswO5avD8mN5JuKWW40Y4+ngXkOg/frZEZSLdI/nnK0uhw+tVHn/bzpySi HGy/3uPnhW9ooc4IENsWaVbD7AI6cNgJWbaAXuUWEXWJ40PfVvcQ6+9npTbWg1LdCv1Jw8 /+l9i2vUI8khHZ2bzufbjCKTJkJG8cg= X-MC-Unique: 8j3PY1W7N1q75mvzP-GnTg-1 X-Mimecast-MFC-AGG-ID: 8j3PY1W7N1q75mvzP-GnTg_1791639535 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 16/26] target/arm/kvm: Pass an Error handle to kvm_arch_init_vcpu Date: Sat, 10 Oct 2026 15:36:20 +0200 Message-ID: <20261010133725.642498-17-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The 2 callers of kvm_arch_init_vcpu(), namely kvm_rebind_vcpus() and kvm_init_vcpu() are passed an Error handle. So it is a pity not using it in kvm_arch_init_vcpu(). Also some functions called within kvm_arch_init_vcpu() could get benefit from it, especially on ARM. This will happen in subsequent patches. Signed-off-by: Eric Auger --- include/system/kvm.h | 2 +- accel/kvm/kvm-all.c | 15 +++++++-------- target/arm/kvm.c | 14 +++++++++----- target/i386/kvm/kvm.c | 22 ++++++++++++---------- target/loongarch/kvm/kvm.c | 27 +++++++++------------------ target/ppc/kvm.c | 6 +++--- target/riscv/kvm/kvm-cpu.c | 3 ++- target/s390x/kvm/kvm.c | 2 +- 8 files changed, 44 insertions(+), 47 deletions(-) diff --git a/include/system/kvm.h b/include/system/kvm.h index d29624034c..26d55cc699 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -358,7 +358,7 @@ int kvm_arch_get_default_type(MachineState *ms); int kvm_arch_init(MachineState *ms, KVMState *s); =20 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp); -int kvm_arch_init_vcpu(CPUState *cpu); +int kvm_arch_init_vcpu(CPUState *cpu, Error **errp); int kvm_arch_destroy_vcpu(CPUState *cpu); =20 #ifdef TARGET_KVM_HAVE_RESET_PARKED_VCPU diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index db52bb9ffb..7c0d12e4f1 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -493,11 +493,11 @@ static int kvm_rebind_vcpus(Error **errp) } } =20 - ret =3D kvm_arch_init_vcpu(cpu); + ret =3D kvm_arch_init_vcpu(cpu, errp); if (ret < 0) { - error_setg_errno(errp, -ret, - "kvm_init_vcpu: kvm_arch_init_vcpu failed (%l= u)", - vcpu_id); + error_prepend(errp, + "kvm_init_vcpu: kvm_arch_init_vcpu failed (%lu)", + vcpu_id); } =20 close(cpu->kvm_vcpu_stats_fd); @@ -740,11 +740,10 @@ int kvm_init_vcpu(CPUState *cpu, Error **errp) } } =20 - ret =3D kvm_arch_init_vcpu(cpu); + ret =3D kvm_arch_init_vcpu(cpu, errp); if (ret < 0) { - error_setg_errno(errp, -ret, - "kvm_init_vcpu: kvm_arch_init_vcpu failed (%lu)", - kvm_arch_vcpu_id(cpu)); + error_prepend(errp, "kvm_init_vcpu: kvm_arch_init_vcpu failed (%lu= )", + kvm_arch_vcpu_id(cpu)); } cpu->kvm_vcpu_stats_fd =3D kvm_vcpu_ioctl(cpu, KVM_GET_STATS_FD, NULL); =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f2b79c0a34..6c15d8522f 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2105,7 +2105,7 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **e= rrp) return 0; } =20 -int kvm_arch_init_vcpu(CPUState *cs) +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { int ret; uint64_t mpidr; @@ -2114,7 +2114,7 @@ int kvm_arch_init_vcpu(CPUState *cs) uint64_t psciver; =20 if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE) { - error_report("KVM is not supported for this guest CPU type"); + error_setg(errp, "KVM is not supported for this guest CPU type"); return -EINVAL; } =20 @@ -2153,16 +2153,19 @@ int kvm_arch_init_vcpu(CPUState *cs) /* Do KVM_ARM_VCPU_INIT ioctl */ ret =3D kvm_arm_vcpu_init(cpu); if (ret) { + error_setg(errp, "failed kvm_arm_vcpu_init (%d)", ret); return ret; } =20 if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D kvm_arm_sve_set_vls(cpu); if (ret) { + error_setg(errp, "failed kvm_arm_sve_set_vls (%d)", ret); return ret; } ret =3D kvm_arm_vcpu_finalize(cpu, KVM_ARM_VCPU_SVE); if (ret) { + error_setg(errp, "failed kvm_arm_vcpu_finalize (%d)", ret); return ret; } } @@ -2171,11 +2174,11 @@ int kvm_arch_init_vcpu(CPUState *cs) psciver =3D cpu->psci_version; ret =3D kvm_set_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver); if (ret) { - error_report("KVM in this kernel does not support PSCI version= %d.%d", + error_setg(errp, "KVM in this kernel does not support PSCI ver= sion %d.%d", (int) PSCI_VERSION_MAJOR(psciver), (int) PSCI_VERSION_MINOR(psciver)); - error_printf("Consider setting the kvm-psci-version property o= n the " - "migration source.\n"); + error_append_hint(errp, "Consider setting the kvm-psci-version= property " + "on the migration source.\n"); return ret; } } @@ -2197,6 +2200,7 @@ int kvm_arch_init_vcpu(CPUState *cs) */ ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); if (ret) { + error_setg(errp, "failed retrieving PMIDR value"); return ret; } SET_IDREG(&cpu->isar, MPIDR, mpidr); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a72b6e6b74..0f5b848e48 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2218,7 +2218,7 @@ static void kvm_init_pmu_info(struct kvm_cpuid2 *cpui= d, X86CPU *cpu) } } =20 -int kvm_arch_init_vcpu(CPUState *cs) +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { struct { struct kvm_cpuid2 cpuid; @@ -2240,12 +2240,12 @@ int kvm_arch_init_vcpu(CPUState *cs) int kvm_base =3D KVM_CPUID_SIGNATURE; int max_nested_state_len; int r; - Error *local_err =3D NULL; =20 if (current_machine->cgs) { r =3D x86_confidential_guest_check_features( X86_CONFIDENTIAL_GUEST(current_machine->cgs), cs); if (r < 0) { + error_setg(errp, "failed x86_confidential_guest_check_features= (%d)", r); return r; } } @@ -2258,6 +2258,7 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 r =3D kvm_arch_set_tsc_khz(cs); if (r < 0) { + error_setg(errp, "failed setting tsc_khz (%d)", r); return r; } =20 @@ -2285,14 +2286,14 @@ int kvm_arch_init_vcpu(CPUState *cs) * can still proceed and check/expand Hyper-V enlightenments here so l= egacy * behavior is preserved. */ - if (!kvm_hyperv_expand_features(cpu, &local_err)) { - error_report_err(local_err); + if (!kvm_hyperv_expand_features(cpu, errp)) { return -ENOSYS; } =20 if (hyperv_enabled(cpu)) { r =3D hyperv_init_vcpu(cpu); if (r) { + error_setg(errp, "failed hyperv_init_vcpu (%d)", r); return r; } =20 @@ -2371,6 +2372,7 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 r =3D kvm_xen_init_vcpu(cs); if (r) { + error_setg(errp, "failed kvm_xen_init_vcpu (%d)", r); return r; } =20 @@ -2419,12 +2421,12 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 ret =3D kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); if (ret < 0) { - fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret= )); + error_setg(errp, "kvm_get_mce_cap_supported: %s", strerror(-re= t)); return ret; } =20 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { - error_report("kvm: Unsupported MCE bank count (QEMU =3D %d, KV= M =3D %d)", + error_setg(errp, "kvm: Unsupported MCE bank count (QEMU =3D %d= , KVM =3D %d)", (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); return -ENOTSUP; } @@ -2432,7 +2434,7 @@ int kvm_arch_init_vcpu(CPUState *cs) unsupported_caps =3D env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK= ); if (unsupported_caps) { if (unsupported_caps & MCG_LMCE_P) { - error_report("kvm: LMCE not supported"); + error_setg(errp, "kvm: LMCE not supported"); return -ENOTSUP; } warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64, @@ -2442,7 +2444,7 @@ int kvm_arch_init_vcpu(CPUState *cs) env->mcg_cap &=3D mcg_cap | MCG_CAP_BANKS_MASK; ret =3D kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); if (ret < 0) { - fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); + error_setg(errp, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); return ret; } } @@ -2470,9 +2472,8 @@ int kvm_arch_init_vcpu(CPUState *cs) error_setg(&invtsc_mig_blocker, "State blocked by non-migratable CPU device" " (invtsc flag)"); - r =3D migrate_add_blocker(&invtsc_mig_blocker, &local_err); + r =3D migrate_add_blocker(&invtsc_mig_blocker, errp); if (r < 0) { - error_report_err(local_err); return r; } } @@ -2501,6 +2502,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpuid_data.cpuid.padding =3D 0; r =3D kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); if (r) { + error_setg(errp, "KVM_SET_CPUID2 failed (%m)"); goto fail; } kvm_init_xsave(env); diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 941142305e..d5bf3a2d83 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -1299,11 +1299,10 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error *= *errp) return 0; } =20 -int kvm_arch_init_vcpu(CPUState *cs) +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { uint64_t val; int ret; - Error *local_err =3D NULL; LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); =20 cpu->vmsentry =3D qemu_add_vm_change_state_handler( @@ -1313,51 +1312,43 @@ int kvm_arch_init_vcpu(CPUState *cs) brk_insn =3D val; } =20 - ret =3D kvm_cpu_check_lsx(cs, &local_err); + ret =3D kvm_cpu_check_lsx(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_lasx(cs, &local_err); + ret =3D kvm_cpu_check_lasx(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_lbt(cs, &local_err); + ret =3D kvm_cpu_check_lbt(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_pmu(cs, &local_err); + ret =3D kvm_cpu_check_pmu(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_pv_features(cs, &local_err); + ret =3D kvm_cpu_check_pv_features(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_ptw(cs, &local_err); + ret =3D kvm_cpu_check_ptw(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_msgint(cs, &local_err); + ret =3D kvm_cpu_check_msgint(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 - ret =3D kvm_cpu_check_misc_v1_1(cs, &local_err); + ret =3D kvm_cpu_check_misc_v1_1(cs, errp); if (ret < 0) { - error_report_err(local_err); return ret; } =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 8e89a6c665..d90e904f90 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -484,7 +484,7 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **err= p) return 0; } =20 -int kvm_arch_init_vcpu(CPUState *cs) +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *cenv =3D &cpu->env; @@ -494,8 +494,8 @@ int kvm_arch_init_vcpu(CPUState *cs) ret =3D kvm_arch_sync_sregs(cpu); if (ret) { if (ret =3D=3D -EINVAL) { - error_report("Register sync failed... If you're using kvm-hv.k= o," - " only \"-cpu host\" is possible"); + error_setg(errp, "Register sync failed... If you're using kvm-= hv.ko," + " only \"-cpu host\" is possible"); } return ret; } diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 68e1501b21..d09048c522 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1544,7 +1544,7 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **e= rrp) return 0; } =20 -int kvm_arch_init_vcpu(CPUState *cs) +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { int ret =3D 0; RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -1554,6 +1554,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { ret =3D kvm_vcpu_set_machine_ids(cpu, cs); if (ret !=3D 0) { + error_setg(errp, "failed setting machine id (%d)", ret); return ret; } } diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index dc67e84886..76dd1e67c0 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -403,7 +403,7 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **err= p) return 0; } =20 -int kvm_arch_init_vcpu(CPUState *cs) +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { unsigned int max_cpus =3D MACHINE(qdev_get_machine())->smp.max_cpus; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639551; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5ahJOvaYHs21/JKqAABHSIlAiPcEjA+M5FAHkRnQW3k=; b=DvI71/UtIWngj9vceE6DdV1yxtvA13ang78G2i3bYdysYIPGEdgvM5NWbL9tgTvrdq4vQI Sx7nsE5OBDPHKy+iW2nU4nTJNpQm9J0wM83pwf9vWS6jqOlFcRC3nvtxTkjIbgrEiGK5/E iMYgtUZVon6r3xa2UKSCu7iIF5At2as= X-MC-Unique: kcQYT6ZWMpy_MzRG2OuGFw-1 X-Mimecast-MFC-AGG-ID: kcQYT6ZWMpy_MzRG2OuGFw_1791639540 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 17/26] target/arm/kvm: Introduce kvm_arm_override_idreg_field helper Date: Sat, 10 Oct 2026 15:36:21 +0200 Message-ID: <20261010133725.642498-18-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639739192158500 Content-Type: text/plain; charset="utf-8" Introduce kvm_arm_override_idreg_field() helper that allows to read an ID register value from a vcpu fd, override a given field value and reinject the new register value in the guest vcpu. The helper is not used yet, hence the G_GNUC_UNUSED marker. It will be used in subsequent patch to apply a new field value set through SYSREG property. Signed-off-by: Eric Auger --- target/arm/kvm.c | 48 ++++++++++++++++++++++++++++++++++++++++- target/arm/trace-events | 1 + 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6c15d8522f..c6c9ea03a5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1247,6 +1247,50 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu) return true; } =20 +static int G_GNUC_UNUSED +kvm_arm_override_idreg_field(int fd, ARM64SysRegField *field, + uint64_t newfv, Error **errp) +{ + uint64_t current, currentfv, value; + struct kvm_one_reg kvm_reg; + int index =3D field->index; + int length =3D field->length; + int lower =3D field->shift; + ARM64SysReg *reg; + uint64_t kvm_idx; + int ret; + + reg =3D &arm64_id_regs[index]; + + kvm_idx =3D idregs_sysreg_to_kvm_reg(id_register_sysreg[index]); + + ret =3D read_sys_reg64(fd, ¤t, kvm_idx); + if (ret) { + error_setg(errp, "failed to read %s current value", reg->name); + return ret; + } + currentfv =3D extract64(current, lower, length); + + if (currentfv !=3D newfv) { + value =3D deposit64(current, lower, length, newfv); + kvm_reg.id =3D kvm_idx; + kvm_reg.addr =3D (uintptr_t)&value; + + ret =3D ioctl(fd, KVM_SET_ONE_REG, &kvm_reg); + if (ret) { + error_setg(errp, + "ID register field %s.%s: fail to apply new value= =3D0x%" + PRIx64" (current is 0x%"PRIx64"): %m", + reg->name, field->name, newfv, currentfv); + + return ret; + } + } + trace_kvm_arm_override_idreg_field(reg->name, field->name, + currentfv, newfv); + return 0; +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -1259,6 +1303,7 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); abort(); } + if (!write_kvmstate_to_list(cpu)) { fprintf(stderr, "write_kvmstate_to_list failed\n"); abort(); @@ -2204,7 +2249,8 @@ int kvm_arch_init_vcpu(CPUState *cs, Error **errp) return ret; } SET_IDREG(&cpu->isar, MPIDR, mpidr); - cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; + + cpu->mp_affinity =3D GET_IDREG(&cpu->isar, MPIDR) & ARM64_AFFINITY_MAS= K; =20 return kvm_arm_init_cpreg_list(cpu, errp); } diff --git a/target/arm/trace-events b/target/arm/trace-events index ddc79eb666..81564f1d96 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -14,6 +14,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 +kvm_arm_override_idreg_field(const char *reg_name, const char *field_name,= uint64_t currentfv, uint64_t newfv) "%s.%s current=3D0x%"PRIx64" new=3D0x%= "PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=dbX7/6NbWU/+92lr0pryibg29b53j8+3gzhn4Kx0DXg=; b=L4KpsaluHswsTeP2TZ6n7E4fEocIYMGJ3JuYxyvUrMPanQawUQciPW77uBoJo0w53k77xx vVhkFXB7qX9o1vvRKwc7aBD4X9B9g2jEu7Wmk9O4YQ88Uhk3dJWUlCNjQ81MQvlEqln34k JFN3cO1e013W9zudKYMN+ybbLiuFFiE= X-MC-Unique: fYQX9bN1O0qu-vdOe2UkIA-1 X-Mimecast-MFC-AGG-ID: fYQX9bN1O0qu-vdOe2UkIA_1791639545 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 18/26] target/arm/cpu64: Introduce arm_cpu_apply_sysreg_props Date: Sat, 10 Oct 2026 15:36:22 +0200 Message-ID: <20261010133725.642498-19-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This helper walks through all stored SYSREG field values and apply them on the vcpu. It uses an accelerator specific callback to apply the field value on the vcpu. If the value is successfully applied, the cpu->isar.idregs[] value is updated accordingly. Signed-off-by: Eric Auger --- target/arm/cpu-idregs.h | 18 +++++++++++++ target/arm/cpu64.c | 57 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h index e0399e251b..56c2324359 100644 --- a/target/arm/cpu-idregs.h +++ b/target/arm/cpu-idregs.h @@ -38,4 +38,22 @@ typedef struct ARM64SysReg { */ extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; =20 +/* accelerator specific callback used to apply a new field value on a vcpu= */ +typedef int (*ARMSysregPropApplyFn)(ARMCPU *cpu, ARM64SysRegField *field, + uint64_t newfv, Error **errp); + +/** + * arm_cpu_apply_sysreg_props: + * + * Apply all SYSREG prop values + * @cpu: vcpu on which the values are applied + * @accel_apply_fn: acceleration specific callback used to override + * a single field value + * @errp: error handle + * + * return 0 on sucess or negative value with errp set on failure + */ +int arm_cpu_apply_sysreg_props(ARMCPU *cpu, ARMSysregPropApplyFn accel_app= ly_fn, + Error **errp); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9662608675..26baee102c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -803,6 +803,63 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *c= pu) =20 #define IDREG_FIELD_KEY(reg_idx, field_shift) \ (((uint64_t)(reg_idx) << 8) | ((uint64_t)(field_shift) & 0xFF)) +#define IDREG_FIELD_KEY_TO_REG_IDX(key) \ + ((uint32_t)(((uint64_t)(key)) >> 8)) +#define IDREG_FIELD_KEY_TO_SHIFT(key) \ + ((uint8_t)(((uint64_t)(key)) & 0xFF)) + +static ARM64SysRegField *arm_sysreg_get_field(ARM64SysReg *reg, int bit) +{ + for (int f =3D 0; f < reg->fields_count; f++) { + ARM64SysRegField *field =3D ®->fields[f]; + int upper =3D field->shift + field->length - 1; + + if (bit >=3D field->shift && bit <=3D upper) { + return field; + } + } + return NULL; +} + +/** + * arm_cpu_apply_sysreg_props: + * + * Iterate over all SYSREG_* property overrides, and apply them on the vcpu + * using the accelerataor specific @accel_apply_fn callback. + */ +int arm_cpu_apply_sysreg_props(ARMCPU *cpu, ARMSysregPropApplyFn accel_app= ly_fn, + Error **errp) +{ + gpointer key_ptr, value_ptr; + GHashTableIter iter; + + g_hash_table_iter_init(&iter, cpu->sysreg_props); + + while (g_hash_table_iter_next(&iter, &key_ptr, &value_ptr)) { + uint64_t key =3D (uint64_t)key_ptr; + uint64_t newfv =3D (uint64_t)value_ptr; + uint32_t reg_idx =3D IDREG_FIELD_KEY_TO_REG_IDX(key); + uint8_t lower =3D IDREG_FIELD_KEY_TO_SHIFT(key); + ARM64SysReg *reg =3D &arm64_id_regs[reg_idx]; + ARM64SysRegField *field =3D arm_sysreg_get_field(reg, lower); + int ret; + + if (!field) { + error_setg(errp, "SYSREG property key 0x%" PRIx64 + " does not match any field of %s", key, reg->name); + return -EINVAL; + } + + ret =3D accel_apply_fn(cpu, field, newfv, errp); + if (ret) { + return ret; + } + cpu->isar.idregs[field->index] =3D + deposit64(cpu->isar.idregs[field->index], + field->shift, field->length, newfv); + } + return 0; +} =20 static void set_sysreg_prop(Object *obj, Visitor *v, const char *name, void *opaque, --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639555; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2e+3CcNTBkD4MMGpHP73g186a5p7lV5juXn4lBjmR0Q=; b=f7cWgZ9anaO8Fhx8IZ3ocxjDqbfh9ZN112YEGYgw1InHI8erhKuvGGVG+0FeyJyQvI6shZ CiLhCAJx8ROPbG4DRiuOc7E02azYIEi1ZiWFWWP/KdZWdO5S24bsI4w8c8IHPSQBeFB7WY 6UDbbiSrFGrBAPcso6I1E4WWqANHSDA= X-MC-Unique: HXkgVivpOn-D1dziElzKEQ-1 X-Mimecast-MFC-AGG-ID: HXkgVivpOn-D1dziElzKEQ_1791639550 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 19/26] target/arm/kvm: Apply SYSREG props Date: Sat, 10 Oct 2026 15:36:23 +0200 Message-ID: <20261010133725.642498-20-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Now the infrastructure is in place let's trigger the SYSREG prop update in the KVM code. This is done in both kvm_arch_init_vcpu() and kvm_arm_reset_vcpu() after the final vcpu has been initialized with the proper kvm init settings and before kvmstate is synced back to the cpreg list. Signed-off-by: Eric Auger --- v9 -> v10 - use ValueRange --- target/arm/cpu64.c | 9 +++++---- target/arm/kvm.c | 20 +++++++++++++++++++- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 26baee102c..ff178bcaf5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -883,10 +883,11 @@ static void set_sysreg_prop(Object *obj, Visitor *v, return; } =20 - if (field->arch_vals) { - /* this field has some enum values */ - for (int i =3D 0; i < field->arch_vals_count; i++) { - if (value =3D=3D field->arch_vals[i]) { + if (field->arch_value_ranges) { + for (uint32_t i =3D 0; i < field->arch_value_ranges_count; i++) { + const ARM64SysRegArchValueRange *r =3D &field->arch_value_rang= es[i]; + + if (value >=3D r->lo && value <=3D r->hi) { goto valid; } } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index c6c9ea03a5..0c7e80aea8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1247,7 +1247,7 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu) return true; } =20 -static int G_GNUC_UNUSED +static int kvm_arm_override_idreg_field(int fd, ARM64SysRegField *field, uint64_t newfv, Error **errp) { @@ -1291,6 +1291,17 @@ kvm_arm_override_idreg_field(int fd, ARM64SysRegFiel= d *field, return 0; } =20 +static int kvm_arm_apply_one_sysreg_prop(ARMCPU *cpu, ARM64SysRegField *fi= eld, + uint64_t newfv, Error **errp) +{ + return kvm_arm_override_idreg_field(CPU(cpu)->kvm_fd, field, newfv, er= rp); +} + +static int kvm_arm_apply_sysreg_props(ARMCPU *cpu, Error **errp) +{ + return arm_cpu_apply_sysreg_props(cpu, kvm_arm_apply_one_sysreg_prop, = errp); +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -1304,6 +1315,8 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) abort(); } =20 + kvm_arm_apply_sysreg_props(cpu, &error_abort); + if (!write_kvmstate_to_list(cpu)) { fprintf(stderr, "write_kvmstate_to_list failed\n"); abort(); @@ -2250,6 +2263,11 @@ int kvm_arch_init_vcpu(CPUState *cs, Error **errp) } SET_IDREG(&cpu->isar, MPIDR, mpidr); =20 + ret =3D kvm_arm_apply_sysreg_props(cpu, errp); + if (ret) { + return ret; + } + cpu->mp_affinity =3D GET_IDREG(&cpu->isar, MPIDR) & ARM64_AFFINITY_MAS= K; =20 return kvm_arm_init_cpreg_list(cpu, errp); --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639615; cv=none; d=zohomail.com; s=zohoarc; b=mrfj7lufKQL0RQLBegEaN3etj5YLgdRPNqacXIbyU6QinKc3IzWceb0m//O9uRgf6qQS9H7c7ACh/AU2xccmzsgPxo4GwLUmBJqfxn6iRyC7xNXKdo5BHs3vI8LI5HBiQdAdOtYyOU1JHU8uZNkzNYA0DDvwxwDxq9wIfrvAFK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639615; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sat, 10 Oct 2026 13:39:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639560; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1P6OGS90P5wwSpHO8d6e35D+/9E59SZZDqpt+CKzk0c=; b=bmkpThEezqoEBx6guZ9OQ3YKUyNwxkLoiYbWdIDTdDxFA3U7+fzk14MpUTsslqIKLuPSSm eOO9PHCV6p2yv81KSikB9759mRmjC423a9GZcRawInjvc8/OP91YKsfL35NhQJIJ4ETFf0 pFAdwFplMjyige8CexMckjeHkkbXd3E= X-MC-Unique: aSmS0IB0ObCGGaOYOF72ig-1 X-Mimecast-MFC-AGG-ID: aSmS0IB0ObCGGaOYOF72ig_1791639555 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 20/26] target/arm/kvm: Add consistency checking for SYSREG props Date: Sat, 10 Oct 2026 15:36:24 +0200 Message-ID: <20261010133725.642498-21-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Since legacy composite options (such as SVE, virtualization, ...) and new SYSREG props coexist, add some basic consistency checks. Those checks are performed in kvm_arch_init_vcpu() before applying the SYSREG props at the end of the initialization chain. Some ID reg fields corresponding to legacy composite option scope are not (yet) writable (EL3, MTE, SVE, ...). As such they are not supposed to be exposed through SYSREG properties. However in the hypothesis they would become writable, and thus would be exposed and attempted to be set, we need to reject any setting because no consistency check is implemented yet. The function is exported because it will be used on the qmp expansion path too. Signed-off-by: Eric Auger --- v9 -> v10 - improve commit description - fix return in !arm_feature(&cpu->env, ARM_FEATURE_AARCH64) block - removed cpu_isar_feature(aa64_sve, cpu) && value =3D=3D 0 check --- target/arm/cpu-idregs.h | 17 ++++++++ target/arm/cpu64.c | 94 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h index 56c2324359..465ec83c97 100644 --- a/target/arm/cpu-idregs.h +++ b/target/arm/cpu-idregs.h @@ -56,4 +56,21 @@ typedef int (*ARMSysregPropApplyFn)(ARMCPU *cpu, ARM64Sy= sRegField *field, int arm_cpu_apply_sysreg_props(ARMCPU *cpu, ARMSysregPropApplyFn accel_app= ly_fn, Error **errp); =20 +/** + * arm_cpu_validate_sysreg_prop: + * + * accelerator agnostic validation of a field value (especially regarding + * the consistency with legacy composite options such as virtualization, p= mu, + * sve ...) + * + * @cpu: vcpu the field value is validated against + * @field: field the value is applied to + * @value: field value to be validated + * @errp: error handle set if validation fails + * + * returns true if validation succeeds + */ +bool arm_cpu_validate_sysreg_prop(ARMCPU *cpu, ARM64SysRegField *field, + uint64_t value, Error **errp); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ff178bcaf5..b7c0a27b16 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -821,6 +821,63 @@ static ARM64SysRegField *arm_sysreg_get_field(ARM64Sys= Reg *reg, int bit) return NULL; } =20 +/** + * arm_cpu_validate_sysreg_prop: + * + * Validate a SYSREG field value against legacy composite options + * (virtualization, pmu, sve, aarch64, ...). Some other fields are known + * to conflict but they are not writable yet. For those we just skip them + * in aarch64_add_one_idreg_properties() in the hypothesis their property + * shows up. + */ +bool arm_cpu_validate_sysreg_prop(ARMCPU *cpu, ARM64SysRegField *field, + uint64_t value, Error **errp) +{ + ARM64SysReg *sysregdesc =3D &arm64_id_regs[field->index]; + g_autofree char *propname =3D + g_strdup_printf("SYSREG_%s_%s", sysregdesc->name, field->name); + + /* virtualization */ + if (!strcmp(propname, "SYSREG_ID_AA64PFR0_EL1_EL2")) { + if (cpu->has_el2 && value =3D=3D 0) { + error_setg(errp, + "Inconsistent -machine virtualization=3Don and %s= =3D0", + propname); + return false; + } else if (!cpu->has_el2 && value > 0) { + error_setg(errp, + "Inconsistent -machine virtualization=3Doff and %s = > 0", + propname); + return false; + } + } else if (!strcmp(propname, "SYSREG_ID_AA64ZFR0_EL1_SVEver")) { + if (!cpu_isar_feature(aa64_sve, cpu) && value > 0) { + error_setg(errp, "sve is not set but %s is greater than 0", + propname); + return false; + } + /* PMU */ + } else if (!strcmp(propname, "SYSREG_ID_AA64DFR0_EL1_PMUVer")) { + if (cpu->has_pmu && value =3D=3D 0) { + error_setg(errp, "%s is 0 whereas pmu is set", propname); + return false; + } else if (!cpu->has_pmu && value) { + error_setg(errp, "%s is non null whereas pmu is unset", propna= me); + return false; + } + /* aarch64=3Doff */ + } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if ((!strcmp(propname, "SYSREG_ID_AA64PFR0_EL1_EL0") || + !strcmp(propname, "SYSREG_ID_AA64PFR0_EL1_EL1") || + !strcmp(propname, "SYSREG_ID_AA64PFR0_EL1_EL2")) && value < 2= ) { + error_setg(errp, "%s is < 2 while aarch64 is set to off", + propname); + return false; + } + } + return true; +} + /** * arm_cpu_apply_sysreg_props: * @@ -850,6 +907,10 @@ int arm_cpu_apply_sysreg_props(ARMCPU *cpu, ARMSysregP= ropApplyFn accel_apply_fn, return -EINVAL; } =20 + if (!arm_cpu_validate_sysreg_prop(cpu, field, newfv, errp)) { + return -EINVAL; + } + ret =3D accel_apply_fn(cpu, field, newfv, errp); if (ret) { return ret; @@ -934,6 +995,35 @@ static void get_sysreg_prop(Object *obj, Visitor *v, trace_get_sysreg_prop(name, value); } =20 +/* + * SYSREG properties that are not exposed yet because the fields + * are not yet writable and which are known to conflict with legacy + * composite options (EL3, MTE, SVE, pauth, ...). In case the + * associated fields would become exposed, we skip them when registering + * the properties. + */ +static const char * const aarch64_sysreg_prop_skip_list[] =3D { + "SYSREG_ID_AA64PFR0_EL1_EL3", + "SYSREG_ID_AA64PFR1_EL1_MTE", + "SYSREG_ID_AA64PFR0_EL1_SVE", + "SYSREG_ID_AA64ISAR1_EL1_APA", + "SYSREG_ID_AA64ISAR1_EL1_API", + "SYSREG_ID_AA64ISAR1_EL1_GPA", + "SYSREG_ID_AA64ISAR1_EL1_GPI", + "SYSREG_ID_AA64ISAR2_EL1_APA3", + "SYSREG_ID_AA64ISAR2_EL1_GPA3", +}; + +static bool aarch64_sysreg_prop_skipped(const char *prop_name) +{ + for (int i =3D 0; i < ARRAY_SIZE(aarch64_sysreg_prop_skip_list); i++) { + if (g_str_equal(prop_name, aarch64_sysreg_prop_skip_list[i])) { + return true; + } + } + return false; +} + /** * aarch64_add_idreg_properties: Add SYSREG__ properties * for named fields of an ID register @@ -985,6 +1075,10 @@ aarch64_add_one_idreg_properties(Object *obj, ARM64Sy= sReg *reg, } =20 prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + if (aarch64_sysreg_prop_skipped(prop_name)) { + g_free(prop_name); + continue; + } object_property_add(obj, prop_name, "uint64", get_sysreg_prop, set_sysreg_prop, NULL, field); trace_add_idreg_property(prop_name, lower, upper, field_writable_m= ask); --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639752; cv=none; d=zohomail.com; s=zohoarc; b=DW2MwlMzlbC8chsRuE1heraMiJS5ILaeTFwH8ZABRrnumSljbWUPWuE77jkMRe7npEzsY19RLSpLKyLmIPtLoLo6g385Rr2JMVy/GyfR6z1M/t7Jp4cnkiTq7LUmUEEcv0CNqMiX+W8Lr54rMfdDqzdP4ub//AfAOABlmaT01WU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791639752; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sat, 10 Oct 2026 13:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639565; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v43ocM3DpQoBMOmnWjOUY1Uk4kwBrzKU6IVEiEb5hkU=; b=Y0Fdprf1pUXjEiZSS4EIPOLyxOgwfdU+VuZYTJMlEuAWiJBWaytp3da7Zo360V+SQBYa4K LQP1dX3a5t+obGvr5zqKZ8h2Rdz1IqMa+oazbe3Z4dsrROL6iHGYgiXh2Wq3NXYvCH1DWO 6roD1heBfEf/TGKE3Xf6++dJnMa7KrI= X-MC-Unique: BPK8EFKOOj6vqxxTk1BCAQ-1 X-Mimecast-MFC-AGG-ID: BPK8EFKOOj6vqxxTk1BCAQ_1791639560 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 21/26] target/arm/cpu64: Add helper to test SYSREG props against a scratch vcpu Date: Sat, 10 Oct 2026 15:36:25 +0200 Message-ID: <20261010133725.642498-22-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639753490158500 Content-Type: text/plain; charset="utf-8" Add kvm_idreg_write_scratch_vcpu helper that will be used by qmp_query_cpu_model_expansion code to test SYSREG settings against a scratch vcpu. Indeed when the expansion code is called the actual vcpu has not been initialized so we use a scratch vcpu. This latter has been initialized with features taken from legacy compositive options (EL2, SVE, ...). So the trial is very close to the final setup. Signed-off-by: Eric Auger --- target/arm/kvm_arm.h | 4 ++++ target/arm/kvm-stub.c | 7 +++++++ target/arm/kvm.c | 21 +++++++++++++++++++++ target/arm/trace-events | 1 + 4 files changed, 33 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c40fb003..25a1dec095 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -14,6 +14,7 @@ #include "qapi/qapi-types-misc-arm.h" #include "system/kvm.h" #include "target/arm/cpu-qom.h" +#include "cpu-idregs.h" =20 #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) @@ -240,4 +241,7 @@ void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapabi= lity *v3); */ char *kvm_print_register_name(uint64_t regidx); =20 +bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpufd, + ARM64SysRegField *field, uint64_t newfv, + Error **errp); #endif diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 88cbe8d85c..8e6fae0a4d 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -119,3 +119,10 @@ char *kvm_print_register_name(uint64_t regidx) { g_assert_not_reached(); } + +bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpufd, + ARM64SysRegField *field, uint64_t newfv, + Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 0c7e80aea8..82ffcac7e3 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1297,6 +1297,27 @@ static int kvm_arm_apply_one_sysreg_prop(ARMCPU *cpu= , ARM64SysRegField *field, return kvm_arm_override_idreg_field(CPU(cpu)->kvm_fd, field, newfv, er= rp); } =20 +bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpufd, + ARM64SysRegField *field, uint64_t newfv, + Error **errp) +{ + int ret; + + if (!arm_cpu_validate_sysreg_prop(cpu, field, newfv, errp)) { + return false; + } + + ret =3D kvm_arm_override_idreg_field(cpufd, field, newfv, errp); + if (ret) { + return false; + } + + cpu->isar.idregs[field->index] =3D + deposit64(cpu->isar.idregs[field->index], + field->shift, field->length, newfv); + return true; +} + static int kvm_arm_apply_sysreg_props(ARMCPU *cpu, Error **errp) { return arm_cpu_apply_sysreg_props(cpu, kvm_arm_apply_one_sysreg_prop, = errp); diff --git a/target/arm/trace-events b/target/arm/trace-events index 81564f1d96..a731b5d4ba 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 kvm_arm_override_idreg_field(const char *reg_name, const char *field_name,= uint64_t currentfv, uint64_t newfv) "%s.%s current=3D0x%"PRIx64" new=3D0x%= "PRIx64 +kvm_arm_idreg_write_scratch_vcpu(const char *name, uint64_t oldfv, uint64_= t newfv, uint64_t actualfv) "successful dry-run for %s old=3D0x%"PRIx64" ne= w=3D0x%"PRIx64" actual=3D0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Oct 22 19:24:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639570; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I182iXUY+xPUHsg/tWpxySUU31EcXiYq269W9BRBUwM=; b=UQRiFaVVnmsAiWxECRXmCQTmgDHOVrHeSYk9Msou1gxpBGnRMXjxrTpuv1h+hoVvKJUyk/ 55ptrzqkY8C2MW3ErRQEwAkWU8MmfgeqfeqcCwcdjvhPSHXGZGe+rD5sCj6+o437IPN2mS vCgcg/0vfLXLN+r2nzdSX8Tz1nMXoQw= X-MC-Unique: bqol17HYOlSzvKJOAYfmiw-1 X-Mimecast-MFC-AGG-ID: bqol17HYOlSzvKJOAYfmiw_1791639565 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 22/26] target/arm/kvm: Add an error handle to kvm_arm_create_scratch_host_vcpu Date: Sat, 10 Oct 2026 15:36:26 +0200 Message-ID: <20261010133725.642498-23-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639775943158500 Content-Type: text/plain; charset="utf-8" This allows to report a precise error message if any error occurs. Signed-off-by: Eric Auger --- target/arm/kvm_arm.h | 3 ++- target/arm/kvm.c | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 25a1dec095..ccab33e571 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -106,6 +106,7 @@ struct kvm_vcpu_init; * @init: filled in with the necessary values for creating a host * vcpu. If NULL is provided, will not init the vCPU (though the cpufd * will still be set up). + * @errp: Error handle * * Create a scratch vcpu in its own VM of the type preferred by the host * kernel (as would be used for '-cpu host'), for purposes of probing it @@ -115,7 +116,7 @@ struct kvm_vcpu_init; * false on failure (and fdarray and init are not valid). */ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, - struct kvm_vcpu_init *init); + struct kvm_vcpu_init *init, Error **= errp); =20 /** * kvm_arm_destroy_scratch_host_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 82ffcac7e3..1f6f9ba586 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -107,13 +107,14 @@ static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int fea= ture) } =20 bool kvm_arm_create_scratch_host_vcpu(int *fdarray, - struct kvm_vcpu_init *init) + struct kvm_vcpu_init *init, Error **= errp) { int ret =3D 0, kvmfd =3D -1, vmfd =3D -1, cpufd =3D -1; int max_vm_pa_size; =20 kvmfd =3D qemu_open_old("/dev/kvm", O_RDWR); if (kvmfd < 0) { + error_setg(errp, "Failed opening /dev/kvm"); goto err; } max_vm_pa_size =3D ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IP= A_SIZE); @@ -124,6 +125,7 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); } while (vmfd =3D=3D -1 && errno =3D=3D EINTR); if (vmfd < 0) { + error_setg(errp, "Failed creating the scratch VM"); goto err; } =20 @@ -143,6 +145,7 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, =20 cpufd =3D ioctl(vmfd, KVM_CREATE_VCPU, 0); if (cpufd < 0) { + error_setg(errp, "Failed creating the scratch VCPU"); goto err; } =20 @@ -156,12 +159,14 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray, =20 ret =3D ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); if (ret < 0) { + error_setg(errp, "Failed getting the preferred target"); goto err; } init->target =3D preferred.target; } ret =3D ioctl(cpufd, KVM_ARM_VCPU_INIT, init); if (ret < 0) { + error_setg(errp, "Failed the init of the scratch vcpu"); goto err; } =20 @@ -380,6 +385,7 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool el2_supported; bool pmu_supported =3D false; uint64_t features =3D 0; + Error *local_err =3D NULL; int err; =20 ahcf->target =3D QEMU_KVM_ARM_TARGET_NONE; @@ -427,7 +433,8 @@ kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) features |=3D 1ULL << ARM_FEATURE_PMU; } =20 - if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) { + if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init, &local_err)) { + error_report_err(local_err); return; } =20 @@ -2838,8 +2845,10 @@ void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int= level) void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3) { int fdarray[3]; + Error *err =3D NULL; =20 - if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL)) { + if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL, &err)) { + error_report_err(err); return; } =20 --=20 2.53.0 From nobody Thu Oct 22 19:24:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639577; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dX+xl4MgWhLToR/5btAo7lKrv5fuNuvLk2lGV95KcY0=; b=FOUSBdhVwyk2vJtTm2E7oNBmLqZpGg5lQGvj9bQj+hrs3Ajamu9yN3wd2JlC1WbiW5wagF v6SgwU+VJOuux+6rZSZeopKdtZsa/h7xIDHWa8VrVkVoiHuNrainoqFpVDPXULsDFncOCk NO13EHDLatQV58r+xz3JGijfgI8kaa8= X-MC-Unique: i6KLxWWUNOKz7jXeBMYRHg-1 X-Mimecast-MFC-AGG-ID: i6KLxWWUNOKz7jXeBMYRHg_1791639570 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 23/26] target/arm/kvm: Introduce kvm_arm_vcpu_prepare_init_features helper Date: Sat, 10 Oct 2026 15:36:27 +0200 Message-ID: <20261010133725.642498-24-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639771827158500 Content-Type: text/plain; charset="utf-8" Factorize the code that initializes the kvm init features from the cpu settings in a helper. Use it kvm_arch_init_vcpu(). Soon it will be used by another function. The only change in the code relates to the check of kvm_state. The future caller won't have the VM created when calling the helper and for this caller it is OK ignoring PSCI version setting. Signed-off-by: Eric Auger --- target/arm/kvm.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1f6f9ba586..840501f9bf 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2191,27 +2191,18 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error *= *errp) return 0; } =20 -int kvm_arch_init_vcpu(CPUState *cs, Error **errp) +/* Determine init features for this CPU */ +static void kvm_arm_vcpu_prepare_init_features(ARMCPU *cpu) { - int ret; - uint64_t mpidr; - ARMCPU *cpu =3D ARM_CPU(cs); + CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; - uint64_t psciver; =20 - if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE) { - error_setg(errp, "KVM is not supported for this guest CPU type"); - return -EINVAL; - } - - qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cpu); - - /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); + if (cs->start_powered_off) { cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_POWER_OFF; } - if (cpu->psci_version !=3D QEMU_PSCI_VERSION_0_1 && + if (cpu->psci_version !=3D QEMU_PSCI_VERSION_0_1 && cs->kvm_state && kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { /* * Versions >=3D v0.2 are backward compatible with v0.2 @@ -2235,6 +2226,23 @@ int kvm_arch_init_vcpu(CPUState *cs, Error **errp) if (cpu->has_el2 && kvm_arm_el2_supported()) { cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; } +} + +int kvm_arch_init_vcpu(CPUState *cs, Error **errp) +{ + int ret; + uint64_t mpidr; + ARMCPU *cpu =3D ARM_CPU(cs); + uint64_t psciver; + + if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE) { + error_setg(errp, "KVM is not supported for this guest CPU type"); + return -EINVAL; + } + + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cpu); + + kvm_arm_vcpu_prepare_init_features(cpu); =20 /* Do KVM_ARM_VCPU_INIT ioctl */ ret =3D kvm_arm_vcpu_init(cpu); --=20 2.53.0 From nobody Thu Oct 22 19:24:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1791639581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eWAeOoa1Aggv8+wq6e4woSeOMPDynBiaXDMHTvXpmn8=; b=hJlbLCm7to9kEs9EkhN9ThIYuJijsdCBOPPi7Hmt09IqTYSRHiurIbx9F3Kj4C2BstGp6Q OFn4y1rPYNtYg9enBp+EFaN5vr7DKeyT4uxmN0ebRGljSDguUJEd4ETuxqPWamR/mHaCx4 we6w0rvElCth1YWYUNlq1ZXg97IhfD0= X-MC-Unique: -t0Vb-m-NQunNUWAFWP68Q-1 X-Mimecast-MFC-AGG-ID: -t0Vb-m-NQunNUWAFWP68Q_1791639575 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@oss.qualcomm.com Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v10 24/26] target/arm/kvm: Introduce kvm_arm_create_init_scratch_vcpu() Date: Sat, 10 Oct 2026 15:36:28 +0200 Message-ID: <20261010133725.642498-25-eric.auger@redhat.com> In-Reply-To: <20261010133725.642498-1-eric.auger@redhat.com> References: <20261010133725.642498-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639712673158500 Content-Type: text/plain; charset="utf-8" Introduce kvm_arm_create_init_scratch_vcpu() that allows to create and initialize a scratch vcpu from cpu settings. We want to use this in arm-qmp-cmds code as well as kvm_arm_destroy_scratch_host_vcpu so export them. Signed-off-by: Eric Auger --- v9 -> v10: - pass the fdarray as a param --- target/arm/kvm_arm.h | 19 ++++++++++++++++++- target/arm/kvm-stub.c | 10 ++++++++++ target/arm/kvm.c | 13 +++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index ccab33e571..2e7e02e4a4 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -118,11 +118,28 @@ struct kvm_vcpu_init; bool kvm_arm_create_scratch_host_vcpu(int *fdarray, struct kvm_vcpu_init *init, Error **= errp); =20 +/** + * kvm_arm_create_init_scratch_vcpu: + * @cpu: ARMCPU whose kvm init features to inherit + * @fdarray: array of fds filled as by kvm_arm_create_scratch_host_vcpu + * + * Create and initialize a scratch vcpu inheriting the features set + * on @cpu. + * + * Return the vcpu fd on success or -1 on failure with a corresponding + * Error handle. On success, @fdarray is populated and must be torn down + * with kvm_arm_destroy_scratch_host_vcpu(). + */ +int kvm_arm_create_init_scratch_vcpu(ARMCPU *cpu, int *fdarray, Error **er= rp); + + /** * kvm_arm_destroy_scratch_host_vcpu: * @fdarray: array of fds as set up by kvm_arm_create_scratch_host_vcpu + * or kvm_arm_create_init_scratch_vcpu * - * Tear down the scratch vcpu created by kvm_arm_create_scratch_host_vcpu. + * Tear down the scratch vcpu created by kvm_arm_create_scratch_host_vcpu + * or kvm_arm_create_init_scratch_vcpu. */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); =20 diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 8e6fae0a4d..c9387f5c8c 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -126,3 +126,13 @@ bool kvm_idreg_write_scratch_vcpu(ARMCPU *cpu, int cpu= fd, { g_assert_not_reached(); } + +int kvm_arm_create_init_scratch_vcpu(ARMCPU *cpu, int *fdarray, Error **er= rp) +{ + g_assert_not_reached(); +} + +void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 840501f9bf..ebe4f408e2 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2228,6 +2228,19 @@ static void kvm_arm_vcpu_prepare_init_features(ARMCP= U *cpu) } } =20 +int kvm_arm_create_init_scratch_vcpu(ARMCPU *cpu, int *fdarray, Error **er= rp) +{ + struct kvm_vcpu_init init =3D {.target =3D cpu->kvm_target, }; + + kvm_arm_vcpu_prepare_init_features(cpu); + memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); + + if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init, errp)) { + return -1; + } + return fdarray[2]; +} + int kvm_arch_init_vcpu(CPUState *cs, Error **errp) { int ret; --=20 2.53.0 From nobody Thu Oct 22 19:24:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1791639739257158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Enhance the current host model query-cpu-model-expansion with the capability to return SYSREG_* options and also test possible values. If no SYSREG prop is set, query-cpu-model-expansion returns the default host values for all SYSREG properties. They are extracted from a scratch vcpu featuring all the KVM advertised capabilities. Here is a qmp-shell example: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} {"return": {"model": {"name": "host", "props": {"SYSREG_ID_AA64PFR0_EL1_EL3= ": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_MIDR_EL1_PartNum": 3407, "SYSREG_CTR_EL0_DminLine": 4, "SYSREG_ID_AA64MMFR0_EL1_PARange": 5, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0 ../.. It becomes also possible to test new SYSREG property values. With Full expansion of the host model, the SYSREG props are tested against a scratch vcpu. With static expansion, no check is performed against KVM but only against qemu code (the value does not exceed the field size and if the field is associated to enum values, the set value belongs to the list of arch enum values. Examples (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host","props"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x13}} {"error": {"class": "GenericError", "desc": "idreg SYSREG_ID_AA64ISAR0_EL1_= DP set value (0x13) exceeds length of field (4)!"}} (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host","props"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x2}} {"error": {"class": "GenericError", "desc": "idreg SYSREG_ID_AA64ISAR0_EL1_= DP set value (0x2) does not match any arch valid enum value!"}} Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v9 -> v10: - use new proto for kvm_arm_create_init_scratch_vcpu, rework error path and fix visit_type_uint64 call v8 -> v9: - fix the leak reported by Khushit - implement static mode for host v7 -> v8: - do not check if the prop exists (this is checked elsewhere with a different error message) - clarify that examples given in the commit msg are based on qmp-shell v5 -> v6: - add the write capability --- target/arm/arm-qmp-cmds.c | 130 ++++++++++++++++++++++++++++++++++---- 1 file changed, 118 insertions(+), 12 deletions(-) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 83ec95c290..2765594c68 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/target-info.h" #include "hw/core/boards.h" #include "kvm_arm.h" @@ -30,6 +31,7 @@ #include "qapi/qapi-commands-machine.h" #include "qapi/qapi-commands-misc-arm.h" #include "qobject/qdict.h" +#include "qobject/qnum.h" #include "qom/qom-qobject.h" #include "cpu.h" =20 @@ -83,15 +85,24 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, CpuModelInfo *model, Error **errp) { + bool use_scratch_vcpu =3D kvm_enabled() && type =3D=3D CPU_MODEL_EXPAN= SION_TYPE_FULL; CpuModelExpansionInfo *expansion_info; + ObjectPropertyIterator iter; const QDict *qdict_in; + ObjectProperty *idregprop; QDict *qdict_out; ObjectClass *oc; Object *obj; + Visitor *visitor =3D NULL; + Error *err =3D NULL; + bool scratch_created =3D false; const char *name; + int fdarray[3]; + int fd =3D -1; int i; =20 - if (type !=3D CPU_MODEL_EXPANSION_TYPE_FULL) { + /* we support static expansion for host model only */ + if (type !=3D CPU_MODEL_EXPANSION_TYPE_FULL && strcmp(model->name, "ho= st")) { error_setg(errp, "The requested expansion type is not supported"); return NULL; } @@ -134,9 +145,6 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, obj =3D object_new(object_class_get_name(oc)); =20 if (model->props) { - Visitor *visitor; - Error *err =3D NULL; - visitor =3D qobject_input_visitor_new(model->props); if (!visit_start_struct(visitor, "model.props", NULL, 0, errp)) { visit_free(visitor); @@ -146,6 +154,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, =20 qdict_in =3D qobject_to(QDict, model->props); i =3D 0; + + /* Test legacy composite option settings */ while ((name =3D cpu_model_advertised_features[i++]) !=3D NULL) { if (qdict_get(qdict_in, name)) { if (!object_property_set(obj, name, visitor, &err)) { @@ -154,19 +164,89 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(= CpuModelExpansionType type, } } =20 - if (!err) { - visit_check_struct(visitor, &err); - } if (!err) { arm_cpu_finalize_features(ARM_CPU(obj), &err); } + if (err) { + goto bail_out; + } + + /** + * Test SYSREG option settings + * In full mode, build a scratch vcpu that reflects composite lega= cy + * options + */ + if (use_scratch_vcpu) { + Error *local_err =3D NULL; + bool has_virt =3D object_property_get_bool(OBJECT(current_mach= ine), + "virtualization", + &local_err); + + if (local_err) { + error_free(local_err); /* the machine property does not ex= ist */ + } else { + if (!has_virt && object_property_find(obj, "has_el2")) { + object_property_set_bool(obj, "has_el2", false, NULL); + } + } + fd =3D kvm_arm_create_init_scratch_vcpu(ARM_CPU(obj), fdarray,= errp); + if (fd < 0) { + goto bail_out; + } + scratch_created =3D true; + } + + qdict_in =3D qobject_to(QDict, model->props); + for (const QDictEntry *entry =3D qdict_first(qdict_in); + entry !=3D NULL; entry =3D qdict_next(qdict_in, entry)) { + const char *key =3D qdict_entry_key(entry); + QObject *val_obj =3D qdict_entry_value(entry); + ObjectProperty *prop; + Visitor *v; + uint64_t val; + + if (!g_str_has_prefix(key, "SYSREG_")) { + continue; + } + + prop =3D object_property_find(obj, key); + + /* consume the prop to avoid unexpected parameter */ + if (!visit_type_uint64(visitor, key, &val, errp)) { + goto bail_out; + } + + v =3D qobject_input_visitor_new(val_obj); + + if (!object_property_set(obj, key, v, errp)) { + visit_free(v); + goto bail_out; + } + + if (use_scratch_vcpu && prop) { + ARM64SysRegField *field =3D (ARM64SysRegField *)prop->opaq= ue; + + if (!kvm_idreg_write_scratch_vcpu(ARM_CPU(obj), fd, + field, val, errp)) { + visit_free(v); + goto bail_out; + } + } + visit_free(v); + } + + visit_check_struct(visitor, &err); + if (err) { + goto bail_out; + } + + if (scratch_created) { + kvm_arm_destroy_scratch_host_vcpu(fdarray); + scratch_created =3D false; + } visit_end_struct(visitor, NULL); visit_free(visitor); - if (err) { - object_unref(obj); - error_propagate(errp, err); - return NULL; - } + visitor =3D NULL; } else { arm_cpu_finalize_features(ARM_CPU(obj), &error_abort); } @@ -190,6 +270,18 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + object_property_iter_init(&iter, obj); + + while ((idregprop =3D object_property_iter_next(&iter))) { + QObject *value; + + if (!g_str_has_prefix(idregprop->name, "SYSREG_")) { + continue; + } + value =3D object_property_get_qobject(obj, idregprop->name, &error= _abort); + qdict_put_obj(qdict_out, idregprop->name, value); + } + if (!qdict_size(qdict_out)) { qobject_unref(qdict_out); } else { @@ -199,6 +291,20 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, object_unref(obj); =20 return expansion_info; + +bail_out: + if (scratch_created) { + kvm_arm_destroy_scratch_host_vcpu(fdarray); + } + if (visitor) { + visit_end_struct(visitor, NULL); + visit_free(visitor); + } + if (err) { + error_propagate(errp, err); + } + object_unref(obj); + return NULL; } =20 static void arm_cpu_add_definition(gpointer data, gpointer user_data) --=20 2.53.0 From nobody Thu Oct 22 19:24:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1791639822; cv=none; d=zohomail.com; s=zohoarc; b=PUrsDZctLvqOiSS/KUMcQbd3YKpDy8F0F72xEfXCMA27lGJ4H2B6GxEPT4XzMLZdZcx99tF9QPoqf+7gp1CV1cCS9Ph2C444h+45JReMtdVidgEmSof9bRyM9hTM9sFB33uLE5QrslDV39mnXVfR9KPboQJs1A0KWyrr2cbDIhQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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charset="utf-8" From: Cornelia Huck Add some documentation for how individual ID registers can be configured with the host cpu model. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- 9 -> 10: - document the fact some props may be willingly hidden because they conflict with legacy composite options - mention max model too --- docs/system/arm/cpu-features.rst | 111 ++++++++++++++++++++++++++++--- 1 file changed, 102 insertions(+), 9 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 10b0eff27e..13454783cf 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -2,8 +2,11 @@ Arm CPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 CPU features are optional features that a CPU of supporting type may -choose to implement or not. In QEMU, optional CPU features have -corresponding boolean CPU proprieties that, when enabled, indicate +choose to implement or not. QEMU provides two different mechanisms +to configure those features: + +1. For most CPU models, optional CPU features may have +corresponding boolean CPU properties that, when enabled, indicate that the feature is implemented, and, conversely, when disabled, indicate that it is not implemented. An example of an Arm CPU feature is the Performance Monitoring Unit (PMU). CPU types such as the @@ -31,6 +34,34 @@ running guests in AArch32. CPU features that are inherently specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 +2. Additionally, the ``host`` and ``max`` CPU models on KVM allow +overwriting a subset of the ID register fields. Not all ID register +fields are writable: this depends on the host. For those which are +writable, and for those only, these models expose +``SYSREG__`` properties. IDREG and FIELD names are those +used in the ARM Architecture Reference Manual. QEMU may still omit some +writable fields that conflict with legacy composite options (for example +EL3/secure, MTE, SVE, or pauth). + +Values set with those properties override the initial values retrieved +from the vCPU after legacy composite property settings (``sve``, +``pauth``, ...) have been applied, whether at machine level or at vCPU +level. + +``SYSREG__`` properties are applied at the end of the chain +and do not substitute for legacy composite options. In other words, if +you want to use pauth, you still need to set ``pauth=3Don``. Indeed legacy +options do more than exposing a different value for ID registers. They +may also interact with KVM to prepare the vCPU for this feature (for +instance at vCPU init time). Whereas ``SYSREG__`` properties +only change the final value of the ID register. Inconsistent settings +between legacy composite options (at machine level or CPU level) which +impact the vCPU and low-level ``SYSREG__`` properties are +rejected. ``SYSREG__`` properties are essentially used to +tune the ``host``/``max`` vCPU model so that it allows migration between +different hardware. + + CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -126,13 +157,21 @@ A note about CPU models and KVM =20 Named CPU models generally do not work with KVM. There are a few cases that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a -seattle host, but mostly if KVM is enabled the ``host`` CPU type must be -used. This means the guest is provided all the same CPU features as the -host CPU type has. And, for this reason, the ``host`` CPU type should -enable all CPU features that the host has by default. Indeed it's even -a bit strange to allow disabling CPU features that the host has when using -the ``host`` CPU type, but in the absence of CPU models it's the best we c= an -do if we want to launch guests without all the host's CPU features enabled. +seattle host, but mostly if KVM is enabled, the ``host`` CPU model must be +used. + +Using the ``host`` type means the guest is provided all the same CPU +features as the host CPU type has. And, for this reason, the ``host`` +CPU type should enable all CPU features that the host has by default. + +In case some features need to be tuned for the guest, and the host kernel +supports it, the ``host`` and ``max`` models can be instructed to change +individual ID register field values. This is especially useful for +migration purposes. +However, this interface will not allow configuring an arbitrary set of +features; the ID registers must describe a subset of the host's features, +and all differences to the host's configuration must actually be supported +by the kernel to be deconfigured. =20 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. = The affect is not only limited to specific features, as pointed out in example @@ -169,6 +208,15 @@ disabling many SVE vector lengths would be quite verbo= se, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +Additionally, if supported by KVM on the host kernel, the ``host`` and +``max`` CPU models may be configured via individual ID register field +properties, for example:: + + $ qemu-system-aarch64 -M virt -cpu host,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 + +This forces ID_AA64ISAR0_EL1 DP field to 0. The same property syntax works +with ``-cpu max``. + KVM VCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -495,3 +543,48 @@ Legal values for ``S`` are 30, 34, 36, and 39; the def= ault is 30. =20 As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or removed in some future QEMU release. + +Configuring CPU features via ID register fields +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Note that this is currently only supported under KVM, and with the +``host`` or ``max`` CPU models. + +Querying available ID register fields +------------------------------------- + +QEMU will create properties for ID register fields that are reported as +being writable by the kernel, known to the QEMU instance, and not omitted +because they conflict with legacy composite options. Therefore, the same +QEMU binary may expose different properties when run under a different +kernel. + +To find out the available ID register field properties, use the +``query-cpu-model-expansion`` QMP command:: + + (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} + {"return": { + "model": {"name": "host", "props": { + "SYSREG_ID_AA64PFR0_EL1_EL2": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, + "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_CTR_EL0_DminLine": 4, + "SYSREG_ID_AA64MMFR0_EL1_BIGEND": 1, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0, + "SYSREG_ID_AA64MMFR2_EL1_CnP": 1, "SYSREG_ID_DFR0_EL1_PerfMon": 4, + "SYSREG_ID_AA64PFR0_EL1_DIT": 0, "SYSREG_ID_AA64MMFR1_EL1_HAFDBS": 2, + "SYSREG_ID_AA64ISAR0_EL1_FHM": 0, "SYSREG_ID_AA64ISAR2_EL1_CSSC": 0, + "SYSREG_ID_AA64ISAR0_EL1_DP": 1, (...) + }}}} + +If a certain field in an ID register does not show up in this list, it is +either not writable with the specific host kernel, unknown to this QEMU +build, or intentionally not exposed because it overlaps a legacy composite +option. + +A note on compatibility +----------------------- + +A common use case for providing a defined set of ID register values is +to be able to present a fixed set of features to a guest, often referred +to as "stable guest ABI". This may take the form of ironing out differences +between two similar CPUs with the intention of being able to migrate +between machines with those CPUs, or providing the same CPU across Linux +kernel updates on the host. --=20 2.53.0