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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586398567158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 2 +- target/hexagon/helper.h | 4 ++-- target/hexagon/hex_mmu.c | 2 +- target/hexagon/hex_mmu.h | 2 +- target/hexagon/op_helper.c | 4 ++-- target/hexagon/translate.c | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index af5032214c4..5163da2f6b3 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/target/hexagon/gen_tcg_sys.h @@ -80,7 +80,7 @@ #define fGEN_TCG_Y2_wait(SHORTCODE) \ do { \ RsV =3D RsV; \ - gen_helper_wait(tcg_env, tcg_constant_tl(ctx->pkt.pc)); \ + gen_helper_hexagon_wait(tcg_env, tcg_constant_tl(ctx->pkt.pc)); \ } while (0) =20 #define fGEN_TCG_Y2_resume(SHORTCODE) \ diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 71c8da4c46d..a2b3d8950f4 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -18,7 +18,7 @@ #include "internal.h" #include "helper_protos_generated.h.inc" =20 -DEF_HELPER_FLAGS_3(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32= , i32) +DEF_HELPER_FLAGS_3(hexagon_raise_exception, TCG_CALL_NO_RETURN, noreturn, = env, i32, i32) DEF_HELPER_2(commit_store, void, env, int) DEF_HELPER_3(gather_store, void, env, i32, int) DEF_HELPER_1(commit_hvx_stores, void, env) @@ -136,7 +136,7 @@ DEF_HELPER_3(sreg_write_masked, void, env, i32, i32) DEF_HELPER_3(setprio, void, env, i32, i32) DEF_HELPER_2(start, void, env, i32) DEF_HELPER_1(stop, void, env) -DEF_HELPER_2(wait, void, env, i32) +DEF_HELPER_2(hexagon_wait, void, env, i32) DEF_HELPER_2(resume, void, env, i32) DEF_HELPER_1(resched, void, env) DEF_HELPER_3(modify_ssr, void, env, i32, i32) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index d6ee7c40798..0c341f04936 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -117,7 +117,7 @@ int hex_tlb_check_overlap(CPUHexagonState *env, uint64_= t entry, uint64_t index) } =20 #ifdef CONFIG_HMP -void dump_mmu(MonitorHMP *hmp, CPUHexagonState *env) +void hexagon_dump_mmu(MonitorHMP *hmp, CPUHexagonState *env) { HexagonCPU *cpu =3D env_archcpu(env); hexagon_tlb_dump(hmp, cpu->tlb); diff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h index 56b2c4a89d0..b477bfcc0ad 100644 --- a/target/hexagon/hex_mmu.h +++ b/target/hexagon/hex_mmu.h @@ -24,5 +24,5 @@ extern int hex_tlb_check_overlap(CPUHexagonState *env, ui= nt64_t entry, uint64_t index); extern void hex_tlb_lock(CPUHexagonState *env); extern void hex_tlb_unlock(CPUHexagonState *env); -void dump_mmu(MonitorHMP *hmp, CPUHexagonState *env); +void hexagon_dump_mmu(MonitorHMP *hmp, CPUHexagonState *env); #endif diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 4f00ca773f3..3d55e5674d2 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -93,7 +93,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonSta= te *env, do_raise_exception(env, exception, pc, 0); } =20 -G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t exc= p, +G_NORETURN void HELPER(hexagon_raise_exception)(CPUHexagonState *env, uint= 32_t excp, uint32_t PC) { hexagon_raise_exception_err(env, excp, PC); @@ -1836,7 +1836,7 @@ void HELPER(resched)(CPUHexagonState *env) resched(env); } =20 -void HELPER(wait)(CPUHexagonState *env, uint32_t PC) +void HELPER(hexagon_wait)(CPUHexagonState *env, uint32_t PC) { BQL_LOCK_GUARD(); =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 827859e052c..e58a12dbc5b 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -141,7 +141,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, static void gen_precise_exception(int cause, uint32_t PC) { tcg_gen_movi_i32(hex_cause_code, cause); - gen_helper_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE= ), + gen_helper_hexagon_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT= _PRECISE), tcg_constant_i32(PC)); } =20 @@ -1143,7 +1143,7 @@ static void check_imprecise_exception(DisasContext *c= tx) TCGLabel *label =3D gen_new_label(); =20 tcg_gen_brcondi_tl(TCG_COND_EQ, hex_imprecise_exception, 0, label); - gen_helper_raise_exception(tcg_env, hex_imprecise_exception, PC); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586414938158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index adda363ac39..862097c6c63 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -70,6 +70,13 @@ bool target_aarch64(void); */ bool target_m68k(void); =20 +/** + * target_hexagon: + * + * Returns whether the target architecture is Hexagon. + */ +bool target_hexagon(void); + /** * target_or1k: * diff --git a/target-info.c b/target-info.c index ab43c9f802c..0efa4d32546 100644 --- a/target-info.c +++ b/target-info.c @@ -68,6 +68,11 @@ bool target_m68k(void) return target_arch() =3D=3D SYS_EMU_TARGET_M68K; } =20 +bool target_hexagon(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_HEXAGON; +} + bool target_or1k(void) { return target_arch() =3D=3D SYS_EMU_TARGET_OR1K; --=20 2.43.0 From nobody Thu Oct 22 19:27:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791586447; cv=none; d=zohomail.com; s=zohoarc; b=XGaARVYAiiq4aF/AMyEcjuJs+OZPaQUjvxzxdl5wA/sUr9l7Fn96SpUhlfXKc+u36mYewAUocdjESvqTa+ZMET0zhAQa+Zive5IVucyfC25c2vrSakFMcw+g2c/0W3GXpb1TZaf+/PRup2uhLN3gJH2tFH3Fiiw5V6jshq6PPKU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586449552158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- hw/hexagon/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c index 64d8366d27d..b601cd77a92 100644 --- a/hw/hexagon/virt.c +++ b/hw/hexagon/virt.c @@ -20,6 +20,7 @@ #include "hw/core/register.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" +#include "qemu/target-info.h" #include "qemu/units.h" #include "machine_cfg_v68n_1024.h.inc" #include "system/address-spaces.h" @@ -379,6 +380,7 @@ static const TypeInfo virt_machine_types[] =3D { { .parent =3D TYPE_HEXAGON_COMMON_MACHINE, .instance_size =3D sizeof(HexagonVirtMachineState), .class_init =3D virt_class_init, + .is_available =3D target_hexagon, } }; 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Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- include/hw/core/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 328e30045ce..8160a301978 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -183,8 +183,10 @@ struct CPUClass { /* when system emulation is not available, this pointer is NULL */ const struct SysemuCPUOps *sysemu_ops; =20 +#ifdef CONFIG_TCG /* when TCG is not available, this pointer is NULL */ const TCGCPUOps *tcg_ops; +#endif =20 /* * Keep non-pointer data at the end to minimize holes. --=20 2.43.0 From nobody Thu Oct 22 19:27:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791586444; cv=none; d=zohomail.com; s=zohoarc; b=luv/u9pms44CR6M4EOvLjXUM+FWVnn6wfibyCVklq1R6Vr7mKc6shxWyeo2LzxAMsT9xBgpEBTLjUiPxDcTUhHa6e0DSEvqxr9hPIIm3Y5pmsiF5KlI9wSQwsCqpFGzVuQaTQYzHA+1VQuGD/59uYjYu+d+1+R+CPFSYXaZqUzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791586444; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z4Gf+z2Z/xRdNBBkQnMdoX+cA6AtKlPh6iaz7kKOB+I=; b=IUIut2zW5Vp28duL6emDncATO2ik2M09Xv/t/NjN9OBm5cbPAwNTqg0bWEfYj5Dhj+5s/v89bpx/wMX1BqbeCoobIwsdCt1b0qAsptdVYTHuZ7+llWp1PIQdVGRUWPXTD3j01dQcnMqIgJcjtffxCLQnkM5z1UO/9laKxJxIPQY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179158644420839.33262741197791; Fri, 9 Oct 2026 15:54:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xFJSP-0006Y3-Vg; Fri, 09 Oct 2026 18:52:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSH-0006Vt-Bo for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:45 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSC-0002cg-F4 for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:42 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 699KhWDS2857752 for ; Fri, 9 Oct 2026 22:52:39 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h74t88yfa-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Oct 2026 22:52:38 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-3517ee4b01cso2269851eec.1 for ; Fri, 09 Oct 2026 15:52:38 -0700 (PDT) Received: from debian.qualcomm.com (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586445474158500 Content-Type: text/plain; charset="utf-8" This allows a specific target to declare its implementation of semihosting. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- include/hw/core/cpu.h | 6 ++++++ include/semihosting/common-semi.h | 17 +++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8160a301978..8432c66906d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -98,6 +98,9 @@ struct AccelCPUClass; /* see sysemu-cpu-ops.h */ struct SysemuCPUOps; =20 +/* see semihosting/common-semi.h */ +struct SemihostingCPUOps; + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -186,6 +189,9 @@ struct CPUClass { #ifdef CONFIG_TCG /* when TCG is not available, this pointer is NULL */ const TCGCPUOps *tcg_ops; + + /* when target does not implement semihosting, this pointer is NULL */ + const struct SemihostingCPUOps *semi_ops; #endif =20 /* diff --git a/include/semihosting/common-semi.h b/include/semihosting/common= -semi.h index 1e7699d7bbd..618f60f76e7 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -34,6 +34,23 @@ #ifndef COMMON_SEMI_H #define COMMON_SEMI_H =20 +typedef struct SemihostingCPUOps { + /* Return argument @argno */ + uint64_t (*arg)(CPUState *cs, int argno); + /* Set return value for semihosting call */ + void (*set_ret)(CPUState *cs, uint64_t ret); + /* Set an error for a semihosting call */ + void (*set_err)(CPUState *cs, int err); + /* True if the guest is using the 64-bit semihosting ABI */ + bool (*is_64bit)(CPUState *cs); + /* True if SYS_EXIT takes an extended parameter block */ + bool (*sys_exit_is_extended)(CPUState *cs); + /* Return lowest address until which stack can grow */ + uint64_t (*stack_bottom)(CPUState *cs); + /* True if SYS_SYNCCACHE is implemented */ + bool (*has_synccache)(CPUState *cs); +} SemihostingCPUOps; + void common_semi_cb(CPUState *cs, uint64_t ret, int err); void do_common_semihosting(CPUState *cs); uint64_t common_semi_arg(CPUState *cs, int argno); --=20 2.43.0 From nobody Thu Oct 22 19:27:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791586422; cv=none; d=zohomail.com; s=zohoarc; b=F6PGRqidj7ZQBzg7Yj98P7qh4CpVOVPzLiqoZS/dv2kq2CRrU34SSf1rJjyKpu3EgGtQO6VUrC5JBVznljlRQzt5Oti0MzGwIFvRkzf2BHA1EpwGCJC5GuAL/sLR288kJBFEtXRKzJMOhwTOZCX9lBeyhxrTolxgAzj7s1awAbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791586422; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZC3Um/evFrM0IPjuDis8svXG4Qk4P0SUfU4iVB3HMmo=; b=AhDjfIhzP65/hquPshu/HSgEZpFNxSZHVQSqveaWrNMdZipkA51h1tv4RZsuBK9TuMVrTat5eW/RXBBgZil2KvcM29bVg7TgCb2H9tKiVEfeH4Ho/5tpVRUyn10KoZS8sujDmzvLLGV3ap+ardO9ctpz6CD+JrSaKQqIrgX+fFg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791586422371449.22607222129943; Fri, 9 Oct 2026 15:53:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xFJSj-0006ZV-Jr; Fri, 09 Oct 2026 18:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSH-0006Vv-Dw for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:45 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSD-0002cv-8K for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:42 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 699KhUtk3371057 for ; Fri, 9 Oct 2026 22:52:40 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h74t8h0cf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Oct 2026 22:52:40 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-3425098ae4bso7482920eec.0 for ; Fri, 09 Oct 2026 15:52:39 -0700 (PDT) Received: from debian.qualcomm.com (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586423102158500 Content-Type: text/plain; charset="utf-8" For now, we keep the global common_* symbols defined. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- target/riscv/common-semi-target.c | 62 +++++++++++++++++++++++++++---- target/riscv/cpu.c | 4 ++ target/riscv/internals.h | 2 + 3 files changed, 60 insertions(+), 8 deletions(-) diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-t= arget.c index 38a00e160c3..7fa3bef6883 100644 --- a/target/riscv/common-semi-target.c +++ b/target/riscv/common-semi-target.c @@ -11,43 +11,89 @@ #include "qemu/osdep.h" #include "cpu.h" #include "semihosting/common-semi.h" +#include "internals.h" =20 -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t riscv_semi_arg(CPUState *cs, int argno) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; return env->gpr[xA0 + argno]; } =20 -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void riscv_semi_set_ret(CPUState *cs, uint64_t ret) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; env->gpr[xA0] =3D ret; } =20 +static void riscv_semi_set_err(CPUState *cs, int err) +{ +} + +static bool riscv_semi_is_64bit(CPUState *cs) +{ + return riscv_cpu_mxl(cpu_env(cs)) !=3D MXL_RV32; +} + +static bool riscv_semi_sys_exit_is_extended(CPUState *cs) +{ + return riscv_semi_is_64bit(cs); +} + +static uint64_t riscv_semi_stack_bottom(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + return env->gpr[xSP]; +} + +static bool riscv_semi_has_synccache(CPUState *cs) +{ + return true; +} + +const SemihostingCPUOps riscv_semihosting_ops =3D { + .arg =3D riscv_semi_arg, + .set_ret =3D riscv_semi_set_ret, + .set_err =3D riscv_semi_set_err, + .is_64bit =3D riscv_semi_is_64bit, + .sys_exit_is_extended =3D riscv_semi_sys_exit_is_extended, + .stack_bottom =3D riscv_semi_stack_bottom, + .has_synccache =3D riscv_semi_has_synccache, +}; + +uint64_t common_semi_arg(CPUState *cs, int argno) +{ + return riscv_semi_arg(cs, argno); +} + +void common_semi_set_ret(CPUState *cs, uint64_t ret) +{ + riscv_semi_set_ret(cs, ret); +} + void common_semi_set_err(CPUState *cs, int err) { + riscv_semi_set_err(cs, err); } =20 bool is_64bit_semihosting(CPUArchState *env) { - return riscv_cpu_mxl(env) !=3D MXL_RV32; + return riscv_semi_is_64bit(env_cpu(env)); } =20 bool common_semi_sys_exit_is_extended(CPUState *cs) { - return is_64bit_semihosting(cpu_env(cs)); + return riscv_semi_sys_exit_is_extended(cs); } =20 uint64_t common_semi_stack_bottom(CPUState *cs) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - return env->gpr[xSP]; + return riscv_semi_stack_bottom(cs); } =20 bool common_semi_has_synccache(CPUArchState *env) { - return true; + return riscv_semi_has_synccache(env_cpu(env)); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b9..63c709ac738 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3053,6 +3053,10 @@ static void riscv_cpu_common_class_init(ObjectClass = *c, const void *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_ops =3D &riscv_tcg_ops; +#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_LINUX) + /* semihosting is not supported for bsd-user */ + cc->semi_ops =3D &riscv_semihosting_ops; +#endif #endif /* CONFIG_TCG */ =20 device_class_set_props(dc, riscv_cpu_properties); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586443518158500 Content-Type: text/plain; charset="utf-8" For now, we keep the global common_* symbols defined. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- target/hexagon/common-semi-target.c | 63 ++++++++++++++++++++++++----- target/hexagon/cpu.c | 2 + target/hexagon/internal.h | 2 + 3 files changed, 58 insertions(+), 9 deletions(-) diff --git a/target/hexagon/common-semi-target.c b/target/hexagon/common-se= mi-target.c index 210d33e54e2..b97ed6796f8 100644 --- a/target/hexagon/common-semi-target.c +++ b/target/hexagon/common-semi-target.c @@ -8,44 +8,89 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "cpu_helper.h" #include "semihosting/common-semi.h" +#include "internal.h" =20 -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t hexagon_semi_arg(CPUState *cs, int argno) { CPUHexagonState *env =3D cpu_env(cs); return env->gpr[HEX_REG_R00 + argno]; } =20 -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void hexagon_semi_set_ret(CPUState *cs, uint64_t ret) { CPUHexagonState *env =3D cpu_env(cs); env->gpr[HEX_REG_R00] =3D ret; } =20 -void common_semi_set_err(CPUState *cs, int err) +static void hexagon_semi_set_err(CPUState *cs, int err) { CPUHexagonState *env =3D cpu_env(cs); env->gpr[HEX_REG_R01] =3D err; } =20 -bool common_semi_sys_exit_is_extended(CPUState *cs) +static bool hexagon_semi_is_64bit(CPUState *cs) { return false; } =20 +static bool hexagon_semi_sys_exit_is_extended(CPUState *cs) +{ + return false; +} + +static uint64_t hexagon_semi_stack_bottom(CPUState *cs) +{ + CPUHexagonState *env =3D cpu_env(cs); + return env->gpr[HEX_REG_SP]; +} + +static bool hexagon_semi_has_synccache(CPUState *cs) +{ + return false; +} + +const SemihostingCPUOps hexagon_semihosting_ops =3D { + .arg =3D hexagon_semi_arg, + .set_ret =3D hexagon_semi_set_ret, + .set_err =3D hexagon_semi_set_err, + .is_64bit =3D hexagon_semi_is_64bit, + .sys_exit_is_extended =3D hexagon_semi_sys_exit_is_extended, + .stack_bottom =3D hexagon_semi_stack_bottom, + .has_synccache =3D hexagon_semi_has_synccache, +}; + +uint64_t common_semi_arg(CPUState *cs, int argno) +{ + return hexagon_semi_arg(cs, argno); +} + +void common_semi_set_ret(CPUState *cs, uint64_t ret) +{ + hexagon_semi_set_ret(cs, ret); +} + +void common_semi_set_err(CPUState *cs, int err) +{ + hexagon_semi_set_err(cs, err); +} + bool is_64bit_semihosting(CPUArchState *env) { - return false; + return hexagon_semi_is_64bit(env_cpu(env)); +} + +bool common_semi_sys_exit_is_extended(CPUState *cs) +{ + return hexagon_semi_sys_exit_is_extended(cs); } =20 uint64_t common_semi_stack_bottom(CPUState *cs) { - CPUHexagonState *env =3D cpu_env(cs); - return env->gpr[HEX_REG_SP]; + return hexagon_semi_stack_bottom(cs); } =20 bool common_semi_has_synccache(CPUArchState *env) { - return false; + return hexagon_semi_has_synccache(env_cpu(env)); } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1f7d8a8df70..24e39531b95 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -837,6 +837,8 @@ static void hexagon_cpu_class_init(ObjectClass *c, cons= t void *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &hexagon_sysemu_ops; dc->vmsd =3D &vmstate_hexagon_cpu; + /* semihosting is only supported in system mode for Hexagon */ + cc->semi_ops =3D &hexagon_semihosting_ops; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586461923158500 Content-Type: text/plain; charset="utf-8" For now, we keep the global common_* symbols defined. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- target/arm/common-semi-target.c | 72 +++++++++++++++++++++++++++------ target/arm/cpu.c | 4 ++ target/arm/internals.h | 2 + 3 files changed, 65 insertions(+), 13 deletions(-) diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-targe= t.c index 38d52deb3d6..5263c0435a8 100644 --- a/target/arm/common-semi-target.c +++ b/target/arm/common-semi-target.c @@ -10,9 +10,10 @@ #include "qemu/osdep.h" #include "cpu.h" #include "semihosting/common-semi.h" +#include "internals.h" #include "target/arm/cpu-qom.h" =20 -uint64_t common_semi_arg(CPUState *cs, int argno) +static uint64_t arm_semi_arg(CPUState *cs, int argno) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -23,7 +24,7 @@ uint64_t common_semi_arg(CPUState *cs, int argno) } } =20 -void common_semi_set_ret(CPUState *cs, uint64_t ret) +static void arm_semi_set_ret(CPUState *cs, uint64_t ret) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -34,29 +35,74 @@ void common_semi_set_ret(CPUState *cs, uint64_t ret) } } =20 +static void arm_semi_set_err(CPUState *cs, int err) +{ +} + +static bool arm_semi_is_64bit(CPUState *cs) +{ + return is_a64(cpu_env(cs)); +} + +static bool arm_semi_sys_exit_is_extended(CPUState *cs) +{ + return is_a64(cpu_env(cs)); +} + +static uint64_t arm_semi_stack_bottom(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + return is_a64(env) ? env->xregs[31] : env->regs[13]; +} + +static bool arm_semi_has_synccache(CPUState *cs) +{ + /* Ok for A64, invalid for A32/T32 */ + return is_a64(cpu_env(cs)); +} + +const SemihostingCPUOps arm_semihosting_ops =3D { + .arg =3D arm_semi_arg, + .set_ret =3D arm_semi_set_ret, + .set_err =3D arm_semi_set_err, + .is_64bit =3D arm_semi_is_64bit, + .sys_exit_is_extended =3D arm_semi_sys_exit_is_extended, + .stack_bottom =3D arm_semi_stack_bottom, + .has_synccache =3D arm_semi_has_synccache, +}; + +uint64_t common_semi_arg(CPUState *cs, int argno) +{ + return arm_semi_arg(cs, argno); +} + +void common_semi_set_ret(CPUState *cs, uint64_t ret) +{ + arm_semi_set_ret(cs, ret); +} + void common_semi_set_err(CPUState *cs, int err) { -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return is_a64(cpu_env(cs)); + arm_semi_set_err(cs, err); } =20 bool is_64bit_semihosting(CPUArchState *env) { - return is_a64(env); + return arm_semi_is_64bit(env_cpu(env)); +} + +bool common_semi_sys_exit_is_extended(CPUState *cs) +{ + return arm_semi_sys_exit_is_extended(cs); } =20 uint64_t common_semi_stack_bottom(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - return is_a64(env) ? env->xregs[31] : env->regs[13]; + return arm_semi_stack_bottom(cs); } =20 bool common_semi_has_synccache(CPUArchState *env) { - /* Ok for A64, invalid for A32/T32 */ - return is_a64(env); + return arm_semi_has_synccache(env_cpu(env)); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10ac6c98318..81ec1ce21c6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2663,6 +2663,10 @@ static void arm_cpu_class_init(ObjectClass *oc, cons= t void *data) =20 #ifdef CONFIG_TCG cc->tcg_ops =3D &arm_tcg_ops; +#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_LINUX) + /* semihosting is not supported for bsd-user */ + cc->semi_ops =3D &arm_semihosting_ops; +#endif #endif /* CONFIG_TCG */ } =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index c41fa5225c7..e849e357cfe 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -437,6 +437,8 @@ bool arm_cpu_exec_halt(CPUState *cs); int arm_cpu_mmu_index(CPUState *cs, bool ifetch); #endif /* CONFIG_TCG */ =20 +extern const struct SemihostingCPUOps arm_semihosting_ops; + typedef enum ARMFPRounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, --=20 2.43.0 From nobody Thu Oct 22 19:27:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791586439; cv=none; d=zohomail.com; s=zohoarc; b=N0qXHBZfCP5ZZcK/NWlwd7asihORquPkfLA2pR7FQgntf1Dm7UMt0neprTzSMxcOQS08w2FtBTMUyBVaJx1YE+kESFXYJrQgPiJserpWeS52MV46qHRAjzK2mvh5ke2zmITMLaU/3nnNaV0jJ+1SJEsdqt8203zXhSDNvWv786Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791586439; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7oX7TVg0RpnRFL+qetKSMYVFqsJHy/GthKLLVYhKmBg=; b=NDQ0+ybwX+NeL1RpomN1VDFEj16ZoYqyw3YPQxsawvAOFpW/JM0iLhUVx5MkKSg0pNrk76sExRpBAFqXLrOcXgAstpbXG3m5NxUmg/cTFZYbD4d/u7q1jvDV5+qmXl5+Rh5Q5NsxPb3uHndbAfdKBdo7Q7S9tQ0xVmBMtaw2v0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791586439810290.4170353687599; Fri, 9 Oct 2026 15:53:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xFJSo-0006Zj-Tb; Fri, 09 Oct 2026 18:53:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSK-0006X8-Sk for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:49 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSJ-0002dp-2X for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:48 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 699KiNsG1849864 for ; Fri, 9 Oct 2026 22:52:46 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h74tbh1f1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Oct 2026 22:52:46 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-3425098ae4bso7483042eec.0 for ; Fri, 09 Oct 2026 15:52:45 -0700 (PDT) Received: from debian.qualcomm.com (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586441455158500 Content-Type: text/plain; charset="utf-8" Now that all targets implement this interface, we can replace function calls with the new interface. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- semihosting/arm-compat-semi.c | 56 +++++++++++++++++------------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index b930a028649..3117eadb3b7 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -188,7 +188,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) */ =20 #define GET_ARG(n) do { \ - if (is_64bit_semihosting(env)) { \ + if (cs->cc->semi_ops->is_64bit(cs)) { \ if (get_user_u64(arg ## n, args + (n) * 8)) { \ goto do_fault; \ } \ @@ -200,7 +200,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) } while (0) =20 #define SET_ARG(n, val) \ - (is_64bit_semihosting(env) ? \ + (cs->cc->semi_ops->is_64bit(cs) ? \ put_user_u64(val, args + (n) * 8) : \ put_user_u32(val, args + (n) * 4)) =20 @@ -237,10 +237,10 @@ void common_semi_cb(CPUState *cs, uint64_t ret, int e= rr) ts->swi_errno =3D err; #else syscall_err =3D err; - common_semi_set_err(cs, err); + cs->cc->semi_ops->set_err(cs, err); #endif } - common_semi_set_ret(cs, ret); + cs->cc->semi_ops->set_ret(cs, ret); } =20 /* @@ -249,7 +249,7 @@ void common_semi_cb(CPUState *cs, uint64_t ret, int err) */ static void common_semi_dead_cb(CPUState *cs, uint64_t ret, int err) { - common_semi_set_ret(cs, 0xdeadbeef); + cs->cc->semi_ops->set_ret(cs, 0xdeadbeef); } =20 /* @@ -260,7 +260,7 @@ static void common_semi_rw_cb(CPUState *cs, uint64_t re= t, int err) { /* Recover the original length from the third argument. */ CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); - uint64_t args =3D common_semi_arg(cs, 1); + uint64_t args =3D cs->cc->semi_ops->arg(cs, 1); uint64_t arg2; GET_ARG(2); =20 @@ -268,7 +268,7 @@ static void common_semi_rw_cb(CPUState *cs, uint64_t re= t, int err) do_fault: ret =3D 0; /* error: no bytes transmitted */ } - common_semi_set_ret(cs, arg2 - ret); + cs->cc->semi_ops->set_ret(cs, arg2 - ret); } =20 /* @@ -302,7 +302,7 @@ static void common_semi_seek_cb(CPUState *cs, uint64_t = ret, int err) */ static uint64_t common_semi_flen_buf(CPUState *cs) { - vaddr sp =3D common_semi_stack_bottom(cs); + vaddr sp =3D cs->cc->semi_ops->stack_bottom(cs); return sp - 64; } =20 @@ -330,7 +330,7 @@ common_semi_readc_cb(CPUState *cs, uint64_t ret, int er= r) CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); uint8_t ch; =20 - if (get_user_u8(ch, common_semi_stack_bottom(cs) - 1)) { + if (get_user_u8(ch, cs->cc->semi_ops->stack_bottom(cs) - 1)) { ret =3D -1, err =3D EFAULT; } else { ret =3D ch; @@ -385,7 +385,7 @@ void semihosting_arm_compatible_init(void) */ void do_common_semihosting(CPUState *cs) { - CPUArchState *env =3D cpu_env(cs); + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); uint64_t args; uint64_t arg0, arg1, arg2, arg3; uint64_t ul_ret; @@ -393,8 +393,8 @@ void do_common_semihosting(CPUState *cs) int nr; int64_t elapsed; =20 - nr =3D common_semi_arg(cs, 0) & 0xffffffffU; - args =3D common_semi_arg(cs, 1); + nr =3D cs->cc->semi_ops->arg(cs, 0) & 0xffffffffU; + args =3D cs->cc->semi_ops->arg(cs, 1); =20 switch (nr) { case TARGET_SYS_OPEN: @@ -494,15 +494,15 @@ void do_common_semihosting(CPUState *cs) =20 case TARGET_SYS_READC: semihost_sys_read_gf(cs, common_semi_readc_cb, &console_in_gf, - common_semi_stack_bottom(cs) - 1, 1); + cs->cc->semi_ops->stack_bottom(cs) - 1, 1); break; =20 case TARGET_SYS_ISERROR: { GET_ARG(0); - bool ret =3D is_64bit_semihosting(env) ? + bool ret =3D cs->cc->semi_ops->is_64bit(cs) ? (int64_t)arg0 < 0 : (int32_t)arg0 < 0; - common_semi_set_ret(cs, ret); + cs->cc->semi_ops->set_ret(cs, ret); break; } case TARGET_SYS_ISTTY: @@ -533,7 +533,7 @@ void do_common_semihosting(CPUState *cs) len =3D asprintf(&s, "%s/qemu-%x%02x", g_get_tmp_dir(), getpid(), (int)arg1 & 0xff); if (len < 0) { - common_semi_set_ret(cs, -1); + cs->cc->semi_ops->set_ret(cs, -1); break; } =20 @@ -542,7 +542,7 @@ void do_common_semihosting(CPUState *cs) /* Make sure there's enough space in the buffer */ if (len > arg2) { free(s); - common_semi_set_ret(cs, -1); + cs->cc->semi_ops->set_ret(cs, -1); break; } p =3D lock_user(VERIFY_WRITE, arg0, len, 0); @@ -553,7 +553,7 @@ void do_common_semihosting(CPUState *cs) memcpy(p, s, len); unlock_user(p, arg0, len); free(s); - common_semi_set_ret(cs, 0); + cs->cc->semi_ops->set_ret(cs, 0); break; } =20 @@ -572,7 +572,7 @@ void do_common_semihosting(CPUState *cs) break; =20 case TARGET_SYS_CLOCK: - common_semi_set_ret(cs, clock() / (CLOCKS_PER_SEC / 100)); + cs->cc->semi_ops->set_ret(cs, clock() / (CLOCKS_PER_SEC / 100)); break; =20 case TARGET_SYS_TIME: @@ -587,7 +587,7 @@ void do_common_semihosting(CPUState *cs) break; =20 case TARGET_SYS_ERRNO: - common_semi_set_ret(cs, get_swi_errno(cs)); + cs->cc->semi_ops->set_ret(cs, get_swi_errno(cs)); break; =20 case TARGET_SYS_GET_CMDLINE: @@ -734,7 +734,7 @@ void do_common_semihosting(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(retvals); i++) { bool fail; =20 - if (is_64bit_semihosting(env)) { + if (cs->cc->semi_ops->is_64bit(cs)) { fail =3D put_user_u64(retvals[i], arg0 + i * 8); } else { fail =3D put_user_u32(retvals[i], arg0 + i * 4); @@ -745,7 +745,7 @@ void do_common_semihosting(CPUState *cs) goto do_fault; } } - common_semi_set_ret(cs, 0); + cs->cc->semi_ops->set_ret(cs, 0); } break; =20 @@ -755,7 +755,7 @@ void do_common_semihosting(CPUState *cs) uint32_t ret; =20 if (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || - common_semi_sys_exit_is_extended(cs)) { + cs->cc->semi_ops->sys_exit_is_extended(cs)) { /* * The A64 version of SYS_EXIT takes a parameter block, * so the application-exit type can return a subcode which @@ -786,7 +786,7 @@ void do_common_semihosting(CPUState *cs) =20 case TARGET_SYS_ELAPSED: elapsed =3D get_clock() - clock_start; - if (is_64bit_semihosting(env)) { + if (cs->cc->semi_ops->is_64bit(cs)) { if (SET_ARG(0, elapsed)) { goto do_fault; } @@ -796,12 +796,12 @@ void do_common_semihosting(CPUState *cs) goto do_fault; } } - common_semi_set_ret(cs, 0); + cs->cc->semi_ops->set_ret(cs, 0); break; =20 case TARGET_SYS_TICKFREQ: /* qemu always uses nsec */ - common_semi_set_ret(cs, 1000000000); + cs->cc->semi_ops->set_ret(cs, 1000000000); break; =20 case TARGET_SYS_SYNCCACHE: @@ -810,8 +810,8 @@ void do_common_semihosting(CPUState *cs) * virtual address range. This is a nop for us since we don't * implement caches. This is only present on A64. */ - if (common_semi_has_synccache(env)) { - common_semi_set_ret(cs, 0); + if (cs->cc->semi_ops->has_synccache(cs)) { + cs->cc->semi_ops->set_ret(cs, 0); break; } /* fall through */ --=20 2.43.0 From nobody Thu Oct 22 19:27:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791586418; cv=none; d=zohomail.com; s=zohoarc; b=DGX1rPNrQ1SKyUZjk8o32cd826/Wz7fOci37scrWT0dTPPE6DOD3+5Z27fNuBsgOyhr9wwrb7Fcbn8fWNUIHWT5d5mN/+8DhW0+t1EU1b6d54mH2Ls/dcVsYqhqLijSDdopBS7u+pIgriodLPSZJ/8ukny3nf2wJOzXstUxS5NM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791586418; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J9GysZY5RssDPBWWoApI6NRazDIO4o3udQj9mkDoCRY=; b=NW8AsPsh1gcJnjh0uNjCijenStuGRE5Hft9wT3PWYMoT2Eg3svwXfm5PeWwpFiJWvH7x7o1JNg15EJkfRovGIdDkioQgGDx2F0e6vCvHaAWBH5uU17zpRXcUoo9zXXZRUkT70Dq6mUS8RMEkjV2ilyV+zUpslkfwKw18iQm/u3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791586418737958.2672291417867; Fri, 9 Oct 2026 15:53:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xFJSS-0006YB-Ry; Fri, 09 Oct 2026 18:52:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSL-0006XB-Tl for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:51 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFJSK-0002e2-3x for qemu-devel@nongnu.org; Fri, 09 Oct 2026 18:52:49 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 699KhksW2021214 for ; Fri, 9 Oct 2026 22:52:46 GMT Received: from mail-dl1-f69.google.com (mail-dl1-f69.google.com [74.125.82.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h74t710ff-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Oct 2026 22:52:46 +0000 (GMT) Received: by mail-dl1-f69.google.com with SMTP id a92af1059eb24-14fed306427so673452c88.1 for ; Fri, 09 Oct 2026 15:52:46 -0700 (PDT) Received: from debian.qualcomm.com (192-80-163-190.dyn.novuscom.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586419184158500 Content-Type: text/plain; charset="utf-8" Now that both targets and semihosting implementation both use the semihosting ops interface, we can remove all common_* functions. This allows us to link together the three targets concerned: arm, hexagon and riscv. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- include/semihosting/common-semi.h | 7 ------ target/arm/common-semi-target.c | 35 ----------------------------- target/hexagon/common-semi-target.c | 35 ----------------------------- target/riscv/common-semi-target.c | 35 ----------------------------- 4 files changed, 112 deletions(-) diff --git a/include/semihosting/common-semi.h b/include/semihosting/common= -semi.h index 618f60f76e7..8875aec3c86 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -53,12 +53,5 @@ typedef struct SemihostingCPUOps { =20 void common_semi_cb(CPUState *cs, uint64_t ret, int err); void do_common_semihosting(CPUState *cs); -uint64_t common_semi_arg(CPUState *cs, int argno); -void common_semi_set_ret(CPUState *cs, uint64_t ret); -void common_semi_set_err(CPUState *cs, int err); -bool is_64bit_semihosting(CPUArchState *env); -bool common_semi_sys_exit_is_extended(CPUState *cs); -uint64_t common_semi_stack_bottom(CPUState *cs); -bool common_semi_has_synccache(CPUArchState *env); =20 #endif /* COMMON_SEMI_H */ diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-targe= t.c index 5263c0435a8..aa5190ee16c 100644 --- a/target/arm/common-semi-target.c +++ b/target/arm/common-semi-target.c @@ -71,38 +71,3 @@ const SemihostingCPUOps arm_semihosting_ops =3D { .stack_bottom =3D arm_semi_stack_bottom, .has_synccache =3D arm_semi_has_synccache, }; - -uint64_t common_semi_arg(CPUState *cs, int argno) -{ - return arm_semi_arg(cs, argno); -} - -void common_semi_set_ret(CPUState *cs, uint64_t ret) -{ - arm_semi_set_ret(cs, ret); -} - -void common_semi_set_err(CPUState *cs, int err) -{ - arm_semi_set_err(cs, err); -} - -bool is_64bit_semihosting(CPUArchState *env) -{ - return arm_semi_is_64bit(env_cpu(env)); -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return arm_semi_sys_exit_is_extended(cs); -} - -uint64_t common_semi_stack_bottom(CPUState *cs) -{ - return arm_semi_stack_bottom(cs); -} - -bool common_semi_has_synccache(CPUArchState *env) -{ - return arm_semi_has_synccache(env_cpu(env)); -} diff --git a/target/hexagon/common-semi-target.c b/target/hexagon/common-se= mi-target.c index b97ed6796f8..0a33b872e3a 100644 --- a/target/hexagon/common-semi-target.c +++ b/target/hexagon/common-semi-target.c @@ -59,38 +59,3 @@ const SemihostingCPUOps hexagon_semihosting_ops =3D { .stack_bottom =3D hexagon_semi_stack_bottom, .has_synccache =3D hexagon_semi_has_synccache, }; - -uint64_t common_semi_arg(CPUState *cs, int argno) -{ - return hexagon_semi_arg(cs, argno); -} - -void common_semi_set_ret(CPUState *cs, uint64_t ret) -{ - hexagon_semi_set_ret(cs, ret); -} - -void common_semi_set_err(CPUState *cs, int err) -{ - hexagon_semi_set_err(cs, err); -} - -bool is_64bit_semihosting(CPUArchState *env) -{ - return hexagon_semi_is_64bit(env_cpu(env)); -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return hexagon_semi_sys_exit_is_extended(cs); -} - -uint64_t common_semi_stack_bottom(CPUState *cs) -{ - return hexagon_semi_stack_bottom(cs); -} - -bool common_semi_has_synccache(CPUArchState *env) -{ - return hexagon_semi_has_synccache(env_cpu(env)); -} diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-t= arget.c index 7fa3bef6883..24c42254558 100644 --- a/target/riscv/common-semi-target.c +++ b/target/riscv/common-semi-target.c @@ -62,38 +62,3 @@ const SemihostingCPUOps riscv_semihosting_ops =3D { .stack_bottom =3D riscv_semi_stack_bottom, .has_synccache =3D riscv_semi_has_synccache, }; - -uint64_t common_semi_arg(CPUState *cs, int argno) -{ - return riscv_semi_arg(cs, argno); -} - -void common_semi_set_ret(CPUState *cs, uint64_t ret) -{ - riscv_semi_set_ret(cs, ret); -} - -void common_semi_set_err(CPUState *cs, int err) -{ - riscv_semi_set_err(cs, err); -} - -bool is_64bit_semihosting(CPUArchState *env) -{ - return riscv_semi_is_64bit(env_cpu(env)); -} - -bool common_semi_sys_exit_is_extended(CPUState *cs) -{ - return riscv_semi_sys_exit_is_extended(cs); -} - -uint64_t common_semi_stack_bottom(CPUState *cs) -{ - return riscv_semi_stack_bottom(cs); -} - -bool common_semi_has_synccache(CPUArchState *env) -{ - return riscv_semi_has_synccache(env_cpu(env)); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1791586396659158500 Content-Type: text/plain; charset="utf-8" Now that semihosting is solved, hexagon can join the list of target compatible with others. Signed-off-by: Pierrick Bouvier Reviewed-by: Brian Cain --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index 48da6cf3e6b..367f3b296c3 100644 --- a/meson.build +++ b/meson.build @@ -4273,6 +4273,7 @@ multi_target_supported_targets =3D [ 'alpha-softmmu', 'arm-softmmu', 'avr-softmmu', + 'hexagon-softmmu', 'hppa-softmmu', 'm68k-softmmu', 'microblaze-softmmu', --=20 2.43.0