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However, libgpiod configures those pins in EINT mode (CFG 0x06) when gpiomon is used, so this patch fixes interrupt path to expect pin configuration to be set to EINT. Signed-off-by: Strahinja Jankovic --- hw/gpio/allwinner-gpio.c | 19 ++++++++++++++----- include/hw/gpio/allwinner-gpio-regs.h | 5 +---- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/gpio/allwinner-gpio.c b/hw/gpio/allwinner-gpio.c index e3bda7cb76..19176e7c56 100644 --- a/hw/gpio/allwinner-gpio.c +++ b/hw/gpio/allwinner-gpio.c @@ -114,7 +114,7 @@ static inline bool gpio_is_output(AWPortMap *port, uint= 32_t pin) uint32_t cfg_n =3D pin / CFG_PINS_PER_REG; uint32_t pin_shift =3D (pin % CFG_PINS_PER_REG) * CFG_PIN_STRIDE; return (extract32(port->cfg[cfg_n], pin_shift, CFG_PIN_STRIDE - 1) =3D= =3D - CFG_OUTPUT_MASK); + AW_GPIO_CFG_OUT); } =20 static inline bool gpio_is_input(AWPortMap *port, uint32_t pin) @@ -122,7 +122,15 @@ static inline bool gpio_is_input(AWPortMap *port, uint= 32_t pin) uint32_t cfg_n =3D pin / CFG_PINS_PER_REG; uint32_t pin_shift =3D (pin % CFG_PINS_PER_REG) * CFG_PIN_STRIDE; return (extract32(port->cfg[cfg_n], pin_shift, CFG_PIN_STRIDE - 1) =3D= =3D - CFG_INPUT_MASK); + AW_GPIO_CFG_IN); +} + +static inline bool gpio_is_eint(AWPortMap *port, uint32_t pin) +{ + uint32_t cfg_n =3D pin / CFG_PINS_PER_REG; + uint32_t pin_shift =3D (pin % CFG_PINS_PER_REG) * CFG_PIN_STRIDE; + return (extract32(port->cfg[cfg_n], pin_shift, CFG_PIN_STRIDE - 1) =3D= =3D + AW_GPIO_CFG_EINT); } =20 static inline int int_ctl_cfg(AWGPIOState *s, int irq_line) @@ -155,8 +163,8 @@ static void allwinner_gpio_set_int_line(AWGPIOState *s,= int port, return; } =20 - /* if this signal isn't configured as an input signal, nothing to do */ - if (!gpio_is_input(&o->ports[port], line)) { + /* if this signal isn't configured as an EINT, nothing to do */ + if (!gpio_is_eint(&o->ports[port], line)) { return; } =20 @@ -225,7 +233,8 @@ static void allwinner_gpio_set(void *opaque, int port, = int line, int level) AWPortsOverlay *o =3D (AWPortsOverlay *)s->regs; AWGPIOLevel aw_level =3D level ? AW_GPIO_LEVEL_HIGH : AW_GPIO_LEVEL_LO= W; =20 - if (gpio_is_input(&o->ports[port], line)) { + if (gpio_is_input(&o->ports[port], line) || + gpio_is_eint(&o->ports[port], line)) { =20 trace_allwinner_gpio_set(portname(port), line, aw_level); =20 diff --git a/include/hw/gpio/allwinner-gpio-regs.h b/include/hw/gpio/allwin= ner-gpio-regs.h index a435b87ec4..5e969c23f6 100644 --- a/include/hw/gpio/allwinner-gpio-regs.h +++ b/include/hw/gpio/allwinner-gpio-regs.h @@ -73,9 +73,6 @@ static const AWPortResetVals aw_gpio_port_reset[] =3D { #define DEFAULT_DRV_MASK 0xffffffff #define DEFAULT_PUL_MASK 0xffffffff =20 -#define CFG_INPUT_MASK 0x0 -#define CFG_OUTPUT_MASK 0x1 -#define CFG_IO_MASK 0x1 #define CFG_PIN_STRIDE 4 #define CFG_PINS_PER_REG (AW_GPIO_PIN_COUNT / CFG_PIN_STRIDE) =20 @@ -172,7 +169,7 @@ typedef enum AWGPIOLevel { typedef enum AWGPIOCfg { AW_GPIO_CFG_IN =3D 0, AW_GPIO_CFG_OUT =3D 1, - AW_GPIO_CFG_FUN =3D 2, + AW_GPIO_CFG_EINT =3D 6, } AWGPIOCfg; =20 typedef enum AWGPIOIrqCfg { --=20 2.56.0 From nobody Thu Oct 22 19:25:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791563246094723.3009284703147; Fri, 9 Oct 2026 09:27:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xFDQZ-0004r9-5S; Fri, 09 Oct 2026 12:26:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xFDQW-0004ow-TY for qemu-devel@nongnu.org; Fri, 09 Oct 2026 12:26:33 -0400 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1xFDQU-0004qq-GO for qemu-devel@nongnu.org; Fri, 09 Oct 2026 12:26:32 -0400 Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-5ba35c0df4fso4430671e87.0 for ; Fri, 09 Oct 2026 09:26:30 -0700 (PDT) Received: from [192.168.31.141] (213-65-111-204-no600.tbcn.telia.com. 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Also add test the configures pin to input mode and validates that manipulating input pin changed value in DAT register. Signed-off-by: Strahinja Jankovic --- tests/qtest/allwinner-gpio-test.c | 57 ++++++++++++++++++++++++++++-------= ---- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/tests/qtest/allwinner-gpio-test.c b/tests/qtest/allwinner-gpio= -test.c index c048f0f88b..5c4a148d82 100644 --- a/tests/qtest/allwinner-gpio-test.c +++ b/tests/qtest/allwinner-gpio-test.c @@ -238,6 +238,32 @@ static void test_set_input_pins(const void *data) qtest_quit(s); } =20 +/* + * Set pin to input, check that the value is written to DAT register + */ +static void test_get_input_pins(const void *data) +{ + PortPinTestParam *param =3D (PortPinTestParam *)data; + g_autofree char *in_name =3D portname_in(param->port); + + QTestState *s =3D qtest_init("-machine cubieboard"); + + /* Configure pin as input */ + update_cfg_reg(s, param->port, param->pin, AW_GPIO_CFG_IN); + qtest_set_irq_in(s, + "/machine/soc/gpio", in_name, param->pin, + AW_GPIO_LEVEL_LOW); + assert_data_reg(s, param->port, param->pin, AW_GPIO_LEVEL_LOW); + + /* Change input value */ + qtest_set_irq_in(s, + "/machine/soc/gpio", in_name, param->pin, + AW_GPIO_LEVEL_HIGH); + assert_data_reg(s, param->port, param->pin, AW_GPIO_LEVEL_HIGH); + + qtest_quit(s); +} + /* Test rising edge interrupt */ static void test_irq_pin_rising(const void *data) { @@ -251,9 +277,9 @@ static void test_irq_pin_rising(const void *data) =20 qtest_irq_intercept_in(s, "/machine/soc"); =20 - /* Configure as input and set pin low */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin low */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_LOW); @@ -296,9 +322,9 @@ static void test_irq_pin_falling(const void *data) =20 qtest_irq_intercept_in(s, "/machine/soc"); =20 - /* Configure as input and set pin high */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin high */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_HIGH); @@ -341,9 +367,9 @@ static void test_irq_pin_high_level(const void *data) =20 qtest_irq_intercept_in(s, "/machine/soc"); =20 - /* Configure as input and set pin low */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin low */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_LOW); @@ -394,9 +420,9 @@ static void test_irq_pin_low_level(const void *data) =20 qtest_irq_intercept_in(s, "/machine/soc"); =20 - /* Configure as input and set pin high */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin high */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_HIGH); @@ -447,9 +473,9 @@ static void test_irq_pin_both_edge(const void *data) =20 qtest_irq_intercept_in(s, "/machine/soc"); =20 - /* Configure as input and set pin low */ - update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_IN); - assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_IN); + /* Configure as EINT and set pin low */ + update_cfg_reg(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); + assert_cfg_regval(s, gpio_port, port_pin, AW_GPIO_CFG_EINT); qtest_set_irq_in(s, "/machine/soc/gpio", in_name, port_pin, AW_GPIO_LEVEL_LOW); @@ -518,6 +544,7 @@ int main(int argc, char **argv) const PortPinTestParam *p =3D &in_out_test_parameters[i]; add_test("set_output_pins", p, test_set_output_pins); add_test("set_input_pins", p, test_set_input_pins); + add_test("get_input_pins", p, test_get_input_pins); } qtest_add_func("/allwinner-cubieboard/gpio/reset_values", test_reset_values); --=20 2.56.0