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Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- configs/targets/hexagon-softmmu.mak | 2 +- gdbstub/gdb-xml/hexagon-sys.xml | 157 ++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 gdbstub/gdb-xml/hexagon-sys.xml diff --git a/configs/targets/hexagon-softmmu.mak b/configs/targets/hexagon-= softmmu.mak index 6cbdc64be56..1ba6420d205 100644 --- a/configs/targets/hexagon-softmmu.mak +++ b/configs/targets/hexagon-softmmu.mak @@ -1,7 +1,7 @@ # Default configuration for hexagon-softmmu =20 TARGET_ARCH=3Dhexagon -TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml +TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml hexagon-sys.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/gdbstub/gdb-xml/hexagon-sys.xml b/gdbstub/gdb-xml/hexagon-sys.= xml new file mode 100644 index 00000000000..273850a733f --- /dev/null +++ b/gdbstub/gdb-xml/hexagon-sys.xml @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.34.1 From nobody Sat Oct 24 00:33:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1791169597; cv=none; d=zohomail.com; s=zohoarc; b=k6wxsHZnamtOpbYMUBhnRUVJN0JTKyIYrhTfHwuHMzywWwF4QVfIM1fQ7+A4W6Bdg701Kun9YMuff5lrAwZEXUORADb/1ImUtxZ3GVNiIOgXtNGuNKM2S6RuklzCNFvXOJftn+c0vTyBLkCBKW7oz7y7XajlEI2ZIqRGjNZHXUI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791169597; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=R3QFNitgaeqnytPkPxznMj55KhvEIwRdFm3cfN9IhC8=; b=NjXOH2DoCubm1JjRu3R3+Yn1BOKA8U/P8RT7chyyktUjmpy/55wri4VBf4bhLmtGILk2l468zmF6PnUSXmganymt2tKimOTHsfQ935WheSOeLyhhO4/Rr/iGjPcpDTqfi2ntzVgOhdF0Qe2sgtqOCfhO67e9tO5hEEpVVdIqE4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1791169597461475.2912540995502; Sun, 4 Oct 2026 20:06:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xDZ1X-0000kX-8O; Sun, 04 Oct 2026 23:05:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xDZ1S-0000js-Uc for qemu-devel@nongnu.org; Sun, 04 Oct 2026 23:05:52 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xDZ1P-0007tg-7t for qemu-devel@nongnu.org; Sun, 04 Oct 2026 23:05:50 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69510HDx4061317 for ; Mon, 5 Oct 2026 03:05:46 GMT Received: from mail-dl1-f72.google.com (mail-dl1-f72.google.com [74.125.82.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h41gn87sf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 05 Oct 2026 03:05:45 +0000 (GMT) Received: by mail-dl1-f72.google.com with SMTP id a92af1059eb24-149e8e8ad71so182747c88.1 for ; Sun, 04 Oct 2026 20:05:45 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/internal.h | 4 +++ target/hexagon/cpu.c | 13 ++++++-- target/hexagon/gdbstub.c | 63 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index df4c0182247..ea54af621d2 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -241,6 +241,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, */ bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); +void hexagon_greg_write(CPUHexagonState *env, uint32_t reg, uint32_t val); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif =20 diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 05d1129916e..3ed83904eb7 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -24,6 +24,10 @@ int hexagon_gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int = n); int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n= ); +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +#endif =20 void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1f7d8a8df70..ec4ced7e3c3 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -494,6 +494,10 @@ static void hexagon_cpu_realize(DeviceState *dev, Erro= r **errp) gdb_find_static_feature("hexagon-hvx.xml")); =20 #ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, hexagon_sys_gdb_read_register, + hexagon_sys_gdb_write_register, + gdb_find_static_feature("hexagon-sys.xml")); + if (!HEXAGON_CPU(dev)->tlb) { error_setg(errp, "hexagon cpu requires 'tlb' link property to be s= et"); return; @@ -858,11 +862,14 @@ uint32_t hexagon_greg_read(CPUHexagonState *env, uint= 32_t reg) case HEX_GREG_GPCYCLEHI: return ssr_ce ? hexagon_get_sys_pcycle_count_high(env) : 0; default: - qemu_log_mask(LOG_UNIMP, "reading greg %" PRId32 - " not yet supported.\n", reg); - return 0; + return env->greg[reg]; } } + +void hexagon_greg_write(CPUHexagonState *env, uint32_t reg, uint32_t val) +{ + env->greg[reg] =3D val; +} #endif =20 static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data) diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 76ab5235f6e..30b4d710cdb 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -16,9 +16,14 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "gdbstub/helpers.h" #include "cpu.h" #include "internal.h" +#ifndef CONFIG_USER_ONLY +#include "cpu_helper.h" +#include "hw/hexagon/hexagon_globalreg.h" +#endif =20 int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { @@ -76,6 +81,64 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) g_assert_not_reached(); } =20 +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + CPUHexagonState *env =3D cpu_env(cs); + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); + + if (n < NUM_SREGS) { + uint32_t val; + if (n < HEX_SREG_GLB_START) { + val =3D env->t_sreg[n]; + } else { + val =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, n, env->threadId) = : 0; + } + return gdb_get_regl(mem_buf, val); + } + n -=3D NUM_SREGS; + + if (n < NUM_GREGS) { + return gdb_get_regl(mem_buf, hexagon_greg_read(env, n)); + } + n -=3D NUM_GREGS; + + g_assert_not_reached(); +} + +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CPUHexagonState *env =3D cpu_env(cs); + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); + + if (n < NUM_SREGS) { + uint32_t val =3D ldl_le_p(mem_buf); + if (n =3D=3D HEX_SREG_SSR) { + uint32_t old =3D env->t_sreg[HEX_SREG_SSR]; + env->t_sreg[HEX_SREG_SSR] =3D val; + hexagon_modify_ssr(env, val, old); + } else if (n < HEX_SREG_GLB_START) { + env->t_sreg[n] =3D val; + } else if (cpu->globalregs) { + hexagon_globalreg_write(cpu->globalregs, n, val, env->threadId= ); + } + return sizeof(uint32_t); + } + n -=3D NUM_SREGS; + + if (n < NUM_GREGS) { + hexagon_greg_write(env, n, ldl_le_p(mem_buf)); + return sizeof(uint32_t); + } + n -=3D NUM_GREGS; + + g_assert_not_reached(); +} +#endif + static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n) { int total =3D 0; --=20 2.34.1