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Wed, 30 Sep 2026 20:17:34 -0700 (PDT) From: 'Portia Stephens To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Portia Stephens , Nicholas Piggin , Michael Ellerman , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Chao Liu , Anirudh Srinivasan , Alistair Francis , Paolo Bonzini , Joel Stanley , Liu Zhiwei , Palmer Dabbelt , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Weiwei Li Subject: [PATCH v2 1/4] hw/riscv/atlantis: Use dw8250 UART model Date: Thu, 1 Oct 2026 13:17:17 +1000 Message-ID: <20261001031720.2334056-2-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001031720.2334056-1-portias@oss.tenstorrent.com> References: <20261001031720.2334056-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=portias@tenstorrent.com; helo=mail-pj2-x11.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790824686316158500 Content-Type: text/plain; charset="utf-8" From: Portia Stephens Replace the ns16550 UART with a Designware UART now that a model is available. The hack which sets the rest of the UART register space as unimplemented can be removed. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza --- hw/riscv/Kconfig | 2 +- hw/riscv/tt_atlantis.c | 45 +++++++++++----------------------- include/hw/riscv/tt_atlantis.h | 4 +-- 3 files changed, 17 insertions(+), 34 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d06ac26648..5d2abdbb67 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -127,7 +127,7 @@ config TENSTORRENT select RISCV_ACLINT select RISCV_APLIC select RISCV_IMSIC - select SERIAL_MM + select DW8250 select DEVICE_TREE select DESIGNWARE_I2C select DS1338 diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8a219afef7..70815e12ef 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -24,9 +24,8 @@ #include "hw/riscv/fdt-common.h" #include "hw/riscv/riscv_hart.h" =20 -#include "hw/char/serial-mm.h" +#include "hw/char/dw8250.h" #include "hw/intc/riscv_aclint.h" -#include "hw/misc/unimp.h" =20 #include "system/system.h" #include "system/device_tree.h" @@ -262,11 +261,15 @@ static void create_fdt_cpu(void *fdt, TTAtlantisSoCSt= ate *s, static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, int irqchip_phandle) { + static const char * const compat[2] =3D { + "snps,dw-apb-uart", "ns16550a" + }; g_autofree char *name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIX, mem->base); =20 qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_string_array(fdt, name, "compatible", + (char **)&compat, ARRAY_SIZE(compat)); qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2); qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4); @@ -409,17 +412,6 @@ static void load_fdt(TTAtlantisState *ams) create_fdt_memory(ms->fdt, &ams->soc); } =20 -static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, - const char *name, hwaddr addr, uint64_t= size) -{ - qdev_prop_set_string(DEVICE(dev), "name", name); - qdev_prop_set_uint64(DEVICE(dev), "size", size); - sysbus_realize(dev, &error_abort); - - memory_region_add_subregion_overlap(memory, addr, - sysbus_mmio_get_region(dev, 0), -1= 000); -} - static void tt_atlantis_machine_done(Notifier *n, void *data) { TTAtlantisState *ams =3D container_of(n, TTAtlantisState, machine_done= ); @@ -488,8 +480,7 @@ static void tt_atlantis_soc_init(Object *obj) =20 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); =20 - object_initialize_child(obj, "uart1", &s->uart1, - TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "uart1", &s->uart1, TYPE_DW8250); =20 for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { object_initialize_child(obj, "i2c[*]", &s->i2c[i], @@ -584,21 +575,13 @@ static void tt_atlantis_soc_realize(DeviceState *dev,= Error **errp) &s->bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ - serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, - qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), - 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); - /* - * Atlantis contains a DesignWare uart while the QEMU machine - * uses the serial_mm model with the base ns16550 register set. - * Linux's dw driver writes outside of serial_mm's 0x20 sized - * mapping and faults. - * - * Create an unimplemented device region so writes don't fault - * and reads return zero, which keeps Linux happy. - */ - mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), - "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, - s->memmap[TT_ATL_UART1].size); + qdev_prop_set_chr(DEVICE(&s->uart1), "chardev", serial_hd(0)); + sysbus_realize(SYS_BUS_DEVICE(&s->uart1), &error_fatal); + memory_region_add_subregion(s->memory, + s->memmap[TT_ATL_UART1].base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->= uart1), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart1), 0, + qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ)); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 3923308b7c..000988c037 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -13,7 +13,7 @@ #include "hw/core/sysbus.h" #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" -#include "hw/misc/unimp.h" +#include "hw/char/dw8250.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -39,7 +39,7 @@ struct TTAtlantisSoCState { RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; 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Wed, 30 Sep 2026 20:17:39 -0700 (PDT) From: 'Portia Stephens To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Portia Stephens , Nicholas Piggin , Michael Ellerman , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Chao Liu , Anirudh Srinivasan , Alistair Francis , Paolo Bonzini , Joel Stanley , Liu Zhiwei , Palmer Dabbelt , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Weiwei Li Subject: [PATCH v2 2/4] hw/riscv/atlantis: Add all UARTs for Atlantis SoC Date: Thu, 1 Oct 2026 13:17:18 +1000 Message-ID: <20261001031720.2334056-3-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001031720.2334056-1-portias@oss.tenstorrent.com> References: <20261001031720.2334056-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=portias@tenstorrent.com; helo=mail-pj2-x11.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790824712364158500 Content-Type: text/plain; charset="utf-8" From: Portia Stephens Previously only the Ascalon console UART was enabled, this enables all 5 UARTs on the SoC. Only UART1 is added to the serial interface for now. The next change will handle adding the rest of the UARTs. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza --- hw/riscv/tt_atlantis.c | 54 +++++++++++++++++++++++++--------- include/hw/riscv/tt_atlantis.h | 11 ++++++- 2 files changed, 50 insertions(+), 15 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 70815e12ef..2342edce93 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -62,7 +62,11 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_I2C2] =3D { 0xd4060000, 0x10000 }, [TT_ATL_I2C3] =3D { 0xd4070000, 0x10000 }, [TT_ATL_I2C4] =3D { 0xd4080000, 0x10000 }, + [TT_ATL_UART0] =3D { 0xd4100000, 0x10000 }, [TT_ATL_UART1] =3D { 0xd4110000, 0x10000 }, + [TT_ATL_UART2] =3D { 0xd4120000, 0x10000 }, + [TT_ATL_UART3] =3D { 0xd4130000, 0x10000 }, + [TT_ATL_UART4] =3D { 0xd4140000, 0x10000 }, [TT_ATL_SAPLIC] =3D { 0xe8000000, 0x4000000 }, [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, }; @@ -259,13 +263,14 @@ static void create_fdt_cpu(void *fdt, TTAtlantisSoCSt= ate *s, } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, - int irqchip_phandle) + int irqchip_phandle, int index) { static const char * const compat[2] =3D { "snps,dw-apb-uart", "ns16550a" }; g_autofree char *name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIX, mem->base); + g_autofree char *alias =3D g_strdup_printf("serial%d", index); =20 qemu_fdt_add_subnode(fdt, name); qemu_fdt_setprop_string_array(fdt, name, "compatible", @@ -277,8 +282,10 @@ static void create_fdt_uart(void *fdt, const MemMapEnt= ry *mem, int irq, qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); =20 - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); - qemu_fdt_setprop_string(fdt, "/aliases", "serial0", name); + if (index =3D=3D 0) { + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); + } + qemu_fdt_setprop_string(fdt, "/aliases", alias, name); } =20 static void create_fdt_rng(void *fdt) @@ -347,8 +354,11 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState= *s) * aplic_s_phandle); */ =20 - create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ, - aplic_s_phandle); + /* Skip UART0 since it is the RCPU console, UART1 is the Ascalon conso= le */ + for (int i =3D 0; i < TT_ATL_NUM_UARTS - 1; i++) { + create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1 + i], TT_ATL_UART1_IR= Q + i, + aplic_s_phandle, i); + } =20 create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); =20 @@ -474,13 +484,21 @@ static void tt_atlantis_machine_done(Notifier *n, voi= d *data) fdt_load_addr); } =20 +static inline int tt_atlantis_uart_index(int uart_dev) +{ + return uart_dev - TT_ATL_UART0; +} + static void tt_atlantis_soc_init(Object *obj) { TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(obj); =20 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); =20 - object_initialize_child(obj, "uart1", &s->uart1, TYPE_DW8250); + for (int i =3D 0; i < TT_ATL_NUM_UARTS; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], + TYPE_DW8250); + } =20 for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { object_initialize_child(obj, "i2c[*]", &s->i2c[i], @@ -574,14 +592,22 @@ static void tt_atlantis_soc_realize(DeviceState *dev,= Error **errp) memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, &s->bootrom); =20 - /* UART1, the soc console (UART0 is for the boot microcontroller) */ - qdev_prop_set_chr(DEVICE(&s->uart1), "chardev", serial_hd(0)); - sysbus_realize(SYS_BUS_DEVICE(&s->uart1), &error_fatal); - memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_UART1].base, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->= uart1), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart1), 0, - qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ)); + /* UART1, the soc console (UART0 is for the boot microcontroller */ + qdev_prop_set_chr(DEVICE(&s->uart[tt_atlantis_uart_index(TT_ATL_UART1)= ]), + "chardev", serial_hd(0)); + + for (int i =3D 0; i < TT_ATL_NUM_UARTS; i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->uart[i]); + if (!sysbus_realize(sbd, errp)) { + return; + } + + memory_region_add_subregion(s->memory, + s->memmap[TT_ATL_UART0 + i].base, + sysbus_mmio_get_region(sbd, 0)); + sysbus_connect_irq(sbd, 0, + qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ += i)); + } =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 000988c037..b81b7c8abd 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -23,6 +23,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_M= ACHINE) OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) =20 #define TT_ATL_NUM_I2C 5 +#define TT_ATL_NUM_UARTS 5 =20 struct TTAtlantisSoCState { /*< private >*/ @@ -39,7 +40,7 @@ struct TTAtlantisSoCState { RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; - DW8250State uart1; + DW8250State uart[TT_ATL_NUM_UARTS]; MemoryRegion bootrom; =20 uint32_t num_harts; @@ -63,7 +64,11 @@ enum { TT_ATL_I2C2_IRQ =3D 35, TT_ATL_I2C3_IRQ =3D 36, TT_ATL_I2C4_IRQ =3D 37, + TT_ATL_UART0_IRQ =3D 38, TT_ATL_UART1_IRQ =3D 39, + TT_ATL_UART2_IRQ =3D 40, + TT_ATL_UART3_IRQ =3D 41, + TT_ATL_UART4_IRQ =3D 42, }; =20 enum { @@ -80,7 +85,11 @@ enum { TT_ATL_MIMSIC, TT_ATL_SAPLIC, TT_ATL_SIMSIC, + TT_ATL_UART0, TT_ATL_UART1, + TT_ATL_UART2, + TT_ATL_UART3, + TT_ATL_UART4, }; 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Wed, 30 Sep 2026 20:17:45 -0700 (PDT) From: 'Portia Stephens To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Portia Stephens , Nicholas Piggin , Michael Ellerman , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Chao Liu , Anirudh Srinivasan , Alistair Francis , Paolo Bonzini , Joel Stanley , Liu Zhiwei , Palmer Dabbelt , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Weiwei Li Subject: [PATCH v2 3/4] hw/riscv/atlantis: Add machine property to select default uart Date: Thu, 1 Oct 2026 13:17:19 +1000 Message-ID: <20261001031720.2334056-4-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001031720.2334056-1-portias@oss.tenstorrent.com> References: <20261001031720.2334056-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=portias@tenstorrent.com; helo=mail-pj2-x11.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790824684623158500 Content-Type: text/plain; charset="utf-8" From: Portia Stephens The Atlantis SoC has 5 UARTs. This adds a machine property to set which uart is on the first serial interface. This is the same pattern that is used by aspeed. The rest of the uart's will be added in sequential order starting at serial interface 1. The default value is uart1 which means the Ascalon console will be on serial interface 0 by default. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza --- hw/riscv/tt_atlantis.c | 76 ++++++++++++++++++++++++++++++---- include/hw/riscv/tt_atlantis.h | 1 + 2 files changed, 68 insertions(+), 9 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 2342edce93..9534ce0031 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "qemu/guest-random.h" #include "qemu/units.h" +#include "qapi/visitor.h" =20 #include "hw/core/boards.h" #include "hw/core/loader.h" @@ -422,6 +423,26 @@ static void load_fdt(TTAtlantisState *ams) create_fdt_memory(ms->fdt, &ams->soc); } =20 +static inline int tt_atlantis_uart_index(int uart_dev) +{ + return uart_dev - TT_ATL_UART0; +} + +static void tt_atlantis_connect_serial_hds_to_uarts(TTAtlantisState *ams) +{ + TTAtlantisSoCState *s =3D &ams->soc; + int uart_index =3D tt_atlantis_uart_index(ams->uart_chosen); + + qdev_prop_set_chr(DEVICE(&s->uart[uart_index]), "chardev", serial_hd(0= )); + + for (int i =3D 1, uart =3D 0; i < TT_ATL_NUM_UARTS; uart++) { + if (uart =3D=3D uart_index) { + continue; + } + qdev_prop_set_chr(DEVICE(&s->uart[uart]), "chardev", serial_hd(i++= )); + } +} + static void tt_atlantis_machine_done(Notifier *n, void *data) { TTAtlantisState *ams =3D container_of(n, TTAtlantisState, machine_done= ); @@ -484,11 +505,6 @@ static void tt_atlantis_machine_done(Notifier *n, void= *data) fdt_load_addr); } =20 -static inline int tt_atlantis_uart_index(int uart_dev) -{ - return uart_dev - TT_ATL_UART0; -} - static void tt_atlantis_soc_init(Object *obj) { TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(obj); @@ -592,10 +608,6 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, &s->bootrom); =20 - /* UART1, the soc console (UART0 is for the boot microcontroller */ - qdev_prop_set_chr(DEVICE(&s->uart[tt_atlantis_uart_index(TT_ATL_UART1)= ]), - "chardev", serial_hd(0)); - for (int i =3D 0; i < TT_ATL_NUM_UARTS; i++) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->uart[i]); if (!sysbus_realize(sbd, errp)) { @@ -663,6 +675,10 @@ static void tt_atlantis_machine_init(MachineState *mac= hine) OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), &error_abort); + + /* Map serial interfaces to uart */ + tt_atlantis_connect_serial_hds_to_uarts(ams); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); =20 /* I2C peripherals: qemu specific */ @@ -680,6 +696,46 @@ static void tt_atlantis_machine_init(MachineState *mac= hine) qemu_add_machine_init_done_notifier(&ams->machine_done); } =20 +static void tt_atlantis_get_console(Object *obj, Visitor *v, const char *n= ame, + void *opaque, Error **errp) +{ + TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(obj); + uint32_t uart_index =3D tt_atlantis_uart_index(ams->uart_chosen); + + visit_type_uint32(v, name, &uart_index, errp); +} + +static void tt_atlantis_set_console(Object *obj, Visitor *v, const char *n= ame, + void *opaque, Error **errp) +{ + TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(obj); + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + if (value >=3D TT_ATL_NUM_UARTS) { + error_setg(errp, "\"console\" should be in range [%d - %d]", + 0, TT_ATL_NUM_UARTS - 1); + return; + } + ams->uart_chosen =3D value + TT_ATL_UART0; +} + +static void tt_atlantis_machine_class_props_init(ObjectClass *oc) +{ + ObjectProperty *console; + + console =3D object_class_property_add(oc, "console", "uint32_t", tt_at= lantis_get_console, + tt_atlantis_set_console, NULL, NULL); + object_class_property_set_description(oc, "console", + "Change the default UART index on -serial. Valid values are 0 \ + through 4 (default: 1, the Ascalon console. 0 for the RCPU con= sole"); + /* Default to UART1, the Ascalon console */ + object_property_set_default_uint(console, 1); +} + static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *da= ta) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -693,6 +749,8 @@ static void tt_atlantis_machine_class_init(ObjectClass = *oc, const void *data) mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; mc->default_ram_id =3D "tt_atlantis.ram"; + + tt_atlantis_machine_class_props_init(oc); } =20 static const TypeInfo tt_atlantis_types[] =3D { diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index b81b7c8abd..7bd46e9c9b 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -56,6 +56,7 @@ struct TTAtlantisState { =20 MemoryRegion soc_memory; TTAtlantisSoCState soc; + uint32_t uart_chosen; }; =20 enum { --=20 2.43.0 From nobody Sat Oct 24 00:35:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 30 Sep 2026 20:17:50 -0700 (PDT) From: 'Portia Stephens To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Portia Stephens , Nicholas Piggin , Michael Ellerman , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Chao Liu , Anirudh Srinivasan , Alistair Francis , Paolo Bonzini , Joel Stanley , Liu Zhiwei , Palmer Dabbelt , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Weiwei Li Subject: [PATCH v2 4/4] docs/atlantis: Update Atlantis UART documentation Date: Thu, 1 Oct 2026 13:17:20 +1000 Message-ID: <20261001031720.2334056-5-portias@oss.tenstorrent.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001031720.2334056-1-portias@oss.tenstorrent.com> References: <20261001031720.2334056-1-portias@oss.tenstorrent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::2b; envelope-from=portias@tenstorrent.com; helo=mail-pj2-x2b.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790824708740158501 Content-Type: text/plain; charset="utf-8" From: Portia Stephens Add documentation describing how to use the console machine property to control the console. Signed-off-by: Portia Stephens Reviewed-by: Daniel Henrique Barboza --- docs/system/riscv/tt_atlantis.rst | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlan= tis.rst index 1f2880d617..e8176d96e8 100644 --- a/docs/system/riscv/tt_atlantis.rst +++ b/docs/system/riscv/tt_atlantis.rst @@ -13,7 +13,21 @@ tt-atlantis QEMU model features =20 * 8-core Ascalon-X CPU Cluster * RISC-V compliant Advanced Interrupt Architecture -* 16550A compatible UART +* DW8250 compatible UART x5 + +Boot options +---------------- + + * ``console`` to change the UART which is on the first serial interface. + Most users will be intersted in the Ascalon boot console ``UART1`` but + Ascalon has 5 UARTs and this may not always be the case. The RCPU conso= le + is on ``UART0``. + +To change the serial console and use device ``UART3`` + +.. code-block:: bash + + -M tt-atlantis,console=3D3 =20 Known limitations ----------------- @@ -24,9 +38,6 @@ real platform. Notably: * There is no PCI host bridge, so virtio-pci devices cannot be attached. Boots that need block storage must use ``-initrd`` with an initramfs. -* The DesignWare UART is modelled with QEMU's ns16550-compatible - ``serial_mm`` device; DesignWare-specific registers beyond that - set return 0. =20 Supported software ------------------ --=20 2.43.0