From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852128; cv=none; d=zohomail.com; s=zohoarc; b=in530ke+Jz70rNO1RwXM5enqMrPtMGDr3H6U3b3Ys5BL6x2TU9gy/EDEwsoTeCGcScPazE1Bpudq7yl+zdqmwU51Bj8vZu2KBhqd9YODTOxp9ggTtn0X9Depymk3mG2UleI27AiFP60QjXHJCg/oLBb0p6yi0t9HQScLDmL1fAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852128; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U0nd/4Iq0xD9cKCsBxbD2ZrG6VpTMUeDNYqS+HS3BmE=; b=d/S4ZfCR1Sy2EgQS99MA1Pk5r7bnNxIhgl/q800USzse5cNgJdXg85q75euZQ258Z0S4bsPpXc6gDGh1AxxVBO7pwX1nFp9Kq/LFucTpxY5bJwqb/6Mh5VxbcnwVh6SjPKT4aoP+BTFNF6wofmjchZIFrlnW/oB6j40me1niz8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790852128868194.14380772860784; Thu, 1 Oct 2026 03:55:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQA-0005v7-N2; Thu, 01 Oct 2026 06:53:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPI-0005de-1E; Thu, 01 Oct 2026 06:52:57 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPF-0002Oy-PQ; Thu, 01 Oct 2026 06:52:55 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id B52CA20B7167; Thu, 1 Oct 2026 03:51:56 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com B52CA20B7167 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851916; bh=U0nd/4Iq0xD9cKCsBxbD2ZrG6VpTMUeDNYqS+HS3BmE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lQx+QhGObGfzJ33rAjJlq7bHbv+ZNF/Lec3Qetdb9prYKO+1fJRhdvtrJAXuSpIXq 2MiaWNfohoxbpPo3ye3eazuy/fYyLDaQqiAJl/53qpxXco75nxbSit4hasMK25P4Tr kYl5xqtaiUBJz6ZSDoRDn+WeKuoGzT4PEjBdIP9Q= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:46 +0000 Subject: [PATCH v6 01/14] accel/mshv: extract common CPU register helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-1-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852129393158500 Move arch-independent MSHV CPU register handling functions into accel/mshv/mshv-cpu-common.c. Update x86 MSHV backends to use these shared helpers. Prefix get_generic_regs() with mshv_ for proper namespacing since it is now public. Signed-off-by: Aastha Rawat --- accel/mshv/meson.build | 3 +- accel/mshv/mshv-cpu-common.c | 151 +++++++++++++++++++++++++++++++++++++++= ++++ include/system/mshv_int.h | 1 + target/i386/mshv/mshv-cpu.c | 125 +---------------------------------- 4 files changed, 155 insertions(+), 125 deletions(-) diff --git a/accel/mshv/meson.build b/accel/mshv/meson.build index e433187cde0..ebe32921b3d 100644 --- a/accel/mshv/meson.build +++ b/accel/mshv/meson.build @@ -1,5 +1,6 @@ system_ss.add(when: 'CONFIG_MSHV', if_true: files( 'irq.c', 'mem.c', - 'mshv-all.c' + 'mshv-all.c', + 'mshv-cpu-common.c' )) diff --git a/accel/mshv/mshv-cpu-common.c b/accel/mshv/mshv-cpu-common.c new file mode 100644 index 00000000000..e8ef34689e3 --- /dev/null +++ b/accel/mshv/mshv-cpu-common.c @@ -0,0 +1,151 @@ +/* + * QEMU MSHV common CPU register helpers + * + * Copyright Microsoft, Corp. 2026 + * + * Authors: Ziqiao Zhou + * Magnus Kulke + * Jinank Jain + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/memalign.h" + +#include "system/mshv.h" +#include "linux/mshv.h" +#include "system/mshv_int.h" + +#include "hw/core/cpu.h" + +#include + +int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, + size_t n_regs) +{ + int cpu_fd =3D mshv_vcpufd(cpu); + int vp_index =3D cpu->cpu_index; + size_t in_sz, assocs_sz; + hv_input_set_vp_registers *in =3D cpu->accel->hvcall_args.input_page; + struct mshv_root_hvcall args =3D {0}; + int ret; + + /* find out the size of the struct w/ a flexible array at the tail */ + assocs_sz =3D n_regs * sizeof(hv_register_assoc); + in_sz =3D sizeof(hv_input_set_vp_registers) + assocs_sz; + + /* fill the input struct */ + memset(in, 0, sizeof(hv_input_set_vp_registers)); + in->vp_index =3D vp_index; + memcpy(in->elements, assocs, assocs_sz); + + /* create the hvcall envelope */ + args.code =3D HVCALL_SET_VP_REGISTERS; + args.in_sz =3D in_sz; + args.in_ptr =3D (uint64_t) in; + args.reps =3D (uint16_t) n_regs; + + /* perform the call */ + ret =3D mshv_hvcall(cpu_fd, &args); + if (ret < 0) { + error_report("Failed to set registers"); + return -1; + } + + /* assert we set all registers */ + if (args.reps !=3D n_regs) { + error_report("Failed to set registers: expected %zu elements" + ", got %u", n_regs, args.reps); + return -1; + } + + return 0; +} + +int mshv_get_generic_regs(CPUState *cpu, hv_register_assoc *assocs, + size_t n_regs) +{ + int cpu_fd =3D mshv_vcpufd(cpu); + int vp_index =3D cpu->cpu_index; + hv_input_get_vp_registers *in =3D cpu->accel->hvcall_args.input_page; + hv_register_value *values =3D cpu->accel->hvcall_args.output_page; + size_t in_sz, names_sz, values_sz; + int i, ret; + struct mshv_root_hvcall args =3D {0}; + + /* find out the size of the struct w/ a flexible array at the tail */ + names_sz =3D n_regs * sizeof(hv_register_name); + in_sz =3D sizeof(hv_input_get_vp_registers) + names_sz; + + /* fill the input struct */ + memset(in, 0, sizeof(hv_input_get_vp_registers)); + in->vp_index =3D vp_index; + for (i =3D 0; i < n_regs; i++) { + in->names[i] =3D assocs[i].name; + } + + /* determine size of value output buffer */ + values_sz =3D n_regs * sizeof(union hv_register_value); + + /* create the hvcall envelope */ + args.code =3D HVCALL_GET_VP_REGISTERS; + args.in_sz =3D in_sz; + args.in_ptr =3D (uint64_t) in; + args.out_sz =3D values_sz; + args.out_ptr =3D (uint64_t) values; + args.reps =3D (uint16_t) n_regs; + + /* perform the call */ + ret =3D mshv_hvcall(cpu_fd, &args); + if (ret < 0) { + error_report("Failed to retrieve registers"); + return -1; + } + + /* assert we got all registers */ + if (args.reps !=3D n_regs) { + error_report("Failed to retrieve registers: expected %zu elements" + ", got %u", n_regs, args.reps); + return -1; + } + + /* copy values into assoc */ + for (i =3D 0; i < n_regs; i++) { + assocs[i].value =3D values[i]; + } + + return 0; +} + +int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd) +{ + int ret; + struct mshv_create_vp vp_arg =3D { + .vp_index =3D vp_index, + }; + + ret =3D ioctl(vm_fd, MSHV_CREATE_VP, &vp_arg); + if (ret < 0) { + error_report("failed to create mshv vcpu: %s", strerror(errno)); + return -1; + } + + *cpu_fd =3D ret; + + return 0; +} + +void mshv_remove_vcpu(int vm_fd, int cpu_fd) +{ + close(cpu_fd); +} + +void mshv_setup_hvcall_args(AccelCPUState *state) +{ + void *mem =3D qemu_memalign(HV_HYP_PAGE_SIZE, 2 * HV_HYP_PAGE_SIZE); + + state->hvcall_args.base =3D mem; + state->hvcall_args.input_page =3D mem; + state->hvcall_args.output_page =3D (uint8_t *)mem + HV_HYP_PAGE_SIZE; +} diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 3dffe3c5fbf..2e8caad8fde 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -107,6 +107,7 @@ void mshv_arch_amend_proc_features( void mshv_arch_disable_partition_proc_features( union hv_partition_processor_features *disabled_features); int mshv_arch_post_init_vm(int vm_fd); +void mshv_setup_hvcall_args(AccelCPUState *state); int mshv_get_vp_state(int cpu_fd, struct mshv_get_set_vp_state *state); int mshv_set_vp_state(int cpu_fd, const struct mshv_get_set_vp_state *stat= e); typedef struct mshv_root_hvcall mshv_root_hvcall; diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index f528dd2b9a2..3eee097432a 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -357,103 +357,6 @@ static int translate_gva(const CPUState *cpu, uint64_= t gva, uint64_t *gpa, return 0; } =20 -int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, - size_t n_regs) -{ - int cpu_fd =3D mshv_vcpufd(cpu); - int vp_index =3D cpu->cpu_index; - size_t in_sz, assocs_sz; - hv_input_set_vp_registers *in =3D cpu->accel->hvcall_args.input_page; - struct mshv_root_hvcall args =3D {0}; - int ret; - - /* find out the size of the struct w/ a flexible array at the tail */ - assocs_sz =3D n_regs * sizeof(hv_register_assoc); - in_sz =3D sizeof(hv_input_set_vp_registers) + assocs_sz; - - /* fill the input struct */ - memset(in, 0, sizeof(hv_input_set_vp_registers)); - in->vp_index =3D vp_index; - memcpy(in->elements, assocs, assocs_sz); - - /* create the hvcall envelope */ - args.code =3D HVCALL_SET_VP_REGISTERS; - args.in_sz =3D in_sz; - args.in_ptr =3D (uint64_t) in; - args.reps =3D (uint16_t) n_regs; - - /* perform the call */ - ret =3D mshv_hvcall(cpu_fd, &args); - if (ret < 0) { - error_report("Failed to set registers"); - return -1; - } - - /* assert we set all registers */ - if (args.reps !=3D n_regs) { - error_report("Failed to set registers: expected %zu elements" - ", got %u", n_regs, args.reps); - return -1; - } - - return 0; -} - -int mshv_get_generic_regs(CPUState *cpu, hv_register_assoc *assocs, - size_t n_regs) -{ - int cpu_fd =3D mshv_vcpufd(cpu); - int vp_index =3D cpu->cpu_index; - hv_input_get_vp_registers *in =3D cpu->accel->hvcall_args.input_page; - hv_register_value *values =3D cpu->accel->hvcall_args.output_page; - size_t in_sz, names_sz, values_sz; - int i, ret; - struct mshv_root_hvcall args =3D {0}; - - /* find out the size of the struct w/ a flexible array at the tail */ - names_sz =3D n_regs * sizeof(hv_register_name); - in_sz =3D sizeof(hv_input_get_vp_registers) + names_sz; - - /* fill the input struct */ - memset(in, 0, sizeof(hv_input_get_vp_registers)); - in->vp_index =3D vp_index; - for (i =3D 0; i < n_regs; i++) { - in->names[i] =3D assocs[i].name; - } - - /* determine size of value output buffer */ - values_sz =3D n_regs * sizeof(union hv_register_value); - - /* create the hvcall envelope */ - args.code =3D HVCALL_GET_VP_REGISTERS; - args.in_sz =3D in_sz; - args.in_ptr =3D (uint64_t) in; - args.out_sz =3D values_sz; - args.out_ptr =3D (uint64_t) values; - args.reps =3D (uint16_t) n_regs; - - /* perform the call */ - ret =3D mshv_hvcall(cpu_fd, &args); - if (ret < 0) { - error_report("Failed to retrieve registers"); - return -1; - } - - /* assert we got all registers */ - if (args.reps !=3D n_regs) { - error_report("Failed to retrieve registers: expected %zu elements" - ", got %u", n_regs, args.reps); - return -1; - } - - /* copy values into assoc */ - for (i =3D 0; i < n_regs; i++) { - assocs[i].value =3D values[i]; - } - - return 0; -} - static int set_standard_regs(const CPUState *cpu) { X86CPU *x86cpu =3D X86_CPU(cpu); @@ -2040,29 +1943,6 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_messa= ge *msg, MshvVmExit *exit) return 0; } =20 -void mshv_remove_vcpu(int vm_fd, int cpu_fd) -{ - close(cpu_fd); -} - - -int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd) -{ - int ret; - struct mshv_create_vp vp_arg =3D { - .vp_index =3D vp_index, - }; - ret =3D ioctl(vm_fd, MSHV_CREATE_VP, &vp_arg); - if (ret < 0) { - error_report("failed to create mshv vcpu: %s", strerror(errno)); - return -1; - } - - *cpu_fd =3D ret; - - return 0; -} - static void read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, enum X86Seg seg_idx) @@ -2121,7 +2001,6 @@ void mshv_arch_init_vcpu(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; AccelCPUState *state =3D cpu->accel; size_t page =3D HV_HYP_PAGE_SIZE, xsave_len; - void *mem =3D qemu_memalign(page, 2 * page); int ret; X86XSaveHeader *header; =20 @@ -2143,9 +2022,7 @@ void mshv_arch_init_vcpu(CPUState *cpu) env->regs_page =3D (struct hv_vp_register_page *) rp; } =20 - state->hvcall_args.base =3D mem; - state->hvcall_args.input_page =3D mem; - state->hvcall_args.output_page =3D (uint8_t *)mem + page; + mshv_setup_hvcall_args(state); =20 env->emu_mmio_buf =3D g_new(char, 4096); =20 --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 1 Oct 2026 03:51:57 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com A8F3420B7168 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851917; bh=5ZHK54BtZ1HmFz5+7cCRNy9EwyJVBkDJHoi8fEbeTsg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CeCGh2nuuyQEriu0HtmwmBz9GNSMFYWmwPXpy1yYmmNk6II9TeRkYViqfy1jYuaCS Vosk0f77r7PN9eYlkC8nqgr6lzoAeFB93rANCovb0GKY/NJDWWxe3cWSr4/7XZebNP qRdRQNiziPzyoKKet8RrzRNdRDoVOVaBytTFeIvs= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:47 +0000 Subject: [PATCH v6 02/14] accel/mshv: add arch-specific accelerator init hook MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-2-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852097139158500 From: "Anirudh Rayabharam (Microsoft)" Introduce mshv_arch_accel_init() as an arch-specific hook called early in mshv_init(), before VM creation. This allows each architecture to perform platform-specific initialization at accelerator init time. For x86, the hook calls mshv_init_mmio_emu() which was previously called directly from the common init path. Also move set_unimplemented_msr_action() and mshv_arch_post_init_vm() from mshv-cpu.c to the new mshv-all.c, as they are not vCPU-specific. Signed-off-by: Anirudh Rayabharam (Microsoft) --- accel/mshv/mshv-all.c | 5 ++- include/system/mshv_int.h | 1 + target/i386/mshv/meson.build | 1 + target/i386/mshv/mshv-all.c | 80 ++++++++++++++++++++++++++++++++++++++++= ++++ target/i386/mshv/mshv-cpu.c | 40 ---------------------- 5 files changed, 86 insertions(+), 41 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 5921ce693ee..860f511fcba 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -544,7 +544,10 @@ static int mshv_init(AccelState *as, MachineState *ms) return -1; } =20 - mshv_init_mmio_emu(); + ret =3D mshv_arch_accel_init(as, ms, mshv_fd); + if (ret < 0) { + return -1; + } =20 ret =3D create_vm(mshv_fd, &vm_fd); if (ret < 0) { diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 2e8caad8fde..0e68365c63f 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -106,6 +106,7 @@ void mshv_arch_amend_proc_features( union hv_partition_synthetic_processor_features *features); void mshv_arch_disable_partition_proc_features( union hv_partition_processor_features *disabled_features); +int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd); int mshv_arch_post_init_vm(int vm_fd); void mshv_setup_hvcall_args(AccelCPUState *state); int mshv_get_vp_state(int cpu_fd, struct mshv_get_set_vp_state *state); diff --git a/target/i386/mshv/meson.build b/target/i386/mshv/meson.build index 31ff4cc9950..0e95c5a00b9 100644 --- a/target/i386/mshv/meson.build +++ b/target/i386/mshv/meson.build @@ -1,6 +1,7 @@ i386_mshv_ss =3D ss.source_set() =20 i386_mshv_ss.add(files( + 'mshv-all.c', 'mshv-cpu.c', 'msr.c', 'synic.c', diff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c new file mode 100644 index 00000000000..f0b43aa86f1 --- /dev/null +++ b/target/i386/mshv/mshv-all.c @@ -0,0 +1,80 @@ +/* + * QEMU MSHV support + * + * Copyright Microsoft, Corp. 2026 + * + * Authors: Ziqiao Zhou + * Magnus Kulke + * Jinank Jain + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/memalign.h" + +#include "system/mshv.h" +#include "system/mshv_int.h" +#include "system/address-spaces.h" +#include "linux/mshv.h" +#include "hw/hyperv/hvgdk.h" +#include "hw/hyperv/hvgdk_mini.h" +#include "hw/hyperv/hvhdk_mini.h" +#include "hw/i386/apic_internal.h" + +#include "cpu.h" +#include "emulate/x86_decode.h" +#include "emulate/x86_emu.h" +#include "emulate/x86_flags.h" + +#include "trace-accel_mshv.h" +#include "trace.h" + +#include + +int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd) +{ + mshv_init_mmio_emu(); + return 0; +} + +/* + * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a + * fault to the guest if it tries to access it. It is possible to override + * this behavior with a more suitable option i.e., ignore writes from the = guest + * and return zero in attempt to read unimplemented. + */ +static int set_unimplemented_msr_action(int vm_fd) +{ + struct hv_input_set_partition_property in =3D {0}; + struct mshv_root_hvcall args =3D {0}; + + in.property_code =3D HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION; + in.property_value =3D HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZE= RO; + + args.code =3D HVCALL_SET_PARTITION_PROPERTY; + args.in_sz =3D sizeof(in); + args.in_ptr =3D (uint64_t)∈ + + trace_mshv_hvcall_args("unimplemented_msr_action", args.code, args.in_= sz); + + int ret =3D mshv_hvcall(vm_fd, &args); + if (ret < 0) { + error_report("Failed to set unimplemented MSR action"); + return -1; + } + return 0; +} + +int mshv_arch_post_init_vm(int vm_fd) +{ + int ret; + + ret =3D set_unimplemented_msr_action(vm_fd); + if (ret < 0) { + error_report("Failed to set unimplemented MSR action"); + } + + return ret; +} diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 3eee097432a..f1056bd215e 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -2125,46 +2125,6 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uin= t32_t idx, int reg) return ret; } =20 -/* - * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a - * fault to the guest if it tries to access it. It is possible to override - * this behavior with a more suitable option i.e., ignore writes from the = guest - * and return zero in attempt to read unimplemented. - */ -static int set_unimplemented_msr_action(int vm_fd) -{ - struct hv_input_set_partition_property in =3D {0}; - struct mshv_root_hvcall args =3D {0}; - - in.property_code =3D HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION; - in.property_value =3D HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZE= RO; - - args.code =3D HVCALL_SET_PARTITION_PROPERTY; - args.in_sz =3D sizeof(in); - args.in_ptr =3D (uint64_t)∈ - - trace_mshv_hvcall_args("unimplemented_msr_action", args.code, args.in_= sz); - - int ret =3D mshv_hvcall(vm_fd, &args); - if (ret < 0) { - error_report("Failed to set unimplemented MSR action"); - return -1; - } - return 0; -} - -int mshv_arch_post_init_vm(int vm_fd) -{ - int ret; - - ret =3D set_unimplemented_msr_action(vm_fd); - if (ret < 0) { - error_report("Failed to set unimplemented MSR action"); - } - - return ret; -} - static void mshv_cpu_xsave_init(void) { static bool first =3D true; --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852027; cv=none; d=zohomail.com; s=zohoarc; b=n6jJaJjWRmIGj9U3QtPrNWT8uxor6Z5FmeN6sLm8//mVaWkGku/pze8KFszGAR/sWx2Shegh+LR67jt6VlBz04ECYC/kwMOgaMhtfBb9l7akBAaw5s0ggMqRcMExCuMVYdVGELL661ZHjnuoA5Em9rGVkb3uNpfKRVQfUR9sI+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852027; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=37MszlWbJzj+NlQUVtLNagGvC4NXZtVf/7aP5kBq1SA=; b=et4YpoLDmndiCRvrJI1RHGGe7jEV/BXVledjENzWtPA2AtASxADd23Ziy78GX/LjkH1XEj7FTWC2MlHdV4A+c1FaFKWKftLM0A151wfnhXYRAf5U5DjUuUDCvJN/VUJxKXH1gSqBbYd2wcyg6EmsBnP+cSEC+uKKZeFOj/Oepps= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790852027269627.2282201321888; Thu, 1 Oct 2026 03:53:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPY-0005fq-7s; Thu, 01 Oct 2026 06:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPH-0005dX-Gm; Thu, 01 Oct 2026 06:52:55 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPF-0002P4-S8; Thu, 01 Oct 2026 06:52:55 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 6E80020B716A; Thu, 1 Oct 2026 03:51:58 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 6E80020B716A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851918; bh=37MszlWbJzj+NlQUVtLNagGvC4NXZtVf/7aP5kBq1SA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MwnWGZGZi08SR9BGkm6ZFg9Atrq9TMT1EL/oOCWIzQEcV9zjiG96mExkX1acDhxdl awh/CYBP2WestHS7bSd30g319q7bRO7IXsi01tPMsbOr5Z1xJ5hM+I4DLDxt2Jo0sb ARsNzE8dTd9CA6OuYIeThsVMZA9RjqAYTecqemag= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:48 +0000 Subject: [PATCH v6 03/14] accel/mshv: make MSHV migration initialization arch-specific MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-3-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852029952158500 x86 specific migration handlers currently live in common MSHV code. Move these handlers into x86 backend and add a generic architecture migration initialization hook. ARM MSHV live migration support is not added yet, this will allow ARM to add an empty initialization hook. Signed-off-by: Aastha Rawat --- accel/mshv/mshv-all.c | 35 ++++------------------------------- include/system/mshv_int.h | 1 + target/i386/mshv/mshv-all.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 31 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 860f511fcba..efe19a39140 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -60,30 +60,6 @@ static int init_mshv(int *mshv_fd) return 0; } =20 -static int mshv_load_cleanup(void *opaque) -{ - CPUState *cpu; - int ret; - - ret =3D mshv_arch_set_partition_msrs(first_cpu); - if (ret < 0) { - error_report("Failed to set partition MSRs: %s", strerror(-ret)); - return -1; - } - - CPU_FOREACH(cpu) { - ret =3D mshv_arch_set_mp_state(cpu); - if (ret < 0) { - error_report("Failed to set mp state for vCPU %d: %s", - cpu->cpu_index, strerror(-ret)); - return -1; - } - } - - return 0; -} - - static int get_host_partition_property(int mshv_fd, uint32_t property_code, uint64_t *value) { @@ -519,10 +495,6 @@ static int mshv_init_vcpu(CPUState *cpu) return 0; } =20 -static SaveVMHandlers savevm_mshv =3D { - .load_cleanup =3D mshv_load_cleanup, -}; - static int mshv_init(AccelState *as, MachineState *ms) { MshvState *s; @@ -574,9 +546,10 @@ static int mshv_init(AccelState *as, MachineState *ms) 0, "mshv-memory"); memory_listener_register(&mshv_io_listener, &address_space_io); =20 - register_savevm_live("mshv", 0, 1, &savevm_mshv, s); - - mshv_clock_init(); + ret =3D mshv_arch_migration_init(s); + if (ret < 0) { + return ret; + } =20 return 0; } diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 0e68365c63f..31d2f4381c7 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -109,6 +109,7 @@ void mshv_arch_disable_partition_proc_features( int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd); int mshv_arch_post_init_vm(int vm_fd); void mshv_setup_hvcall_args(AccelCPUState *state); +int mshv_arch_migration_init(MshvState *s); int mshv_get_vp_state(int cpu_fd, struct mshv_get_set_vp_state *state); int mshv_set_vp_state(int cpu_fd, const struct mshv_get_set_vp_state *stat= e); typedef struct mshv_root_hvcall mshv_root_hvcall; diff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c index f0b43aa86f1..968fe2a4494 100644 --- a/target/i386/mshv/mshv-all.c +++ b/target/i386/mshv/mshv-all.c @@ -78,3 +78,37 @@ int mshv_arch_post_init_vm(int vm_fd) =20 return ret; } + +static int mshv_load_cleanup(void *opaque) +{ + CPUState *cpu; + int ret; + + ret =3D mshv_arch_set_partition_msrs(first_cpu); + if (ret < 0) { + error_report("Failed to set partition MSRs: %s", strerror(-ret)); + return -1; + } + + CPU_FOREACH(cpu) { + ret =3D mshv_arch_set_mp_state(cpu); + if (ret < 0) { + error_report("Failed to set mp state for vCPU %d: %s", + cpu->cpu_index, strerror(-ret)); + return -1; + } + } + + return 0; +} + +static SaveVMHandlers savevm_mshv =3D { + .load_cleanup =3D mshv_load_cleanup, +}; + +int mshv_arch_migration_init(MshvState *s) +{ + register_savevm_live("mshv", 0, 1, &savevm_mshv, s); + mshv_clock_init(); + return 0; +} --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852036; cv=none; d=zohomail.com; s=zohoarc; b=hNRjhNEcmHnwUtNCDwNSlXUiFGdfdKTI5UNGncG40584Z42dHuxd25UxtwzkOxBcGM0315sdQWqMMu5SMn4HfV+2S/JbAWyAjvLARKdA/a02fWHnrGsQUUbo+yB6rhqC6XDxV60pLrPxea9EnoSIwqevJaN8aTr4JzPChearkVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852036; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u3lGqUx8su4RL2vAD7EuzNczAiGM9+1NMl/RudEEoVg=; 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Thu, 01 Oct 2026 06:52:56 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 5E4EE20B7169; Thu, 1 Oct 2026 03:51:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 5E4EE20B7169 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851919; bh=u3lGqUx8su4RL2vAD7EuzNczAiGM9+1NMl/RudEEoVg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=klUhGS83KDk8PJwuq0tH2l5T7U7Qvu9x38WZn+pqV1GFpQ3itY9ZXO9XXE2gNhczn 5UcqwNHIFqsBYZJ2WfsaMOJjwKVrhwT/5uUDdkuHwfCFJmlYMol7A2/HMomUIoj/9u +WvnKMWO6cGb+ftVXMdseVN8gcFbUGPIkU+P9oLU= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:49 +0000 Subject: [PATCH v6 04/14] meson, target/arm/mshv: Enable arm64 build & add initial MSHV support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-4-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852036881158500 Enable the build of the MSHV accelerator for arm64 in the Meson build system. Introduce initial files and stub implementations to support MSHV for the ARM target. Signed-off-by: Aastha Rawat --- accel/mshv/mshv-all.c | 10 ++++-- hw/i386/mshv/clock.c | 2 +- include/system/mshv.h | 2 +- meson.build | 8 ++--- target/arm/meson.build | 1 + target/arm/mshv/meson.build | 7 ++++ target/arm/mshv/mshv-all.c | 81 +++++++++++++++++++++++++++++++++++++++++= ++++ 7 files changed, 103 insertions(+), 8 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index efe19a3914..f3f1825b0b 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -142,8 +142,10 @@ static int create_partition(int mshv_fd, int *vm_fd) { int ret; uint64_t pt_flags, host_proc_features; - union hv_partition_processor_xsave_features disabled_xsave_features; union hv_partition_processor_features disabled_partition_features =3D = {0}; +#if defined(__x86_64__) + union hv_partition_processor_xsave_features disabled_xsave_features; +#endif =20 struct mshv_create_partition_v2 args =3D {0}; =20 @@ -155,7 +157,8 @@ static int create_partition(int mshv_fd, int *vm_fd) (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) | (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES); =20 - /* enable all */ +#if defined(__x86_64__) + /* enable all xsave features (0 =3D enabled) */ disabled_xsave_features.as_uint64 =3D 0; /* * AMX TILE XSAVE state (XTILE_DATA) is 8KB, which exceeds the @@ -165,6 +168,7 @@ static int create_partition(int mshv_fd, int *vm_fd) disabled_xsave_features.amx_bf16_support =3D 1; disabled_xsave_features.amx_int8_support =3D 1; disabled_xsave_features.amx_fp16_support =3D 1; +#endif =20 /* * query host for supported processor features and disable unsupported @@ -196,7 +200,9 @@ static int create_partition(int mshv_fd, int *vm_fd) /* populate args structure */ args.pt_flags =3D pt_flags; args.pt_isolation =3D MSHV_PT_ISOLATION_NONE; +#if defined(__x86_64__) args.pt_disabled_xsave =3D disabled_xsave_features.as_uint64; +#endif args.pt_num_cpu_fbanks =3D MSHV_NUM_CPU_FEATURES_BANKS; =20 ret =3D ioctl(mshv_fd, MSHV_CREATE_PARTITION, &args); diff --git a/hw/i386/mshv/clock.c b/hw/i386/mshv/clock.c index 02c586503a..b7db382752 100644 --- a/hw/i386/mshv/clock.c +++ b/hw/i386/mshv/clock.c @@ -182,7 +182,7 @@ static const VMStateDescription vmstate_mshv_clock =3D { }, }; =20 -void mshv_clock_init(void) +void mshv_arch_clock_init(void) { vmstate_register(NULL, 0, &vmstate_mshv_clock, &mshv_clock); qemu_add_vm_change_state_handler(mshv_clock_vm_state_change, &mshv_clo= ck); diff --git a/include/system/mshv.h b/include/system/mshv.h index f98ddff9b5..114f065db5 100644 --- a/include/system/mshv.h +++ b/include/system/mshv.h @@ -58,7 +58,7 @@ DECLARE_INSTANCE_CHECKER(MshvState, MSHV_STATE, extern MshvState *mshv_state; =20 /* clock (partition reference time) */ -void mshv_clock_init(void); +void mshv_arch_clock_init(void); =20 /* interrupt */ int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type,= uint32_t vector, diff --git a/meson.build b/meson.build index cae1591cd2..6a90a394a2 100644 --- a/meson.build +++ b/meson.build @@ -304,7 +304,8 @@ if cpu =3D=3D 'aarch64' accelerator_targets +=3D { 'CONFIG_HVF': ['aarch64-softmmu'], 'CONFIG_NITRO': ['aarch64-softmmu'], - 'CONFIG_WHPX': ['aarch64-softmmu'] + 'CONFIG_WHPX': ['aarch64-softmmu'], + 'CONFIG_MSHV': ['aarch64-softmmu'], } elif cpu =3D=3D 'x86_64' accelerator_targets +=3D { @@ -884,10 +885,9 @@ if get_option('kvm').allowed() and host_os =3D=3D 'lin= ux' endif =20 if get_option('mshv').allowed() and host_os =3D=3D 'linux' - if get_option('mshv').enabled() and host_machine.cpu() !=3D 'x86_64' - error('mshv accelerator requires x64_64 host') + if host_machine.cpu() in [ 'x86_64', 'aarch64' ] + accelerators +=3D 'CONFIG_MSHV' endif - accelerators +=3D 'CONFIG_MSHV' endif =20 if get_option('whpx').allowed() and host_os =3D=3D 'windows' diff --git a/target/arm/meson.build b/target/arm/meson.build index 0369f96b4c..1ac2cef26b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -63,6 +63,7 @@ arm_common_system_ss.add(files( =20 subdir('hvf') subdir('whpx') +subdir('mshv') =20 if 'CONFIG_TCG' in config_all_accel subdir('tcg') diff --git a/target/arm/mshv/meson.build b/target/arm/mshv/meson.build new file mode 100644 index 0000000000..169643691e --- /dev/null +++ b/target/arm/mshv/meson.build @@ -0,0 +1,7 @@ +arm_mshv_ss =3D ss.source_set() + +arm_mshv_ss.add(files( + 'mshv-all.c', +)) + +arm_system_ss.add_all(when: 'CONFIG_MSHV', if_true: arm_mshv_ss) diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c new file mode 100644 index 0000000000..00c54f5d66 --- /dev/null +++ b/target/arm/mshv/mshv-all.c @@ -0,0 +1,81 @@ +/* + * QEMU MSHV support + * + * Copyright Microsoft, Corp. 2026 + * + * Authors: Aastha Rawat + * Anirudh Rayabharam + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/arm/virt.h" +#include "system/mshv.h" +#include "system/mshv_int.h" + +static int load_regs(CPUState *cpu) +{ + return 0; +} + +static int store_regs(const CPUState *cpu) +{ + return 0; +} + +int mshv_arch_load_vcpu_state(CPUState *cpu) +{ + return load_regs(cpu); +} + +int mshv_arch_store_vcpu_state(const CPUState *cpu) +{ + return store_regs(cpu); +} + +int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit) +{ + return 0; +} + +void mshv_arch_init_vcpu(CPUState *cpu) +{ + +} + +void mshv_arch_destroy_vcpu(CPUState *cpu) +{ + +} + +int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd) +{ + return 0; +} + +void mshv_arch_amend_proc_features( + union hv_partition_synthetic_processor_features *features) +{ + /* + * TLB-flush hypercalls are an x86 enlightenment. ARM guests use + * broadcast TLBI instructions instead. + */ + features->tb_flush_hypercalls =3D 0; +} + +void mshv_arch_disable_partition_proc_features( + union hv_partition_processor_features *disabled_features) +{ + /* No processor features to disable on ARM */ +} + +int mshv_arch_post_init_vm(int vm_fd) +{ + return 0; +} + +int mshv_arch_migration_init(MshvState *s) +{ + return 0; +} --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852107; cv=none; d=zohomail.com; s=zohoarc; b=SIJ9h7FM698j4Qmf+P25bd/pgey2eKm9JaiviHfGWB3NTP1/U9KaQ1bqGo2J01Ei4Q3nJhYNOkJ1EyM96U8dcNSohAuejVAGDOw0afTu9jIlWkX3SZHnUJTpvzaTn920+FBBKWIjIo5cPOoFIkt9QSZXQ5DYL5+eqojSERm3RF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852107; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VUi4mhmOj2SX7mZK32XO+03lc0VjNpBSAoUREVNFH+4=; b=C0cBov2H0YERzdpXWkaVnW/d/1W5A5QY+chyMyqp2Z3rbvK262REZjmkHj7690RVC/P9GPY57bpn9QWwA9L9J7MbNiY5Q9hfu6dQ9wmjzTUBVDBPzNFqH0DsvqS9W3E50u2TfUszpe3NJb0qdT4qiOUmeLDxf+dBhJGfh1c1E1I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790852107375924.9403943332258; Thu, 1 Oct 2026 03:55:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQC-00060J-6p; Thu, 01 Oct 2026 06:53:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPK-0005dk-2F; Thu, 01 Oct 2026 06:52:58 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPI-0002PZ-6G; Thu, 01 Oct 2026 06:52:57 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 4501520B716B; Thu, 1 Oct 2026 03:52:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4501520B716B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851920; bh=VUi4mhmOj2SX7mZK32XO+03lc0VjNpBSAoUREVNFH+4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lOQxxG/tn7pPdL9PXCTwjWNmdkE9wVtN8+lLSRK+p5pCiltnmKHaFQjbCDDbej4St jk2rXhFV8+a2h62SKIAp4JoczWoViZMFpNo07nl9kOXRqRAZtohOZcJaVUEOSwz+f9 eGQG9rB/XWaPSWUoUWoe7aTKU8/I9TsQ7pfG77og= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:50 +0000 Subject: [PATCH v6 05/14] target/arm/mshv: implement vcpu state operations for ARM64 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-5-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852109105158500 Add support for reading and writing ARM64 CPU registers in the MSHV accelerator. This includes functions to set and get registers, initialize and destroy VCPU state, and manage register state synchronization between QEMU and hypervisor. Signed-off-by: Aastha Rawat --- include/hw/hyperv/hvgdk_mini.h | 42 +++++++++++++++ target/arm/mshv/mshv-all.c | 119 +++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 161 insertions(+) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index a5527d49cf..b5bcea353a 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -32,6 +32,46 @@ typedef enum hv_register_name { HV_REGISTER_PENDING_EVENT0 =3D 0x00010004, HV_REGISTER_PENDING_EVENT1 =3D 0x00010005, =20 +#if defined(__aarch64__) + HV_ARM64_REGISTER_XZR =3D 0x0002FFFE, + HV_ARM64_REGISTER_X0 =3D 0x00020000, + HV_ARM64_REGISTER_X1 =3D 0x00020001, + HV_ARM64_REGISTER_X2 =3D 0x00020002, + HV_ARM64_REGISTER_X3 =3D 0x00020003, + HV_ARM64_REGISTER_X4 =3D 0x00020004, + HV_ARM64_REGISTER_X5 =3D 0x00020005, + HV_ARM64_REGISTER_X6 =3D 0x00020006, + HV_ARM64_REGISTER_X7 =3D 0x00020007, + HV_ARM64_REGISTER_X8 =3D 0x00020008, + HV_ARM64_REGISTER_X9 =3D 0x00020009, + HV_ARM64_REGISTER_X10 =3D 0x0002000A, + HV_ARM64_REGISTER_X11 =3D 0x0002000B, + HV_ARM64_REGISTER_X12 =3D 0x0002000C, + HV_ARM64_REGISTER_X13 =3D 0x0002000D, + HV_ARM64_REGISTER_X14 =3D 0x0002000E, + HV_ARM64_REGISTER_X15 =3D 0x0002000F, + HV_ARM64_REGISTER_X16 =3D 0x00020010, + HV_ARM64_REGISTER_X17 =3D 0x00020011, + HV_ARM64_REGISTER_X18 =3D 0x00020012, + HV_ARM64_REGISTER_X19 =3D 0x00020013, + HV_ARM64_REGISTER_X20 =3D 0x00020014, + HV_ARM64_REGISTER_X21 =3D 0x00020015, + HV_ARM64_REGISTER_X22 =3D 0x00020016, + HV_ARM64_REGISTER_X23 =3D 0x00020017, + HV_ARM64_REGISTER_X24 =3D 0x00020018, + HV_ARM64_REGISTER_X25 =3D 0x00020019, + HV_ARM64_REGISTER_X26 =3D 0x0002001A, + HV_ARM64_REGISTER_X27 =3D 0x0002001B, + HV_ARM64_REGISTER_X28 =3D 0x0002001C, + HV_ARM64_REGISTER_FP =3D 0x0002001D, + HV_ARM64_REGISTER_LR =3D 0x0002001E, + HV_ARM64_REGISTER_PC =3D 0x00020022, + + /* AArch64 System Register Descriptions: General system control regist= ers */ + HV_ARM64_REGISTER_MIDR_EL1 =3D 0x00040051, + HV_ARM64_REGISTER_MPIDR_EL1 =3D 0x00040001, + +#elif defined(__x86_64__) /* X64 User-Mode Registers */ HV_X64_REGISTER_RAX =3D 0x00020000, HV_X64_REGISTER_RCX =3D 0x00020001, @@ -188,6 +228,8 @@ typedef enum hv_register_name { /* Other MSRs */ HV_X64_REGISTER_MSR_IA32_MISC_ENABLE =3D 0x000800A0, =20 +#endif + /* Misc */ HV_X64_REGISTER_HYPERCALL =3D 0x00090001, HV_REGISTER_GUEST_OS_ID =3D 0x00090002, diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c index 00c54f5d66..29dd45a123 100644 --- a/target/arm/mshv/mshv-all.c +++ b/target/arm/mshv/mshv-all.c @@ -10,17 +10,128 @@ */ =20 #include "qemu/osdep.h" +#include + +#include "qemu/error-report.h" +#include "qemu/memalign.h" #include "hw/arm/virt.h" + +#include "system/cpus.h" +#include "target/arm/cpu.h" + #include "system/mshv.h" #include "system/mshv_int.h" +#include "hw/hyperv/hvgdk_mini.h" + +static const enum hv_register_name STANDARD_REGISTER_NAMES[32] =3D { + HV_ARM64_REGISTER_X0, + HV_ARM64_REGISTER_X1, + HV_ARM64_REGISTER_X2, + HV_ARM64_REGISTER_X3, + HV_ARM64_REGISTER_X4, + HV_ARM64_REGISTER_X5, + HV_ARM64_REGISTER_X6, + HV_ARM64_REGISTER_X7, + HV_ARM64_REGISTER_X8, + HV_ARM64_REGISTER_X9, + HV_ARM64_REGISTER_X10, + HV_ARM64_REGISTER_X11, + HV_ARM64_REGISTER_X12, + HV_ARM64_REGISTER_X13, + HV_ARM64_REGISTER_X14, + HV_ARM64_REGISTER_X15, + HV_ARM64_REGISTER_X16, + HV_ARM64_REGISTER_X17, + HV_ARM64_REGISTER_X18, + HV_ARM64_REGISTER_X19, + HV_ARM64_REGISTER_X20, + HV_ARM64_REGISTER_X21, + HV_ARM64_REGISTER_X22, + HV_ARM64_REGISTER_X23, + HV_ARM64_REGISTER_X24, + HV_ARM64_REGISTER_X25, + HV_ARM64_REGISTER_X26, + HV_ARM64_REGISTER_X27, + HV_ARM64_REGISTER_X28, + HV_ARM64_REGISTER_FP, + HV_ARM64_REGISTER_LR, + HV_ARM64_REGISTER_PC, +}; + +static int set_standard_regs(const CPUState *cpu) +{ + size_t n_regs =3D ARRAY_SIZE(STANDARD_REGISTER_NAMES); + struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)] = =3D {}; + int ret; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + + for (size_t i =3D 0; i < n_regs - 1; i++) { + assocs[i].name =3D STANDARD_REGISTER_NAMES[i]; + assocs[i].value.reg64 =3D env->xregs[i]; + } + + /* Last register is the program counter */ + assocs[n_regs - 1].name =3D STANDARD_REGISTER_NAMES[n_regs - 1]; + assocs[n_regs - 1].value.reg64 =3D env->pc; + + ret =3D mshv_set_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to set standard registers"); + return -1; + } + + return 0; +} + +static int get_standard_regs(CPUState *cpu) +{ + size_t n_regs =3D ARRAY_SIZE(STANDARD_REGISTER_NAMES); + struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)] = =3D {}; + int ret; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + + for (size_t i =3D 0; i < n_regs; i++) { + assocs[i].name =3D STANDARD_REGISTER_NAMES[i]; + } + ret =3D mshv_get_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to get standard registers"); + return -1; + } + + for (size_t i =3D 0; i < n_regs - 1; i++) { + env->xregs[i] =3D assocs[i].value.reg64; + } + env->pc =3D assocs[n_regs - 1].value.reg64; + + return 0; +} =20 static int load_regs(CPUState *cpu) { + int ret; + + ret =3D get_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to load standard registers"); + return -1; + } + return 0; } =20 static int store_regs(const CPUState *cpu) { + int ret; + + ret =3D set_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to store standard registers"); + return -1; + } + return 0; } =20 @@ -41,12 +152,20 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message= *msg, MshvVmExit *exit) =20 void mshv_arch_init_vcpu(CPUState *cpu) { + AccelCPUState *state =3D cpu->accel; =20 + mshv_setup_hvcall_args(state); } =20 void mshv_arch_destroy_vcpu(CPUState *cpu) { + AccelCPUState *state =3D cpu->accel; + + if (state->hvcall_args.base) { + qemu_vfree(state->hvcall_args.base); + } =20 + state->hvcall_args =3D (MshvHvCallArgs){0}; } =20 int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd) --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852038; cv=none; d=zohomail.com; s=zohoarc; b=FBcXum8+YWf2ycuQ3dH8A/hkAT53EZ4rKEktZqfWLC71eWv0D9J7ZDaHew5YWRbwsy9a8j3rYAoagYUsVmiWFP14wZHXHtCwF27yy0ylMAUT2VyinRCeddYFHTtSHtScaUxDqrYPqYrDMezhrZ4mMJwrqCaCykqHVrWzuaPv4kA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852038; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-6-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852040876158500 Replace the compile-time #if/#elif preprocessor ladder in aarch64_host_initfn() with runtime calls and add mshv_enabled() to it. This ensures the correct accelerator is selected at runtime when multiple accelerators are compiled in. Add CONFIG_MSHV to the aarch64_cpus[] guard so that mshv accelerator can register the "host" CPU type. Signed-off-by: Aastha Rawat --- target/arm/cpu64.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dcd0d698b3..a9e346049d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -811,17 +811,21 @@ void aarch64_host_initfn(Object *obj) } #endif =20 + if (mshv_enabled()) { + mshv_arm_set_cpu_features_from_host(cpu); + } else if (kvm_enabled()) { #if defined(CONFIG_KVM) - kvm_arm_set_cpreg_mig_tolerances(cpu); - kvm_arm_set_cpu_features_from_host(cpu); - aarch64_add_sve_properties(obj); -#elif defined(CONFIG_HVF) - hvf_arm_set_cpu_features_from_host(cpu); -#elif defined(CONFIG_WHPX) - whpx_arm_set_cpu_features_from_host(cpu); -#else - g_assert_not_reached(); + kvm_arm_set_cpreg_mig_tolerances(cpu); #endif + kvm_arm_set_cpu_features_from_host(cpu); + aarch64_add_sve_properties(obj); + } else if (hvf_enabled()) { + hvf_arm_set_cpu_features_from_host(cpu); + } else if (whpx_enabled()) { + whpx_arm_set_cpu_features_from_host(cpu); + } else { + g_assert_not_reached(); + } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_pauth_properties(obj); } @@ -830,7 +834,8 @@ void aarch64_host_initfn(Object *obj) static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || \ + defined(CONFIG_WHPX) || defined(CONFIG_MSHV) { .name =3D "host", .initfn =3D aarch64_host_initfn }, #endif }; --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852056; cv=none; d=zohomail.com; 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Thu, 1 Oct 2026 03:54:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQ2-0005oi-D9; Thu, 01 Oct 2026 06:53:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPL-0005eh-FA; Thu, 01 Oct 2026 06:53:00 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPI-0002Pr-UV; Thu, 01 Oct 2026 06:52:59 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id DA60E20B716C; Thu, 1 Oct 2026 03:52:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com DA60E20B716C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851921; bh=h7x1VQ2/cO6ObnaTE3oiGHXeoaEPG3yQY7j+xBadS5k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RLDwpwnvvN8VWFmEietlyWgwFw7H+n202MeBnMRxjEQolBD1hgbX7CjRprQL7Cr/9 OUHUtozmRsaRkNcVJIzwV55d6k8v5tw4GZB83wYGMaghDasy8yq5p+yMlICKSu6Bip S1Si/IhJ77az9WKdaonoK9qPc+FQVTlXdX2RZ5R8= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:52 +0000 Subject: [PATCH v6 07/14] target/arm/mshv: implement -cpu host for MSHV MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-7-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852057212158500 This commit enables support for the `-cpu host` option with MSHV accelerator on ARM64. The implementation queries the partition's CPU's ID registers and features via hypervisor interface, allowing to pass all CPU capabilities for the host CPU to the guest. Signed-off-by: Aastha Rawat --- hw/arm/virt.c | 3 +- include/hw/hyperv/hvgdk_mini.h | 17 ++++ include/system/hw_accel.h | 3 +- target/arm/cpu.c | 6 +- target/arm/cpu64.c | 2 + target/arm/mshv/mshv-all.c | 217 +++++++++++++++++++++++++++++++++++++= ++++ target/arm/mshv_arm.h | 18 ++++ 7 files changed, 262 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index bdac33a1de8..ee03a85f482 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -48,6 +48,7 @@ #include "system/kvm.h" #include "system/hvf.h" #include "system/whpx.h" +#include "system/mshv.h" #include "system/qtest.h" #include "system/system.h" #include "hw/core/loader.h" @@ -4143,7 +4144,7 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57"))); - if (kvm_enabled() || hvf_enabled() || whpx_enabled()) { + if (kvm_enabled() || hvf_enabled() || whpx_enabled() || mshv_enabl= ed()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host"))); } } diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index b5bcea353aa..33c9e4f3e08 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -67,6 +67,20 @@ typedef enum hv_register_name { HV_ARM64_REGISTER_LR =3D 0x0002001E, HV_ARM64_REGISTER_PC =3D 0x00020022, =20 + /* AArch64 System Register Descriptions: ID Registers */ + HV_ARM64_REGISTER_ID_MIDR_EL1 =3D 0x00022000, + HV_ARM64_REGISTER_ID_MPIDR_EL1 =3D 0x00022005, + HV_ARM64_REGISTER_ID_AA64_PFR0_EL1 =3D 0x00022020, + HV_ARM64_REGISTER_ID_AA64_PFR1_EL1 =3D 0x00022021, + HV_ARM64_REGISTER_ID_AA64_ISAR0_EL1 =3D 0x00022030, + HV_ARM64_REGISTER_ID_AA64_ISAR1_EL1 =3D 0x00022031, + HV_ARM64_REGISTER_ID_AA64_ISAR2_EL1 =3D 0x00022032, + HV_ARM64_REGISTER_ID_AA64_MMFR0_EL1 =3D 0x00022038, + HV_ARM64_REGISTER_ID_AA64_MMFR1_EL1 =3D 0x00022039, + HV_ARM64_REGISTER_ID_AA64_MMFR2_EL1 =3D 0x0002203a, + HV_ARM64_REGISTER_ID_AA64_DFR0_EL1 =3D 0x00022028, + HV_ARM64_REGISTER_ID_AA64_DFR1_EL1 =3D 0x00022029, + /* AArch64 System Register Descriptions: General system control regist= ers */ HV_ARM64_REGISTER_MIDR_EL1 =3D 0x00040051, HV_ARM64_REGISTER_MPIDR_EL1 =3D 0x00040001, @@ -988,6 +1002,9 @@ struct hv_cpuid { #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) =20 +#define HV_ANY_VP ((uint32_t)-1) +#define HV_VTL_ALL 0xF + #define HVCALL_GET_PARTITION_PROPERTY 0x0044 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 #define HVCALL_GET_VP_REGISTERS 0x0050 diff --git a/include/system/hw_accel.h b/include/system/hw_accel.h index f0c10b6d805..614ea60be3f 100644 --- a/include/system/hw_accel.h +++ b/include/system/hw_accel.h @@ -51,7 +51,8 @@ static inline bool hwaccel_enabled(void) return hvf_enabled() || kvm_enabled() || nvmm_enabled() - || whpx_enabled(); + || whpx_enabled() + || mshv_enabled(); } =20 #endif /* QEMU_HW_ACCEL_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10ac6c98318..8ad5e346d1a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -47,6 +47,7 @@ #include "system/tcg.h" #include "system/qtest.h" #include "system/hw_accel.h" +#include "system/mshv.h" #include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" @@ -1843,8 +1844,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * this is the first point where we can report it. */ if (cpu->host_cpu_probe_failed) { - if (!kvm_enabled() && !hvf_enabled() && !whpx_enabled()) { - error_setg(errp, "The 'host' CPU type can only be used with KV= M, HVF or WHPX"); + if (!kvm_enabled() && !hvf_enabled() && !whpx_enabled() && !mshv_e= nabled()) { + error_setg(errp, + "The 'host' CPU type can only be used with KVM, HVF= , WHPX, or MSHV"); } else { error_setg(errp, "Failed to retrieve host CPU features"); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a9e346049df..71fc6824188 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -26,12 +26,14 @@ #include "qemu/units.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/mshv.h" #include "system/whpx.h" #include "system/hw_accel.h" #include "system/qtest.h" #include "system/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "mshv_arm.h" #include "whpx_arm.h" #include "qapi/visitor.h" #include "hw/core/qdev-properties.h" diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c index 29dd45a1231..d835614fd59 100644 --- a/target/arm/mshv/mshv-all.c +++ b/target/arm/mshv/mshv-all.c @@ -18,10 +18,23 @@ =20 #include "system/cpus.h" #include "target/arm/cpu.h" +#include "target/arm/internals.h" +#include "target/arm/mshv_arm.h" =20 #include "system/mshv.h" #include "system/mshv_int.h" #include "hw/hyperv/hvgdk_mini.h" +#include "hw/hyperv/hvhdk_mini.h" + +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; =20 static const enum hv_register_name STANDARD_REGISTER_NAMES[32] =3D { HV_ARM64_REGISTER_X0, @@ -168,8 +181,46 @@ void mshv_arch_destroy_vcpu(CPUState *cpu) state->hvcall_args =3D (MshvHvCallArgs){0}; } =20 + +static uint32_t mshv_arm_get_ipa_bit_size(int mshv_fd) +{ + int ret; + struct hv_input_get_partition_property in =3D {0}; + struct hv_output_get_partition_property out =3D {0}; + struct mshv_root_hvcall args =3D {0}; + + in.property_code =3D HV_PARTITION_PROPERTY_PHYSICAL_ADDRESS_WIDTH; + + args.code =3D HVCALL_GET_PARTITION_PROPERTY; + args.in_sz =3D sizeof(in); + args.in_ptr =3D (uint64_t)∈ + args.out_sz =3D sizeof(out); + args.out_ptr =3D (uint64_t)&out; + + ret =3D mshv_hvcall(mshv_fd, &args); + + if (ret < 0) { + error_report("Failed to get IPA size"); + exit(1); + } + + return out.property_value; +} + int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd) { + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + int pa_range; + uint32_t ipa_size; + + if (mc->get_physical_address_range) { + ipa_size =3D mshv_arm_get_ipa_bit_size(mshv_fd); + pa_range =3D mc->get_physical_address_range(ms, ipa_size, ipa_size= ); + if (pa_range < 0) { + return -EINVAL; + } + } + return 0; } =20 @@ -198,3 +249,169 @@ int mshv_arch_migration_init(MshvState *s) { return 0; } + +static void clamp_id_aa64mmfr0_parange_to_ipa_size(int mshv_fd, + ARMISARegisters *isar) +{ + uint32_t ipa_size =3D mshv_arm_get_ipa_bit_size(mshv_fd); + uint64_t id_aa64mmfr0; + + /* Clamp down the PARange to the IPA size the kernel supports. */ + uint8_t index =3D round_down_to_parange_index(ipa_size); + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D FIELD_DP64(id_aa64mmfr0, ID_AA64MMFR0, PARANGE, index= ); + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); +} + +static int mshv_get_partition_regs(int vm_fd, hv_register_name *names, + hv_register_value *values, size_t n_regs) +{ + int ret =3D 0; + size_t in_sz, names_sz, values_sz; + void *in_buffer =3D qemu_memalign(HV_HYP_PAGE_SIZE, HV_HYP_PAGE_SIZE); + void *out_buffer =3D qemu_memalign(HV_HYP_PAGE_SIZE, HV_HYP_PAGE_SIZE); + hv_input_get_vp_registers *in =3D in_buffer; + + struct mshv_root_hvcall args =3D {0}; + + names_sz =3D n_regs * sizeof(hv_register_name); + in_sz =3D sizeof(hv_input_get_vp_registers) + names_sz; + + memset(in, 0, HV_HYP_PAGE_SIZE); + + in->vp_index =3D HV_ANY_VP; + in->input_vtl.target_vtl =3D HV_VTL_ALL; + in->input_vtl.use_target_vtl =3D 1; + + for (int i =3D 0; i < n_regs; i++) { + in->names[i] =3D names[i]; + } + + values_sz =3D n_regs * sizeof(hv_register_value); + + args.code =3D HVCALL_GET_VP_REGISTERS; + args.in_sz =3D in_sz; + args.in_ptr =3D (uintptr_t)in_buffer; + args.out_sz =3D values_sz; + args.out_ptr =3D (uintptr_t)out_buffer; + args.reps =3D n_regs; + + ret =3D mshv_hvcall(vm_fd, &args); + + if (ret =3D=3D 0) { + memcpy(values, out_buffer, values_sz); + } + + qemu_vfree(in_buffer); + qemu_vfree(out_buffer); + + return ret; +} + +static bool mshv_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + int mshv_fd =3D mshv_state->fd; + int vm_fd =3D mshv_state->vm; + int i, ret; + bool success =3D true; + uint64_t pfr0, pfr1; + gchar *contents =3D NULL; + + static const struct { + hv_register_name name; + int isar_idx; + } regs[] =3D { + { HV_ARM64_REGISTER_ID_AA64_PFR0_EL1, ID_AA64PFR0_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_PFR1_EL1, ID_AA64PFR1_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_ISAR0_EL1, ID_AA64ISAR0_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_ISAR1_EL1, ID_AA64ISAR1_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_ISAR2_EL1, ID_AA64ISAR2_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_MMFR0_EL1, ID_AA64MMFR0_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_MMFR1_EL1, ID_AA64MMFR1_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_MMFR2_EL1, ID_AA64MMFR2_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_DFR0_EL1, ID_AA64DFR0_EL1_IDX }, + { HV_ARM64_REGISTER_ID_AA64_DFR1_EL1, ID_AA64DFR1_EL1_IDX }, + }; + + size_t n_regs =3D ARRAY_SIZE(regs); + hv_register_name *reg_names =3D g_new(hv_register_name, n_regs); + hv_register_value *reg_values =3D g_new(hv_register_value, n_regs); + + for (i =3D 0; i < n_regs; i++) { + reg_names[i] =3D regs[i].name; + } + + ret =3D mshv_get_partition_regs(vm_fd, reg_names, reg_values, n_regs); + + if (ret < 0) { + error_report("Failed to get host ID registers"); + success =3D false; + goto out; + } + + for (i =3D 0; i < n_regs; i++) { + ahcf->isar.idregs[regs[i].isar_idx] =3D reg_values[i].reg64; + } + + /* Read MIDR_EL1 from sysfs */ + if (g_file_get_contents( + "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1", + &contents, NULL, NULL)) { + ahcf->midr =3D g_ascii_strtoull(contents, NULL, 0); + } else { + error_report("Failed to read MIDR_EL1 from sysfs"); + success =3D false; + goto out; + } + + ahcf->dtb_compatible =3D "arm,armv8"; + ahcf->features =3D (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER) | + (1ULL << ARM_FEATURE_NEON); + + clamp_id_aa64mmfr0_parange_to_ipa_size(mshv_fd, &ahcf->isar); + + /* + * SVE (Scalable Vector Extension) and SME (Scalable Matrix Extension) + * require specific context switch logic in the accelerator. + * Mask them out for now to ensure stability. + */ + /* Mask SVE in PFR0 */ + pfr0 =3D GET_IDREG(&ahcf->isar, ID_AA64PFR0); + pfr0 &=3D ~R_ID_AA64PFR0_SVE_MASK; + SET_IDREG(&ahcf->isar, ID_AA64PFR0, pfr0); + + /* Mask SME in PFR1 */ + pfr1 =3D GET_IDREG(&ahcf->isar, ID_AA64PFR1); + pfr1 &=3D ~R_ID_AA64PFR1_SME_MASK; + SET_IDREG(&ahcf->isar, ID_AA64PFR1, pfr1); + +out: + g_free(contents); + g_free(reg_names); + g_free(reg_values); + return success; +} + +void mshv_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!mshv_enabled() || + !mshv_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* + * We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->host_cpu_probe_failed =3D true; + return; + } + } + + cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; + cpu->env.features =3D arm_host_cpu_features.features; + cpu->midr =3D arm_host_cpu_features.midr; + cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; +} diff --git a/target/arm/mshv_arm.h b/target/arm/mshv_arm.h new file mode 100644 index 00000000000..a03f9a4405e --- /dev/null +++ b/target/arm/mshv_arm.h @@ -0,0 +1,18 @@ +/* + * QEMU MSHV support + * + * Copyright Microsoft, Corp. 2026 + * + * Authors: Aastha Rawat + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_MSHV_ARM_H +#define QEMU_MSHV_ARM_H + +#include "target/arm/cpu.h" + +void mshv_arm_set_cpu_features_from_host(ARMCPU *cpu); + +#endif --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851922; bh=kLyvmCLMXT7DfvfYtsKKM05/x39s9i2kRcqJoImJrzw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DbOYKNmvelr5DAYqAnen2Ijx9GHmYXNbGjdD2JhaqSwfZh6Zq1gXoOC54OcV96FCa kYhtjdGcgxwafp3s1ycSLtXBcnIEH91bwAQ3RbxjY59IRYYyDowrwV0aVT35EGwOf7 3qa1rjiWaKitQTaqpZLnmdYts/FnqWo4CYjAukoE= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:53 +0000 Subject: [PATCH v6 08/14] accel/mshv: Add access_vp_regs synthetic proc features MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-8-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852125336158501 Enable access_vp_regs feature for regs. In arm64, this feature bit allows the guest to set VP registers using hypercall. This wasn't required for x86 because such registers are set using wrmsr instead of hypercall. Signed-off-by: Aastha Rawat --- accel/mshv/mshv-all.c | 1 + include/hw/hyperv/hvhdk.h | 91 +++++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index f3f1825b0b..9603f0360e 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -235,6 +235,7 @@ static int set_synthetic_proc_features(int vm_fd) features.tb_flush_hypercalls =3D 1; features.synthetic_cluster_ipi =3D 1; features.direct_synthetic_timers =3D 1; + features.access_vp_regs =3D 1; =20 mshv_arch_amend_proc_features(&features); =20 diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h index 9e6dcb22f6..d0adbea0c7 100644 --- a/include/hw/hyperv/hvhdk.h +++ b/include/hw/hyperv/hvhdk.h @@ -94,11 +94,16 @@ union hv_partition_synthetic_processor_features { */ uint64_t access_partition_reference_tsc:1; =20 +#if defined(__x86_64__) + /* * Partition has access to the guest idle reg. Corresponds to * access_guest_idle_reg privilege. */ uint64_t access_guest_idle_reg:1; +#else + uint64_t reserved_z10:1; +#endif =20 /* * Partition has access to frequency regs. corresponds to @@ -110,11 +115,16 @@ union hv_partition_synthetic_processor_features { uint64_t reserved_z13:1; /* Reserved for access_root_scheduler_reg= */ uint64_t reserved_z14:1; /* Reserved for access_tsc_invariant_cont= rols */ =20 +#if defined(__x86_64__) + /* * Extended GVA ranges for HvCallFlushVirtualAddressList hypercall. * Corresponds to privilege. */ uint64_t enable_extended_gva_ranges_for_flush_virtual_address_list= :1; +#else + uint64_t reserved_z15:1; +#endif =20 uint64_t reserved_z16:1; /* Reserved for access_vsm. */ uint64_t reserved_z17:1; /* Reserved for access_vp_registers. */ @@ -161,13 +171,92 @@ union hv_partition_synthetic_processor_features { /* HvCallRetargetDeviceInterrupt is supported. */ uint64_t retarget_device_interrupt:1; =20 +#if defined(__x86_64__) /* HvCallRestorePartitionTime is supported. */ uint64_t restore_time:1; =20 /* EnlightenedVmcs nested enlightenment is supported. */ uint64_t enlightened_vmcs:1; =20 - uint64_t reserved:30; + uint64_t nested_debug_ctl:1; + uint64_t synthetic_time_unhalted_timer:1; + uint64_t idle_spec_ctrl:1; + +#else + uint64_t reserved_z31:1; + uint64_t reserved_z32:1; + uint64_t reserved_z33:1; + uint64_t reserved_z34:1; + uint64_t reserved_z35:1; +#endif + +#if defined(__aarch64__) + /* + * Register intercepts supported in V1. As more registers are supp= orted + * in future releases, new bits will be added here to prevent migr= ation + * between incompatible hosts. + * + * List of registers supported in V1: + * 1. TPIDRRO_EL0 + * 2. TPIDR_EL1 + * 3. SCTLR_EL1 - Supports write intercept mask. + * 4. VBAR_EL1 + * 5. TCR_EL1 - Supports write intercept mask. + * 6. MAIR_EL1 - Supports write intercept mask. + * 7. CPACR_EL1 - Supports write intercept mask. + * 8. CONTEXTIDR_EL1 + * 9. PAuth keys (total 10 registers) + * 10. HvArm64RegisterSyntheticException + */ + uint64_t register_intercepts_v1:1; +#else + uint64_t reserved_z36:1; +#endif + + /* HvCallWakeVps is supported */ + uint64_t wake_vps:1; + + /* + * HvCallGet/SetVpRegisters is supported. + * Corresponds to AccessVpRegisters privilege. + * This feature only affects exo partitions. + */ + uint64_t access_vp_regs:1; + +#if defined(__aarch64__) + /* HvCallSyncContext/Ex is supported. */ + uint64_t sync_context:1; +#else + uint64_t reserved_z39:1; +#endif /* __aarch64__ */ + + /* + * Management VTL synic support is allowed. + * Corresponds to the ManagementVtlSynicSupport privilege. + */ + uint64_t management_vtl_synic_support:1; + +#if defined(__x86_64__) + /* + * Hypervisor supports guest mechanism to signal pending interrupt= s to + * paravisor. + */ + uint64_t proxy_interrupt_doorbell_support:1; +#else + uint64_t reserved_z41:1; +#endif + +#if defined(__aarch64__) + /* InterceptSystemResetAvailable is exposed. */ + uint64_t intercept_system_reset:1; +#else + uint64_t reserved_z42:1; +#endif + + /* Hypercalls for host MMIO operations are available. */ + uint64_t mmio_hypercalls:1; + + uint64_t reserved:20; }; }; =20 --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852071; cv=none; d=zohomail.com; s=zohoarc; b=XhQ4Y4P6myPal7AcD6ShXmfu5sZj05qHlrFDobNwZZW40Y1t4YfLY9sliFzbgpI3ovGjdRcqg4EKj6xE4OwW4OuNoHEj28g1pqkJo0OGBxcgxb+/LvRaTErK3XoSPbZHtWqXmUOqQQDPbdTwGFY+6UUhN9L12nWXWkgKSzhlW5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852071; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uSXwHTJb8tc67PA6p6qDCz/p3md3rYFwY3c6sCXie60=; b=kk7w8kRglhiJVWgWo5B6OnNvFF5grsavEdld1p8cWazwG11E5O7hqzPVcLyu073bQRF6SNFP5whwjY2ZKbcFlZBOcyr8m5x8OQ12dnq4e+jrIQygMvgaK/wNne1dCY/DnfonpX99QkyQijmq0HTsPQPAErqsq7onZQ0T0x3aHIM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790852071897300.7752270653524; Thu, 1 Oct 2026 03:54:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQB-0005yx-NZ; Thu, 01 Oct 2026 06:53:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPk-0005ir-L0; Thu, 01 Oct 2026 06:53:29 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPf-0002QN-BF; Thu, 01 Oct 2026 06:53:22 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 9C95820B7171; Thu, 1 Oct 2026 03:52:03 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 9C95820B7171 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851923; bh=uSXwHTJb8tc67PA6p6qDCz/p3md3rYFwY3c6sCXie60=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hMWhMQb9jr7aFn/i2N4X/6MjFQRaVO9FNJic00peoT1HbnNP1vQwBgYsy9cr20WLJ 6a6P+emJlm/YO39SbxiT4Tsv3G7one2dOFxzJHqOu5G3duHp+rdZVnTLVHMEfSHsJb lIsbA7BNW4MM3A3Bag8d3/Ivehbcb1NsOMyxDywo= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:54 +0000 Subject: [PATCH v6 09/14] target/arm: cpu: Mark MSHV supporting PSCI 1.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-9-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. 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Expose this version to guests. Signed-off-by: Aastha Rawat Reviewed-by: Mohamed Mediouni --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8ad5e346d1..624cb72610 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1295,7 +1295,7 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled() || hvf_enabled()) { /* TCG and HVF implement PSCI 1.1 */ cpu->psci_version =3D QEMU_PSCI_VERSION_1_1; - } else if (whpx_enabled()) { + } else if (whpx_enabled() || mshv_enabled()) { cpu->psci_version =3D QEMU_PSCI_VERSION_1_3; } } --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852092; cv=none; d=zohomail.com; s=zohoarc; b=FlnnFzKDlAVZtZar2CmxCUZLRCJ7FOXA0BdkerqTZnpevpdCU8KOmC5RpdgaBp8yDQ4vPwSL6rWI6ILu0bqVpCGWTQv+1TDOfKwWV/6IEO7jqEv2Of0Vhbls/wVADCdsZOcQGuGOdsnDE0mYrNQqB9zbyH/2/WrU5Xu55N14Tc0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852092; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CoV8Sy7A5mnADwg7UKQwOQeAVfM/T8H4zfhB+xDhULQ=; b=OproPkTzFuU1+c/xh7bhlZ/7frRMakWG3gIiyBFZ8QvT9IKSk1V7Nka5xH3AtpkaN6XIM5Drk9O3T4KJOWM2lm85oW1qBfvOIi7/QsS0e3mv9ptRE1CvHn7HhKlHul0stI6Ni+4UKW9c47lU+3sFFZyoS1HEiMw5lVpbShEHV9o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179085209287036.69250093721257; Thu, 1 Oct 2026 03:54:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQF-00063F-2y; Thu, 01 Oct 2026 06:53:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPM-0005ek-KN; Thu, 01 Oct 2026 06:53:02 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPK-0002Pa-D9; Thu, 01 Oct 2026 06:53:00 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 1FE4C20B716E; Thu, 1 Oct 2026 03:52:04 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 1FE4C20B716E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851924; bh=CoV8Sy7A5mnADwg7UKQwOQeAVfM/T8H4zfhB+xDhULQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=h1Fowt8e3B9PwB0J2Cp+/JX0RHUwhH0xkO6cWPtUuwHTjeLTTFXmkQKstc9Pwxor6 fNu9NxgtL9fuihccp9pzS4yZUYsM5mifCml89ZvEhSF6y4X8KtJQNKu/++uHXCQZ/A foLPAdHA97E2QhjzW3wBXsMuvt8rmykh1c+CxGC4= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:55 +0000 Subject: [PATCH v6 10/14] target/arm: extract MMIO emulation logic for HVF & WHPX MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-10-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852095443158500 - Move common MMIO emulation code from HVF and WHPX backend to arm_emulate_mmio() in helper.c. - Update HVF and WHPX to use the new helper and shared types. Signed-off-by: Aastha Rawat --- target/arm/helper.c | 62 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/helper.h | 16 ++++++++++++ target/arm/hvf/hvf.c | 57 +++++++++++++++++++----------------------- target/arm/syndrome.h | 47 +++++++++++++++++++++++++++++++++++ target/arm/whpx/whpx-all.c | 45 ++++++++++++++------------------- 5 files changed, 169 insertions(+), 58 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ff0b766b73d..5b14f0bff72 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,8 @@ #endif #include "cpregs.h" #include "target/arm/gtimer.h" +#include "target/arm/helper.h" +#include "target/arm/syndrome.h" #include "qemu/plugin.h" =20 static void switch_mode(CPUARMState *env, int mode); @@ -9455,6 +9457,66 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) take_aarch32_exception(env, new_mode, mask, offset, addr); } =20 +/* + * Emulate a data abort syndrome for MMIO/guest memory access + */ +int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa, + const struct arm_emul_ops *ops) +{ + int ret; + IssDataAbort iss =3D { 0 }; + iss.raw =3D syndrome.iss; + + if (!(syndrome.ec =3D=3D data_abort_lower || syndrome.ec =3D=3D data_a= bort)) { + error_report("Unknown exception class 0x%x", syndrome.ec); + return -1; + } + + if (!iss.isv) { + error_report("Cannot emulate MMIO. ISS not valid."); + return -1; + } + + AddressSpace *as =3D cpu_get_address_space(cpu, ARMASIdx_NS); + uint64_t len =3D 1ULL << iss.sas; + bool sign_extend =3D iss.sse; + uint64_t reg_index =3D iss.srt; + + if (iss.wnr) { + uint8_t data[8]; + uint64_t val =3D reg_index < 31 ? ops->get_reg(cpu, reg_index) : 0= ULL; + val =3D cpu_to_le64(val); + memcpy(data, &val, sizeof(val)); + ret =3D address_space_write(as, gpa, MEMTXATTRS_UNSPECIFIED, data,= len); + if (ret !=3D MEMTX_OK) { + error_report("Failed to write guest memory"); + return -1; + } + } else { + uint8_t data[8] =3D { 0 }; + ret =3D address_space_read(as, gpa, MEMTXATTRS_UNSPECIFIED, data, = len); + if (ret !=3D MEMTX_OK) { + error_report("Failed to read guest memory"); + return -1; + } + uint64_t val; + memcpy(&val, data, sizeof(val)); + val =3D le64_to_cpu(val); + if (sign_extend) { + uint64_t shift =3D 64 - (len * 8); + val =3D (((int64_t)val << shift) >> shift); + } + if (!iss.sf) { + val &=3D 0xffffffff; + } + if (reg_index < 31) { + ops->set_reg(cpu, reg_index, val); + } + } + + return 0; +} + static int aarch64_regnum(CPUARMState *env, int aarch32_reg) { /* diff --git a/target/arm/helper.h b/target/arm/helper.h index b1c26c180ea..503404112d4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,8 +3,24 @@ #ifndef HELPER__H #define HELPER__H =20 +#include +#include #include "exec/helper-proto-common.h" #include "exec/helper-gen-common.h" +#include "target/arm/syndrome.h" + +/* + * Callback ops for per-register access during MMIO emulation. + * Each hypervisor backend provides its own implementation to avoid + * syncing the full CPU state for a single-register MMIO access. + */ +struct arm_emul_ops { + uint64_t (*get_reg)(CPUState *cpu, int reg); + void (*set_reg)(CPUState *cpu, int reg, uint64_t val); +}; + +int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa, + const struct arm_emul_ops *ops); =20 #define HELPER_H "tcg/helper-defs.h" #include "exec/helper-proto.h.inc" diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b00a7e1a845..99a66a68812 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -13,6 +13,7 @@ #include "qemu/error-report.h" #include "qemu/log.h" =20 +#include "syndrome.h" #include "system/runstate.h" #include "system/hvf.h" #include "system/hvf_int.h" @@ -37,6 +38,7 @@ #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" #include "target/arm/trace.h" +#include "target/arm/helper.h" #include "trace.h" #include "migration/vmstate.h" =20 @@ -2338,12 +2340,15 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) { CPUARMState *env =3D cpu_env(cpu); ARMCPU *arm_cpu =3D env_archcpu(env); - uint64_t syndrome =3D excp->syndrome; - uint32_t ec =3D syn_get_ec(syndrome); + uint64_t syndrome; + uint32_t ec; bool advance_pc =3D false; hv_return_t r; int ret =3D 0; =20 + syndrome =3D excp->syndrome; + ec =3D syn_get_ec(syndrome); + switch (ec) { case EC_SOFTWARESTEP: { ret =3D EXCP_DEBUG; @@ -2389,29 +2394,22 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) break; } case EC_DATAABORT: { - bool isv =3D FIELD_EX32(syndrome, DABORT_ISS, ISV); - bool iswrite =3D FIELD_EX32(syndrome, DABORT_ISS, WNR); - bool s1ptw =3D FIELD_EX32(syndrome, DABORT_ISS, S1PTW); - bool sse =3D FIELD_EX32(syndrome, DABORT_ISS, SSE); - uint32_t sas =3D FIELD_EX32(syndrome, DABORT_ISS, SAS); - uint32_t len =3D 1 << sas; - uint32_t srt =3D FIELD_EX32(syndrome, DABORT_ISS, SRT); - uint32_t cm =3D FIELD_EX32(syndrome, DABORT_ISS, CM); - uint64_t val =3D 0; + EsrEl2 esr_el2 =3D { .raw =3D syndrome }; + IssDataAbort iss =3D { .raw =3D esr_el2.iss }; uint64_t ipa =3D excp->physical_address; AddressSpace *as =3D cpu_get_address_space(cpu, ARMASIdx_NS); =20 - trace_hvf_data_abort(excp->virtual_address, ipa, isv, - iswrite, s1ptw, len, srt); + trace_hvf_data_abort(excp->virtual_address, ipa, iss.isv, + iss.wnr, iss.s1ptw, 1ULL << iss.sas, iss.srt); =20 - if (cm) { + if (iss.cm) { /* We don't cache MMIO regions */ advance_pc =3D true; break; } =20 /* Handle dirty page logging for ram. */ - if (iswrite) { + if (iss.wnr) { hwaddr xlat; MemoryRegion *mr =3D address_space_translate(as, ipa, &xlat, NULL, true, @@ -2438,28 +2436,25 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) * TODO: If s1ptw, this is an error in the guest os page tables. * Inject the exception into the guest. */ - assert(!s1ptw); - - /* - * TODO: ISV will be 0 for SIMD or SVE accesses. - * Inject the exception into the guest. - */ - assert(isv); + assert(!iss.s1ptw); =20 /* * Emulate MMIO. * TODO: Inject faults for errors. */ - if (iswrite) { - val =3D hvf_get_reg(cpu, srt); - address_space_write(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len= ); - } else { - address_space_read(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len); - if (sse) { - val =3D sextract64(val, 0, len * 8); - } - hvf_set_reg(cpu, srt, val); + + static const struct arm_emul_ops hvf_arm_emul_ops =3D { + .get_reg =3D hvf_get_reg, + .set_reg =3D hvf_set_reg, + }; + + ret =3D arm_emulate_mmio(cpu, esr_el2, ipa, &hvf_arm_emul_ops); + if (ret < 0) { + error_report("Failed to emulate MMIO, syndrome=3D0x%llx, gpa= =3D0x%llx", + esr_el2.raw, ipa); + return -1; } + advance_pc =3D true; break; } diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 2a6fa903f27..8b4cc7f7b21 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -106,6 +106,53 @@ typedef enum { GCS_IT_GCSPOPX =3D 9, } GCSInstructionType; =20 +typedef union { + uint64_t raw; + struct { + uint32_t iss:25; + uint32_t il:1; + uint32_t ec:6; + uint32_t iss2:5; + uint32_t _rsvd:27; + } QEMU_PACKED; +} EsrEl2; + +typedef union { + uint32_t raw; + struct { + uint32_t dfsc:6; + uint32_t wnr:1; + uint32_t s1ptw:1; + uint32_t cm:1; + uint32_t ea:1; + uint32_t fnv:1; + uint32_t set:2; + uint32_t vncr:1; + uint32_t ar:1; + uint32_t sf:1; + uint32_t srt:5; + uint32_t sse:1; + uint32_t sas:2; + uint32_t isv:1; + uint32_t _unused:7; + } QEMU_PACKED; +} IssDataAbort; + +typedef enum { + data_abort_lower =3D 36, + data_abort =3D 37, +} ExceptionClass; + +#define ARM_EL_EC_LENGTH 6 +#define ARM_EL_EC_SHIFT 26 +#define ARM_EL_IL_SHIFT 25 +#define ARM_EL_ISV_SHIFT 24 +#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) +#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) + +/* In the Data Abort syndrome */ +#define ARM_EL_VNCR (1 << 13) + static inline uint32_t syn_get_ec(uint32_t syn) { return FIELD_EX32(syn, SYNDROME, EC); diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 46f0b9524e0..93d89f79ffe 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -28,6 +28,8 @@ =20 #include "syndrome.h" #include "target/arm/cpregs.h" +#include "target/arm/helper.h" +#include "target/arm/syndrome.h" #include "internals.h" =20 #include "system/whpx-internal.h" @@ -352,34 +354,23 @@ static void whpx_set_gp_reg(CPUState *cpu, int rt, ui= nt64_t val) =20 static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { - uint64_t syndrome =3D ctx->Syndrome; - - bool isv =3D FIELD_EX32(syndrome, DABORT_ISS, ISV); - bool iswrite =3D FIELD_EX32(syndrome, DABORT_ISS, WNR); - bool sse =3D FIELD_EX32(syndrome, DABORT_ISS, SSE); - uint32_t sas =3D FIELD_EX32(syndrome, DABORT_ISS, SAS); - uint32_t len =3D 1 << sas; - uint32_t srt =3D FIELD_EX32(syndrome, DABORT_ISS, SRT); - uint32_t cm =3D FIELD_EX32(syndrome, DABORT_ISS, CM); - uint64_t val =3D 0; - - assert(syn_get_ec(syndrome) =3D=3D EC_DATAABORT); + int ret =3D 0; + EsrEl2 esr =3D { .raw =3D ctx->Syndrome }; + uint32_t cm =3D (esr.iss >> 8) & 0x1; + + assert(syn_get_ec(esr.raw) =3D=3D EC_DATAABORT); assert(!cm); - assert(isv); - - if (iswrite) { - val =3D whpx_get_gp_reg(cpu, srt); - address_space_write(&address_space_memory, - ctx->Gpa, - MEMTXATTRS_UNSPECIFIED, &val, len); - } else { - address_space_read(&address_space_memory, - ctx->Gpa, - MEMTXATTRS_UNSPECIFIED, &val, len); - if (sse) { - val =3D sextract64(val, 0, len * 8); - } - whpx_set_gp_reg(cpu, srt, val); + + static const struct arm_emul_ops whpx_arm_emul_ops =3D { + .get_reg =3D whpx_get_gp_reg, + .set_reg =3D whpx_set_gp_reg, + }; + + ret =3D arm_emulate_mmio(cpu, esr, ctx->Gpa, &whpx_arm_emul_ops); + if (ret < 0) { + error_report("WHPX: Failed to handle MMIO, syndrome=3D0x%llx, gpa= =3D0x%llx", + esr.raw, ctx->Gpa); + return -1; } =20 return 0; --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852108; cv=none; d=zohomail.com; s=zohoarc; b=nDpae/W1uDCfauLMqcp53PgybJIZPAodU5GJVG+H1uteZJcxLYMaqVZn7+9ByR1pTRGU0oUOkB0pAcrZ5H9M7MUNqguRfUpnieOHODNU3JQVL0MawHl25+q4nKWsI9eMISbXMT0e02/LnWwFEdFiqPo0Q4F+OVDPRNKKj9EAr4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852108; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 01 Oct 2026 06:53:29 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPf-0002PZ-BG; Thu, 01 Oct 2026 06:53:23 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 1543C20B7170; Thu, 1 Oct 2026 03:52:05 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 1543C20B7170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851925; bh=g32FtN7zhAeCl2w8hrf4rtf6fwQeoKilahj640QmQXQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kV1gNORdxbLn0dkkvwensOwOblLftn/G5u8y1Myps5H5D7TIOWBSiV8ZlgjpSGdiq h/szVhRO15TKE/kJeQZdTOBdEgeuEjNaq8DZ/drjS+nms46XbiqgxshqYEshw1TiZN gBbNL2BsiVe12paAMd4RNCdRa35pNVD1y0QSU13o= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:56 +0000 Subject: [PATCH v6 11/14] target/arm/mshv: add vCPU run loop MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-11-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852109101158500 From: "Anirudh Rayabharam (Microsoft)" Add the main vCPU run loop for MSHV using the MSHV_RUN_VP_IOCTL. Handle MMIO exits by emulating the instruction using the syndrome information from ESR_EL2. Signed-off-by: Anirudh Rayabharam (Microsoft) --- include/hw/hyperv/hvgdk_mini.h | 44 +++++++++++++++++ target/arm/mshv/mshv-all.c | 107 +++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 151 insertions(+) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index 33c9e4f3e0..53dc58813e 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -896,6 +896,50 @@ struct hv_x64_memory_intercept_message { uint8_t instruction_bytes[16]; } QEMU_PACKED; =20 +union hv_arm64_vp_execution_state { + uint16_t as_uint16; + struct { + uint16_t cpl:2; + uint16_t debug_active:1; + uint16_t interruption_pending:1; + uint16_t vtl:4; + uint16_t virtualization_fault_active:1; + uint16_t reserved:7; + }; +}; + +struct hv_arm64_intercept_message_header { + uint32_t vp_index; + uint8_t instruction_length; + uint8_t intercept_access_type; + union hv_arm64_vp_execution_state execution_state; + uint64_t pc; + uint64_t cpsr; +}; + +union hv_arm64_memory_access_info { + uint8_t as_uint8; + struct { + uint8_t gva_valid:1; + uint8_t gva_gpa_valid:1; + uint8_t hypercall_output_pending:1; + uint8_t reserved:5; + }; +}; + +struct hv_arm64_memory_intercept_message { + struct hv_arm64_intercept_message_header header; + uint32_t cache_type; /* enum hv_cache_type */ + uint8_t instruction_byte_count; + union hv_arm64_memory_access_info memory_access_info; + uint16_t reserved1; + uint8_t instruction_bytes[4]; + uint32_t reserved2; + uint64_t guest_virtual_address; + uint64_t guest_physical_address; + uint64_t syndrome; +}; + union hv_message_flags { uint8_t asu8; struct { diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c index d835614fd5..786d815312 100644 --- a/target/arm/mshv/mshv-all.c +++ b/target/arm/mshv/mshv-all.c @@ -20,6 +20,7 @@ #include "target/arm/cpu.h" #include "target/arm/internals.h" #include "target/arm/mshv_arm.h" +#include "target/arm/helper.h" =20 #include "system/mshv.h" #include "system/mshv_int.h" @@ -158,8 +159,114 @@ int mshv_arch_store_vcpu_state(const CPUState *cpu) return store_regs(cpu); } =20 +static int set_memory_info(const struct hyperv_message *msg, + struct hv_arm64_memory_intercept_message *info) +{ + if (msg->header.message_type !=3D HVMSG_GPA_INTERCEPT + && msg->header.message_type !=3D HVMSG_UNMAPPED_GPA + && msg->header.message_type !=3D HVMSG_UNACCEPTED_GPA) { + error_report("invalid message type"); + return -1; + } + memcpy(info, msg->payload, sizeof(*info)); + + return 0; +} + +static uint64_t mshv_mmio_get_reg(CPUState *cpu, int reg_index) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + return reg_index < 31 ? env->xregs[reg_index] : 0ULL; +} + +static void mshv_mmio_set_reg(CPUState *cpu, int reg_index, uint64_t val) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + if (reg_index < 31) { + env->xregs[reg_index] =3D val; + } +} + +static int handle_unmapped_mem(int vm_fd, CPUState *cpu, + const struct hyperv_message *msg, + MshvVmExit *exit_reason) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + struct hv_arm64_memory_intercept_message info =3D { 0 }; + int ret; + EsrEl2 syndrome; + + ret =3D set_memory_info(msg, &info); + if (ret < 0) { + error_report("failed to convert message to memory info"); + return -1; + } + + syndrome.raw =3D info.syndrome; + + ret =3D load_regs(cpu); + if (ret < 0) { + error_report("Failed to load registers"); + return -1; + } + + static const struct arm_emul_ops mshv_arm_emul_ops =3D { + .get_reg =3D mshv_mmio_get_reg, + .set_reg =3D mshv_mmio_set_reg, + }; + + ret =3D arm_emulate_mmio(cpu, syndrome, info.guest_physical_address, + &mshv_arm_emul_ops); + if (ret < 0) { + error_report("Failed to emulate with syndrome"); + return -1; + } + + /* Advance PC past the faulting instruction */ + env->pc +=3D (syndrome.il =3D=3D 1) ? 4 : 2; + + ret =3D store_regs(cpu); + if (ret < 0) { + error_report("Failed to store registers"); + return -1; + } + + *exit_reason =3D MshvVmExitIgnore; + + return 0; +} + int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit) { + int ret; + int cpu_fd =3D mshv_vcpufd(cpu); + + ret =3D ioctl(cpu_fd, MSHV_RUN_VP, msg); + if (ret < 0) { + *exit =3D MshvVmExitShutdown; + return ret; + } + + switch (msg->header.message_type) { + case HVMSG_UNRECOVERABLE_EXCEPTION: + *exit =3D MshvVmExitShutdown; + break; + case HVMSG_GPA_INTERCEPT: + case HVMSG_UNMAPPED_GPA: + ret =3D handle_unmapped_mem(vm_fd, cpu, msg, exit); + if (ret < 0) { + error_report("failed to handle mmio"); + return -1; + } + break; + default: + error_report("Unhandled message type: 0x%x", msg->header.message_t= ype); + return -1; + } + return 0; } =20 --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852087; cv=none; d=zohomail.com; s=zohoarc; b=dsuFCCp74aatQ0idXVYdy3FxQeJmR5LHtQjw4PdQqiIN+YKDvoSqSuFxwtVRwErJ/hJwdgbUbjOthP8qjUIiVCkodGXFkWD77I5zdhfnFa7CfmXFC/CcrQGnhRc92m8ENS5M1kN4SEjeTxvewUElnDtTWHkSEmJQ1biXYOYJ388= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852087; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ztMns0JIKVqtle/u8ZbtSkyBlQL02nAkjxvnQRhIFBg=; b=nUQhocR3LqlLxxdIDZ+51kb+4oTL/R+zCy9jN4PiUM/Ww+ZG7B8bMiJrwVa2QK3biBFDPeGxpUzVWCLnF9mgv7ldBWRX99xmEPXOCQJ0DbvSSJ62PoT0jendbcMnDsqJJdK1N5PJlhFPcQAfAAkhyFFkrLk/7mP/CoFp3l0BZVM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790852087373573.2147457678326; Thu, 1 Oct 2026 03:54:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQG-00065N-1l; Thu, 01 Oct 2026 06:53:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPk-0005is-L4; Thu, 01 Oct 2026 06:53:29 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPf-0002Pw-M5; Thu, 01 Oct 2026 06:53:22 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id D63B920B7172; Thu, 1 Oct 2026 03:52:05 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com D63B920B7172 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851925; bh=ztMns0JIKVqtle/u8ZbtSkyBlQL02nAkjxvnQRhIFBg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=S9j8xA5lKPnU5n2Puj1msk8IJpCkB5zFKVxXdSaZSI81vf0HkGWMoGxp2gbC7DL38 ldIJVb4AmSEStmw3uD/wSYjMOuwdkSOVJMr3EkShcGxG2wmI4jSc4oSOx0uIXw1IPr RjA7bVXANZOiwGZiQMD7az44UobuWwaIoqRwjMXM= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:57 +0000 Subject: [PATCH v6 12/14] include/hw/hyperv: adjust hv_interrupt_control structure for arm64 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-12-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852089314158500 From: "Anirudh Rayabharam (Microsoft)" Add the arm64 specific fields to the hv_interrupt_control struct and adjust the existing usage accordingly. mshv_request_interrupt is only needed only for x86 so compile it out entirely for arm64. Signed-off-by: Anirudh Rayabharam (Microsoft) --- accel/mshv/irq.c | 2 ++ include/hw/hyperv/hvgdk_mini.h | 24 ++++++++++++++++++++++++ include/system/mshv.h | 2 ++ 3 files changed, 28 insertions(+) diff --git a/accel/mshv/irq.c b/accel/mshv/irq.c index 4828ac51ac..f18e6a0f66 100644 --- a/accel/mshv/irq.c +++ b/accel/mshv/irq.c @@ -259,6 +259,7 @@ int mshv_irqchip_update_msi_route(int virq, MSIMessage = msg, PCIDevice *dev) return 0; } =20 +#if defined(__x86_64__) int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type,= uint32_t vector, uint32_t vp_index, bool logical_dest_mode, bool level_triggered) @@ -295,6 +296,7 @@ int mshv_request_interrupt(MshvState *mshv_state, uint3= 2_t interrupt_type, uint3 } return 0; } +#endif =20 void mshv_irqchip_commit_routes(MshvState *s) { diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index 53dc58813e..d81c9816e7 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -543,14 +543,38 @@ typedef struct hv_input_set_vp_registers { } QEMU_PACKED hv_input_set_vp_registers; =20 #define MSHV_VP_MAX_REGISTERS 128 +enum hv_interrupt_type { +#if defined(__x86_64__) + HV_X64_INTERRUPT_TYPE_FIXED =3D 0x0000, + HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY =3D 0x0001, + HV_X64_INTERRUPT_TYPE_SMI =3D 0x0002, + HV_X64_INTERRUPT_TYPE_REMOTEREAD =3D 0x0003, + HV_X64_INTERRUPT_TYPE_NMI =3D 0x0004, + HV_X64_INTERRUPT_TYPE_INIT =3D 0x0005, + HV_X64_INTERRUPT_TYPE_SIPI =3D 0x0006, + HV_X64_INTERRUPT_TYPE_EXTINT =3D 0x0007, + HV_X64_INTERRUPT_TYPE_LOCALINT0 =3D 0x0008, + HV_X64_INTERRUPT_TYPE_LOCALINT1 =3D 0x0009, + HV_X64_INTERRUPT_TYPE_MAXIMUM =3D 0x000A, +#elif defined(__aarch64__) + HV_ARM64_INTERRUPT_TYPE_FIXED =3D 0x0000, + HV_ARM64_INTERRUPT_TYPE_MAXIMUM =3D 0x0008, +#endif +}; =20 union hv_interrupt_control { uint64_t as_uint64; struct { uint32_t interrupt_type; /* enum hv_interrupt type */ +#if defined(__x86_64__) uint32_t level_triggered:1; uint32_t logical_dest_mode:1; uint32_t rsvd:30; +#elif defined(__aarch64__) + uint32_t rsvd1:2; + uint32_t asserted:1; + uint32_t rsvd2:29; +#endif }; }; =20 diff --git a/include/system/mshv.h b/include/system/mshv.h index 114f065db5..80b6712af9 100644 --- a/include/system/mshv.h +++ b/include/system/mshv.h @@ -60,10 +60,12 @@ extern MshvState *mshv_state; /* clock (partition reference time) */ void mshv_arch_clock_init(void); =20 +#if defined(__x86_64__) /* interrupt */ int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type,= uint32_t vector, uint32_t vp_index, bool logical_destination_mod= e, bool level_triggered); +#endif =20 int mshv_irqchip_add_msi_route(AccelRouteChange *c, int vector, PCIDevice = *dev); int mshv_irqchip_update_msi_route(int virq, MSIMessage msg, PCIDevice *dev= ); --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851926; bh=kO5yDa9MjuEH9aJfOVbxhXNcke2p8aFjNpu6Rd0pTuE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DUUTpSUrKKJ1W/4hKG93p63XCnnguWusBUM42NoLUPTNYNnN0UIvkPPobztSAIOKa LqJSORGDzV2duZq38kNQDPlxmLcvTdtOIie0eUdGw8inwWT8Sza1e92WdS0HudyM9t NFdSHtrjlE2hH/SJdZNX/GiEfA+q5af8cqU0t31A= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:58 +0000 Subject: [PATCH v6 13/14] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-13-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852042776158500 From: "Anirudh Rayabharam (Microsoft)" Add in-kernel GICv3 support for the MSHV accelerator, following the same approach as the KVM and WHPX vGIC backends. The implementation handles IRQ injection via the HVCALL_ASSERT_VIRTUAL_INTERRUPT hypercall. Introduce mshv_arch_pre_init_vm(), an arch-specific hook called after VM creation but before VM initialization, used on arm64 to configure GIC partition properties (GICD base, ITS translater base, timer and PMU PPI numbers). The x86 side provides a no-op stub. Update the virt machine to treat MSHV like WHPX for GIC version selection (GICv3 only) and MSI controller finalization (no ITS support). Signed-off-by: Anirudh Rayabharam (Microsoft) --- accel/mshv/mshv-all.c | 5 + hw/arm/virt.c | 8 +- hw/intc/arm_gicv3_common.c | 3 + hw/intc/arm_gicv3_mshv.c | 181 +++++++++++++++++++++++++++++++++= ++++ hw/intc/meson.build | 2 + include/hw/hyperv/hvgdk_mini.h | 2 + include/hw/hyperv/hvhdk_mini.h | 6 ++ include/hw/intc/arm_gicv3_common.h | 1 + include/system/mshv_int.h | 1 + target/arm/mshv/mshv-all.c | 61 +++++++++++++ target/i386/mshv/mshv-all.c | 5 + 11 files changed, 273 insertions(+), 2 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 9603f0360e1..e1264952873 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -279,6 +279,11 @@ static int create_vm(int mshv_fd, int *vm_fd) return -1; } =20 + ret =3D mshv_arch_pre_init_vm(*vm_fd); + if (ret < 0) { + return -1; + } + ret =3D initialize_vm(*vm_fd); if (ret < 0) { return -1; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ee03a85f482..67a1f19190b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2706,7 +2706,7 @@ static void finalize_gic_version(VirtMachineState *vm= s) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; - } else if (whpx_enabled()) { + } else if (whpx_enabled() || mshv_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_3_MASK; } else if (hvf_enabled()) { if (!hvf_irqchip_in_kernel()) { @@ -2760,7 +2760,7 @@ static void finalize_msi_controller(VirtMachineState = *vms) if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_AUTO) { if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; - } else if (whpx_enabled()) { + } else if (whpx_enabled() || mshv_enabled()) { vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } else if (hvf_enabled() && hvf_irqchip_in_kernel()) { vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; @@ -2790,6 +2790,10 @@ static void finalize_msi_controller(VirtMachineState= *vms) error_report("ITS not supported on WHPX."); exit(1); } + if (mshv_enabled()) { + error_report("ITS not supported on MSHV."); + exit(1); + } if (hvf_enabled() && hvf_irqchip_in_kernel()) { error_report("ITS not supported on HVF when using the hardware= vGIC."); exit(1); diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index f7ba74e6d52..fb34b6a942d 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -34,6 +34,7 @@ #include "system/kvm.h" #include "system/whpx.h" #include "system/hvf.h" +#include "system/mshv.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -662,6 +663,8 @@ const char *gicv3_class_name(void) return TYPE_WHPX_GICV3; } else if (hvf_enabled() && hvf_irqchip_in_kernel()) { return TYPE_HVF_GICV3; + } else if (mshv_enabled()) { + return TYPE_MSHV_GICV3; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/hw/intc/arm_gicv3_mshv.c b/hw/intc/arm_gicv3_mshv.c new file mode 100644 index 00000000000..a87819a5ba3 --- /dev/null +++ b/hw/intc/arm_gicv3_mshv.c @@ -0,0 +1,181 @@ +/* + * ARM Generic Interrupt Controller using MSHV in-kernel support + * + * Copyright Microsoft, Corp. 2026 + * Based on vGICv3 KVM code by Pavel Fedin + * + * Authors: + * Aastha Rawat + * Anirudh Rayabharam (Microsoft) + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "hw/intc/arm_gicv3_common.h" +#include "migration/blocker.h" +#include "target/arm/cpregs.h" +#include "hw/hyperv/hvgdk_mini.h" +#include "system/mshv.h" +#include "system/mshv_int.h" + +struct MSHVARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +OBJECT_DECLARE_TYPE(GICv3State, MSHVARMGICv3Class, MSHV_GICV3) + +static void mshv_gicv3_get(GICv3State *s) +{ +} + +static void mshv_gicv3_put(GICv3State *s) +{ +} + +static void mshv_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + MSHVARMGICv3Class *mgc =3D MSHV_GICV3_GET_CLASS(s); + + if (mgc->parent_phases.hold) { + mgc->parent_phases.hold(obj, type); + } + + mshv_gicv3_put(s); +} + +static void mshv_gicv3_set_irq(void *opaque, int irq, int level) +{ + int ret; + GICv3State *s =3D (GICv3State *)opaque; + int vm_fd =3D mshv_state->vm; + struct hv_input_assert_virtual_interrupt arg =3D {0}; + struct mshv_root_hvcall args =3D {0}; + union hv_interrupt_control control =3D { + .interrupt_type =3D HV_ARM64_INTERRUPT_TYPE_FIXED, + .rsvd1 =3D 0, + .asserted =3D level, + .rsvd2 =3D 0 + }; + + if (irq >=3D s->num_irq) { + return; + } + + arg.control =3D control; + arg.vector =3D GIC_INTERNAL + irq; + + args.code =3D HVCALL_ASSERT_VIRTUAL_INTERRUPT; + args.in_sz =3D sizeof(arg); + args.in_ptr =3D (uint64_t)&arg; + + ret =3D mshv_hvcall(vm_fd, &args); + if (ret < 0) { + error_report("Failed to set GICv3 IRQ %d to level %d", irq, level); + } +} + +static void mshv_gicv3_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + GICv3State *s =3D MSHV_GICV3(dev); + MSHVARMGICv3Class *mgc =3D MSHV_GICV3_GET_CLASS(s); + int i, ret; + + mgc->parent_realize(dev, errp); + if (*errp) { + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + return; + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by MSHV"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, mshv_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + CPUState *cpu_state =3D qemu_get_cpu(i); + + hv_register_assoc gicr_base =3D { + .name =3D HV_ARM64_REGISTER_GICR_BASE_GPA, + .value =3D { + .reg64 =3D 0x080A0000 + (GICV3_REDIST_SIZE * i) + } + }; + + ret =3D mshv_set_generic_regs(cpu_state, &gicr_base, 1); + if (ret < 0) { + error_setg(errp, "Failed to set GICR base for CPU %d", i); + return; + } + } + + if (s->maint_irq) { + error_setg(errp, + "Nested virtualisation not currently supported by MSHV"); + return; + } + + error_setg(&s->migration_blocker, + "Live migration disabled because GIC state save/restore not suppor= ted on MSHV"); + if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { + error_report_err(*errp); + } +} + +static void mshv_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + MSHVARMGICv3Class *mgc =3D MSHV_GICV3_CLASS(klass); + + agcc->pre_save =3D mshv_gicv3_get; + agcc->post_load =3D mshv_gicv3_put; + + device_class_set_parent_realize(dc, mshv_gicv3_realize, + &mgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, mshv_gicv3_reset_hold, NU= LL, + &mgc->parent_phases); +} + +static const TypeInfo mshv_arm_gicv3_info =3D { + .name =3D TYPE_MSHV_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D mshv_gicv3_class_init, + .class_size =3D sizeof(MSHVARMGICv3Class), +}; + +static void mshv_gicv3_register_types(void) +{ + type_register_static(&mshv_arm_gicv3_info); +} + +type_init(mshv_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 0620b0792a1..e0047ab1c0f 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -49,6 +49,8 @@ specific_ss.add(when: ['CONFIG_WHPX', 'CONFIG_ARM_GICV3']= , if_true: files('arm_g specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('= arm_gicv3_hvf.c')) stub_ss.add(files('arm_gicv3_hvf_stub.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gicv3_kvm.= c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: ['CONFIG_MSHV', 'TARGET_AARCH64'], if_true: files('a= rm_gicv3_mshv.c')) arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index d81c9816e7f..2b4b1406ab0 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -85,6 +85,8 @@ typedef enum hv_register_name { HV_ARM64_REGISTER_MIDR_EL1 =3D 0x00040051, HV_ARM64_REGISTER_MPIDR_EL1 =3D 0x00040001, =20 + HV_ARM64_REGISTER_GICR_BASE_GPA =3D 0x00063000, + #elif defined(__x86_64__) /* X64 User-Mode Registers */ HV_X64_REGISTER_RAX =3D 0x00020000, diff --git a/include/hw/hyperv/hvhdk_mini.h b/include/hw/hyperv/hvhdk_mini.h index 9c2f3cf5aee..4d78fa06777 100644 --- a/include/hw/hyperv/hvhdk_mini.h +++ b/include/hw/hyperv/hvhdk_mini.h @@ -62,6 +62,12 @@ enum hv_partition_property_code { HV_PARTITION_PROPERTY_ISOLATION_POLICY =3D 0x000= 50014, HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION =3D 0x000= 50017, HV_PARTITION_PROPERTY_SEV_VMGEXIT_OFFLOADS =3D 0x000= 50022, + HV_PARTITION_PROPERTY_GICD_BASE_ADDRESS =3D 0x000= 50028, + HV_PARTITION_PROPERTY_GITS_TRANSLATER_BASE_ADDRESS =3D 0x000= 50029, + HV_PARTITION_PROPERTY_GIC_LPI_INT_ID_BITS =3D 0x000= 5002A, + HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTV =3D 0x000= 5002B, + HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTP =3D 0x000= 5002C, + HV_PARTITION_PROPERTY_GIC_PPI_PERFORMANCE_MONITORS_INTERRUPT =3D 0x000= 5002D, =20 /* Compatibility properties */ HV_PARTITION_PROPERTY_PROCESSOR_VENDOR =3D 0x00060000, diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 03ab3e8f2ff..2ed456e654a 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -316,6 +316,7 @@ DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass, /* Types for GICv3 kernel-irqchip */ #define TYPE_WHPX_GICV3 "whpx-arm-gicv3" #define TYPE_HVF_GICV3 "hvf-arm-gicv3" +#define TYPE_MSHV_GICV3 "mshv-arm-gicv3" =20 struct ARMGICv3CommonClass { /*< private >*/ diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 31d2f4381c7..2dcfd11d8df 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -107,6 +107,7 @@ void mshv_arch_amend_proc_features( void mshv_arch_disable_partition_proc_features( union hv_partition_processor_features *disabled_features); int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd); +int mshv_arch_pre_init_vm(int vm_fd); int mshv_arch_post_init_vm(int vm_fd); void mshv_setup_hvcall_args(AccelCPUState *state); int mshv_arch_migration_init(MshvState *s); diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c index 786d815312b..8fa497c9a89 100644 --- a/target/arm/mshv/mshv-all.c +++ b/target/arm/mshv/mshv-all.c @@ -288,6 +288,67 @@ void mshv_arch_destroy_vcpu(CPUState *cpu) state->hvcall_args =3D (MshvHvCallArgs){0}; } =20 +static int set_partition_prop(int vm_fd, uint32_t prop_code, + uint64_t prop_value) +{ + int ret; + struct hv_input_set_partition_property in =3D {0}; + in.property_code =3D prop_code; + in.property_value =3D prop_value; + + struct mshv_root_hvcall args =3D {0}; + args.code =3D HVCALL_SET_PARTITION_PROPERTY; + args.in_sz =3D sizeof(in); + args.in_ptr =3D (uint64_t)∈ + + ret =3D mshv_hvcall(vm_fd, &args); + if (ret < 0) { + error_report("Failed to set partition property code %u", prop_code= ); + return -1; + } + + return 0; +} + +int mshv_arch_pre_init_vm(int vm_fd) +{ + int ret; + VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); + + ret =3D set_partition_prop(vm_fd, + HV_PARTITION_PROPERTY_GICD_BASE_ADDRESS, + vms->memmap[VIRT_GIC_DIST].base); + if (ret < 0) { + return ret; + } + + ret =3D set_partition_prop(vm_fd, + HV_PARTITION_PROPERTY_GITS_TRANSLATER_BASE_ADDRESS, + vms->memmap[VIRT_GIC_ITS].base); + if (ret < 0) { + return ret; + } + + ret =3D set_partition_prop(vm_fd, + HV_PARTITION_PROPERTY_GIC_LPI_INT_ID_BITS, + 0); + if (ret < 0) { + return ret; + } + + ret =3D set_partition_prop(vm_fd, + HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_F= ROM_CNTV, + ARCH_TIMER_VIRT_IRQ); + if (ret < 0) { + return ret; + } + + ret =3D set_partition_prop(vm_fd, + HV_PARTITION_PROPERTY_GIC_PPI_PERFORMANCE_MONITORS= _INTERRUPT, + VIRTUAL_PMU_IRQ); + + return ret; +} =20 static uint32_t mshv_arm_get_ipa_bit_size(int mshv_fd) { diff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c index 968fe2a4494..85dbacf98ff 100644 --- a/target/i386/mshv/mshv-all.c +++ b/target/i386/mshv/mshv-all.c @@ -39,6 +39,11 @@ int mshv_arch_accel_init(AccelState *as, MachineState *m= s, int mshv_fd) return 0; } =20 +int mshv_arch_pre_init_vm(int vm_fd) +{ + return 0; +} + /* * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a * fault to the guest if it tries to access it. It is possible to override --=20 2.45.4 From nobody Sat Oct 24 00:34:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1790852107; cv=none; d=zohomail.com; s=zohoarc; b=VbejD+XuL0692xCHksN1EfL3BxeMcbmrC1F5nhh9wMUbKZfWZMHqF2aYZBqx6kr3mePkUh62KsyO2YxOu4eDZuovPNfImTc1BpLps+WojSz045dZ17Taxh5VCuaFwKMGqzPwtHJiHflVMI9UXkpfEtrjj9TaOeS3QD8RXcSknXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790852107; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7hOufKOPzIQwADcMhT46WTXAlBvQ3DlmIGHDoOfMqeI=; b=Qj+3GO4vcs5Y1tHEblrPF5RkiQvSlr47nDhE8uwyD+uLmRXWbWqWQ17+qE6vfP3qRihLdcAi62tOiCpfBhSggAt3cCFr2zJQozL0C+tIVc95C8TVy2g3yvGK6OPVLPpye2jM0IW2UQJ6aAs5WzZE8otwYyXJNlfSo3W+dS2YMpw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790852107506310.0693997360115; Thu, 1 Oct 2026 03:55:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEQD-00062K-MU; Thu, 01 Oct 2026 06:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCEPm-0005iv-1E; Thu, 01 Oct 2026 06:53:29 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCEPh-0002Pa-MT; Thu, 01 Oct 2026 06:53:24 -0400 Received: from localhost (unknown [131.107.1.165]) by linux.microsoft.com (Postfix) with ESMTPSA id 9BE3320B7179; Thu, 1 Oct 2026 03:52:07 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 9BE3320B7179 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1790851927; bh=7hOufKOPzIQwADcMhT46WTXAlBvQ3DlmIGHDoOfMqeI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ePpi67xxgSMJTqvUcfzB0atpkH6uf9bcWUPkssdJaS2NXEwwkRrm1RwK+5EsiYP/S 9mYLYqMIEIKeFzDwv2F2t/ZtNa5cSRKUm6jsJBB8j2QWLfgz8nrOsf8rEGzC3PN4P5 e4IH4OhQSctTne0GvD/UJs/kz9vP8D5iN8EKxc+k= From: Aastha Rawat Date: Thu, 01 Oct 2026 10:52:59 +0000 Subject: [PATCH v6 14/14] MAINTAINERS: updates for MSHV arm64 code MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-mshv_accel_arm64_supp-v6-14-aefe5e76a0e3@linux.microsoft.com> References: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> In-Reply-To: <20261001-mshv_accel_arm64_supp-v6-0-aefe5e76a0e3@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , =?utf-8?q?Doru_Bl=C3=A2nzeanu?= , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Pierrick Bouvier , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni , "Michael S. Tsirkin" , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1790852109114158500 From: "Anirudh Rayabharam (Microsoft)" Add myself and Aastha Rawat as maintainers. Add Magnus Kulke as reviewer. Signed-off-by: Anirudh Rayabharam (Microsoft) --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1312bbd1bd..84a911ac26 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,6 +624,14 @@ S: Supported F: target/i386/mshv/ F: hw/i386/mshv/ =20 +ARM64 MSHV CPUs +M: Anirudh Rayabharam +M: Aastha Rawat +R: Magnus Kulke +S: Supported +F: target/arm/mshv/ +F: hw/intc/arm_gicv3_mshv.c + X86 Instruction Emulator M: Roman Bolshakov R: Phil Dennis-Jordan --=20 2.45.4