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Thu, 01 Oct 2026 06:52:26 -0700 (PDT) From: Anirudh Srinivasan Date: Thu, 01 Oct 2026 08:52:08 -0500 Subject: [PATCH v4 1/3] hw/misc: Add Tenstorrent Atlantis PRCM model MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-atlantis_prcm-v4-1-95d33c470eeb@oss.tenstorrent.com> References: <20261001-atlantis_prcm-v4-0-95d33c470eeb@oss.tenstorrent.com> In-Reply-To: <20261001-atlantis_prcm-v4-0-95d33c470eeb@oss.tenstorrent.com> To: qemu-devel@nongnu.org Cc: Joel Stanley , Nicholas Piggin , Michael Ellerman , Portia Stephens , qemu-riscv@nongnu.org, Pierrick Bouvier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Anirudh Srinivasan X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:41::e; envelope-from=asrinivasan@tenstorrent.com; helo=mail-yx2-x0e.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790862834938158500 This device present in Tenstorrent Atlantis has registers that control clocks, reset and other misc functionality in the SoC. This commit adds models for the RCPU, HSIO, PCIE, MM and 2 DDR PRCMs. Co-developed-by: Portia Stephens Signed-off-by: Portia Stephens Reviewed-by: Joel Stanley Signed-off-by: Anirudh Srinivasan Acked-by: Alistair Francis --- MAINTAINERS | 2 + hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + hw/misc/tt_atlantis_prcm.c | 428 +++++++++++++++++++++++++++++++++= ++++ include/hw/misc/tt_atlantis_prcm.h | 51 +++++ 5 files changed, 486 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f524d90523..b6cc077602 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1830,7 +1830,9 @@ R: Portia Stephens L: qemu-riscv@nongnu.org S: Supported F: docs/system/riscv/tt_*.rst +F: hw/misc/tt_*.c F: hw/riscv/tt_*.c +F: include/hw/misc/tt_*.h F: include/hw/riscv/tt_*.h F: tests/functional/riscv64/test_tt_*.py =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 54e07aacda..11b9593e03 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -39,6 +39,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files= ('sifive_e_aon.c')) system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.= c')) system_ss.add(when: 'CONFIG_K230_DECOMP_GZIP', if_true: files('k230_decomp= _gzip.c')) +system_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis_prcm= .c')) =20 subdir('macio') =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 0b8be3d0f2..8b80b71107 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -452,3 +452,7 @@ launch_update_write(void) "" vmlaunch_reset_enter(void) "" vm_launchupdate_finalize(void) "" restore_host_x86_igvm(void) "" + +# tt_atlantis_prcm.c +tt_atlantis_prcm_read(uint32_t domain, uint64_t offset, uint64_t data) "do= main 0x%02x offset 0x%" PRIx64 " data 0x%" PRIx64 +tt_atlantis_prcm_write(uint32_t domain, uint64_t offset, uint64_t data) "d= omain 0x%02x offset 0x%" PRIx64 " data 0x%" PRIx64 diff --git a/hw/misc/tt_atlantis_prcm.c b/hw/misc/tt_atlantis_prcm.c new file mode 100644 index 0000000000..31caca08fc --- /dev/null +++ b/hw/misc/tt_atlantis_prcm.c @@ -0,0 +1,428 @@ +/* + * PRCM (Clock and Reset Controller) in Tenstorrent Atlantis SoC + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2026 Tenstorrent + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/misc/tt_atlantis_prcm.h" +#include "trace.h" + +#define TO_REG(offset) ((offset) >> 2) + +#define PLL_LOCK_BIT 31 +#define PLL_FBDIV_LSB 14 +#define PLL_POSTDIV2_LSB 11 +#define PLL_POSTDIV1_LSB 8 +#define PLL_REFDIV_LSB 2 +#define PLL_BYPASS_BIT 1 + +#define PLL_RESET_VAL(BYPASS, REFDIV, POSTDIV1, POSTDIV2, FBDIV, LOCK) = \ + ((LOCK << PLL_LOCK_BIT) | (FBDIV << PLL_FBDIV_LSB) | = \ + (POSTDIV2 << PLL_POSTDIV2_LSB) | (POSTDIV1 << PLL_POSTDIV1_LSB) | = \ + (REFDIV << PLL_REFDIV_LSB) | (BYPASS << PLL_BYPASS_BIT)) + +#define RCPU_PLL_RCPU_CFG TO_REG(0x000) +#define RCPU_PLL_NOCC_CFG TO_REG(0x004) +#define RCPU_NOCC_CLK_CFG TO_REG(0x008) +#define RCPU_RCPU_DIV_CFG TO_REG(0x00c) +#define RCPU_RCPU_BLK_CG TO_REG(0x014) +#define RCPU_LSIO_BLK_CG TO_REG(0x018) +#define RCPU_RCPU_BLK_RST TO_REG(0x01c) +#define RCPU_LSIO_BLK_RST TO_REG(0x020) +#define RCPU_PLL_RCPU_EN TO_REG(0x11c) +#define RCPU_PLL_NOCC_EN TO_REG(0x120) +#define RCPU_PLL_MM_EN TO_REG(0x124) +#define RCPU_PLL1_MM_EN TO_REG(0x128) +#define RCPU_PLL_HSIO_EN TO_REG(0x12c) +#define RCPU_PLL_PCIE_EN TO_REG(0x138) +#define RCPU_PLL_I2S_EN TO_REG(0x13c) +#define RCPU_PLL_MM_CFG TO_REG(0x19c) +#define RCPU_PLL_HSIO_CFG TO_REG(0x1a0) +#define RCPU_PLL_PCIE_CFG TO_REG(0x1ac) +#define RCPU_BOOT_MODE_CFG TO_REG(0x1b0) +#define RCPU_PLL_I2S_CFG TO_REG(0x1f4) +#define RCPU_I2S_DIV_CFG TO_REG(0x1f8) +#define RCPU_BUS_CFG TO_REG(0x1fc) +#define RCPU_PLL1_MM_CFG TO_REG(0x2a4) + +#define HSIO_HSIO_DIV_CFG TO_REG(0x00) +#define HSIO_HSIO_DIV_CFG1 TO_REG(0x04) +#define HSIO_HSIO_BLK_CG TO_REG(0x08) +#define HSIO_HSIO_BLK_RST TO_REG(0x0c) +#define HSIO_HSIO_GMAC_DIV_CFG TO_REG(0x10) + +#define PCIE_SUBS_RST_CTL TO_REG(0x0) +#define PCIE_SUBS_CG_CTL TO_REG(0x4) +#define PCIE_SUBS_CK_CTL TO_REG(0x8) + +#define MM_MM_CLK_GATE_CFG TO_REG(0x008) +#define MM_MM_CLK_DIV_CFG TO_REG(0x00c) +#define MM_MM_CLK_SEL_CFG TO_REG(0x010) +#define MM_MM_RSTN TO_REG(0x014) +#define MM_MM_CLK_DIV_CFG1 TO_REG(0x130) + +#define DDRC_STAT TO_REG(0x10014) +#define DDRC_DFISTAT TO_REG(0x10514) +#define DDRC_SWSTAT TO_REG(0x10c84) + +#define PLL_EN BIT(0) +#define RCPU_PLL_BUS_CG_EN BIT(7) +#define HSIO_PLL_BUS_CG_EN BIT(3) +#define PCIE_PLL_BUS_CG_EN BIT(1) +#define NOCC_PLL_BUS_CG_EN BIT(0) + +#define RCPU_BOOT_MODE_UART (0x0 << 4) +#define RCPU_BOOT_MODE_NOR (0x1 << 4) +#define RCPU_BOOT_MODE_SD (0x2 << 4) + +#define RCPU_DOMAIN_SIZE 0x10000 +#define HSIO_DOMAIN_SIZE 0x510 +#define PCIE_DOMAIN_SIZE 0x100 +#define MM_DOMAIN_SIZE 0x1000 +#define DDRC0_DOMAIN_SIZE 0x101000 +#define DDRC1_DOMAIN_SIZE 0x101000 + +static uint64_t tt_atlantis_prcm_read(void *opaque, hwaddr offset, + unsigned size) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(opaque); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + uint32_t data; + + if (offset >=3D c->regs_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, offset); + return 0; + } + data =3D s->regs[TO_REG(offset)]; + + trace_tt_atlantis_prcm_read(c->domain, offset, data); + return data; +} + +static void tt_atlantis_prcm_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(opaque); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + + if (offset >=3D c->regs_size) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + trace_tt_atlantis_prcm_write(c->domain, offset, data); + + s->regs[TO_REG(offset)] =3D data; +} + +static void tt_atlantis_prcm_rcpu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(opaque); + uint32_t pll_reg_offset; + + tt_atlantis_prcm_write(opaque, offset, data, size); + + switch (TO_REG(offset)) { + case RCPU_PLL_RCPU_EN: + pll_reg_offset =3D RCPU_PLL_RCPU_CFG; + break; + case RCPU_PLL_NOCC_EN: + pll_reg_offset =3D RCPU_PLL_NOCC_CFG; + break; + case RCPU_PLL_HSIO_EN: + pll_reg_offset =3D RCPU_PLL_HSIO_CFG; + break; + case RCPU_PLL_PCIE_EN: + pll_reg_offset =3D RCPU_PLL_PCIE_CFG; + break; + case RCPU_PLL_MM_EN: + pll_reg_offset =3D RCPU_PLL_MM_CFG; + break; + case RCPU_PLL1_MM_EN: + pll_reg_offset =3D RCPU_PLL1_MM_CFG; + break; + case RCPU_PLL_I2S_EN: + pll_reg_offset =3D RCPU_PLL_I2S_CFG; + break; + default: + return; + } + + if (data & PLL_EN) { + s->regs[pll_reg_offset] |=3D BIT(PLL_LOCK_BIT); + } else { + s->regs[pll_reg_offset] &=3D ~BIT(PLL_LOCK_BIT); + } +} + +static const MemoryRegionOps tt_atlantis_prcm_ops =3D { + .read =3D tt_atlantis_prcm_read, + .write =3D tt_atlantis_prcm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static const MemoryRegionOps tt_atlantis_prcm_rcpu_ops =3D { + .read =3D tt_atlantis_prcm_read, + .write =3D tt_atlantis_prcm_rcpu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static void tt_atlantis_prcm_realize(DeviceState *dev, Error **errp) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + + assert(c->domain < TT_ATLANTIS_PRCM_DOMAIN_COUNT); + + s->regs =3D g_new0(uint32_t, TO_REG(c->regs_size)); + + memory_region_init_io(&s->mmio, OBJECT(s), c->ops, s, + TYPE_TT_ATLANTIS_PRCM, c->regs_size); + sysbus_init_mmio(sbd, &s->mmio); +} + +static void tt_atlantis_prcm_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_GET_CLASS(s); + + memset(s->regs, 0, c->regs_size); +} + +static void tt_atlantis_prcm_rcpu_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[RCPU_PLL_RCPU_CFG] =3D PLL_RESET_VAL(1, 0, 4, 0, 100, 1); + s->regs[RCPU_PLL_NOCC_CFG] =3D PLL_RESET_VAL(0, 2, 2, 2, 267, 1); + s->regs[RCPU_NOCC_CLK_CFG] =3D (0x25f31 << 1) | BIT(0); + s->regs[RCPU_RCPU_DIV_CFG] =3D (0xb8c2 << 1); + s->regs[RCPU_RCPU_BLK_CG] =3D 0; + s->regs[RCPU_LSIO_BLK_CG] =3D 0; + s->regs[RCPU_RCPU_BLK_RST] =3D 0xffffffff; + s->regs[RCPU_LSIO_BLK_RST] =3D 0xffffffff; + s->regs[RCPU_PLL_RCPU_EN] =3D PLL_EN; + s->regs[RCPU_PLL_NOCC_EN] =3D PLL_EN; + s->regs[RCPU_PLL_HSIO_EN] =3D 0; + s->regs[RCPU_PLL_MM_EN] =3D 0; + s->regs[RCPU_PLL1_MM_EN] =3D 0; + s->regs[RCPU_PLL_I2S_EN] =3D 0; + s->regs[RCPU_PLL_PCIE_EN] =3D 0; + s->regs[RCPU_PLL_HSIO_CFG] =3D PLL_RESET_VAL(0, 1, 2, 1, 50, 0); + s->regs[RCPU_PLL_PCIE_CFG] =3D PLL_RESET_VAL(0, 2, 3, 1, 250, 0); + s->regs[RCPU_BOOT_MODE_CFG] =3D RCPU_BOOT_MODE_SD; + s->regs[RCPU_PLL_MM_CFG] =3D PLL_RESET_VAL(0, 1, 2, 1, 50, 1); + s->regs[RCPU_PLL1_MM_CFG] =3D PLL_RESET_VAL(0, 1, 2, 1, 50, 1); + s->regs[RCPU_PLL_I2S_CFG] =3D PLL_RESET_VAL(0, 1, 6, 6, 33, 0); + s->regs[RCPU_I2S_DIV_CFG] =3D 0xde69ad31; + s->regs[RCPU_BUS_CFG] =3D NOCC_PLL_BUS_CG_EN | HSIO_PLL_BUS_CG_EN; +} + +static void tt_atlantis_prcm_ddrc_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[DDRC_STAT] =3D 0x1; + s->regs[DDRC_DFISTAT] =3D 0x1; + s->regs[DDRC_SWSTAT] =3D 0x1; +} + +static void tt_atlantis_prcm_hsio_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[HSIO_HSIO_DIV_CFG] =3D 0x20821731; + s->regs[HSIO_HSIO_DIV_CFG1] =3D 0x8; + s->regs[HSIO_HSIO_BLK_CG] =3D 0; + s->regs[HSIO_HSIO_BLK_RST] =3D 0; + s->regs[HSIO_HSIO_GMAC_DIV_CFG] =3D 0; +} + +static void tt_atlantis_prcm_pcie_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[PCIE_SUBS_RST_CTL] =3D 0; + s->regs[PCIE_SUBS_CG_CTL] =3D 0; + s->regs[PCIE_SUBS_CK_CTL] =3D 0x44908; +} + +static void tt_atlantis_prcm_mm_reset_hold(Object *obj, ResetType type) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(obj); + tt_atlantis_prcm_reset_hold(obj, type); + + /* Reset values come from Datasheet */ + s->regs[MM_MM_CLK_GATE_CFG] =3D 0; + s->regs[MM_MM_CLK_DIV_CFG] =3D 0xddc8312; + s->regs[MM_MM_CLK_SEL_CFG] =3D 0; + s->regs[MM_MM_RSTN] =3D 0; + s->regs[MM_MM_CLK_DIV_CFG1] =3D 0x333; +} + +static void tt_atlantis_prcm_unrealize(DeviceState *dev) +{ + TTAtlantisPRCMState *s =3D TT_ATLANTIS_PRCM(dev); + + g_free(s->regs); +} + +static void tt_atlantis_prcm_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->realize =3D tt_atlantis_prcm_realize; + dc->unrealize =3D tt_atlantis_prcm_unrealize; + dc->desc =3D "Tenstorrent Atlantis PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_reset_hold; + c->ops =3D &tt_atlantis_prcm_ops; +} + +static void tt_atlantis_prcm_rcpu_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis RCPU PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_rcpu_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_RCPU; + c->regs_size =3D RCPU_DOMAIN_SIZE; + c->ops =3D &tt_atlantis_prcm_rcpu_ops; +} + +static void tt_atlantis_prcm_hsio_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis HSIO PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_hsio_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_HSIO; + c->regs_size =3D HSIO_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_pcie_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis PCIE PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_pcie_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_PCIE; + c->regs_size =3D PCIE_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_mm_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis MM PRCM Controller"; + rc->phases.hold =3D tt_atlantis_prcm_mm_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_MM; + c->regs_size =3D MM_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_ddrc0_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis DDR Memory Controller 0 PRCM"; + rc->phases.hold =3D tt_atlantis_prcm_ddrc_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_DDRC0; + c->regs_size =3D DDRC0_DOMAIN_SIZE; +} + +static void tt_atlantis_prcm_ddrc1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + TTAtlantisPRCMClass *c =3D TT_ATLANTIS_PRCM_CLASS(klass); + + dc->desc =3D "Tenstorrent Atlantis DDR Memory Controller 1 PRCM"; + rc->phases.hold =3D tt_atlantis_prcm_ddrc_reset_hold; + c->domain =3D TT_ATLANTIS_PRCM_DOMAIN_DDRC1; + c->regs_size =3D DDRC1_DOMAIN_SIZE; +} + +static const TypeInfo tt_atlantis_prcm_types[] =3D { + { + .name =3D TYPE_TT_ATLANTIS_PRCM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TTAtlantisPRCMState), + .class_init =3D tt_atlantis_prcm_class_init, + .class_size =3D sizeof(TTAtlantisPRCMClass), + .abstract =3D true, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_RCPU, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_rcpu_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_HSIO, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_hsio_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_PCIE, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_pcie_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_MM, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_mm_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_DDRC0, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_ddrc0_class_init, + }, + { + .name =3D TYPE_TT_ATLANTIS_PRCM_DDRC1, + .parent =3D TYPE_TT_ATLANTIS_PRCM, + .class_init =3D tt_atlantis_prcm_ddrc1_class_init, + }, +}; + +DEFINE_TYPES(tt_atlantis_prcm_types); diff --git a/include/hw/misc/tt_atlantis_prcm.h b/include/hw/misc/tt_atlant= is_prcm.h new file mode 100644 index 0000000000..4b72618346 --- /dev/null +++ b/include/hw/misc/tt_atlantis_prcm.h @@ -0,0 +1,51 @@ +/* + * PRCM (Clock and Reset Controller) in Tenstorrent Atlantis SoC + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2026 Tenstorrent + */ + +#ifndef TT_ATLANTIS_PRCM_H +#define TT_ATLANTIS_PRCM_H + +#include "hw/core/sysbus.h" + +#define TYPE_TT_ATLANTIS_PRCM "tt.atlantis.prcm" +#define TYPE_TT_ATLANTIS_PRCM_RCPU "tt.atlantis.prcm.rcpu" +#define TYPE_TT_ATLANTIS_PRCM_HSIO "tt.atlantis.prcm.hsio" +#define TYPE_TT_ATLANTIS_PRCM_PCIE "tt.atlantis.prcm.pcie" +#define TYPE_TT_ATLANTIS_PRCM_MM "tt.atlantis.prcm.mm" +#define TYPE_TT_ATLANTIS_PRCM_DDRC0 "tt.atlantis.prcm.ddrc0" +#define TYPE_TT_ATLANTIS_PRCM_DDRC1 "tt.atlantis.prcm.ddrc1" +OBJECT_DECLARE_TYPE(TTAtlantisPRCMState, TTAtlantisPRCMClass, + TT_ATLANTIS_PRCM); + + +enum { + TT_ATLANTIS_PRCM_DOMAIN_RCPU =3D 0, + TT_ATLANTIS_PRCM_DOMAIN_HSIO =3D 1, + TT_ATLANTIS_PRCM_DOMAIN_PCIE =3D 2, + TT_ATLANTIS_PRCM_DOMAIN_MM =3D 3, + TT_ATLANTIS_PRCM_DOMAIN_DDRC0 =3D 4, + TT_ATLANTIS_PRCM_DOMAIN_DDRC1 =3D 5, + TT_ATLANTIS_PRCM_DOMAIN_COUNT =3D 6 +}; + +struct TTAtlantisPRCMState { + SysBusDevice parent; + + MemoryRegion mmio; + + uint32_t *regs; +}; + +struct TTAtlantisPRCMClass { + SysBusDeviceClass parent_class; + + uint32_t domain; + uint32_t regs_size; + const MemoryRegionOps *ops; +}; + +#endif --=20 2.43.0 From nobody Sat Oct 24 00:34:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.tenstorrent.com ARC-Seal: i=1; a=rsa-sha256; t=1790862822; cv=none; d=zohomail.com; s=zohoarc; b=eBc7x76PkcddYfW/TyoKHJIR2MezhpL1cNP5HxAQODnRKMqYjHL357jOXdxn/rzYZ2LezrfJix96v0/WXISeH7vf6OycLBtobJqKEk7gW98YmJFZOBYeEqgCGAtnCqpXmVlImShbGbto8oyP9ETwfbiKddRlOZoaEOJETzMgbnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790862822; 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qVwpEOT+C5gs7UP5TODFReDN6V798k3M4TXYkV3uxtp+s02ee4YCHefIstLrui2HKWMChuEPK5L LrR0D2sCS5L752hCyakKNE97mXRv54jUvAEizEhZNZViBYf X-Received: by 2002:a05:690e:4141:b0:673:e272:f3f0 with SMTP id 956f58d0204a3-676832e1a8emr1799618d50.12.1790862747388; Thu, 01 Oct 2026 06:52:27 -0700 (PDT) From: Anirudh Srinivasan Date: Thu, 01 Oct 2026 08:52:09 -0500 Subject: [PATCH v4 2/3] hw/riscv/tt-atlantis: Add PRCMs to tt-atlantis model MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-atlantis_prcm-v4-2-95d33c470eeb@oss.tenstorrent.com> References: <20261001-atlantis_prcm-v4-0-95d33c470eeb@oss.tenstorrent.com> In-Reply-To: <20261001-atlantis_prcm-v4-0-95d33c470eeb@oss.tenstorrent.com> To: qemu-devel@nongnu.org Cc: Joel Stanley , Nicholas Piggin , Michael Ellerman , Portia Stephens , qemu-riscv@nongnu.org, Pierrick Bouvier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Anirudh Srinivasan X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:41::d; envelope-from=asrinivasan@tenstorrent.com; helo=mail-yx2-x0d.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790862825162158500 Atlantis has 4 PRCMs that are visible from S mode by the Ascalon Core (RCPU, HSIO, PCIe and MM). The remaining 2 are only accessed by the boot cpu which isn't modelled yet. This commit adds these 4 PRCM blocks to the tt-atlantis model, along with necessary device tree nodes for them. Reviewed-by: Chao Liu Reviewed-by: Joel Stanley Signed-off-by: Anirudh Srinivasan Acked-by: Alistair Francis --- docs/system/riscv/tt_atlantis.rst | 1 + hw/riscv/tt_atlantis.c | 104 ++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/tt_atlantis.h | 22 ++++++++ 3 files changed, 127 insertions(+) diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlan= tis.rst index 1f2880d617..539c22354f 100644 --- a/docs/system/riscv/tt_atlantis.rst +++ b/docs/system/riscv/tt_atlantis.rst @@ -14,6 +14,7 @@ tt-atlantis QEMU model features * 8-core Ascalon-X CPU Cluster * RISC-V compliant Advanced Interrupt Architecture * 16550A compatible UART +* 4 PRCMs (Clock and Reset Controllers) =20 Known limitations ----------------- diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 8a219afef7..10ae3c2850 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -27,6 +27,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/riscv_aclint.h" #include "hw/misc/unimp.h" +#include "hw/misc/tt_atlantis_prcm.h" =20 #include "system/system.h" #include "system/device_tree.h" @@ -58,12 +59,16 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_ACLINT] =3D { 0xa2180000, 0x10000 }, [TT_ATL_SIMSIC] =3D { 0xa4000000, 0x200000 }, [TT_ATL_MAPLIC] =3D { 0xcc000000, 0x4000000 }, + [TT_ATL_PRCM_RCPU] =3D { 0xd0000000, 0x10000 }, [TT_ATL_I2C0] =3D { 0xd4040000, 0x10000 }, [TT_ATL_I2C1] =3D { 0xd4050000, 0x10000 }, [TT_ATL_I2C2] =3D { 0xd4060000, 0x10000 }, [TT_ATL_I2C3] =3D { 0xd4070000, 0x10000 }, [TT_ATL_I2C4] =3D { 0xd4080000, 0x10000 }, [TT_ATL_UART1] =3D { 0xd4110000, 0x10000 }, + [TT_ATL_PRCM_PCIE] =3D { 0xd8000000, 0x100 }, + [TT_ATL_PRCM_MM] =3D { 0xdc000000, 0x1000 }, + [TT_ATL_PRCM_HSIO] =3D { 0xe00c0000, 0x510 }, [TT_ATL_SAPLIC] =3D { 0xe8000000, 0x4000000 }, [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, }; @@ -327,11 +332,34 @@ static void create_fdt_i2c_device(void *fdt, TTAtlant= isSoCState *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 +static char *create_fdt_prcm(void *fdt, const MemMapEntry *mem, + const char *prcm_name) +{ + hwaddr base =3D mem->base; + hwaddr size =3D mem->size; + char *name =3D g_strdup_printf("/soc/clock-controller@%" PRIx64, + base); + g_autofree char *compatible =3D + g_strdup_printf("tenstorrent,atlantis-prcm-%s", prcm_name); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", compatible); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, base, 2, size); + qemu_fdt_setprop_cell(fdt, name, "#clock-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "#reset-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "phandle", next_phandle()); + + return name; +} + static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); uint32_t periph_clk_phandle =3D next_phandle(); + uint32_t osc_24m_phandle =3D next_phandle(); + uint32_t prcm_rcpu_phandle; + g_autofree char *rcpu_name, *hsio_name, *pcie_name, *mm_name; =20 create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); =20 @@ -348,6 +376,30 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState= *s) aplic_s_phandle); =20 create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); + create_fdt_clk(fdt, "osc-24m", 24000000, osc_24m_phandle); + + rcpu_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_RCPU], "rcpu= "); + prcm_rcpu_phandle =3D qemu_fdt_get_phandle(fdt, rcpu_name); + qemu_fdt_setprop_cells(fdt, rcpu_name, "clocks", osc_24m_phandle); + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clocks", + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_ROOT, + prcm_rcpu_phandle, TT_ATL_CLK_NOCC_CLK); + qemu_fdt_setprop_cells(fdt, rcpu_name, "assigned-clock-parents", + prcm_rcpu_phandle, TT_ATL_CLK_RCPU_PLL, + prcm_rcpu_phandle, TT_ATL_CLK_NOC_PLL); + + hsio_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_HSIO], "hsio= "); + qemu_fdt_setprop_cells(fdt, hsio_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_HSIO_PLL); + + pcie_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_PCIE], "pcie= "); + qemu_fdt_setprop_cells(fdt, pcie_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_PCIE_PLL); + + mm_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_MM], "mm"); + qemu_fdt_setprop_cells(fdt, mm_name, "clocks", osc_24m_phandle, + prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL0, + prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL1); =20 for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { create_fdt_i2c(fdt, @@ -491,6 +543,19 @@ static void tt_atlantis_soc_init(Object *obj) object_initialize_child(obj, "uart1", &s->uart1, TYPE_UNIMPLEMENTED_DEVICE); =20 + object_initialize_child(obj, "prcm-rcpu", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU], + TYPE_TT_ATLANTIS_PRCM_RCPU); + object_initialize_child(obj, "prcm-hsio", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO], + TYPE_TT_ATLANTIS_PRCM_HSIO); + object_initialize_child(obj, "prcm-pcie", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE], + TYPE_TT_ATLANTIS_PRCM_PCIE); + object_initialize_child(obj, "prcm-mm", + &s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM], + TYPE_TT_ATLANTIS_PRCM_MM); + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_DESIGNWARE_I2C); @@ -587,6 +652,44 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); + + /* 4 PRCM blocks */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RC= PU]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_RCPU].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_RCPU]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HS= IO]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_HSIO].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_HSIO]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PC= IE]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_PCIE].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_PCIE]), 0)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM= ]), + errp)) { + return; + } + memory_region_add_subregion( + s->memory, s->memmap[TT_ATL_PRCM_MM].base, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(&s->prcm[TT_ATLANTIS_PRCM_DOMAIN_MM]), 0)); + /* * Atlantis contains a DesignWare uart while the QEMU machine * uses the serial_mm model with the base ns16550 register set. @@ -654,6 +757,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), &error_abort); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); =20 /* I2C peripherals: qemu specific */ diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 3923308b7c..db1dfed157 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -14,6 +14,7 @@ #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" #include "hw/misc/unimp.h" +#include "hw/misc/tt_atlantis_prcm.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -23,6 +24,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_M= ACHINE) OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) =20 #define TT_ATL_NUM_I2C 5 +#define TT_ATL_NUM_PRCM 4 =20 struct TTAtlantisSoCState { /*< private >*/ @@ -41,6 +43,7 @@ struct TTAtlantisSoCState { DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; MemoryRegion bootrom; + TTAtlantisPRCMState prcm[TT_ATL_NUM_PRCM]; =20 uint32_t num_harts; char *cpu_type; @@ -81,6 +84,25 @@ enum { TT_ATL_SAPLIC, TT_ATL_SIMSIC, TT_ATL_UART1, + TT_ATL_PRCM_RCPU, + TT_ATL_PRCM_HSIO, + TT_ATL_PRCM_PCIE, + TT_ATL_PRCM_MM, +}; + +/* + * RCPU PRCM Clock IDs, sourced from linux dt-bindings + * include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h + */ +enum { + TT_ATL_CLK_RCPU_PLL =3D 0, + TT_ATL_CLK_RCPU_ROOT =3D 1, + TT_ATL_CLK_NOC_PLL =3D 25, + TT_ATL_CLK_NOCC_CLK =3D 26, + TT_ATL_CLK_HSIO_PLL =3D 54, + TT_ATL_CLK_PCIE_PLL =3D 55, + TT_ATL_CLK_MM_PLL0 =3D 56, + TT_ATL_CLK_MM_PLL1 =3D 57, }; =20 #endif --=20 2.43.0 From nobody Sat Oct 24 00:34:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.tenstorrent.com ARC-Seal: i=1; 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Thu, 01 Oct 2026 06:52:28 -0700 (PDT) From: Anirudh Srinivasan Date: Thu, 01 Oct 2026 08:52:10 -0500 Subject: [PATCH v4 3/3] hw/riscv/tt-atlantis: Update UART and I2C to use clk from PRCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20261001-atlantis_prcm-v4-3-95d33c470eeb@oss.tenstorrent.com> References: <20261001-atlantis_prcm-v4-0-95d33c470eeb@oss.tenstorrent.com> In-Reply-To: <20261001-atlantis_prcm-v4-0-95d33c470eeb@oss.tenstorrent.com> To: qemu-devel@nongnu.org Cc: Joel Stanley , Nicholas Piggin , Michael Ellerman , Portia Stephens , qemu-riscv@nongnu.org, Pierrick Bouvier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Anirudh Srinivasan X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:41::16; envelope-from=asrinivasan@tenstorrent.com; helo=mail-yx2-x16.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1790862834929158500 Now that we have the PRCM modelled, update the DT nodes for UART1 and the 5 I2C controllers to use the rcpu_prcm as a clock provider. This also allows us to eliminate the periph_clk that was added to the DT previously. Signed-off-by: Anirudh Srinivasan Acked-by: Alistair Francis --- hw/riscv/tt_atlantis.c | 23 ++++++++++++++--------- include/hw/riscv/tt_atlantis.h | 6 ++++++ 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 10ae3c2850..4e6c39982c 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -265,7 +265,8 @@ static void create_fdt_cpu(void *fdt, TTAtlantisSoCStat= e *s, } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, - int irqchip_phandle) + int irqchip_phandle, uint32_t clk_parent_phand= le, + uint32_t clk_phandle) { g_autofree char *name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIX, mem->base); @@ -275,6 +276,8 @@ static void create_fdt_uart(void *fdt, const MemMapEntr= y *mem, int irq, qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2); qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_parent_phandle, + clk_phandle); qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); @@ -305,7 +308,9 @@ static void create_fdt_clk(void *fdt, const char *clock= _name, } =20 static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq, - uint32_t irqchip_phandle, uint32_t clk_phandle) + uint32_t irqchip_phandle, + uint32_t clk_parent_phandle, + uint32_t clk_phandle) { g_autofree char *name =3D g_strdup_printf("/soc/i2c@%"HWADDR_PRIX, mem= ->base); =20 @@ -314,7 +319,8 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry= *mem, uint32_t irq, qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); - qemu_fdt_setprop_cell(fdt, name, "clocks", clk_phandle); + qemu_fdt_setprop_cells(fdt, name, "clocks", clk_parent_phandle, + clk_phandle); qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 100000); qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); @@ -356,7 +362,6 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState = *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); - uint32_t periph_clk_phandle =3D next_phandle(); uint32_t osc_24m_phandle =3D next_phandle(); uint32_t prcm_rcpu_phandle; g_autofree char *rcpu_name, *hsio_name, *pcie_name, *mm_name; @@ -372,10 +377,6 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCState= *s) * aplic_s_phandle); */ =20 - create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ, - aplic_s_phandle); - - create_fdt_clk(fdt, "periph-clk", 100000000, periph_clk_phandle); create_fdt_clk(fdt, "osc-24m", 24000000, osc_24m_phandle); =20 rcpu_name =3D create_fdt_prcm(fdt, &s->memmap[TT_ATL_PRCM_RCPU], "rcpu= "); @@ -401,11 +402,15 @@ static void finalize_fdt(void *fdt, TTAtlantisSoCStat= e *s) prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL0, prcm_rcpu_phandle, TT_ATL_CLK_MM_PLL1); =20 + create_fdt_uart(fdt, &s->memmap[TT_ATL_UART1], TT_ATL_UART1_IRQ, + aplic_s_phandle, prcm_rcpu_phandle, TT_ATL_CLK_UART1_P= CLK); + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { create_fdt_i2c(fdt, &s->memmap[TT_ATL_I2C0 + i], TT_ATL_I2C0_IRQ + i, - aplic_s_phandle, periph_clk_phandle); + aplic_s_phandle, prcm_rcpu_phandle, + TT_ATL_CLK_I2C0_PCLK + i); } =20 /* I2C peripherals: qemu specific */ diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index db1dfed157..577c867d71 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -99,6 +99,12 @@ enum { TT_ATL_CLK_RCPU_ROOT =3D 1, TT_ATL_CLK_NOC_PLL =3D 25, TT_ATL_CLK_NOCC_CLK =3D 26, + TT_ATL_CLK_I2C0_PCLK =3D 33, + TT_ATL_CLK_I2C1_PCLK =3D 34, + TT_ATL_CLK_I2C2_PCLK =3D 35, + TT_ATL_CLK_I2C3_PCLK =3D 36, + TT_ATL_CLK_I2C4_PCLK =3D 37, + TT_ATL_CLK_UART1_PCLK =3D 39, TT_ATL_CLK_HSIO_PLL =3D 54, TT_ATL_CLK_PCIE_PLL =3D 55, TT_ATL_CLK_MM_PLL0 =3D 56, --=20 2.43.0