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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790717426158500 Add the hexagon-sys.xml gdb feature describing the system and guest registers. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- configs/targets/hexagon-softmmu.mak | 2 +- gdbstub/gdb-xml/hexagon-sys.xml | 157 ++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 gdbstub/gdb-xml/hexagon-sys.xml diff --git a/configs/targets/hexagon-softmmu.mak b/configs/targets/hexagon-= softmmu.mak index 6cbdc64be56..1ba6420d205 100644 --- a/configs/targets/hexagon-softmmu.mak +++ b/configs/targets/hexagon-softmmu.mak @@ -1,7 +1,7 @@ # Default configuration for hexagon-softmmu =20 TARGET_ARCH=3Dhexagon -TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml +TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml hexagon-sys.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/gdbstub/gdb-xml/hexagon-sys.xml b/gdbstub/gdb-xml/hexagon-sys.= xml new file mode 100644 index 00000000000..434f11c0747 --- /dev/null +++ b/gdbstub/gdb-xml/hexagon-sys.xml @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.34.1 From nobody Sat Oct 24 00:32:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790790733; cv=none; d=zohomail.com; s=zohoarc; b=kdiOfp8PeX5075KPAVH/Dw4x1qoVLF8I+dSfSUoMX56nqYNuyYMAIMh588v23GKen1YgHmzkxwLIQNjeRwMZEGD1EUuJbxRb0g1pU5Xg/GwhljuaSLSyjVbSquW6DS7rjZEVw2lXJDVEthu0yEeu+PS0CPN9Q0lalZR01XoK9KA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790790733; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vQG2DSJsT3sImAhUm+M1OaxGKeflxppaqcynB6KSreo=; b=Mshs/W5wocqCKdOuxoM3b0gNiwGvQSfLrbS1PfMjb/cAijnJBMqnqkF+ESr8+d7/mlbIkD6SXA8gcPym8/qUKRtJmvi2prCYdFRV1vUN4R79Y3yJtil1cVXmQQyIV2TJM0C0bJfVs/qbPd3DeXSWoVoQ6rQxzdsxkxyX6beuFd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790790733597552.7852978644897; Wed, 30 Sep 2026 10:52:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xBySn-0003s7-At; Wed, 30 Sep 2026 13:51:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xBySl-0003et-II for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:51:27 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xBySj-0001bE-Jv for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:51:27 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68UHfEkr4014402 for ; Wed, 30 Sep 2026 17:51:14 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h0x27jtdp-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 30 Sep 2026 17:51:14 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-34344599f01so5553052eec.0 for ; Wed, 30 Sep 2026 10:51:14 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- target/hexagon/cpu.h | 1 + target/hexagon/internal.h | 4 +++ target/hexagon/cpu.c | 14 ++++++++ target/hexagon/gdbstub.c | 68 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index df4c0182247..ea54af621d2 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -241,6 +241,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonS= tate *env, */ bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); +void hexagon_greg_write(CPUHexagonState *env, uint32_t reg, uint32_t val); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif =20 diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 05d1129916e..3ed83904eb7 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -24,6 +24,10 @@ int hexagon_gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int = n); int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); +#ifndef CONFIG_USER_ONLY +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n= ); +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +#endif =20 void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1f7d8a8df70..45eb9a5fb99 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -494,6 +494,10 @@ static void hexagon_cpu_realize(DeviceState *dev, Erro= r **errp) gdb_find_static_feature("hexagon-hvx.xml")); =20 #ifndef CONFIG_USER_ONLY + gdb_register_coprocessor(cs, hexagon_sys_gdb_read_register, + hexagon_sys_gdb_write_register, + gdb_find_static_feature("hexagon-sys.xml")); + if (!HEXAGON_CPU(dev)->tlb) { error_setg(errp, "hexagon cpu requires 'tlb' link property to be s= et"); return; @@ -863,6 +867,16 @@ uint32_t hexagon_greg_read(CPUHexagonState *env, uint3= 2_t reg) return 0; } } + +void hexagon_greg_write(CPUHexagonState *env, uint32_t reg, uint32_t val) +{ + if (reg <=3D HEX_GREG_G3) { + env->greg[reg] =3D val; + return; + } + qemu_log_mask(LOG_UNIMP, "writing greg %" PRIu32 + " not yet supported.\n", reg); +} #endif =20 static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data) diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 76ab5235f6e..159c3fac48d 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -16,9 +16,14 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "gdbstub/helpers.h" #include "cpu.h" #include "internal.h" +#ifndef CONFIG_USER_ONLY +#include "cpu_helper.h" +#include "hw/hexagon/hexagon_globalreg.h" +#endif =20 int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { @@ -76,6 +81,69 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) g_assert_not_reached(); } =20 +#ifndef CONFIG_USER_ONLY +/* + * Sys regs below HEX_SREG_GLB_START are per-thread and live in env->t_sre= g[]; + * at or above it they are shared across threads and live in the + * HexagonGlobalRegState object, same as SET_SYSTEM_FIELD() in sys_macros.= h. + */ +int hexagon_sys_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + CPUHexagonState *env =3D cpu_env(cs); + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); + + if (n < NUM_SREGS) { + uint32_t val; + if (n < HEX_SREG_GLB_START) { + val =3D env->t_sreg[n]; + } else { + val =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, n, env->threadId) = : 0; + } + return gdb_get_regl(mem_buf, val); + } + n -=3D NUM_SREGS; + + if (n < NUM_GREGS) { + return gdb_get_regl(mem_buf, hexagon_greg_read(env, n)); + } + n -=3D NUM_GREGS; + + g_assert_not_reached(); +} + +int hexagon_sys_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + CPUHexagonState *env =3D cpu_env(cs); + HexagonCPU *cpu =3D env_archcpu(env); + BQL_LOCK_GUARD(); + + if (n < NUM_SREGS) { + uint32_t val =3D ldl_le_p(mem_buf); + if (n =3D=3D HEX_SREG_SSR) { + uint32_t old =3D env->t_sreg[HEX_SREG_SSR]; + env->t_sreg[HEX_SREG_SSR] =3D val; + hexagon_modify_ssr(env, val, old); + } else if (n < HEX_SREG_GLB_START) { + env->t_sreg[n] =3D val; + } else if (cpu->globalregs) { + hexagon_globalreg_write(cpu->globalregs, n, val, env->threadId= ); + } + return sizeof(uint32_t); + } + n -=3D NUM_SREGS; + + if (n < NUM_GREGS) { + hexagon_greg_write(env, n, ldl_le_p(mem_buf)); + return sizeof(uint32_t); + } + n -=3D NUM_GREGS; + + g_assert_not_reached(); +} +#endif + static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n) { int total =3D 0; --=20 2.34.1