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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790379484158500 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c8ffe94cd8..e34c0c676d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -684,6 +684,20 @@ bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr= addr, bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); +/** + * riscv_cpu_update_mip: + * @env: CPURISCVState + * @mask: Mask of the MIP bits to update + * @value: New values for the bits set in @mask. + * Use BOOL_TO_MASK() for boolean values. + * + * Set or clear the Machine Interrupt Pending register (MIP) + * bits selected by @mask. + * + * Note: VSTIP is not maintained in MIP, so it is ignored here. + * + * Returns: the value of mip before the update. + */ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); --=20 2.55.0 From nobody Sat Oct 24 00:32:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm_riscv.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 61eaa12443e..7317255cba2 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -22,6 +22,12 @@ #include "target/riscv/cpu-qom.h" =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu); +/** + * kvm_riscv_set_irq: + * @cpu: RISC-V CPU + * @irq: Interrupt to set or clear (only %IRQ_S_EXT is supported). + * @level: %0 to clear the interrupt, non-zero to set it. + */ void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, uint64_t aia_irq_num, uint64_t aia_msi_num, --=20 2.55.0 From nobody Sat Oct 24 00:32:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790790397; cv=none; d=zohomail.com; s=zohoarc; b=Bl+Waak33FxRhfuI7Q74h4Msn2JxcGG1pGcXGl6gMda1gF16MVOCOMi04ZR3roJxUuXnoi7Vjelvll6fUzwXEctUggU4z/C+EQ2tLWtYd5blJD0t+5SX1V6nLaoQk87JcfJekycKGrMbnbqWvFwQDQfNK0A+56jiQPmnSHHZo8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790790397; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gdnue3HpjS60XlqIAot4rWXNu0pQdK8uUTPTWvh2zVc=; b=g4V3knbMpc0+mpgQW0LLkzk2tHHXqLPu7qhRzuqIhBCxnv7ttSIWMpzxej9sjitTmYTncICOO4la518mQp5msS9UJ4FrbJOiwLn8QAZT+S05ty0c7GzuMkPHLfDnuOwX2DzThAPh9nUWo+mDb0kQscMZdP/BFbQH3LlyofEOweM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790790397332376.5619004574294; Wed, 30 Sep 2026 10:46:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xByNO-0006Tj-OL; Wed, 30 Sep 2026 13:45:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByN6-00066w-W9 for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:45:38 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByN4-0000rv-R6 for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:45:36 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68UHfEk64014402 for ; Wed, 30 Sep 2026 17:45:33 GMT Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h0x27jsnv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 30 Sep 2026 17:45:32 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-93c58ee2116so1010167785a.3 for ; Wed, 30 Sep 2026 10:45:32 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790398860158501 Use per-accelerator locals to make the differing conventions explicit: TCG takes a MIP bitmask and value, KVM takes an IRQ number and a level. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/time_helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index ede1a4c2a34..29bbebb96fc 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -25,18 +25,24 @@ #include "system/kvm.h" #include "system/tcg.h" =20 -static void riscv_accel_set_irq(RISCVCPU *cpu, int irq, int level) +static void riscv_accel_set_irq(RISCVCPU *cpu, + int irq_or_mask, int level_or_value) { if (kvm_enabled()) { + int irq =3D irq_or_mask; + int level =3D level_or_value; + kvm_riscv_set_irq(cpu, irq, level); } =20 if (tcg_enabled()) { - riscv_cpu_update_mip(&cpu->env, irq, level); + uint64_t mask =3D irq_or_mask; + uint64_t value =3D level_or_value; + + riscv_cpu_update_mip(&cpu->env, mask, value); } } =20 - static void riscv_vstimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; --=20 2.55.0 From nobody Sat Oct 24 00:32:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790790397; cv=none; d=zohomail.com; s=zohoarc; b=Ong3uTNuW75u6eyuYXEFcKYiL7xZhA2Qu/Z2aLjc6dGGpIknDo/iBRFZxindN829ohuocc2/9HOPRxRz3S38AtWM7PEbPMlR476kSYMiNyykx6k5aw5y1E728Qcz+fo7R0N+Gf0KAUbM0jLU1nDUWIekYP61n5DeUDEz/uvCh68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790790397; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sAmDnVhA0i46kh20ES8xQX1cBL9fdB8dlxe4KkbGoaE=; b=WH1RegBrxiExQKIaISbSQy2GkrN2fr+9a2DYAUp9tfAY0RVPcF7igzWs1x8hb0eV/3GzlsaG+kZFmBGSC9tkN88FrgOHvrUXuAC6auvuLIS4QgQh/CQ9r/euzpy9BdExUHbdgmJr5N72WZZIC4N5hFKvnEpzc+Gk9ww9kCGGRI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790790397210191.14572428272822; Wed, 30 Sep 2026 10:46:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xByNN-0006PI-NS; Wed, 30 Sep 2026 13:45:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByNE-0006Ej-3k for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:45:48 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByNC-0000zw-KM for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:45:43 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68UHfdkP3785234 for ; Wed, 30 Sep 2026 17:45:41 GMT Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h0tkn3pq3-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 30 Sep 2026 17:45:40 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-92e82060977so4668385a.1 for ; Wed, 30 Sep 2026 10:45:40 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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Wed, 30 Sep 2026 10:45:39 -0700 (PDT) X-Received: by 2002:a05:620a:458f:b0:93a:1196:ce5 with SMTP id af79cd13be357-93cb5c2654bmr70345085a.33.1790790339012; Wed, 30 Sep 2026 10:45:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Chao Liu , Liu Zhiwei , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , qemu-riscv@nongnu.org, Weiwei Li , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v4 4/7] target/riscv: Have riscv_cpu_set_mode() call riscv_cpu_interrupt() Date: Wed, 30 Sep 2026 19:45:04 +0200 Message-ID: <20260930174508.81497-5-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930174508.81497-1-philmd@oss.qualcomm.com> References: <20260930174508.81497-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=CKy/zhrD c=1 sm=1 tr=0 ts=6abd4ac4 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=EurB-bMe9Chw_IDMuCwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: IPjKQz9AmRzpOYxnXS9wrIojAJ_X7omt X-Proofpoint-GUID: IPjKQz9AmRzpOYxnXS9wrIojAJ_X7omt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA3MCBTYWx0ZWRfXy06uxz7NNm+Q umbmBZngJSBtpl6XM4/2T/vXPH7xhoNUdpCJwD3rxXjMxgTxlk2+skG2SJeQRdUkWb9Al0e7wQc z7CWnZNN1HhWcNFyw30XUHTdkea3q2RliD082szdWyEP67wIyF1kIWz2H2b38zah0owOM1lVPKz m0ldGs2hmDzd36KQ5k0LQAxs64uHYx8f7CjXi+m08U81I08T6g7snAZA/NrBBQZ717UFrbanu73 Ut7CkOZVUIdLJh5lPOqTStIqMlNWtPCZsovjX/+IFJxqdXj5kwlgVgXaD6NgJ6D80XhlMpqynmP X2CVknr/Q4o9gAzhsqp9cW4G2mH/5UowwBjYPllWHp0Q1sE3LPYVnAwRHClej0NCX+0bVRax86p TdNCewApBfmL9NldBEihJS1dF/HkVxEEyeaqETBwYzCJVKrFmieaj8dTTGMUxZtyTm+3CPtvGuc DmMqEXF+wuxT/1CN37g== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA3MCBTYWx0ZWRfX3XTtOuTLTwU1 7GmSuq8kkirtAlYh/OkhdAzDOxUUYmaFyjjWodfnbDB2xAH/oHA9wP9vSLfei7Epr+oG99VHzlu 8KRfDnKVHwzUqyW1uikbR02XE5Q9DMw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300070 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790398854158500 riscv_cpu_set_mode() only want the interrupt re-poll: the mip update with a zero mask is a no-op. Call riscv_cpu_interrupt() directly. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/tcg/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 07d92226527..91f5eb72930 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -886,7 +886,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, privilege_m= ode_t newpriv, * * To solve this, we check and inject interrupt after setting = V=3D1. */ - riscv_cpu_update_mip(env, 0, 0); + riscv_cpu_interrupt(env); } } } --=20 2.55.0 From nobody Sat Oct 24 00:32:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790790398; cv=none; d=zohomail.com; s=zohoarc; b=SC6pvC3WUNSUGwaAuP4nQYvEnOlAC2jiCeeFNwbTrDKBH6igshs6bF4wWXndaNXJ7xwMdx+m36LgG41ZEDij0StlHdF6QLfNrkHTwBQv9RKrWSX51nK4Mc6p7CYjIvfakmYG5hGKFL46tovkGF8vLSbdCUaT5lbiBtSs0nmX4zg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790790398; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D+42UtXFtsYPVXGSZMwnMSEP8guAR1nanVRzeeC5iLk=; b=VJh14a6uPmgQP4XxjWYxALlJ1BXp7IMAZbsK3yYz30gK3z3vSHPj0E8hAznPZVSUQHuWyc1vpVbNx71r62zoLWxjeYc9/2rdexREbgN2Qc71UuG5zWPatupcmzR7Fk2H73iDWy3YjlUOL2XXEm1yw4shVL3CYUljsfAlacD8T54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790790398490822.3830894103903; Wed, 30 Sep 2026 10:46:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xByNO-0006Pa-2u; Wed, 30 Sep 2026 13:45:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByNL-0006IV-Jq for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:45:51 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByNJ-00016H-NT for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:45:51 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68UHfeUK3785246 for ; Wed, 30 Sep 2026 17:45:48 GMT Received: from mail-vs1-f72.google.com (mail-vs1-f72.google.com [209.85.217.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h0tkn3pqp-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 30 Sep 2026 17:45:48 +0000 (GMT) Received: by mail-vs1-f72.google.com with SMTP id ada2fe7eead31-7bf3a0a498fso35136137.0 for ; Wed, 30 Sep 2026 10:45:47 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790398924158500 Route MIP reads in the interrupt, CSR, ACLINT and pending-IRQ code through a single riscv_cpu_get_mip() accessor, so the implementation can change in one place. riscv_cpu_update_mip() now reads the old value under the BQL, so the returned value matches the one written. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 7 +++++++ hw/intc/riscv_aclint.c | 2 +- target/riscv/cpu.c | 8 +++++++- target/riscv/tcg/cpu_helper.c | 12 +++++++----- target/riscv/tcg/csr.c | 6 ++++-- 5 files changed, 26 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e34c0c676d5..ad731bf5d34 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -684,6 +684,13 @@ bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr= addr, bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); +/** + * riscv_cpu_get_mip: + * @env: CPURISCVState + * + * Returns: the current value of the Machine Interrupt Pending (MIP) regis= ter. + */ +uint64_t riscv_cpu_get_mip(const CPURISCVState *env); /** * riscv_cpu_update_mip: * @env: CPURISCVState diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 2d133d0dcf9..4bd359c3380 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -438,7 +438,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwa= ddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-swi: invalid hartid: %zu", hartid); } else if ((addr & 0x3) =3D=3D 0) { - return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); + return (swi->sswi) ? 0 : ((riscv_cpu_get_mip(env) & MIP_MSIP) = > 0); } } =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b9..b8d6f992ba4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -916,8 +916,9 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env) uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; + uint64_t mip =3D riscv_cpu_get_mip(env); =20 - return (env->mip | vsgein | vstip) & env->mie; + return (mip | vsgein | vstip) & env->mie; } =20 int riscv_cpu_mirq_pending(CPURISCVState *env) @@ -953,6 +954,11 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } =20 +uint64_t riscv_cpu_get_mip(const CPURISCVState *env) +{ + return env->mip; +} + bool riscv_cpu_has_work(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 91f5eb72930..f8f779a01d8 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -567,7 +567,7 @@ void riscv_cpu_interrupt(CPURISCVState *env) =20 vstip =3D env->vstime_irq ? MIP_VSTIP : 0; =20 - if (env->mip | vsgein | vstip | irqf) { + if (riscv_cpu_get_mip(env) | vsgein | vstip | irqf) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -576,14 +576,15 @@ void riscv_cpu_interrupt(CPURISCVState *env) =20 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t = value) { - uint64_t old =3D env->mip; + uint64_t old; =20 /* No need to update mip for VSTIP */ mask =3D ((mask =3D=3D MIP_VSTIP) && env->vstime_irq) ? 0 : mask; =20 BQL_LOCK_GUARD(); =20 - env->mip =3D (env->mip & ~mask) | (value & mask); + old =3D riscv_cpu_get_mip(env); + env->mip =3D (old & ~mask) | (value & mask); =20 riscv_cpu_interrupt(env); =20 @@ -2061,10 +2062,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; + uint64_t mip =3D riscv_cpu_get_mip(env); bool s_injected =3D env->mvip & (1ULL << cause) & env->mvien && - !(env->mip & (1ULL << cause)); + !(mip & (1ULL << cause)); bool vs_injected =3D env->hvip & (1ULL << cause) & env->hvien && - !(env->mip & (1ULL << cause)); + !(mip & (1ULL << cause)); bool smode_double_trap =3D false; uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; const bool prev_virt =3D env->virt_enabled; diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 061bc9db77b..a0e32f14276 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3816,7 +3816,7 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, if (mask) { old_mip =3D riscv_cpu_update_mip(env, mask, (new_val & mask)); } else { - old_mip =3D env->mip; + old_mip =3D riscv_cpu_get_mip(env); } =20 if (csrno !=3D CSR_HVIP) { @@ -4549,8 +4549,10 @@ static RISCVException read_vstopi(CPURISCVState *env= , int csrno, hviprio =3D get_field(env->hvictl, HVICTL_IPRIO); =20 if (gein) { + uint64_t mip =3D riscv_cpu_get_mip(env); + vsgein =3D (env->hgeip & (1ULL << gein)) ? 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Wed, 30 Sep 2026 10:45:54 -0700 (PDT) X-Received: by 2002:a05:620a:2686:b0:93c:7a5c:77d8 with SMTP id af79cd13be357-93cabf2a172mr343980885a.4.1790790353412; Wed, 30 Sep 2026 10:45:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Chao Liu , Liu Zhiwei , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , qemu-riscv@nongnu.org, Weiwei Li , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson Subject: [PATCH v4 6/7] target/riscv: Access MIP atomically Date: Wed, 30 Sep 2026 19:45:06 +0200 Message-ID: <20260930174508.81497-7-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930174508.81497-1-philmd@oss.qualcomm.com> References: <20260930174508.81497-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=CKy/zhrD c=1 sm=1 tr=0 ts=6abd4ad3 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=20KFwNOVAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=snbnvTbt-5-dSQZ-83gA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: k8upuRtVWv_7_7AVTizOgWLoKNZtZ-lm X-Proofpoint-GUID: k8upuRtVWv_7_7AVTizOgWLoKNZtZ-lm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA3MCBTYWx0ZWRfXwxsMSiecYs9A w02e1pJLOCRtQdat2hGo87WvvW0Rdy0FLBPWBbxGI6LaWdQ6zP3Txsje+QRjm3MvwFzZMMlm5X4 4uwl5rvqNcubcEcGTFS6ZW+XoEFR0HlfUzb2Q/351ipMacyo32lmV9ywBZTBm9O+FeUyqnvLy0C UPwqrONuth8exik+0my6c2rE1Nefl7sJfyhKNoxsDb/rwZoqJTxYH9JCikLMemgJmQN0pPSVAAA tc0HBthgqfdFkugi64oORTur5KdnzoP399Z+mOyVJECxD1E3Dlx2kxuJT331fbrmWKxCZ/pL8L2 3hw3ffoklutRZFFA79HfhFbojtcrM4L3JTT857og7FJ+ctqFKMyc1zE9qe5bh8qyutJdZ2bpmzi 7TyD/ETWPXLuakf2EqHEqj1YRTDSZOYU2MusKWS6IWBuhA3d5Oz4+MQGyA6DplmdnFdQC3FIZ76 V6DWlweXSQUooC7vtyg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA3MCBTYWx0ZWRfXwyz64cEZxbgd 4L8JGvcso0vZwu8xJfBHMdIw+DqdN7/ZPoziV/WKYbLD7+yvNsbGRYMWyhvr1jA4FmcBqDIWaol 5iaS5JjX4ug0hEHjGJynrYdqmYnFpAU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300070 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790407088158500 Make riscv_cpu_get_mip() read env->mip with qatomic_read() and riscv_cpu_update_mip() store it with qatomic_set(). This makes MIP reads and writes safe for riscv_cpu_has_work(), which may run without the BQL. Reported-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/tcg/cpu_helper.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8d6f992ba4..45e82fc30c5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "qemu/guest-random.h" +#include "qemu/atomic.h" #include "cpu.h" #include "cpu_vendorid.h" #include "target/riscv/tcg/csr.h" @@ -956,7 +957,7 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) =20 uint64_t riscv_cpu_get_mip(const CPURISCVState *env) { - return env->mip; + return qatomic_read(&env->mip); } =20 bool riscv_cpu_has_work(CPUState *cs) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index f8f779a01d8..db7f2bd6de7 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "qemu/atomic.h" #include "cpu.h" #include "internals.h" #include "pmu.h" @@ -584,7 +585,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, uint64_t value) BQL_LOCK_GUARD(); =20 old =3D riscv_cpu_get_mip(env); - env->mip =3D (old & ~mask) | (value & mask); + qatomic_set(&env->mip, (old & ~mask) | (value & mask)); =20 riscv_cpu_interrupt(env); =20 --=20 2.55.0 From nobody Sat Oct 24 00:32:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790790384; cv=none; d=zohomail.com; s=zohoarc; b=a6I0j3upaGJJdC9mt/0ulidkfa0Obaw3fs0lSgVEniPp8aMf4n4+ecxXSbJX0HSaSKD4gQnCOLX67bIbx05nHR/XcOtWXQPvMDbXKkRZA/V1rWmoHIcaaCGOxY/orGvi9Lhc6FzLCFw9beiY1FdxNpZh2iCpindi8w+pPAOc5/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790790384; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NKFkuHP5kHsFlr48mIqBrzrwJma0vgwROjVU+AFRLRs=; b=Pk5uwV9751uP53EbJUQ5JzViP2oByeMZ95sfcFJE1+iVB1QIql2ImGc+hMcftabmTVIwhSJmmltAavEtMgCGM4le9hn3wjsIGcimLESGAavrqIxGcpY0/5UXzGu5C8Ppzk6VK4zJd8Pyst1ivi0WTnwpAAMa7zI5xOFRr2kh8Iw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790790384674646.1747272992948; Wed, 30 Sep 2026 10:46:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xByNa-0006kQ-Pb; Wed, 30 Sep 2026 13:46:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByNZ-0006ju-PC for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:46:05 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xByNY-00017e-1f for qemu-devel@nongnu.org; Wed, 30 Sep 2026 13:46:05 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68UHf5jX3566639 for ; Wed, 30 Sep 2026 17:46:02 GMT Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h0smjky98-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 30 Sep 2026 17:46:02 +0000 (GMT) Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-93bf4c0af4eso3347085a.1 for ; Wed, 30 Sep 2026 10:46:02 -0700 (PDT) Received: from localhost.localdomain (pmd666.hd.free.fr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790790387088158500 riscv_cpu_update_mip() was called with a zero mask only to re-poll interrupts after updating env->vstime_irq, where the VS timer keeps VSTIP (see 14cb78bfaf4 "target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP"). Move that re-poll to riscv_accel_set_irq(), which now calls riscv_cpu_interrupt() directly for the zero-mask case, and keep the early return for the no-op VSTIP update. No caller passes a zero mask anymore, so document @mask as non-zero and assert it. AI-used-for: code (prototype) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 2 +- target/riscv/tcg/cpu_helper.c | 6 +++++- target/riscv/time_helper.c | 11 ++++++++++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad731bf5d34..6173360e407 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -694,7 +694,7 @@ uint64_t riscv_cpu_get_mip(const CPURISCVState *env); /** * riscv_cpu_update_mip: * @env: CPURISCVState - * @mask: Mask of the MIP bits to update + * @mask: Mask of the MIP bits to update (must be non-zero) * @value: New values for the bits set in @mask. * Use BOOL_TO_MASK() for boolean values. * diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index db7f2bd6de7..16b2c486934 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -579,8 +579,12 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint= 64_t mask, uint64_t value) { uint64_t old; =20 + assert(mask); + /* No need to update mip for VSTIP */ - mask =3D ((mask =3D=3D MIP_VSTIP) && env->vstime_irq) ? 0 : mask; + if (mask =3D=3D MIP_VSTIP && env->vstime_irq) { + return riscv_cpu_get_mip(env); + } =20 BQL_LOCK_GUARD(); =20 diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 29bbebb96fc..6bd917383e3 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -39,7 +39,16 @@ static void riscv_accel_set_irq(RISCVCPU *cpu, uint64_t mask =3D irq_or_mask; uint64_t value =3D level_or_value; =20 - riscv_cpu_update_mip(&cpu->env, mask, value); + if (!mask) { + /* + * The VS timer keeps VSTIP in env->vstime_irq rather than + * in mip, so callers pass a zero mask only to re-poll + * interrupts after updating it. + */ + riscv_cpu_interrupt(&cpu->env); + } else { + riscv_cpu_update_mip(&cpu->env, mask, value); + } } } =20 --=20 2.55.0