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Mon, 28 Sep 2026 13:11:14 -0700 (PDT) X-Received: by 2002:a05:6214:29c4:b0:914:cdbf:b6a with SMTP id 6a1803df08f44-914cdbf132fmr104516936d6.29.1790626274189; Mon, 28 Sep 2026 13:11:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v13 1/5] target/riscv/cpu.c: remove 'bare' condition for .profile Date: Mon, 28 Sep 2026 17:11:02 -0300 Message-ID: <20260928201107.2049458-2-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260928201107.2049458-1-daniel.barboza@oss.qualcomm.com> References: <20260928201107.2049458-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=N6i8hG9B c=1 sm=1 tr=0 ts=6abac9e4 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=0kFmPUMe/4ewoYCJjrGTNA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=JF9118EUAAAA:8 a=FRSEYCzRAAAA:8 a=GhL2bEVCvcqOW28JNKkA:9 a=OIgjcC2v60KrkQgK7BGD:22 a=xVlTc564ipvMDusKsbsT:22 a=H4N_Y-AU75W7NKDNhZlT:22 X-Proofpoint-ORIG-GUID: JhYBS0OxmeRMvTtTmTx-b0VKkxmJq6E3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDA4MCBTYWx0ZWRfXyy+RoCt9amFR bmGfUNBdIi1xPBHJxhYi5Jui93socykJLVVxEoM9HzCSRdi9QzlbGOx6/RXq6JxuXEvute521jp 3KVNwBiI2KawNVSPenfL64+DaKItj/kIPhQqU2h13MkXPYsvUPNnyCi3qwr3vHyugrLNLMoKJCT AXSol+CdSyp8e6a68Gb09xKiBD8d7BtVvEy7ZPJoPTDmCGkYMadbvU5pAHbfei/88mPuoIwlk1M Fa7nMbrT0Kzc3Gvudqje2MrHuxt8SUVfO9dP5L1iyQ8gi7+yz0pIJtbHaosvAu+KNGZr4eEJfnJ Ubi4pz8eFyttV9RQFCdv5zBnRCDBkIlN0s11pzv48ddRtGQtxXGF0o9QotTRDcHDTrOffiU/5sj TsaBoQ4ueyfNARfIOxMNLuOYRLJVIruye0IDiOYd23n2SOH+rVqhsdR7h88j+JGGzXzi5hC5kBn y8EjkNM9tiz8rEi+vGw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDA4MCBTYWx0ZWRfX4Ad9XanuyS3K n6e79/fIHv45HtOp5xbh1LPMP1XMxZndxFyde108by8dUZH+UttQhEbuXXE2EuNqj7YKV9GtYJk OZwX1RuKcUTwjiuMexhfBmVnCZx2Vw0= X-Proofpoint-GUID: JhYBS0OxmeRMvTtTmTx-b0VKkxmJq6E3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-28_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280080 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790626311232158500 Content-Type: text/plain; charset="utf-8" We want to configure other CPU types to use profiles as an alternative to adding every profile extension explicitly, i.e. a profile is nothing more than an extension bundle. This means that a vendor CPU can set .profile=3Drva23s64 while having the same handling as any other vendor CPU. Same thing with all other CPU types. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Sunil V L --- target/riscv/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f5490c81ea..766b9424d5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3107,7 +3107,6 @@ static void riscv_cpu_class_base_init(ObjectClass *c,= const void *data) mcc->def->bare |=3D def->bare; if (def->profile) { assert(profile_extends(def->profile, mcc->def->profile)); - assert(mcc->def->bare); mcc->def->profile =3D def->profile; } if (def->misa_mxl_max) { --=20 2.43.0 From nobody Fri Oct 23 22:37:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; 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Mon, 28 Sep 2026 13:11:17 -0700 (PDT) X-Received: by 2002:ad4:4eed:0:b0:8ea:c243:84e0 with SMTP id 6a1803df08f44-917862dfebdmr9137856d6.1.1790626276658; Mon, 28 Sep 2026 13:11:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v13 2/5] target/riscv: add riscv-server-ref CPU Date: Mon, 28 Sep 2026 17:11:03 -0300 Message-ID: <20260928201107.2049458-3-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260928201107.2049458-1-daniel.barboza@oss.qualcomm.com> References: <20260928201107.2049458-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDA4MCBTYWx0ZWRfX3iI7TrC6X/TX 5oxthEE2u/t9ZNNrvdoNtboiKBnBI0tPGA5uSfREz2QNnyaCb+5YFco7vVCPGth8BgzoGMpHBgt agw7wUxSZ5nG0fBbVAsQHo7sqcgCdAhvFDtKwaQsvbps4I3wDxlXRHJPi9LzKhBejhLHZxdDyEu VLBrM/f61p9NEjiENkKEJ/HH7gvfn3An37HNS86eM3CwYx7HdSeWVRuOYcmq7HEn874P3m+YOxL TEt7ytA062+7dfjIz4mv2BMwgkx+vQs7o9t+WpYMrc6FEVg+NWmogAQW6I3QirAf9Tlme+OgHrD 5daIiRdLxOngfD3pYcovuB9+HahxGeGzQ/Swj9Rzo4qmP5ydWGc/jVY/3I/0w4WEKBaA1VtBwGq kMTetGTAXfWFoW2I/7E5r78B94uRQm7ZC5T/5jiqKMgKGm1PvDzhRt9SGTyFiquY+9rJDTN75nt 5Q4OjkWZLtSOle2ztHA== X-Proofpoint-ORIG-GUID: kJwKT-j351jzbw1Nn2SOT1qymmCF68lB X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDA4MCBTYWx0ZWRfX/8JuzjCoOsUC oXtbIb/DIYAIiB3OzZ9cUCAhzNRE23RKiUfmAvSQcN3uSgsBNhzUjLkHGTgrB4CfGsyQ/hMqf/o HscQGda+EFVkDO0jV6GlPKJ7g/B2+wI= X-Proofpoint-GUID: kJwKT-j351jzbw1Nn2SOT1qymmCF68lB X-Authority-Analysis: v=2.4 cv=TptzFzXh c=1 sm=1 tr=0 ts=6abac9e6 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=0kFmPUMe/4ewoYCJjrGTNA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=V1jnuoLLAAAA:20 a=EUspDBNiAAAA:8 a=JF9118EUAAAA:8 a=PXcuKL70AAAA:8 a=FRSEYCzRAAAA:8 a=zLUtPzHEVTZWnbMtJKMA:9 a=1HOtulTD9v-eNWfpl4qZ:22 a=xVlTc564ipvMDusKsbsT:22 a=1qLaeP4TCVy2vqIEy19U:22 a=H4N_Y-AU75W7NKDNhZlT:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-28_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280080 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790626312907158500 Content-Type: text/plain; charset="utf-8" The harts requirements of RISC-V server platform [1] require RVA23 ISA profile support and others. We're going for a profile-based implementation, instead of a regular CPU that can inherit RVA23, to allow future CPUs to use it internally as a starting base for their own extension sets. There's also a new 'rvserver-ref-1.0' flag that can be used to set the extensions in the command line for other CPUs, which can be used for testing/debugging purposes. Note that for all intents and purposes "riscv-server-ref" is a regular CPU and no, we're not trying to set a precedent of calling the riscv server platform spec a profile. [1] defines in rule SEE_020 that we must support at least 11 debug triggers (4 for insn address, 4 for insn load/store, 1 for icount, one for int, one for excp). We're going for the minimum. If more triggers are needed users can set any trigger amount (N <=3D 1024) with: -cpu riscv-server-ref,num-triggers=3DN [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server= _platform_requirements.adoc Suggested-by: Icenowy Zheng Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Matheus Ferst Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 1a28f1369c..61234842e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -42,6 +42,7 @@ #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") +#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-= ref") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 766b9424d5..408b412c7b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2428,11 +2428,37 @@ static RISCVCPUProfile RVA23S64 =3D { } }; =20 +/* + * This riscv-server-ref entry isn't a profile per se but its + * CPU definition can be modelled as a profile that extends + * RVA23, with additional things on top of it, and allowing + * future CPUs to derive from it via + * ".profile =3D &RVServerRef1_0;". + */ +static RISCVCPUProfile RVServerRef1_0 =3D { + .s_parent =3D &RVA23S64, + .name =3D "riscv-server-ref-1.0", + .satp_mode =3D VM_1_10_SV48, + .priv_spec =3D PRIV_VERSION_1_13_0, + .ext_offsets =3D { + CPU_CFG_OFFSET(ext_zkr), + CPU_CFG_OFFSET(ext_sdext), + CPU_CFG_OFFSET(ext_sdtrig), + CPU_CFG_OFFSET(ext_ssaia), + CPU_CFG_OFFSET(ext_ssccfg), + /* ssstrict is always enabled for PRIV_VER_1_12+ */ + + RISCV_PROFILE_EXT_LIST_END + } +}; + + RISCVCPUProfile *riscv_profiles[] =3D { &RVA22U64, &RVA22S64, &RVA23U64, &RVA23S64, + &RVServerRef1_0, NULL, }; =20 @@ -3770,6 +3796,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU, + .profile =3D &RVServerRef1_0, + .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 6), + .num_triggers =3D 11, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode =3D VM_1_10_SV57, --=20 2.43.0 From nobody Fri Oct 23 22:37:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790626363459158500 Content-Type: text/plain; charset="utf-8" The RISC-V Server Platform specification [1] defines a standardized set of hardware and software capabilities, that portable system software, such as OS and hypervisors can rely on being present in a RISC-V server platform. The main features included in this emulation are: - Based on riscv virt machine type; - A new memory map as close as virt machine as possible; - An always present IOMMU platform device (riscv-iommu-sys) that uses IRQs 36 to 39, one IRQ for queue, similar to the 'virt' board; - AIA; - No default AHCI (can be added via command line); - No default NIC (can be added via command line); - No virtio device; - No fw_cfg device; - No ACPI table provided; - Only minimal device tree nodes; - a platform bus for TPM support. A note about TPM support: TPM devices in QEMU comes usually in two flavors - emulated or passthrough. A passthrough device requires a host TPM device that the QEMU process can borrow and it's usually coupled with KVM acceleration. To use the TPM emulator we'll need help from an external TPM emulator called swtpm. More info can be found in [2]. For our purposes this is a process that, if running Ubuntu, can be installed via 'swtpm' package. We'll go back to it shortly. For now, adding support for the emulated TPM device 'tpm-tis' (other TPM flavors might work as well, 'tpm-tis' is the one tested with this work) requires a platform bus. Adding a platform bus will open the door for more devices to be added in the board. This is ok - a reference board isn't a restricted board and users are free to add devices at their leisure. Here's how to use tpm-tis with the riscv-server-ref board: - in a separated shell/term run 'swtpm' (--log is optional): $ mkdir /tmp/mytpm1 $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ --tpm2 \ --log level=3D20 Then start QEMU with: $ qemu-system-riscv64 -M riscv-server-ref (...) \ -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm\ -device tpm-tis-device,tpmdev=3Dtpm0 [1] https://github.com/riscv-non-isa/riscv-server-platform [2] https://qemu-project.gitlab.io/qemu/specs/tpm.html Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Acked-by: Alistair Francis Reviewed-by: Alistair Francis --- configs/devices/riscv64-softmmu/default.mak | 1 + hw/riscv/Kconfig | 17 + hw/riscv/meson.build | 1 + hw/riscv/server_platform_ref.c | 776 ++++++++++++++++++++ 4 files changed, 795 insertions(+) create mode 100644 hw/riscv/server_platform_ref.c diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/= riscv64-softmmu/default.mak index a8e4d0ab33..ae3f62e2d4 100644 --- a/configs/devices/riscv64-softmmu/default.mak +++ b/configs/devices/riscv64-softmmu/default.mak @@ -9,6 +9,7 @@ # CONFIG_SIFIVE_E=3Dn # CONFIG_SIFIVE_U=3Dn # CONFIG_RISCV_VIRT=3Dn +# CONFIG_RISCV_SERVER_PLATFORM_REF=3Dn # CONFIG_MICROCHIP_PFSOC=3Dn # CONFIG_SHAKTI_C=3Dn # CONFIG_XIANGSHAN_KUNMINGHU=3Dn diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d06ac26648..35b92dc395 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -69,6 +69,23 @@ config RISCV_VIRT select ACPI select ACPI_PCI =20 +config RISCV_SERVER_PLATFORM_REF + bool + default y + depends on RISCV64 + imply TPM_TIS_SYSBUS + select GOLDFISH_RTC + select PCI_EXPRESS_GENERIC_BRIDGE + select PCIE_DEVICES + select PFLASH_CFI01 + select PLATFORM_BUS + select RISCV_ACLINT + select RISCV_APLIC + select RISCV_IMSIC + select RISCV_IOMMU + select RISCV_NUMA + select SERIAL_MM + config SHAKTI_C bool default y diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 7aa3c1578d..cc5a019f7c 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -7,6 +7,7 @@ riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('num= a.c')) riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_RISCV_SERVER_PLATFORM_REF', if_true: files('ser= ver_platform_ref.c')) riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) diff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c new file mode 100644 index 0000000000..5f485b1c79 --- /dev/null +++ b/hw/riscv/server_platform_ref.c @@ -0,0 +1,776 @@ +/* + * QEMU RISC-V Server Platform Reference Board (riscv-server-ref) + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-common.h" +#include "hw/core/boards.h" +#include "hw/core/platform-bus.h" +#include "hw/core/loader.h" +#include "hw/core/sysbus.h" +#include "hw/core/qdev-properties.h" +#include "hw/char/serial.h" +#include "hw/block/flash.h" +#include "hw/ide/pci.h" +#include "hw/ide/ahci-pci.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" +#include "hw/core/sysbus-fdt.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/boot.h" +#include "hw/riscv/device-common.h" +#include "hw/riscv/fdt-common.h" +#include "hw/riscv/numa.h" +#include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" +#include "hw/intc/riscv_aclint.h" +#include "hw/intc/riscv_aplic.h" +#include "hw/intc/riscv_imsic.h" +#include "chardev/char.h" +#include "hw/char/serial-mm.h" +#include "system/device_tree.h" +#include "system/runstate.h" +#include "system/system.h" +#include "system/kvm.h" +#include "system/qtest.h" +#include "system/tcg.h" +#include "kvm/kvm_riscv.h" +#include "system/tpm.h" +#include "target/riscv/cpu.h" +#include "net/net.h" + +#include "aia.h" + +#define RVSERVER_ACLINT_TIMEBASE_FREQ 1000000000 /* 1Ghz */ +#define RVSERVER_CPUS_MAX_BITS 9 +#define RVSERVER_CPUS_MAX (1 << RVSERVER_CPUS_MAX_BIT= S) +#define RVSERVER_IRQCHIP_NUM_MSIS 255 +#define RVSERVER_IRQCHIP_NUM_SOURCES 96 +#define RVSERVER_IRQCHIP_NUM_PRIO_BITS 3 +#define RVSERVER_IRQCHIP_DEFAULT_AIA_GUESTS 5 +#define RVSERVER_IRQCHIP_MAX_GUESTS_BITS 3 +#define RVSERVER_IRQCHIP_MAX_GUESTS \ + ((1U << RVSERVER_IRQCHIP_MAX_GUESTS_BITS) - 1U) +#define RVSERVER_SOCKETS_MAX_BITS 2 +#define RVSERVER_SOCKETS_MAX (1 << RVSERVER_SOCKETS_MAX_= BITS) + +#define SYSCON_RESET 0x1 +#define SYSCON_POWEROFF 0x2 + +#define RVSERVER_PLATFORM_BUS_NUM_IRQS 8 + +#define TYPE_RISCV_SERVER_REF_MACHINE MACHINE_TYPE_NAME("riscv-server-ref") +OBJECT_DECLARE_SIMPLE_TYPE(RISCVServerRefMachineState, RISCV_SERVER_REF_MA= CHINE) + +struct RISCVServerRefMachineState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + RISCVHartArrayState soc[RVSERVER_SOCKETS_MAX]; + DeviceState *irqchip[RVSERVER_SOCKETS_MAX]; + PFlashCFI01 *flash[2]; + + int fdt_size; + int aia_guests; + const MemMapEntry *memmap; + + DeviceState *platform_bus_dev; +}; + +enum { + RVSERVER_MROM, + RVSERVER_RESET_SYSCON, + RVSERVER_RTC, + RVSERVER_IOMMU_SYS, + RVSERVER_ACLINT, + RVSERVER_APLIC_M, + RVSERVER_APLIC_S, + RVSERVER_UART0, + RVSERVER_IMSIC_M, + RVSERVER_IMSIC_S, + RVSERVER_FLASH, + RVSERVER_DRAM, + RVSERVER_PCIE_MMIO, + RVSERVER_PCIE_PIO, + RVSERVER_PLATFORM_BUS, + RVSERVER_PCIE_ECAM, + RVSERVER_PCIE_MMIO_HIGH +}; + +enum { + RVSERVER_UART0_IRQ =3D 10, + RVSERVER_RTC_IRQ =3D 11, + RVSERVER_PCIE_IRQ =3D 32, /* 32 to 35 */ + IOMMU_SYS_IRQ =3D 36, /* 36 to 39 */ + RVSERVER_PLATFORM_BUS_IRQ =3D 40, /* 40 to 47 */ +}; + +/* + * The server soc reference machine physical address space used by some of= the + * devices namely ACLINT, APLIC and IMSIC depend on number of Sockets, num= ber + * of CPUs, and number of IMSIC guest files. + * + * Various limits defined by RVSERVER_SOCKETS_MAX_BITS, RVSERVER_CPUS_MAX_= BITS, + * and RVSERVER_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization = of + * server reference machine physical address space. + */ + +#define RVSERVER_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHI= FT) +#if RVSERVER_IMSIC_GROUP_MAX_SIZE < \ + IMSIC_GROUP_SIZE(RVSERVER_CPUS_MAX_BITS, RVSERVER_IRQCHIP_MAX_GUESTS_B= ITS) +#error "Can't accommodate single IMSIC group in address space" +#endif + +#define RVSERVER_IMSIC_MAX_SIZE \ + (RVSERVER_SOCKETS_MAX * RVSERVER_IMSIC_GROUP_MAX_SIZE) +#if 0x4000000 < RVSERVER_IMSIC_MAX_SIZE +#error "Can't accommodate all IMSIC groups in address space" +#endif + +static const MemMapEntry rvserver_ref_memmap[] =3D { + [RVSERVER_MROM] =3D { 0x1000, 0xf000 }, + [RVSERVER_RESET_SYSCON] =3D { 0x100000, 0x1000 }, + [RVSERVER_RTC] =3D { 0x101000, 0x1000 }, + [RVSERVER_IOMMU_SYS] =3D { 0x102000, 0x1000 }, + [RVSERVER_ACLINT] =3D { 0x2000000, 0x10000 }, + [RVSERVER_PCIE_PIO] =3D { 0x3000000, 0x10000 }, + [RVSERVER_PLATFORM_BUS] =3D { 0x4000000, 0x2000000 }, + [RVSERVER_APLIC_M] =3D { 0xc000000, APLIC_SIZE(RVSERVER_CPUS_M= AX) }, + [RVSERVER_APLIC_S] =3D { 0xd000000, APLIC_SIZE(RVSERVER_CPUS_M= AX) }, + [RVSERVER_UART0] =3D { 0x10000000, 0x100 }, + [RVSERVER_FLASH] =3D { 0x20000000, 0x4000000 }, + [RVSERVER_IMSIC_M] =3D { 0x24000000, RVSERVER_IMSIC_MAX_SIZE }, + [RVSERVER_IMSIC_S] =3D { 0x28000000, RVSERVER_IMSIC_MAX_SIZE }, + [RVSERVER_PCIE_ECAM] =3D { 0x30000000, 0x10000000 }, + [RVSERVER_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, + [RVSERVER_DRAM] =3D { 0x80000000, 0xff80000000ull }, + [RVSERVER_PCIE_MMIO_HIGH] =3D { 0x10000000000ull, 0x10000000000ull }, +}; + +#define RVSERVER_FLASH_SECTOR_SIZE (256 * KiB) + +static void rvserver_flash_maps(RISCVServerRefMachineState *s, + MemoryRegion *sysmem) +{ + hwaddr flashsize =3D rvserver_ref_memmap[RVSERVER_FLASH].size / 2; + hwaddr flashbase =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + + riscv_init_flash_map(s->flash[0], flashbase, flashsize, + sysmem, RVSERVER_FLASH_SECTOR_SIZE); + riscv_init_flash_map(s->flash[1], flashbase + flashsize, flashsize, + sysmem, RVSERVER_FLASH_SECTOR_SIZE); +} + +static void create_fdt_pmu(RISCVServerRefMachineState *s) +{ + g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); + MachineState *ms =3D MACHINE(s); + RISCVCPU *hart =3D &s->soc[0].harts[0]; + + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart->pmu_avail_ctrs, pmu_name); +} + +static void create_fdt_sockets(RISCVServerRefMachineState *s, + const MemMapEntry *memmap, + uint32_t *phandle, + uint32_t *irq_mmio_phandle, + uint32_t *irq_pcie_phandle, + uint32_t *msi_pcie_phandle) +{ + int socket, phandle_pos; + MachineState *ms =3D MACHINE(s); + uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; + uint32_t xplic_phandles[MAX_NODES]; + g_autofree uint32_t *intc_phandles =3D NULL; + int socket_count =3D riscv_socket_count(ms); + bool numa_enabled =3D riscv_numa_enabled(ms); + bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); + IMSICFdtProps imsic_fdt_props; + APLICFdtProps aplic_fdt_props; + ACLINTFdtProps aclint_props; + + riscv_fdt_create_cpu_socket_subnode(ms->fdt, + kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) + : RVSERVER_ACLINT_TIMEBASE_FREQ); + + intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + + aclint_props.clint =3D &memmap[RVSERVER_ACLINT]; + aclint_props.aia_type =3D AIA_TYPE_APLIC_IMSIC; + aclint_props.numa_enabled =3D numa_enabled; + + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + hwaddr memaddr =3D s->memmap[RVSERVER_DRAM].base + + riscv_socket_mem_offset(ms, socket); + uint64_t memsize =3D riscv_socket_mem_size(ms, socket); + + phandle_pos -=3D s->soc[socket].num_harts; + + riscv_create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, so= cket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + phandle, &intc_phandles[phandle_pos], + numa_enabled, is_32_bit); + + riscv_create_fdt_socket_memory(ms->fdt, memaddr, memsize, + socket, riscv_numa_enabled(ms)); + + aclint_props.socket =3D socket; + aclint_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aclint(ms->fdt, &aclint_props, + &intc_phandles[phandle_pos]); + } + + imsic_fdt_props.soc =3D &s->soc; + imsic_fdt_props.socket_count =3D socket_count; + imsic_fdt_props.smp_cpus =3D ms->smp.cpus; + imsic_fdt_props.imsic_m_base =3D memmap[RVSERVER_IMSIC_M].base; + imsic_fdt_props.imsic_s_base =3D memmap[RVSERVER_IMSIC_S].base; + imsic_fdt_props.imsic_group_max_size =3D RVSERVER_IMSIC_GROUP_MAX_SIZE; + imsic_fdt_props.irqchip_num_msis =3D RVSERVER_IRQCHIP_NUM_MSIS; + imsic_fdt_props.aia_guests =3D s->aia_guests; + + riscv_create_fdt_imsic(ms->fdt, &imsic_fdt_props, phandle, intc_phandl= es, + &msi_m_phandle, &msi_s_phandle); + *msi_pcie_phandle =3D msi_s_phandle; + + aplic_fdt_props.aplic_m =3D !kvm_enabled() + ? &memmap[RVSERVER_APLIC_M] : NULL; + aplic_fdt_props.aplic_s =3D &memmap[RVSERVER_APLIC_S]; + aplic_fdt_props.platform_bus =3D &memmap[RVSERVER_PLATFORM_BUS]; + aplic_fdt_props.platform_bus_irq =3D RVSERVER_PLATFORM_BUS_IRQ; + aplic_fdt_props.num_harts =3D ms->smp.cpus; + aplic_fdt_props.numa_enabled =3D numa_enabled; + aplic_fdt_props.irqchip_num_sources =3D RVSERVER_IRQCHIP_NUM_SOURCES; + aplic_fdt_props.aia_type =3D AIA_TYPE_APLIC_IMSIC; + + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + phandle_pos -=3D s->soc[socket].num_harts; + + aplic_fdt_props.socket =3D socket; + aplic_fdt_props.num_harts =3D s->soc[socket].num_harts; + riscv_create_fdt_socket_aplic(ms->fdt, &aplic_fdt_props, + msi_m_phandle, msi_s_phandle, phandl= e, + &intc_phandles[phandle_pos], + xplic_phandles); + } + + for (socket =3D 0; socket < socket_count; socket++) { + if (socket =3D=3D 0) { + *irq_mmio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 1) { + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + } + + riscv_socket_fdt_write_distance_matrix(ms); +} + +static void finalize_fdt(RISCVServerRefMachineState *s) +{ + uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; + uint32_t irq_pcie_phandle =3D 1, iommu_sys_phandle; + g_autofree char *name =3D NULL; + MachineState *ms =3D MACHINE(s); + + create_fdt_sockets(s, rvserver_ref_memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &msi_pcie_phandle); + + iommu_sys_phandle =3D riscv_create_fdt_riscv_iommu_sys(ms->fdt, + s->memmap[RVSERVER_IOMMU_SYS].bas= e, + s->memmap[RVSERVER_IOMMU_SYS].siz= e, + &phandle, irq_mmio_phandle, + msi_pcie_phandle, IOMMU_SYS_IRQ); + + riscv_create_fdt_pcie(ms->fdt, AIA_TYPE_APLIC_IMSIC, true, + &s->memmap[RVSERVER_PCIE_ECAM], + &s->memmap[RVSERVER_PCIE_PIO], + &s->memmap[RVSERVER_PCIE_MMIO], + &s->memmap[RVSERVER_PCIE_MMIO_HIGH], + irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle, RVSERVER_PCIE_IRQ); + + riscv_create_fdt_syscon(ms->fdt, &phandle, + rvserver_ref_memmap[RVSERVER_RESET_SYSCON].bas= e, + rvserver_ref_memmap[RVSERVER_RESET_SYSCON].siz= e, + SYSCON_RESET, SYSCON_POWEROFF, false); + + riscv_create_fdt_uart(ms->fdt, &rvserver_ref_memmap[RVSERVER_UART0], + RVSERVER_UART0_IRQ, AIA_TYPE_APLIC_IMSIC, + irq_mmio_phandle); + name =3D riscv_fdt_get_uart_nodename(rvserver_ref_memmap[RVSERVER_UART= 0].base); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); + + riscv_create_fdt_rtc(ms->fdt, &rvserver_ref_memmap[RVSERVER_RTC], + RVSERVER_RTC_IRQ, AIA_TYPE_APLIC_IMSIC, + irq_mmio_phandle); +} + +static void create_fdt(RISCVServerRefMachineState *s, + const MemMapEntry *memmap) +{ + MachineState *ms =3D MACHINE(s); + uint8_t rng_seed[32]; + g_autofree char *name =3D NULL; + + ms->fdt =3D riscv_create_board_device_tree(MACHINE_GET_CLASS(s)->desc, + "qemu,riscv-server-ref", + &s->fdt_size); + + /* + * This versioning scheme is for informing platform fw only. It is nei= ther: + * - A QEMU versioned machine type; a given version of QEMU will emula= te + * a given version of the platform. + * - A reflection of level of server platform support provided. + * + * machine-version-major: updated when changes breaking fw compatibili= ty + * are introduced. + * machine-version-minor: updated when features are added that don't b= reak + * fw compatibility. + * + * It's the same as the scheme in arm sbsa-ref. + */ + qemu_fdt_setprop_cell(ms->fdt, "/", "machine-version-major", 0); + qemu_fdt_setprop_cell(ms->fdt, "/", "machine-version-minor", 0); + + /* + * The "/soc/pci@..." node is needed for PCIE hotplugs + * that might happen before finalize_fdt(). + */ + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[RVSERVER_PCIE_ECAM].base); + qemu_fdt_add_subnode(ms->fdt, name); + + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_add_subnode(ms->fdt, "/aliases"); + + /* Pass seed to RNG */ + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); + + riscv_create_fdt_flash(ms->fdt, rvserver_ref_memmap[RVSERVER_FLASH].ba= se, + rvserver_ref_memmap[RVSERVER_FLASH].size / 2); + create_fdt_pmu(s); + +} + +static uint64_t rvserver_reset_syscon_read(void *opaque, hwaddr addr, + unsigned size) +{ + return 0; +} + +static void rvserver_reset_syscon_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + switch (val64) { + case SYSCON_POWEROFF: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + return; + case SYSCON_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + default: + break; + } +} + +static const MemoryRegionOps rvserver_reset_syscon_ops =3D { + .read =3D rvserver_reset_syscon_read, + .write =3D rvserver_reset_syscon_write, + .endianness =3D DEVICE_LITTLE_ENDIAN +}; + +static void rvserver_ref_machine_done(Notifier *notifier, void *data) +{ + RISCVServerRefMachineState *s =3D container_of( + notifier, RISCVServerRefMachineState, machine_done); + const MemMapEntry *memmap =3D rvserver_ref_memmap; + MachineState *machine =3D MACHINE(s); + hwaddr start_addr =3D memmap[RVSERVER_DRAM].base; + target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); + uint64_t fdt_load_addr; + uint64_t kernel_entry =3D 0; + BlockBackend *pflash_blk0; + RISCVBootInfo boot_info; + + /* + * An user provided dtb must include everything, including + * dynamic sysbus devices. Our FDT needs to be finalized. + */ + if (machine->dtb =3D=3D NULL) { + finalize_fdt(s); + } + + riscv_boot_info_init(&boot_info, &s->soc[0]); + + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, + &start_addr, NULL); + + pflash_blk0 =3D pflash_cfi01_get_blk(s->flash[0]); + if (pflash_blk0) { + if (machine->firmware && !strcmp(machine->firmware, "none")) { + /* + * Pflash was supplied but bios is none and not KVM guest, + * let's overwrite the address we jump to after reset to + * the base of the flash. + */ + start_addr =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + } else { + /* + * Pflash was supplied but either KVM guest or bios is not non= e. + * In this case, base of the flash would contain S-mode payloa= d. + */ + riscv_setup_firmware_boot(machine); + kernel_entry =3D rvserver_ref_memmap[RVSERVER_FLASH].base; + } + } + + if (machine->kernel_filename && !kernel_entry) { + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, + firmware_end_addr= ); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NU= LL); + kernel_entry =3D boot_info.image_low_addr; + } + + fdt_load_addr =3D riscv_compute_fdt_addr(memmap[RVSERVER_DRAM].base, + memmap[RVSERVER_DRAM].size, + machine, &boot_info); + + riscv_load_fdt(fdt_load_addr, machine->fdt); + + /* load the reset vector */ + riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, + rvserver_ref_memmap[RVSERVER_MROM].base, + rvserver_ref_memmap[RVSERVER_MROM].size, + kernel_entry, + fdt_load_addr); +} + +static bool rvserver_aclint_allowed(void) +{ + return tcg_enabled() || qtest_enabled(); +} + +static void rvserver_ref_machine_init(MachineState *machine) +{ + const MemMapEntry *memmap =3D rvserver_ref_memmap; + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(machine); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + MemoryRegion *reset_syscon_io =3D g_new(MemoryRegion, 1); + DeviceState *mmio_irqchip, *pcie_irqchip; + int i, base_hartid, hart_count; + int socket_count =3D riscv_socket_count(machine); + int imsic_bits; + + /* Check socket count limit */ + if (RVSERVER_SOCKETS_MAX < socket_count) { + error_report("number of sockets/nodes should be less than %d", + RVSERVER_SOCKETS_MAX); + exit(1); + } + + if (!rvserver_aclint_allowed()) { + error_report("'aclint' is only available with TCG acceleration"); + exit(1); + } + + s->memmap =3D rvserver_ref_memmap; + + /* + * We can't set aia_guests with 'qtest' because it'll skip the + * TCG exclusive init code, setting a blank CPU without RVH + * (among other things). If aia_guests is not zero we'll + * enter riscv_imsic_reset_enter(), which will reset its + * external irqs via qemu_irq_lower(), and qtest will hit an + * assert in riscv_cpu_set_irq() because we don't have RVH + * for handling guest local interrupts. + * + * qtest just want to inspect realized devices using QOM and + * HMP, so do not set aia_guests in that case. + */ + if (qtest_enabled()) { + s->aia_guests =3D 0; + } + + imsic_bits =3D imsic_num_bits(s->aia_guests + 1); + + /* Initialize sockets */ + mmio_irqchip =3D pcie_irqchip =3D NULL; + for (i =3D 0; i < socket_count; i++) { + g_autofree char *soc_name =3D g_strdup_printf("soc%d", i); + + if (!riscv_socket_check_hartids(machine, i)) { + error_report("discontinuous hartids in socket%d", i); + exit(1); + } + + base_hartid =3D riscv_socket_first_hartid(machine, i); + if (base_hartid < 0) { + error_report("can't find hartid base for socket%d", i); + exit(1); + } + + hart_count =3D riscv_socket_hart_count(machine, i); + if (hart_count < 0) { + error_report("can't find hart count for socket%d", i); + exit(1); + } + + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + TYPE_RISCV_HART_ARRAY); + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", + machine->cpu_type, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", + base_hartid, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + hart_count, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); + + /* Per-socket ACLINT MTIMER */ + riscv_aclint_mtimer_create(system_memory, + memmap[RVSERVER_ACLINT].base + i * RISCV_ACLINT_DEFAULT_MT= IMER_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + base_hartid, hart_count, + RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + + /* Per-socket interrupt controller */ + s->irqchip[i] =3D riscv_create_aia(system_memory, true, s->aia_gue= sts, + IMSIC_HART_SIZE(0), + IMSIC_HART_SIZE(imsic_bits), + RVSERVER_IRQCHIP_NUM_SOURCES, + &s->memmap[RVSERVER_APLIC_M], + &s->memmap[RVSERVER_APLIC_S], + &s->memmap[RVSERVER_IMSIC_M], + &s->memmap[RVSERVER_IMSIC_S], + i, base_hartid, hart_count, + RVSERVER_IRQCHIP_NUM_MSIS, + RVSERVER_IRQCHIP_NUM_PRIO_BITS); + + /* Try to use different IRQCHIP instance based device type */ + if (i =3D=3D 0) { + mmio_irqchip =3D s->irqchip[i]; + pcie_irqchip =3D s->irqchip[i]; + } + if (i =3D=3D 1) { + pcie_irqchip =3D s->irqchip[i]; + } + } + + /* register system main memory (actual RAM) */ + memory_region_add_subregion(system_memory, memmap[RVSERVER_DRAM].base, + machine->ram); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv_rvserver_ref_board.mrom", + memmap[RVSERVER_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[RVSERVER_MROM].base, + mask_rom); + + memory_region_init_io(reset_syscon_io, NULL, &rvserver_reset_syscon_op= s, + NULL, "reset_syscon_io", + memmap[RVSERVER_RESET_SYSCON].size); + memory_region_add_subregion(system_memory, + memmap[RVSERVER_RESET_SYSCON].base, + reset_syscon_io); + + riscv_gpex_pcie_init(system_memory, pcie_irqchip, + &rvserver_ref_memmap[RVSERVER_PCIE_ECAM], + &rvserver_ref_memmap[RVSERVER_PCIE_MMIO], + &rvserver_ref_memmap[RVSERVER_PCIE_MMIO_HIGH], + &rvserver_ref_memmap[RVSERVER_PCIE_PIO], + RVSERVER_PCIE_IRQ); + + s->platform_bus_dev =3D riscv_create_platform_bus(mmio_irqchip, + &s->memmap[RVSERVER_PL= ATFORM_BUS], + RVSERVER_PLATFORM_BUS_= IRQ, + RVSERVER_PLATFORM_BUS_= NUM_IRQS); + + serial_mm_init(system_memory, memmap[RVSERVER_UART0].base, + 0, qdev_get_gpio_in(mmio_irqchip, RVSERVER_UART0_IRQ), 399193, + serial_hd(0), DEVICE_LITTLE_ENDIAN); + + sysbus_create_simple("goldfish_rtc", memmap[RVSERVER_RTC].base, + qdev_get_gpio_in(mmio_irqchip, RVSERVER_RTC_IRQ)); + + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + /* Map legacy -drive if=3Dpflash to machine properties */ + pflash_cfi01_legacy_drive(s->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + rvserver_flash_maps(s, system_memory); + + /* load/create device tree */ + if (machine->dtb) { + machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); + if (!machine->fdt) { + error_report("load_device_tree() failed"); + exit(1); + } + } else { + create_fdt(s, memmap); + } + + riscv_create_iommu_sys(mmio_irqchip, s->memmap[RVSERVER_IOMMU_SYS].bas= e, + IOMMU_SYS_IRQ, false); + + s->machine_done.notify =3D rvserver_ref_machine_done; + qemu_add_machine_init_done_notifier(&s->machine_done); +} + +static void rvserver_ref_machine_instance_init(Object *obj) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + s->flash[0] =3D riscv_flash_create(OBJECT(s), "riscv-server-ref.flash0= ", + "pflash0", RVSERVER_FLASH_SECTOR_SIZE= ); + s->flash[1] =3D riscv_flash_create(OBJECT(s), "riscv-server-ref.flash1= ", + "pflash1", RVSERVER_FLASH_SECTOR_SIZE= ); + + s->aia_guests =3D RVSERVER_IRQCHIP_DEFAULT_AIA_GUESTS; +} + +static void rvserver_ref_machine_instance_finalize(Object *obj) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + for (int i =3D 0; i < ARRAY_SIZE(s->flash); i++) { + if (s->flash[i] && !qdev_is_realized(DEVICE(s->flash[i]))) { + object_unref(OBJECT(s->flash[i])); + } + } +} + +static char *rvserver_ref_get_aia_guests(Object *obj, Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + char val[32]; + + sprintf(val, "%d", s->aia_guests); + return g_strdup(val); +} + +static void rvserver_ref_set_aia_guests(Object *obj, const char *val, + Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(obj); + + s->aia_guests =3D atoi(val); + if (s->aia_guests < 0 || s->aia_guests > RVSERVER_IRQCHIP_MAX_GUESTS) { + error_setg(errp, "Invalid number of AIA IMSIC guests"); + error_append_hint(errp, "Valid values be between 0 and %d.\n", + RVSERVER_IRQCHIP_MAX_GUESTS); + } +} + +static const HotplugHandler * +rvserver_machine_get_hotplug_handler(MachineState *ms, DeviceState *dev) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + if (device_is_dynamic_sysbus(mc, dev)) { + return HOTPLUG_HANDLER(ms); + } + + return NULL; +} + +static void rvserver_machine_device_plug_cb(const HotplugHandler *hotplug_= dev, + DeviceState *dev, Error **errp) +{ + RISCVServerRefMachineState *s =3D RISCV_SERVER_REF_MACHINE(hotplug_dev= ); + + if (s->platform_bus_dev) { + MachineClass *mc =3D MACHINE_GET_CLASS(s); + + if (device_is_dynamic_sysbus(mc, dev)) { + platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_d= ev), + SYS_BUS_DEVICE(dev)); + } + } +} + +static void rvserver_ref_machine_class_init(ObjectClass *oc, const void *d= ata) +{ + char str[128]; + MachineClass *mc =3D MACHINE_CLASS(oc); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + TYPE_RISCV_CPU_RVSERVER_REF, + NULL + }; + + /* Note: this is used as /model in the FDT. */ + mc->desc =3D "RISC-V Server Platform Reference Board v1.0"; + mc->init =3D rvserver_ref_machine_init; + mc->max_cpus =3D RVSERVER_CPUS_MAX; + mc->default_cpu_type =3D TYPE_RISCV_CPU_RVSERVER_REF; + mc->valid_cpu_types =3D valid_cpu_types; + mc->pci_allow_0_address =3D true; + mc->default_nic =3D "e1000e"; + mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; + mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; + mc->numa_mem_supported =3D true; + /* platform instead of architectural choice */ + mc->cpu_cluster_has_numa_boundary =3D true; + mc->default_ram_id =3D "riscv_rvserver_ref_board.ram"; + + object_class_property_add_str(oc, "aia-guests", + rvserver_ref_get_aia_guests, + rvserver_ref_set_aia_guests); + sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid valu= e " + "should be between 0 and %d.", RVSERVER_IRQCHIP_MAX_GUEST= S); + object_class_property_set_description(oc, "aia-guests", str); + + assert(!mc->get_hotplug_handler); + mc->get_hotplug_handler =3D rvserver_machine_get_hotplug_handler; + hc->plug =3D rvserver_machine_device_plug_cb; +#ifdef CONFIG_TPM + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); +#endif +} + +static const TypeInfo rvserver_ref_typeinfo =3D { + .name =3D TYPE_RISCV_SERVER_REF_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D rvserver_ref_machine_class_init, + .instance_init =3D rvserver_ref_machine_instance_init, + .instance_finalize =3D rvserver_ref_machine_instance_finalize, + .instance_size =3D sizeof(RISCVServerRefMachineState), + .interfaces =3D (const InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + }, +}; + +static void rvserver_ref_init_register_types(void) +{ + type_register_static(&rvserver_ref_typeinfo); +} + +type_init(rvserver_ref_init_register_types) --=20 2.43.0 From nobody Fri Oct 23 22:37:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790626369341158500 Content-Type: text/plain; charset="utf-8" Add tests for the recently added riscv-server-ref machine: - a new test_opensbi.py test. The idea is to have a quick test that can catch trivial regressions that would prevent OpenSBI to finish; - a new Linux boot "thorough" test that will boot the machine up to the buildroot prompt. - a TPM specific selftest for the riscv-server-ref board. The test will be skipped if there's no 'swtpm' in the host. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Reviewed-by: Nutty Liu Reviewed-by: Alistair Francis Reviewed-by: Sunil V L --- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_server_ref.py | 90 +++++++++++++++++++++ 3 files changed, 96 insertions(+) create mode 100755 tests/functional/riscv64/test_server_ref.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index d1a3e6c2bf..2d22e49efd 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -3,6 +3,7 @@ test_riscv64_timeouts =3D { 'boston' : 120, 'k230' : 120, + 'server_ref' : 120, 'tuxrun' : 120, } =20 @@ -15,6 +16,7 @@ tests_riscv64_system_thorough =3D [ 'endianness', 'boston', 'k230', + 'server_ref', 'sifive_u', 'tt_atlantis', 'tuxrun', diff --git a/tests/functional/riscv64/test_opensbi.py b/tests/functional/ri= scv64/test_opensbi.py index 0f8beb7e7a..367e131164 100755 --- a/tests/functional/riscv64/test_opensbi.py +++ b/tests/functional/riscv64/test_opensbi.py @@ -36,5 +36,9 @@ def test_riscv_virt(self): self.set_machine('virt') self.boot_opensbi() =20 + def test_riscv_server_ref(self): + self.set_machine('riscv-server-ref') + self.boot_opensbi() + if __name__ =3D=3D '__main__': QemuSystemTest.main() diff --git a/tests/functional/riscv64/test_server_ref.py b/tests/functional= /riscv64/test_server_ref.py new file mode 100755 index 0000000000..ad29094dbe --- /dev/null +++ b/tests/functional/riscv64/test_server_ref.py @@ -0,0 +1,90 @@ +#!/usr/bin/env python3 +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +""" +riscv-server-ref board test +""" + +import os +import tempfile +import subprocess + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern +from qemu_test import skipIfMissingCommands + +class RiscvServerRefTest(QemuSystemTest): + """ + Test the riscv-server-ref board + """ + + ASSET_KERNEL =3D Asset( + ('https://github.com/danielhb/qemu-machine-boot/raw/refs/heads/' + 'master/riscv/images/virt64/buildroot/Image'), + '6bacc876c769c1bb6057d2bf549eba67fbe83916e8223f9fe21c8e8fff665a36') + + ASSET_ROOTFS =3D Asset( + ('https://github.com/danielhb/qemu-machine-boot/raw/refs/heads/' + 'master/riscv/images/virt64/buildroot/rootfs.ext2'), + 'f00bb88749f945d80675540a1338bd1ccb226574685a5b6c65ab44027d0411a8') + + def do_test_boot_linux_test(self, tpmstate_dir=3DNone): + self.set_machine('riscv-server-ref') + kernel_path =3D self.ASSET_KERNEL.fetch() + rootfs_path =3D self.ASSET_ROOTFS.fetch() + + self.vm.add_args('-kernel', kernel_path) + self.vm.add_args('-append', 'rw rootwait root=3D/dev/sda') + self.vm.add_args('-drive', + f'file=3D{rootfs_path},format=3Draw,id=3Dhd0,snapshot=3Don,if= =3Dnone') + self.vm.add_args('-device', 'ich9-ahci,id=3Dahci0') + self.vm.add_args('-device', 'ide-hd,drive=3Dhd0,bus=3Dahci0.0') + self.vm.add_args('-netdev', 'user,id=3Dnet0') + self.vm.add_args('-device', 'e1000e,netdev=3Dnet0') + + if tpmstate_dir is not None: + # Note: code taken verbatim from + # tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py + + # We must put the TPM state dir in /tmp/, not the build dir, + # because some distros use AppArmor to lock down swtpm and + # restrict the set of locations it can access files in. + socket =3D os.path.join(tpmstate_dir, 'swtpm-socket') + subprocess.run(['swtpm', 'socket', '-d', '--tpm2', + '--tpmstate', f'dir=3D{tpmstate_dir}', + '--ctrl', f'type=3Dunixio,path=3D{socket}'], + check=3DTrue) + self.vm.add_args('-chardev', f'socket,id=3Dchrtpm,path=3D{sock= et}') + self.vm.add_args('-tpmdev', 'emulator,id=3Dtpm0,chardev=3Dchrt= pm') + self.vm.add_args('-device', 'tpm-tis-device,tpmdev=3Dtpm0') + + self.vm.set_console() + self.vm.launch() + + # Wait for OpenSBI + wait_for_console_pattern(self, 'OpenSBI') + + # Wait for Linux kernel boot + wait_for_console_pattern(self, 'Linux version') + wait_for_console_pattern(self, 'Machine model: RISC-V Server Platf= orm') + + # Test e1000e network card functionality + wait_for_console_pattern(self, 'e1000e') + wait_for_console_pattern(self, 'Network Connection') + + # Wait for boot to complete - system reaches login prompt + wait_for_console_pattern(self, 'Run /sbin/init as init process') + + def test_boot_linux_test(self): + self.do_test_boot_linux_test() + + @skipIfMissingCommands('swtpm') + def test_boot_linux_test_tpm(self): + with tempfile.TemporaryDirectory(prefix=3D"qemu_") as tpmstate_dir: + self.do_test_boot_linux_test(tpmstate_dir) + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.43.0 From nobody Fri Oct 23 22:37:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790626337504158501 Content-Type: text/plain; charset="utf-8" Add documentation for the new riscv-server-ref board. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Sunil V L Reviewed-by: Andrew Jones --- docs/system/riscv/riscv-server-ref.rst | 65 ++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 2 files changed, 66 insertions(+) create mode 100644 docs/system/riscv/riscv-server-ref.rst diff --git a/docs/system/riscv/riscv-server-ref.rst b/docs/system/riscv/ris= cv-server-ref.rst new file mode 100644 index 0000000000..da043ed096 --- /dev/null +++ b/docs/system/riscv/riscv-server-ref.rst @@ -0,0 +1,65 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +RISC-V Server Platform Reference board (``riscv-server-ref``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The RISC-V Server Platform specification `spec`_ defines a standardized +set of hardware and software capabilities that portable system software, +such as OS and hypervisors, can rely on being present in a RISC-V server +platform. This machine aims to emulate this specification, providing +an environment for firmware/OS development and testing. + +`spec`_ is version 1.0 at the introduction of this board. For each new +supported spec version a new versioned board will be added, keeping +"riscv-server-ref" as an alias for the newest version supported. E.g. +for spec version 2.0: + +* riscv-server-ref-1.0 - board that complies with spec version 1.0 +* riscv-server-ref-2.0 - board that complies with spec version 2.0 +* riscv-server-ref - alias for riscv-server-ref-2.0 + +The main features included in the riscv-server-ref board are: + +* IOMMU platform device (riscv-iommu-sys) +* AIA +* No AHCI (can be added via command line) +* No NIC (can be added via command line) +* No virtio mmio bus +* No fw_cfg device +* No ACPI table +* Minimal device tree nodes + +There are multiple ways of using this reference board. The spec compliant= way +is using an EDK2 image and a TPM device. The board was tested with the TPM +device ``tpm-tis`` that uses the external ``swtpm`` emulator. More info o= n how +to use this device can be found in `tpm`_. + +To use this board coupled with the tpm-tis device, first start the ``swtpm= `` +process in a shell (the ``log`` parameter is optional): + +.. code-block:: bash + + $ mkdir /tmp/mytpm1 + $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ + --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ + --tpm2 \ + --log level=3D20 + +And then start QEMU with: + +.. code-block:: bash + + qemu-system-riscv64 -M riscv-server-ref \ + -bios fw_dynamic.bin \ + -kernel EDK2.fd \ + -drive file=3Dnvme_disk.ext2,format=3Draw,id=3Dhd0,if=3Dnone \ + -device nvme,drive=3Dhd0,serial=3Dddaaddaa \ + -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm \ + -device tpm-tis-device,tpmdev=3Dtpm0 \ + -netdev user,id=3Dnet0 -device e1000e,netdev=3Dnet0 \ + -nographic + + +.. _spec: https://github.com/riscv-non-isa/riscv-server-platform +.. _tpm: https://qemu-project.gitlab.io/qemu/specs/tpm.html diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 2639866a3e..74e23fa64c 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -70,6 +70,7 @@ undocumented; you can get a complete list by running riscv/microblaze-v-generic riscv/microchip-icicle-kit riscv/mips + riscv/riscv-server-ref riscv/shakti-c riscv/sifive_u riscv/tt_atlantis --=20 2.43.0