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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625688403158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add architectural state for Sdext Debug Mode: debug_mode, dcsr, dpc and dscratch0/1. Wire up CSR access for dcsr/dpc/dscratch and gate them to Debug Mode (or host debugger access). The Sdext is not fully implemented, so it is disabled by default. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu --- target/riscv/cpu.c | 7 ++ target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 33 ++++++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/machine.c | 22 ++++++ target/riscv/tcg/csr.c | 126 ++++++++++++++++++++++++++++++ 6 files changed, 193 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b..f5490c81ea 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -248,6 +248,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext), ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_INTERNAL_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1094,6 +1095,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) =20 #ifndef CONFIG_USER_ONLY #ifdef CONFIG_TCG + env->debug_mode =3D false; + env->dcsr =3D DCSR_DEBUGVER(4); + env->dpc =3D 0; + env->dscratch[0] =3D 0; + env->dscratch[1] =3D 0; + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5489c564ae..5de8b2ceb4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -510,6 +510,10 @@ struct CPUArchState { =20 /* True if in debugger mode. */ bool debugger; + bool debug_mode; + uint32_t dcsr; + target_ulong dpc; + target_ulong dscratch[2]; =20 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c01050ce2b..3579789a1f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -467,6 +467,39 @@ #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 +#define CSR_DSCRATCH1 0x7b3 + +/* DCSR fields */ +#define DCSR_XDEBUGVER_SHIFT 28 +#define DCSR_XDEBUGVER_MASK (0xfu << DCSR_XDEBUGVER_SHIFT) +#define DCSR_DEBUGVER(val) ((val) << DCSR_XDEBUGVER_SHIFT) +#define DCSR_EXTCAUSE_SHIFT 24 +#define DCSR_EXTCAUSE_MASK (0x7u << DCSR_EXTCAUSE_SHIFT) +#define DCSR_CETRIG BIT(19) +#define DCSR_PELP BIT(18) +#define DCSR_EBREAKVS BIT(17) +#define DCSR_EBREAKVU BIT(16) +#define DCSR_EBREAKM BIT(15) +#define DCSR_EBREAKS BIT(13) +#define DCSR_EBREAKU BIT(12) +#define DCSR_STEPIE BIT(11) +#define DCSR_STOPCOUNT BIT(10) +#define DCSR_STOPTIME BIT(9) +#define DCSR_CAUSE_SHIFT 6 +#define DCSR_CAUSE_MASK (0x7u << DCSR_CAUSE_SHIFT) +#define DCSR_V BIT(5) +#define DCSR_MPRVEN BIT(4) +#define DCSR_NMIP BIT(3) +#define DCSR_STEP BIT(2) +#define DCSR_PRV_MASK 0x3u + +#define DCSR_CAUSE_EBREAK 1 +#define DCSR_CAUSE_TRIGGER 2 +#define DCSR_CAUSE_HALTREQ 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_RESET 5 +#define DCSR_CAUSE_GROUP 6 +#define DCSR_CAUSE_OTHER 7 =20 /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index f91c780299..24f3606f94 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -105,6 +105,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_sdext) BOOL_FIELD(ext_sdtrig) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ed10e65259..0de06e9588 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -327,6 +327,13 @@ static bool debug_needed(void *opaque) return cpu->cfg.debug || cpu->cfg.ext_sdtrig; } =20 +static bool sdext_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_sdext; +} + static int debug_post_load(void *opaque, int version_id) { RISCVCPU *cpu =3D opaque; @@ -361,6 +368,20 @@ static const VMStateDescription vmstate_debug =3D { } }; =20 +static const VMStateDescription vmstate_sdext =3D { + .name =3D "cpu/sdext", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sdext_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_BOOL(env.debug_mode, RISCVCPU), + VMSTATE_UINT32(env.dcsr, RISCVCPU), + VMSTATE_UINTTL(env.dpc, RISCVCPU), + VMSTATE_UINTTL_ARRAY(env.dscratch, RISCVCPU, 2), + VMSTATE_END_OF_LIST() + } +}; + static int riscv_cpu_post_load(void *opaque, int version_id) { RISCVCPU *cpu =3D opaque; @@ -634,6 +655,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_ctr, &vmstate_sstc, &vmstate_mseccfg, + &vmstate_sdext, NULL } }; diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index fe561c7649..09897c59fb 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -3254,6 +3254,126 @@ static RISCVException write_mtval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +#if !defined(CONFIG_USER_ONLY) +static RISCVException sdext(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_sdext) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (!env->debug_mode && !env->debugger) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + +static target_ulong dcsr_visible_mask(CPURISCVState *env) +{ + target_ulong mask =3D (target_ulong)-1; + RISCVCPU *cpu =3D env_archcpu(env); + + if (!riscv_has_ext(env, RVH)) { + mask &=3D ~(DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V); + } + if (!riscv_has_ext(env, RVS)) { + mask &=3D ~DCSR_EBREAKS; + } + if (!riscv_has_ext(env, RVU)) { + mask &=3D ~DCSR_EBREAKU; + } + if (!cpu->cfg.ext_zicfilp) { + mask &=3D ~DCSR_PELP; + } + if (!cpu->cfg.ext_smdbltrp) { + mask &=3D ~DCSR_CETRIG; + } + + return mask; +} + +static RISCVException read_dcsr(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->dcsr & dcsr_visible_mask(env); + return RISCV_EXCP_NONE; +} + +static target_ulong dcsr_writable_mask(CPURISCVState *env) +{ + target_ulong mask =3D DCSR_EBREAKM | DCSR_EBREAKS | DCSR_EBREAKU | + DCSR_STEPIE | DCSR_STOPCOUNT | DCSR_STOPTIME | + DCSR_STEP | DCSR_PRV_MASK; + RISCVCPU *cpu =3D env_archcpu(env); + + mask |=3D DCSR_MPRVEN; + + if (riscv_has_ext(env, RVH)) { + mask |=3D DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V; + } + if (riscv_has_ext(env, RVS)) { + mask |=3D DCSR_EBREAKS; + } + if (riscv_has_ext(env, RVU)) { + mask |=3D DCSR_EBREAKU; + } + if (cpu->cfg.ext_zicfilp) { + mask |=3D DCSR_PELP; + } + if (cpu->cfg.ext_smdbltrp) { + mask |=3D DCSR_CETRIG; + } + + return mask; +} + +static RISCVException write_dcsr(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + target_ulong mask =3D dcsr_writable_mask(env); + target_ulong new_val =3D env->dcsr; + + new_val &=3D ~mask; + new_val |=3D val & mask; + new_val &=3D ~DCSR_XDEBUGVER_MASK; + new_val |=3D DCSR_DEBUGVER(4); + env->dcsr =3D new_val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_dpc(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->dpc & get_xepc_mask(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_dpc(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->dpc =3D val & get_xepc_mask(env); + return RISCV_EXCP_NONE; +} + +static RISCVException read_dscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D (csrno =3D=3D CSR_DSCRATCH1) ? 1 : 0; + + *val =3D env->dscratch[index]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_dscratch(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + int index =3D (csrno =3D=3D CSR_DSCRATCH1) ? 1 : 0; + + env->dscratch[index] =3D val; + return RISCV_EXCP_NONE; +} +#endif /* !CONFIG_USER_ONLY */ + /* Execution environment configuration setup */ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, target_ulong *val) @@ -6498,6 +6618,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata = }, [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore = }, [CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex= t }, +#if !defined(CONFIG_USER_ONLY) + [CSR_DCSR] =3D { "dcsr", sdext, read_dcsr, write_dcsr }, + [CSR_DPC] =3D { "dpc", sdext, read_dpc, write_dpc }, + [CSR_DSCRATCH] =3D { "dscratch0", sdext, read_dscratch, write_dscrat= ch }, + [CSR_DSCRATCH1] =3D { "dscratch1", sdext, read_dscratch, write_dscrat= ch }, +#endif =20 [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, --=20 2.43.0 From nobody Mon Sep 28 23:17:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625664238158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add helpers to enter/leave Debug Mode and to update dpc/dcsr. Model resume without a Debug Module by leaving Debug Mode at cpu_exec_enter and continuing from dpc. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 3 ++ target/riscv/tcg/cpu_helper.c | 88 +++++++++++++++++++++++++++++++++++ target/riscv/tcg/debug.c | 5 ++ target/riscv/tcg/tcg-cpu.c | 14 ++++++ 4 files changed, 110 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5de8b2ceb4..fa253b32d0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -678,6 +678,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, char *riscv_isa_string(RISCVCPU *cpu); int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, + uint32_t cause); +void riscv_cpu_leave_debug_mode(CPURISCVState *env); =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index e78acf37dc..b6b8c2518b 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -132,6 +132,94 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env= , bool virt) #endif } =20 +#ifndef CONFIG_USER_ONLY +static bool riscv_sdext_enabled(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_sdext; +} +#endif + +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, + uint32_t cause) +{ +#ifndef CONFIG_USER_ONLY + if (!riscv_sdext_enabled(env)) { + return; + } + + env->debug_mode =3D true; + env->dpc =3D pc & get_xepc_mask(env); + env->dcsr &=3D ~(DCSR_CAUSE_MASK | DCSR_PRV_MASK | DCSR_V); + env->dcsr |=3D (cause & 0x7) << DCSR_CAUSE_SHIFT; + env->dcsr |=3D env->priv & DCSR_PRV_MASK; + if (env->virt_enabled && riscv_has_ext(env, RVH)) { + env->dcsr |=3D DCSR_V; + } + + if (env_archcpu(env)->cfg.ext_zicfilp) { + if (env->elp) { + env->dcsr |=3D DCSR_PELP; + } else { + env->dcsr &=3D ~DCSR_PELP; + } + env->elp =3D false; + } +#endif +} + +void riscv_cpu_leave_debug_mode(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + uint32_t new_priv; + bool new_virt; + + if (!riscv_sdext_enabled(env)) { + return; + } + + new_priv =3D env->dcsr & DCSR_PRV_MASK; + new_virt =3D riscv_has_ext(env, RVH) && (env->dcsr & DCSR_V); + + if (new_priv > PRV_M) { + new_priv =3D PRV_M; + } + if (new_priv =3D=3D PRV_M) { + new_virt =3D false; + } + + if (new_priv =3D=3D PRV_S && !riscv_has_ext(env, RVS)) { + new_priv =3D PRV_M; + new_virt =3D false; + } else if (new_priv =3D=3D PRV_U && !riscv_has_ext(env, RVU)) { + new_priv =3D riscv_has_ext(env, RVS) ? PRV_S : PRV_M; + new_virt =3D false; + } + + env->debug_mode =3D false; + riscv_cpu_set_mode(env, new_priv, new_virt); + + if (env_archcpu(env)->cfg.ext_zicfilp) { + env->elp =3D cpu_get_fcfien(env) && (env->dcsr & DCSR_PELP); + env->dcsr &=3D ~DCSR_PELP; + } + + if (new_priv !=3D PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, 0); + } + + if (env_archcpu(env)->cfg.ext_smdbltrp && new_priv !=3D PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 0); + } + if (env_archcpu(env)->cfg.ext_ssdbltrp && (new_priv =3D=3D PRV_U || ne= w_virt)) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_SDT, 0); + if (new_virt && new_priv =3D=3D PRV_U) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } +#endif +} + + /* * Returns the effective PMM field. * diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index e4d719a1da..2537515f54 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -973,6 +973,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 + /* Triggers must not match or fire while in Debug Mode. */ + if (env->debug_mode) { + return; + } + if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { do_trigger_action(env, DBG_ACTION_BP); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b68160af83..959a1e89c8 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -269,6 +269,19 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_= idx, } return extract64(result, 0, 64 - pm_len); } + +static void riscv_cpu_exec_enter(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (!cpu->cfg.ext_sdext || !env->debug_mode) { + return; + } + target_ulong pc =3D env->dpc; + riscv_cpu_leave_debug_mode(env); + env->pc =3D pc; +} #endif =20 const TCGCPUOps riscv_tcg_ops =3D { @@ -285,6 +298,7 @@ const TCGCPUOps riscv_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D riscv_cpu_tlb_fill, .pointer_wrap =3D riscv_pointer_wrap, + .cpu_exec_enter =3D riscv_cpu_exec_enter, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .cpu_exec_halt =3D riscv_cpu_has_work, .cpu_exec_reset =3D cpu_reset, --=20 2.43.0 From nobody Mon Sep 28 23:17:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625666287158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add DRET decode/translate and a helper to leave Debug Mode and return to dpc. Executing DRET outside Debug Mode raises illegal instruction. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 18 ++++++++++++++++++ target/riscv/tcg/op_helper.c | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index aab92bf132..a790595b40 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -132,6 +132,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(dret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index aa02dae3c9..46b00411ff 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -118,6 +118,7 @@ sctrclr 000100000100 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 +dret 0111101 10010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma =20 diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index ebbbb01179..f1a042d57f 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -125,6 +125,24 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_dret(DisasContext *ctx, arg_dret *a) +{ +#ifndef CONFIG_USER_ONLY + if (!ctx->cfg_ptr->ext_sdext) { + return false; + } + decode_save_opc(ctx, 0); + translator_io_start(&ctx->base); + gen_update_pc(ctx, 0); + gen_helper_dret(cpu_pc, tcg_env); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_mnret(DisasContext *ctx, arg_mnret *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b67c7718db..dbdaa64f5e 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -508,6 +508,24 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } =20 +target_ulong helper_dret(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +#else + target_ulong retpc; + + if (!riscv_cpu_cfg(env)->ext_sdext || !env->debug_mode) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + retpc =3D env->dpc & get_xepc_mask(env); + riscv_cpu_leave_debug_mode(env); + return retpc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625670412158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Route EBREAK via helper_sdext_ebreak. If Sdext is enabled and the matching dcsr.ebreak* bit is set, enter Debug Mode with cause=3Debreak and stop with EXCP_DEBUG. Otherwise keep the normal breakpoint trap. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu --- target/riscv/helper.h | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 6 ++++ target/riscv/tcg/op_helper.c | 34 +++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a790595b40..533dee1765 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -142,6 +142,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 /* Hypervisor functions */ diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index f1a042d57f..e22df6fbe7 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -68,9 +68,15 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *= a) if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D 0= x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); } else { +#ifndef CONFIG_USER_ONLY + gen_update_pc(ctx, 0); + gen_helper_sdext_ebreak(tcg_env, tcg_constant_tl(ebreak_addr)); + ctx->base.is_jmp =3D DISAS_NORETURN; +#else tcg_gen_st_i64(tcg_constant_i64(ebreak_addr), tcg_env, offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_BREAKPOINT); +#endif } return true; } diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index dbdaa64f5e..53e9eb445f 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -526,6 +526,40 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) +{ + CPUState *cs =3D env_cpu(env); + bool enter_debug =3D false; + + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode) { + if (env->virt_enabled) { + if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKVS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKVU; + } + } else { + if (env->priv =3D=3D PRV_M) { + enter_debug =3D env->dcsr & DCSR_EBREAKM; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625630447158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Use a TB flag when dcsr.step is set (and we are not in Debug Mode). When the flag is on, build 1-insn TBs and do not chain to the next TB. Add a TB-exit helper that enters Debug Mode with cause=3Dstep and sets dpc to the next pc, then stops with EXCP_DEBUG. If dcsr.stepie is 0, do not take interrupts while stepping. Treat WFI as a nop so the hart does not sleep during a step. PS: This patch references Max Chou's handling of ext_tb_flags. https://lore.kernel.org/qemu-devel/20260108132631.9429-6-max.chou@sifive.co= m/ Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu --- include/exec/translation-block.h | 4 ++-- target/riscv/cpu.h | 2 ++ target/riscv/helper.h | 1 + target/riscv/tcg/cpu_helper.c | 6 ++++++ target/riscv/tcg/op_helper.c | 20 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 5 +++++ target/riscv/tcg/translate.c | 15 +++++++++++++-- 7 files changed, 49 insertions(+), 4 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 40cc699031..ee15608c89 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -64,8 +64,8 @@ struct TranslationBlock { * x86: the original user, the Code Segment virtual base, * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). - * riscv: an extension of tb->flags, + * sparc: the next pc of the instruction queue (for delay slots), + * riscv: an extension of tb->flags. */ uint64_t cs_base; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fa253b32d0..4b56cacc86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -762,6 +762,8 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) +/* sdext single-step needs a TB flag to build 1-insn TBs */ +FIELD(EXT_TB_FLAGS, SDEXT_STEP, 34, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 533dee1765..32225471bc 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -142,6 +142,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_1(sdext_step, void, env) DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index b6b8c2518b..ffa9e78cc1 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -503,6 +503,12 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP) && !(env->dcsr & DCSR_STEPIE)) { + return false; + } + int interruptno =3D riscv_cpu_local_irq_pending(env); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index 53e9eb445f..dc76055b80 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -526,6 +526,22 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_step(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + CPUState *cs =3D env_cpu(env); + + if (!riscv_cpu_cfg(env)->ext_sdext || env->debug_mode || + !(env->dcsr & DCSR_STEP)) { + return; + } + + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_STEP); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); +#endif +} + void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) { CPUState *cs =3D env_cpu(env); @@ -658,6 +674,10 @@ void helper_wfi(CPURISCVState *env) (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW))))= { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP)) { + return; + } cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; cpu_loop_exit(cs); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 959a1e89c8..16d26cee5c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -196,6 +196,11 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *= cs) ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_= ext); ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, BIG_ENDIAN, mo_endian_env(env) =3D=3D MO_BE); +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sdext && !env->debug_mode && (env->dcsr & DCSR_STEP))= { + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, SDEXT_STEP, 1); + } +#endif =20 return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index cce3b6dc72..d6b1f9bfee 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -115,6 +115,8 @@ typedef struct DisasContext { bool ztso; /* Use icount trigger for native debug */ bool itrigger; + /* Enter Debug Mode after next instruction (sdext single-step). */ + bool sdext_step; /* FRM is known to contain a valid value. */ bool frm_valid; bool insn_start_updated; @@ -289,6 +291,9 @@ static void lookup_and_goto_ptr(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_lookup_and_goto_ptr(); } @@ -299,6 +304,9 @@ static void exit_tb(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_exit_tb(NULL, 0); } @@ -312,7 +320,8 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_= slot_idx, * Under itrigger, instruction executes one by one like singlestep, * direct block chain benefits will be small. */ - if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { + if (translator_use_goto_tb(&ctx->base, dest) && + !ctx->itrigger && !ctx->sdext_step) { /* * For pcrel, the pc must always be up-to-date on entry to * the linked TB, so that it can use simple additions for all @@ -1380,6 +1389,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->bcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); ctx->fcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); + ctx->sdext_step =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, SDEXT_STEP); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; @@ -1432,7 +1442,8 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) =20 /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { - if (ctx->itrigger || !translator_is_same_page(&ctx->base, ctx->bas= e.pc_next)) { + if (ctx->itrigger || ctx->sdext_step || + !translator_is_same_page(&ctx->base, ctx->base.pc_next)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } else { unsigned page_ofs =3D ctx->base.pc_next & ~TARGET_PAGE_MASK; --=20 2.43.0 From nobody Mon Sep 28 23:17:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625678440158500 Content-Type: text/plain; charset="utf-8" From: Chao Liu RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Allow mcontrol/mcontrol6 action=3D1 when Sdext is enabled. When such a trigger hits, enter Debug Mode with cause=3Dtrigger and stop with EXCP_DEBUG. Also report inst-count triggers in tinfo and read their action field. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/tcg/debug.c | 54 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 2537515f54..aaf2dca17e 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -34,6 +34,7 @@ #include "exec/watchpoint.h" #include "system/cpu-timers.h" #include "exec/icount.h" +#include "accel/tcg/cpu-loop.h" =20 /* * The following M-mode trigger CSRs are implemented: @@ -117,6 +118,8 @@ static trigger_action_t get_trigger_action(CPURISCVStat= e *env, action =3D (tdata1 & TYPE6_ACTION) >> 12; break; case TRIGGER_TYPE_INST_CNT: + action =3D tdata1 & ITRIGGER_ACTION; + break; case TRIGGER_TYPE_INT: case TRIGGER_TYPE_EXCP: case TRIGGER_TYPE_EXT_SRC: @@ -287,6 +290,7 @@ static target_ulong textra_validate(CPURISCVState *env,= target_ulong tdata3) =20 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_ind= ex) { + CPUState *cs =3D env_cpu(env); trigger_action_t action =3D get_trigger_action(env, trigger_index); =20 switch (action) { @@ -296,6 +300,21 @@ static void do_trigger_action(CPURISCVState *env, targ= et_ulong trigger_index) riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); break; case DBG_ACTION_DBG_MODE: + if (!env_archcpu(env)->cfg.ext_sdext) { + qemu_log_mask(LOG_GUEST_ERROR, + "trigger action=3Ddebug mode requires Sdext\n"); + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_TRIGGER); + /* + * If this came from the Trigger Module's CPU breakpoint/watchpoin= t, + * we're already returning via EXCP_DEBUG. Otherwise, stop now. + */ + if (cs->exception_index !=3D EXCP_DEBUG) { + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); + } + break; case DBG_ACTION_TRACE0: case DBG_ACTION_TRACE1: case DBG_ACTION_TRACE2: @@ -448,6 +467,7 @@ static target_ulong type2_mcontrol_validate(CPURISCVSta= te *env, { target_ulong val; uint32_t size; + uint32_t action; =20 /* validate the generic part first */ val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); @@ -455,11 +475,25 @@ static target_ulong type2_mcontrol_validate(CPURISCVS= tate *env, /* validate unimplemented (always zero) bits */ warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); - warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); =20 + action =3D (ctrl & TYPE2_ACTION) >> 12; + if (action =3D=3D DBG_ACTION_BP) { + val |=3D ctrl & TYPE2_ACTION; + } else if (action =3D=3D DBG_ACTION_DBG_MODE) { + if (env_archcpu(env)->cfg.ext_sdext) { + val |=3D ctrl & TYPE2_ACTION; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "trigger action=3Ddebug mode requires Sdext\n"); + } + } else { + qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n", + action); + } + /* validate size encoding */ size =3D type2_breakpoint_size(env, ctrl); if (access_size[size] =3D=3D -1) { @@ -576,6 +610,7 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, { target_ulong val; uint32_t size; + uint32_t action; =20 /* validate the generic part first */ val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6); @@ -583,7 +618,6 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, /* validate unimplemented (always zero) bits */ warn_always_zero_bit(ctrl, TYPE6_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain"); - warn_always_zero_bit(ctrl, TYPE6_ACTION, "action"); warn_always_zero_bit(ctrl, TYPE6_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE6_HIT, "hit"); =20 @@ -593,6 +627,21 @@ static target_ulong type6_mcontrol6_validate(CPURISCVS= tate *env, warn_always_zero_bit(ctrl, TYPE6_TIMING_0_13, "timing"); } =20 + action =3D (ctrl & TYPE6_ACTION) >> 12; + if (action =3D=3D DBG_ACTION_BP) { + val |=3D ctrl & TYPE6_ACTION; + } else if (action =3D=3D DBG_ACTION_DBG_MODE) { + if (env_archcpu(env)->cfg.ext_sdext) { + val |=3D ctrl & TYPE6_ACTION; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "trigger action=3Ddebug mode requires Sdext\n"); + } + } else { + qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n", + action); + } + /* validate size encoding */ size =3D extract32(ctrl, 16, 4); if (access_size[size] =3D=3D -1) { @@ -959,6 +1008,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) target_ulong tinfo_csr_read(CPURISCVState *env) { target_ulong val =3D BIT(TRIGGER_TYPE_AD_MATCH) | + BIT(TRIGGER_TYPE_INST_CNT) | BIT(TRIGGER_TYPE_AD_MATCH6); =20 if (debug_trigger_version_1_0(env)) { --=20 2.43.0 From nobody Mon Sep 28 23:17:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790625660078158501 Content-Type: text/plain; charset="utf-8" Adding proper TCG automated tests to sdext CSRs requires enabling gdbstub support for riscv64, which we don't have, since the nature of the CSRs added is that they run in a higher privilege than M mode. DCSR has bits to allow for context switching from other modes to Debug mode, but those bits must be set via an external entity (e.g. gdb) beforehand. What we can do for now is a "negative" TCG test to ensure that we'll throw illegal insn traps when trying to write sdext CSRs in machine mode. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- tests/tcg/riscv64/system/meson.build | 8 +++ tests/tcg/riscv64/test-sdext-sigill.S | 83 +++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S diff --git a/tests/tcg/riscv64/system/meson.build b/tests/tcg/riscv64/syste= m/meson.build index 2aca68e078..8f920815cb 100644 --- a/tests/tcg/riscv64/system/meson.build +++ b/tests/tcg/riscv64/system/meson.build @@ -62,6 +62,14 @@ tests +=3D { } } =20 +tests +=3D { + 'test-sdext-sigill.S': { + 'exe_name': 'test-sdext-sigill', + 'cflags': cflags + ['-march=3Drv64gcv'], + 'qemu_args': ['-cpu', 'rv64,sdtrig=3Dtrue,sdext=3Dtrue', qemu_args], + } +} + if 'qemu-system-riscv64' in emulators tcg_tests +=3D { 'riscv64-softmmu': { diff --git a/tests/tcg/riscv64/test-sdext-sigill.S b/tests/tcg/riscv64/test= -sdext-sigill.S new file mode 100644 index 0000000000..80a6c06465 --- /dev/null +++ b/tests/tcg/riscv64/test-sdext-sigill.S @@ -0,0 +1,83 @@ +/* + * RISC-V sdext extension "SIGILL" test: check if sdext CSRs + * and 'dret' will throw SIGILLs outside of Debug Mode. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +.equ CSR_DCSR, 0x7b0 +.equ CSR_DPC, 0x7b1 +.equ CSR_DSCRATCH0, 0x7b2 + + .option norvc + .text + + .global _start + +_start: + la t0, trap_handler + csrw mtvec, t0 + + dret + j _fail + + li t0, 1 + csrw CSR_DPC, t0 + j _fail + + li t0, 1 + csrw CSR_DSCRATCH0, t0 + j _fail + + li t0, 1 + csrw CSR_DCSR, t0 + j _fail + + li a0, 0 + j _exit + +_fail: + li a0, 1 + +/* Exit through the semihosting SYS_EXIT_EXTENDED call with a0 as the code= . */ +_exit: + la a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + + .balign 4 +trap_handler: + csrr t4, mcause + la t5, trap_mcause + sd t4, 0(t5) + csrr t4, mtval + la t5, trap_mtval + sd t4, 0(t5) + csrr t4, mepc + + /* + * Skip 2 insns (8 increment in mepc) to skip both the + * insn that caused the trap and the "j _fail" insn + * that follows it. + */ + addi t4, t4, 8 + csrw mepc, t4 + mret + + .data + .balign 8 +semiargs: + .space 16 +trap_mcause: + .space 8 +trap_mtval: + .space 8 --=20 2.43.0