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Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Tested-by: Mikulas Patocka --- accel/tcg/cpu-exec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5226cfb7650..f4428e9f7b7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -566,7 +566,8 @@ void cpu_exec_step_atomic(CPUState *cpu) /* Execute in a serial context. */ s.cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ - s.cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + s.cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_NOIRQ | 1; + /* * No need to check_for_breakpoints here. * We only arrive in cpu_exec_step_atomic after beginning execution --=20 2.53.0 From nobody Sat Sep 26 19:16:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790201281; cv=none; d=zohomail.com; s=zohoarc; b=Rx0p7ZXCng0ieVz+i5SPPEY6hTwvZsaTMkpDO6yc6TiZw7DBa7beOdlyfxv/vkky4/QbBkCB1PcvvQgne+jOPWgLjUCHbAINZvHTZWfdae2W71RPJOBKpZt5oLS5TcBv2RVSckSYzS21z1WONaTSZ/DGwo2LahRUXkzlELmX0sI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790201281; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jIJSx8eVwK44OkARebMcKW855hARnx67VTeEo6/YBh8=; b=TZvp8EmV/b4E08Yx3FfnnJMSiM/KtUTp2qOmqyodpy22rZJQvQ/hnbrIaqkUvo5u5Ej4yVke/TpG8Frm3IAguKCuU/helaQKk/iVxhjQCGIwjpEB96FdzrN82m0/Fta460kQni2IH21u4QnGQe3AkpA9HrIWwE/8/Y0fmtIGUzw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790201281597330.17017588254157; Wed, 23 Sep 2026 15:08:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9V7H-0007Rq-07; Wed, 23 Sep 2026 18:07:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9V7G-0007RQ-3a for qemu-devel@nongnu.org; Wed, 23 Sep 2026 18:07:02 -0400 Received: from mail-pj2-x11.google.com ([2607:f8b0:4864:39::11]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9V7D-0005nF-Ko for qemu-devel@nongnu.org; Wed, 23 Sep 2026 18:07:01 -0400 Received: by mail-pj2-x11.google.com with SMTP id 98e67ed59e1d1-396ccdaea76so653248a91.0 for ; Wed, 23 Sep 2026 15:06:59 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Wed, 23 Sep 2026 15:06:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mpatocka@redhat.com, qemu-stable@nongnu.org Subject: [PATCH v4 2/3] target/sh4: Replace TB_FLAG_GUSA_EXCLUSIVE with CF_STEP_ATOMIC Date: Wed, 23 Sep 2026 15:06:53 -0700 Message-ID: <20260923220654.127167-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923220654.127167-1-richard.henderson@linaro.org> References: <20260923220654.127167-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1790201283532158500 Content-Type: text/plain; charset="utf-8" There was a complex bug with gUSA wherein: * decode_gusa calls gen_restart_exclusive * gen_restart_exclusive generates code that sets TB_FLAG_GUSA_EXCLUSIVE and generates a call to helper_exclusive * when the code is executed, TB_FLAG_GUSA_EXCLUSIVE is set * helper_exclusive calls cpu_loop_exit_atomic, this makes cpu_exec exit with EXCP_ATOMIC * we go to cpu_loop, we execute cpu_exec_step_atomic * suppose that exit request is set, cpu_exec_step_atomic does nothing, it leaves the CPU in the same state as it was before * we go back to cpu_loop * suppose that no signal is delivered, so the gUSA is not rewound * cpu_loop goes to cpu_exec * there is one difference - now, TB_FLAG_GUSA_EXCLUSIVE is set and it was clear before - so cpu_exec will not use the TB that calls helper_exclusive, it will instead use the TB that performs the atomic operation (both of these TBs have the same PC, they only differ in flag= s) * the TB that performs the atomic operation is executed inside cpu_exec =3D> race condition Fix the bug by managing the "are we in cpu_exec_step_atomic" flag from cpu_exec_step_atomic itself, rather from the translator. Cc: qemu-stable@nongnu.org Fixes: 4bfa602bc22 ("target/sh4: Handle user-space atomics") Reported-by: Mikulas Patocka Signed-off-by: Richard Henderson Tested-by: Mikulas Patocka --- include/exec/translation-block.h | 1 + target/sh4/cpu.h | 6 ++---- accel/tcg/cpu-exec.c | 3 ++- target/sh4/translate.c | 34 +++++++++++++++++++++++--------- 4 files changed, 30 insertions(+), 14 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 40cc6990318..7c42c57cca6 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -84,6 +84,7 @@ struct TranslationBlock { #define CF_NOIRQ 0x00010000 /* Generate an uninterruptible TB */ #define CF_PCREL 0x00020000 /* Opcodes in TB are PC-relative */ #define CF_BP_PAGE 0x00040000 /* Breakpoint present in code page */ +#define CF_STEP_ATOMIC 0x00080000 /* Running in cpu_exec_step_atomic */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 33027023763..6984bb462fb 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -84,8 +84,7 @@ #define TB_FLAG_DELAY_SLOT_RTE (1 << 2) #define TB_FLAG_PENDING_MOVCA (1 << 3) #define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */ -#define TB_FLAG_GUSA_EXCLUSIVE (1 << 12) -#define TB_FLAG_UNALIGN (1 << 13) +#define TB_FLAG_UNALIGN (1 << 12) #define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */ #define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */ #define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */ @@ -96,8 +95,7 @@ #define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \ TB_FLAG_DELAY_SLOT_COND | \ TB_FLAG_DELAY_SLOT_RTE) -#define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \ - TB_FLAG_GUSA_EXCLUSIVE) +#define TB_FLAG_GUSA_MASK (0xff << TB_FLAG_GUSA_SHIFT) #define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \ TB_FLAG_FPSCR_SZ | \ TB_FLAG_FPSCR_FR) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f4428e9f7b7..5b4bca5084f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -566,7 +566,8 @@ void cpu_exec_step_atomic(CPUState *cpu) /* Execute in a serial context. */ s.cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ - s.cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_NOIRQ | 1; + s.cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | + CF_NOIRQ | CF_STEP_ATOMIC | 1; =20 /* * No need to check_for_breakpoints here. diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 373950fd662..c15c0802f78 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -47,6 +47,9 @@ typedef struct DisasContext { uint16_t opcode; =20 bool has_movcal; +#ifdef CONFIG_USER_ONLY + bool in_gusa_exclusive; +#endif } DisasContext; =20 #if defined(CONFIG_USER_ONLY) @@ -220,7 +223,11 @@ static inline void gen_save_cpu_state(DisasContext *ct= x, bool save_pc) =20 static inline bool use_exit_tb(DisasContext *ctx) { - return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) !=3D 0; +#ifdef CONFIG_USER_ONLY + return ctx->in_gusa_exclusive; +#else + return false; +#endif } =20 static bool use_goto_tb(DisasContext *ctx, vaddr dest) @@ -273,7 +280,8 @@ static void gen_conditional_jump(DisasContext *ctx, vad= dr dest, TCGLabel *l1 =3D gen_new_label(); TCGCond cond_not_taken =3D jump_if_true ? TCG_COND_EQ : TCG_COND_NE; =20 - if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { +#ifdef CONFIG_USER_ONLY + if (ctx->in_gusa_exclusive) { /* When in an exclusive region, we must continue to the end. Therefore, exit the region on a taken branch, but otherwise fall through to the next instruction. */ @@ -286,6 +294,7 @@ static void gen_conditional_jump(DisasContext *ctx, vad= dr dest, ctx->base.is_jmp =3D DISAS_NEXT; return; } +#endif =20 gen_save_cpu_state(ctx, false); tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); @@ -304,7 +313,8 @@ static void gen_delayed_conditional_jump(DisasContext *= ctx) tcg_gen_mov_i32(ds, cpu_delayed_cond); tcg_gen_discard_i32(cpu_delayed_cond); =20 - if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { +#ifdef CONFIG_USER_ONLY + if (ctx->in_gusa_exclusive) { /* When in an exclusive region, we must continue to the end. Therefore, exit the region on a taken branch, but otherwise fall through to the next instruction. */ @@ -318,6 +328,7 @@ static void gen_delayed_conditional_jump(DisasContext *= ctx) ctx->base.is_jmp =3D DISAS_NEXT; return; } +#endif =20 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1); gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); @@ -1793,16 +1804,18 @@ static void decode_opc(DisasContext * ctx) /* go out of the delay slot */ ctx->envflags &=3D ~TB_FLAG_DELAY_SLOT_MASK; =20 +#ifdef CONFIG_USER_ONLY /* When in an exclusive region, we must continue to the end for conditional branches. */ - if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE - && old_flags & TB_FLAG_DELAY_SLOT_COND) { + if (ctx->in_gusa_exclusive && old_flags & TB_FLAG_DELAY_SLOT_COND)= { gen_delayed_conditional_jump(ctx); return; } + /* Otherwise this is probably an invalid gUSA region. Drop the GUSA bits so the next TB doesn't see them. */ ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; +#endif =20 tcg_gen_movi_i32(cpu_flags, ctx->envflags); if (old_flags & TB_FLAG_DELAY_SLOT_COND) { @@ -1820,7 +1833,6 @@ static void decode_opc(DisasContext * ctx) */ static void gen_restart_exclusive(DisasContext *ctx) { - ctx->envflags |=3D TB_FLAG_GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -2208,11 +2220,13 @@ static void sh4_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) int backup =3D sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8); int max_insns =3D (pc_end - pc) / 2; =20 + ctx->in_gusa_exclusive =3D ctx->base.tb->cflags & CF_STEP_ATOMIC; + if (pc !=3D pc_end + backup || max_insns < 2) { /* This is a malformed gUSA region. Don't do anything special, since the interpreter is likely to get confused. */ ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; - } else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) { + } else if (ctx->in_gusa_exclusive) { /* Regardless of single-stepping or the end of the page, we must complete execution of the gUSA region while holding the exclusive lock. */ @@ -2246,7 +2260,7 @@ static void sh4_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) =20 #ifdef CONFIG_USER_ONLY if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK) - && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) { + && !ctx->in_gusa_exclusive) { /* * We're in an gUSA region, and we have not already fallen * back on using an exclusive region. Attempt to parse the @@ -2276,10 +2290,12 @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) { +#ifdef CONFIG_USER_ONLY + if (ctx->in_gusa_exclusive) { /* Ending the region of exclusivity. Clear the bits. */ ctx->envflags &=3D ~TB_FLAG_GUSA_MASK; } +#endif =20 switch (ctx->base.is_jmp) { case DISAS_STOP: --=20 2.53.0 From nobody Sat Sep 26 19:16:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790201285; cv=none; d=zohomail.com; s=zohoarc; b=LhwH7X6GQVznq0oMRjUmWQbOtMwsG0kcvBXW2geuyHtRl2TJpmP8ralMUoEorTZmxStWpk1qBVJKm3MF/19fCSXwnDHdzO7WC/np51HEhjXQIzC0p7tJygijKS1RpGP0Gj/cwTYPO5BvTEFe7pcq0CXQ53CZ2I/WMroSEwiEHEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790201285; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zAyp949LNBvVK79JDJyQf1Lb+4iiscDMV5iiqGpwpfM=; b=Az4hdI1CGpouGCN+dcuzVsEHXm3dF41YqWIEXX8+B5I0tPXb7i3Of7kS7SzyHci+U48VvDy6FKsaU1NUdJQBAWUMyGrU5W3cMmJd1YDqBPChArCkWl/UbkTcaNweC3IqKVg2AprKyIkKIMm22YteLr0FaFjxaL7yJ4WOm9fLwwU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790201285808314.0414146114131; Wed, 23 Sep 2026 15:08:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9V7H-0007SF-EY; Wed, 23 Sep 2026 18:07:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9V7G-0007RS-5Z for qemu-devel@nongnu.org; Wed, 23 Sep 2026 18:07:02 -0400 Received: from mail-pj2-x10.google.com ([2607:f8b0:4864:39::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9V7E-0005nP-NC for qemu-devel@nongnu.org; Wed, 23 Sep 2026 18:07:01 -0400 Received: by mail-pj2-x10.google.com with SMTP id 98e67ed59e1d1-398c066106cso872995a91.1 for ; Wed, 23 Sep 2026 15:07:00 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Signed-off-by: Richard Henderson Tested-by: Mikulas Patocka --- target/sh4/translate.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index c15c0802f78..5729a757f19 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -221,20 +221,8 @@ static inline void gen_save_cpu_state(DisasContext *ct= x, bool save_pc) } } =20 -static inline bool use_exit_tb(DisasContext *ctx) -{ -#ifdef CONFIG_USER_ONLY - return ctx->in_gusa_exclusive; -#else - return false; -#endif -} - static bool use_goto_tb(DisasContext *ctx, vaddr dest) { - if (use_exit_tb(ctx)) { - return false; - } return translator_use_goto_tb(&ctx->base, dest); } =20 @@ -246,11 +234,7 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb= _slot_idx, vaddr dest) tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx); } else { tcg_gen_movi_i32(cpu_pc, dest); - if (use_exit_tb(ctx)) { - tcg_gen_exit_tb(NULL, 0); - } else { - tcg_gen_lookup_and_goto_ptr(); - } + tcg_gen_lookup_and_goto_ptr(); } ctx->base.is_jmp =3D DISAS_NORETURN; } @@ -262,11 +246,7 @@ static void gen_jump(DisasContext * ctx) delayed jump as immediate jump are conditinal jumps */ tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); tcg_gen_discard_i32(cpu_delayed_pc); - if (use_exit_tb(ctx)) { - tcg_gen_exit_tb(NULL, 0); - } else { - tcg_gen_lookup_and_goto_ptr(); - } + tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp =3D DISAS_NORETURN; } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); --=20 2.53.0