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Do that now. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7f7c208ba12..ae5af014960 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1369,7 +1369,6 @@ static int probe_access_internal(CPUState *cpu, vaddr= addr, uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); vaddr page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; - bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(cpu); CPUTLBEntryFull *full; =20 if (!tlb_hit_page(tlb_addr, page_addr)) { @@ -1399,16 +1398,13 @@ static int probe_access_internal(CPUState *cpu, vad= dr addr, =20 *pfull =3D full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags |=3D full->slow_flags[access_type]; - - /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGN= ED)) - || (access_type !=3D MMU_INST_FETCH && force_mmio)) { - *phost =3D NULL; - return TLB_MMIO; + if (check_mem_cbs && cpu_plugin_mem_cbs_enabled(cpu)) { + flags |=3D TLB_FORCE_SLOW; } =20 - /* Everything else is RAM. */ - *phost =3D (void *)((uintptr_t)addr + entry->addend); + *phost =3D (flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGNE= D) + ? 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Cc: qemu-stable@nongnu.org Fixes: 24b5e0fdb543 ("include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slo= w flags") Reviewed-by: Richard Henderson Signed-off-by: Anton Blanchard Message-ID: <20260916123958.1884903-1-antonb@tenstorrent.com> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ae5af014960..dc83f3bad8c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1589,7 +1589,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int= mmu_idx, data->phys_addr =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); =20 /* We must have an iotlb entry for MMIO */ - if (tlb_addr & TLB_MMIO) { + if (full->slow_flags[access_type] & TLB_MMIO) { MemoryRegionSection *section =3D full->section; data->is_io =3D true; data->mr =3D section->mr; --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195746; cv=none; d=zohomail.com; s=zohoarc; b=L0bt1aRkSwkQMUne6j3F3xQViQveW6tqimS0Xbf2hhrm1THEcBcN67pLPnTlU2qXNFLcxQ1zDJrH2O7lcM5zFEMX43CAd7NLAO0xNN+jozLjyxZtndQbbMctcAmqNj7XA3vMRs17L1mLQUqfpW/tg+VyJ3SlGqOAu1RN3EfQPxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195746; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r/EOfq5GSU111ySEUtewdGy4DqHR5fHEKzlTJljRbrI=; b=Xkm5a6gfpURI7TPSF02vi2yK/4i5V4hkU9eKWKsutC2Kmh95cSROe2teOLj/d/DOoJc928e+AKWRXRq+hdax4YM25hyZ6twVhGz2OM9FCbcy3a8XTGkqdGsboHql7ytOe6HE4ds+28vPv6EZHMd6mGw+yW8q5gTsU3i9jhJJMHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179019574617915.661799527524977; Wed, 23 Sep 2026 13:35:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9TgV-0008Di-Lp; Wed, 23 Sep 2026 16:35:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9Tg3-00089P-31 for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:55 -0400 Received: from mail-pz2-x10.google.com ([2607:f8b0:4864:3b::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg1-0004zD-8T for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:50 -0400 Received: by mail-pz2-x10.google.com with SMTP id d2e1a72fcca58-86b90133ae8so778375b3a.1 for ; Wed, 23 Sep 2026 13:34:47 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Nothing reads it in a user-only build. There is no memory-mapped I/O in linux-user, and every reader is in system_ss: cputlb.c, watchpoint.c, icount-common.c and tcg-accel-ops-icount.c. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Matt Turner Signed-off-by: Richard Henderson Message-ID: <20260901034808.3524945-4-mattst88@gmail.com> --- accel/tcg/translator.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 57daded60ff..e9943006947 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -21,12 +21,14 @@ #include "disas/disas.h" #include "tb-internal.h" =20 +#ifndef CONFIG_USER_ONLY static void set_can_do_io(DisasContextBase *db, bool val) { QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) !=3D 1); tcg_gen_st8_i32(tcg_constant_i32(val), tcg_env, offsetof(CPUState, neg.can_do_io) - sizeof(CPUState)); } +#endif =20 bool translator_io_start(DisasContextBase *db) { @@ -125,8 +127,10 @@ void translator_loop(CPUState *cpu, TranslationBlock *= tb, int *max_insns, { uint32_t cflags =3D tb_cflags(tb); TCGOp *icount_start_insn; - TCGOp *first_insn_start =3D NULL; bool plugin_enabled; +#ifndef CONFIG_USER_ONLY + TCGOp *first_insn_start =3D NULL; +#endif =20 tcg_ctx->addr_type =3D addr_type; =20 @@ -160,9 +164,11 @@ void translator_loop(CPUState *cpu, TranslationBlock *= tb, int *max_insns, *max_insns =3D ++db->num_insns; ops->insn_start(db, cpu); db->insn_start =3D tcg_last_op(); +#ifndef CONFIG_USER_ONLY if (first_insn_start =3D=3D NULL) { first_insn_start =3D db->insn_start; } +#endif tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit = */ =20 if (plugin_enabled) { @@ -207,9 +213,14 @@ void translator_loop(CPUState *cpu, TranslationBlock *= tb, int *max_insns, ops->tb_stop(db, cpu); gen_tb_end(tb, cflags, icount_start_insn, db->num_insns); =20 +#ifndef CONFIG_USER_ONLY /* * Manage can_do_io for the translation block: set to false before * the first insn and set to true before the last insn. + * + * Nothing reads can_do_io in user-only builds. There is no MMIO + * there, and every reader (cputlb.c, watchpoint.c, icount) is in + * system_ss, so skip the two stores per TB entirely. */ if (db->num_insns =3D=3D 1) { tcg_debug_assert(first_insn_start =3D=3D db->insn_start); @@ -221,6 +232,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, tcg_ctx->emit_before_op =3D db->insn_start; set_can_do_io(db, true); tcg_ctx->emit_before_op =3D NULL; +#endif =20 /* May be used by disas_log or plugin callbacks. */ tb->size =3D db->pc_next - db->pc_first; --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195796; cv=none; d=zohomail.com; s=zohoarc; b=DFnmS/8GxXJcVVTgJlXAnSTLzaN3H+7P/7gXQBZ9xLVlsAlerx+7D6BaYh+N76UD9AY9BEQU6ue8PYFVexOTyitqsvmhQiWcTxNTwh84/Et3DyN238lsJi6YIRN7lNFX2LndPel7KF5qWdqolwJUYTZ30jlp6E1I1Wepf2BdmXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195796; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Bt4kpkESK+vp3J4Ch1F5d1RcFGSfxhQzGfObV4jbjgQ=; b=dbnLDYXnHB5tYsKjYBFHWVsd9bRurvVRLM5G11R6arG54eERoEPfP7dT8mepj+XU279Jdys83v8+cvybzQoY46n9MiF0RKuY+PV8NlBdw6wf1M7mWU5TUIeB2eyNRZJuKDwKb8Vd7Tz1cSZQmo6B9XxDJ+S6nnIbuISDWXGq1Ig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790195796071638.2526853472189; Wed, 23 Sep 2026 13:36:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Tgh-0008GG-MG; Wed, 23 Sep 2026 16:35:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9Tg2-00089O-Ui for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:53 -0400 Received: from mail-pz2-x0e.google.com ([2607:f8b0:4864:3b::e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg1-0004zU-8f for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:50 -0400 Received: by mail-pz2-x0e.google.com with SMTP id d2e1a72fcca58-86efece610cso754333b3a.0 for ; Wed, 23 Sep 2026 13:34:48 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Assert when using --pargs with a system mode program. Reviewed-by: Matt Turner Signed-off-by: Richard Henderson --- tests/guest-debug/run-test.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py index 75e9c92e036..838c1c26971 100755 --- a/tests/guest-debug/run-test.py +++ b/tests/guest-debug/run-test.py @@ -24,6 +24,7 @@ def get_args(): parser.add_argument("--qemu", help=3D"Qemu binary for test", required=3DTrue) parser.add_argument("--qargs", help=3D"Qemu arguments for test") + parser.add_argument("--pargs", help=3D"Program arguments for test") parser.add_argument("--binary", help=3D"Binary to debug", required=3DTrue) parser.add_argument("--test", help=3D"GDB test script") @@ -81,6 +82,8 @@ def log(output, msg): suspend =3D ' -S' cmd =3D f'{args.qemu} {args.qargs} {args.binary}' \ f'{suspend} -gdb unix:path=3D{socket_name},server=3Don' + # There is no guest program command-line in system mode. + assert not args.pargs else: if args.no_suspend: suspend =3D ',suspend=3Dn' @@ -88,6 +91,8 @@ def log(output, msg): suspend =3D '' cmd =3D f'{args.qemu} {args.qargs} -g {socket_name}{suspend}' \ f' {args.binary}' + if args.pargs: + cmd +=3D f' {args.pargs}' =20 log(output, "QEMU CMD: %s" % (cmd)) inferior =3D subprocess.Popen(shlex.split(cmd)) --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195791; cv=none; d=zohomail.com; s=zohoarc; b=b5cbIBcTVOB+i2vmtBYgY7Os89SLhLEisXGBch3bxUC55W/bo980ZbFcdlX/vJOYhmSRCNMrmaTm/4F94O4RU4/m5XqqwDqxlCy/liI1Mh4KPK2U9gvAJ/IQKFz63XFQY4+tWbS/WfAbGc2tgnjViRc2IFXpMrKI4sDWRbphJmM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195791; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/vignENIEkthU0rUkkomMduDGfwUZLI5agjrp6DrhWE=; b=EHYynJ/w1oXZCh/9L7Y+cBG88i83gNaelbfMyP2dzI4jkB620tlb/EHyLQuYSSGcJ2MZTnaxCr8PUe3N+nVU+5uV/OWV4Ly3k1WPsRox1GZ5PljJ0irT/7AQ1zkoNlUkGv1YIw236dfmFkFbyqGkJPXFRAucOleanszExAfDBL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790195791177430.86063770714554; Wed, 23 Sep 2026 13:36:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9ThI-0000Fj-Qk; Wed, 23 Sep 2026 16:36:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9Tg5-00089n-Rg for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:56 -0400 Received: from mail-pz2-x10.google.com ([2607:f8b0:4864:3b::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg1-0004zc-IA for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:53 -0400 Received: by mail-pz2-x10.google.com with SMTP id d2e1a72fcca58-85469f204f6so729952b3a.2 for ; Wed, 23 Sep 2026 13:34:49 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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For guests whose text is much larger than a page this is expensive: an emulated alpha gcc compiling a 255k line translation unit takes the indirect dispatch path for 8.4 billion of its 34.2 billion TB exits, and a large share of those are ordinary direct branches that simply crossed an 8 KiB page boundary. The restriction was made unconditional by d3a2a1d803 ("accel/tcg: Introduce translator_use_goto_tb"), whose rationale was: Various targets avoid the page crossing test for CONFIG_USER_ONLY, but that is wrong: mmap and mprotect can change page permissions. That is true, but in user-only builds the invalidation path already covers it. There are no page tables: every mmap, mprotect and munmap reaches page_set_flags(), which calls tb_invalidate_phys_range() whenever the flags actually change, and tb_phys_invalidate() calls tb_jmp_unlink() to reset incoming jumps. A chained cross-page jump is therefore broken whenever the destination page's permissions change. This is not true in system mode, where TBs are keyed by physical address and a page table change invalidates nothing, so the restriction is kept there. The rule protects one more thing, which the original rationale does not mention: it guarantees that execution cannot enter a page without a TB lookup, and so without check_for_breakpoints(). That is what makes a breakpoint set after a block was translated take effect, since insertion deliberately invalidates nothing. A link established before the breakpoint was set would jump straight over it. So the chaining is only enabled for a run that can never acquire a breakpoint. In user-only mode every breakpoint comes from gdb -- BP_CPU is g_assert_not_reached() there, and the guest cannot ask for one -- and gdb has to be requested with -g before the first block is translated, even though with suspend=3Dn it may connect later. gdb_may_set_breakpoints() reports whether it was, and is fixed for the lifetime of the process. Add tests/tcg/multiarch/test-xpage-chain.c to cover both hazards directly. It writes the last instruction of one page and the first of the next, so that the fall-through between them is a cross-page goto_tb, runs it 200000 times so the chain is established, then checks that mprotect(PROT_NONE) makes the next call fault, and that different code written into the page once it is mapped back runs rather than a stale translation. The two instructions -- set the return value register, and return -- are all the architecture specific code there is; thirteen architectures supply them and the rest skip. The test detects the hazard it is meant to detect: with the tb_invalidate_phys_range() call in page_set_flags() commented out, it fails both phases, executing page B after PROT_NONE and returning the stale result. Run with -b, the same binary stops once the chain is established and lets tests/tcg/multiarch/gdbstub/xpage-bp.py set a breakpoint on the far side of it, which the next call has to stop on. With gdb_may_set_breakpoints() forced to false so that the chaining stays on under gdb, that breakpoint is missed and the test fails, which is what makes it a test of the gate rather than of gdb. Signed-off-by: Matt Turner Reviewed-by: Richard Henderson [rth: Update for meson test infrastructure] Signed-off-by: Richard Henderson Message-ID: <20260901034808.3524945-8-mattst88@gmail.com> --- include/gdbstub/user.h | 11 + accel/tcg/translator.c | 33 ++- gdbstub/user.c | 14 + tests/tcg/multiarch/test-xpage-chain.c | 360 ++++++++++++++++++++++++ tests/tcg/multiarch/gdbstub/xpage-bp.py | 37 +++ tests/tcg/multiarch/meson.build | 7 + 6 files changed, 461 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/multiarch/test-xpage-chain.c create mode 100644 tests/tcg/multiarch/gdbstub/xpage-bp.py diff --git a/include/gdbstub/user.h b/include/gdbstub/user.h index 654986d483b..c091cd97586 100644 --- a/include/gdbstub/user.h +++ b/include/gdbstub/user.h @@ -11,6 +11,17 @@ =20 #define MAX_SIGINFO_LENGTH 128 =20 +/** + * gdb_may_set_breakpoints() - whether a breakpoint can ever be inserted + * + * In user-only mode every breakpoint comes from gdb, and gdb is only ever + * reachable if -g was given at startup, before the guest ran a single + * instruction. A run that has no gdbstub can therefore never acquire a + * breakpoint, which lets translation take shortcuts that a breakpoint + * would invalidate. Stays true once true, even if gdb detaches. + */ +bool gdb_may_set_breakpoints(void); + /** * gdb_handlesig() - yield control to gdb * @cpu: CPU diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index e9943006947..3f08c1c15c7 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -15,6 +15,9 @@ #include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #include "exec/translator.h" +#ifdef CONFIG_USER_ONLY +#include "gdbstub/user.h" +#endif #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" #include "internal-common.h" @@ -110,6 +113,34 @@ bool translator_is_same_page(const DisasContextBase *d= b, vaddr addr) return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) =3D=3D 0; } =20 +/* + * Whether a direct jump may be chained to a destination outside the page + * the TB started in. + * + * In user-only mode there are no page tables. Every mmap, mprotect and + * munmap goes through page_set_flags(), which calls tb_invalidate_phys_ra= nge() + * whenever a change in flags so warrants, and tb_phys_invalidate() unlinks + * incoming jumps. A cross-page link is therefore broken whenever the + * destination page's permissions change. + * + * What the same-page rule also provides is that execution cannot enter a = page + * without a TB lookup, and so without check_for_breakpoints(), which is w= hat + * makes a breakpoint set after a block was translated take effect. Nothi= ng + * invalidates on breakpoint insertion, so a link established beforehand w= ould + * jump straight over it. In user-only mode breakpoints only ever come fr= om + * gdb -- BP_CPU is g_assert_not_reached() there and the guest has no way = to + * ask for one -- and gdb has to be requested with -g before the first blo= ck + * is translated, so a run that has no gdbstub can never acquire a breakpo= int. + */ +static bool use_cross_page_goto_tb(void) +{ +#ifdef CONFIG_USER_ONLY + return !gdb_may_set_breakpoints(); +#else + return false; +#endif +} + bool translator_use_goto_tb(DisasContextBase *db, vaddr dest) { /* Suppress goto_tb if requested. */ @@ -118,7 +149,7 @@ bool translator_use_goto_tb(DisasContextBase *db, vaddr= dest) } =20 /* Check for the dest on the same page as the start of the TB. */ - return translator_is_same_page(db, dest); + return use_cross_page_goto_tb() || translator_is_same_page(db, dest); } =20 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, diff --git a/gdbstub/user.c b/gdbstub/user.c index 9e6f9a6f376..d810f0f38c3 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -470,6 +470,18 @@ static void *gdbserver_accept_thread(void *arg) =20 #define USAGE "\nUsage: -g {port|path}[,suspend=3D{y|n}]" =20 +/* + * Set before the guest runs and never cleared, so that code translated at + * any point can rely on it: with suspend=3Dn gdb may connect long after + * startup, and once connected it can insert a breakpoint at any time. + */ +static bool gdbserver_requested; + +bool gdb_may_set_breakpoints(void) +{ + return gdbserver_requested; +} + bool gdbserver_start(const char *args, Error **errp) { g_auto(GStrv) argv =3D g_strsplit(args, ",", 0); @@ -513,6 +525,8 @@ bool gdbserver_start(const char *args, Error **errp) return false; } =20 + gdbserver_requested =3D true; + if (suspend) { if (gdbserver_accept(port, gdb_fd, port_or_path)) { gdb_handlesig(first_cpu, 0, NULL, NULL, 0); diff --git a/tests/tcg/multiarch/test-xpage-chain.c b/tests/tcg/multiarch/t= est-xpage-chain.c new file mode 100644 index 00000000000..8e60692d157 --- /dev/null +++ b/tests/tcg/multiarch/test-xpage-chain.c @@ -0,0 +1,360 @@ +/* + * Cross-page TB chaining hazard test. + * + * Two adjacent pages of hand-written code. The last instruction of page A + * sets the return value and falls through into page B, which returns; a TB + * always ends at a page boundary, so page A reaches page B through a + * cross-page goto_tb. + * + * Phase 1: run it enough times that QEMU chains TB_A -> TB_B. + * Phase 2: mprotect page B away. Re-running must fault. + * Phase 3: map it back and write different code into it. Re-running must + * execute the NEW code, not a stale chained translation. + * + * With -b, phases 2 and 3 are replaced by a stop at break_here(), where t= he + * gdbstub test sets a breakpoint on page B -- after the chain exists -- a= nd + * checks that re-running the chain still stops on it. See + * tests/tcg/multiarch/gdbstub/xpage-bp.py. + * + * The code the two pages hold is architecture specific, so each + * architecture supplies two emitters: + * + * emit_set_ret(p, val) - set the integer return value register to val + * emit_ret(p) - return to the caller + * + * both writing at @p and returning the number of bytes written. Neither + * may contain a branch: the fall-through from page A into page B is the + * whole point, and a delay slot must not straddle the boundary. An + * architecture that supplies neither skips the test. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#if defined(__aarch64__) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* movz w0, #val */ + *p =3D 0x52800000u | val << 5; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + /* ret */ + *p =3D 0xd65f03c0u; + return 4; +} +#elif defined(__alpha__) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* lda $0, val($31) */ + *p =3D 0x201f0000u | val; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + /* ret */ + *p =3D 0x6bfa8001u; + return 4; +} +#elif defined(__arm__) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* mov r0, #val */ + *p =3D 0xe3a00000u | val; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + /* bx lr */ + *p =3D 0xe12fff1eu; + return 4; +} +#elif defined(__hppa__) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* ldi val, %ret0 */ + *p =3D 0x341c0000u | val << 1; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + p[0] =3D 0xe840c000u; /* bv %r0(%rp) */ + p[1] =3D 0x08000240u; /* nop (delay slot) */ + return 8; +} +#elif defined(__i386__) || defined(__x86_64__) +#define HAVE_EMITTERS +static size_t emit_set_ret(void *p, int val) +{ + /* mov $val, %eax */ + *(unsigned char *)p =3D 0xb8; + *(int *)(p + 1) =3D val; + return 5; +} +static size_t emit_ret(void *p) +{ + /* ret */ + *(unsigned char *)p =3D 0xc3; + return 1; +} +#elif defined(__loongarch64) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* ori $a0, $zero, val */ + *p =3D 0x03800004u | val << 10; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + /* jr $ra */ + *p =3D 0x4c000020u; + return 4; +} +#elif defined(__m68k__) +#define HAVE_EMITTERS +static size_t emit_set_ret(void *p, int val) +{ + /* moveq #val, %d0 */ + *(uint16_t *)p =3D 0x7000u | val; + return 2; +} +static size_t emit_ret(void *p) +{ + /* rts */ + *(uint16_t *)p =3D 0x4e75u; + return 2; +} +#elif defined(__mips__) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* li $v0, val */ + *p =3D 0x24020000u | val; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + p[0] =3D 0x03e00008u; /* jr $ra */ + p[1] =3D 0x00000000u; /* nop (delay slot) */ + return 8; +} +/* + * ELFv1 function pointers are descriptors rather than code addresses, so + * there is nothing to call the raw code through. + */ +#elif defined(__powerpc__) && \ + (!defined(__powerpc64__) || (defined(_CALL_ELF) && _CALL_ELF =3D=3D = 2)) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* li r3, val */ + *p =3D 0x38600000u | val; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + /* blr */ + *p =3D 0x4e800020u; + return 4; +} +#elif defined(__riscv) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* addi a0, zero, val -- the 4 byte form */ + *p =3D 0x00000513u | val << 20; + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + /* jalr zero, 0(ra) */ + *p =3D 0x00008067u; + return 4; +} +#elif defined(__s390x__) +#define HAVE_EMITTERS +static size_t emit_set_ret(void *p, int val) +{ + /* lghi %r2, val */ + uint16_t *p2 =3D p; + p2[0] =3D 0xa729u; + p2[1] =3D val; + return 4; +} +static size_t emit_ret(void *p) +{ + /* br %r14 */ + *(uint16_t *)p =3D 0x07feu; + return 2; +} +#elif defined(__sh__) +#define HAVE_EMITTERS +static size_t emit_set_ret(void *p, int val) +{ + /* mov #val, r0 */ + *(uint16_t *)p =3D 0xe000u | val; + return 2; +} +static size_t emit_ret(void *p) +{ + uint16_t *p2 =3D p; + p2[0] =3D 0x000bu; /* rts */ + p2[1] =3D 0x0009u; /* nop (delay slot) */ + return 4; +} +#elif defined(__sparc__) +#define HAVE_EMITTERS +static size_t emit_set_ret(uint32_t *p, int val) +{ + /* mov val, %o0 */ + *p =3D 0x90102000u | (val & 0x1fff); + return 4; +} +static size_t emit_ret(uint32_t *p) +{ + p[0] =3D 0x81c3e008u; /* retl */ + p[1] =3D 0x01000000u; /* nop (delay slot) */ + return 8; +} +#endif + +/* Where the fall-through lands, for the gdbstub test to breakpoint on. */ +void *page_b_entry; + +/* Somewhere for the gdbstub test to stop once the chain is established. */ +void __attribute__((noinline)) break_here(void) +{ + asm volatile(""); +} + +#ifdef HAVE_EMITTERS +static sigjmp_buf jb; +/* + * Written by the SIGSEGV handler and read by main(), so it must not be + * cached in a register across the faulting call. + */ +static volatile sig_atomic_t caught; + +static void segv(int sig) +{ + caught =3D 1; + siglongjmp(jb, 1); +} +#endif + +int main(int argc, char **argv) +{ + bool bp_mode =3D argc > 1 && strcmp(argv[1], "-b") =3D=3D 0; +#ifndef HAVE_EMITTERS + printf("SKIP: no code emitters for this architecture\n"); + if (bp_mode) { + break_here(); + } + return 0; +#else + uint32_t tmp[4]; + struct sigaction sa; + long (*fn)(void); + size_t setlen, n; + long ps =3D sysconf(_SC_PAGESIZE); + int rc =3D 0; + unsigned char *m =3D mmap(NULL, 2 * ps, PROT_READ | PROT_WRITE | PROT_= EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (m =3D=3D MAP_FAILED) { + perror("mmap"); + return 2; + } + + void *pb =3D m + ps; + + /* + * Page A ends with the store to the return value register, so that the + * next instruction executed is the first one on page B. + */ + setlen =3D emit_set_ret(tmp, 1); + memcpy(pb - setlen, tmp, setlen); + emit_ret(pb); + __builtin___clear_cache((char *)m, (char *)m + 2 * ps); + + page_b_entry =3D pb; + fn =3D (long (*)(void))(pb - setlen); + + for (int i =3D 0; i < 200000; i++) { + if (fn() !=3D 1) { + printf("FAIL: phase 1 wrong result\n"); + return 1; + } + } + printf("phase 1 ok (chained)\n"); + + if (bp_mode) { + /* + * The chain from page A to page B now exists. gdb puts a breakpo= int + * on page_b_entry here; the call below has to stop on it rather t= han + * jump over it. + */ + break_here(); + if (fn() !=3D 1) { + printf("FAIL: bp phase wrong result\n"); + return 1; + } + printf("bp phase ok\n"); + return 0; + } + + memset(&sa, 0, sizeof(sa)); + sa.sa_handler =3D segv; + sigemptyset(&sa.sa_mask); + if (sigaction(SIGSEGV, &sa, NULL) !=3D 0) { + perror("sigaction"); + return 2; + } + if (mprotect(pb, ps, PROT_NONE) !=3D 0) { + perror("mprotect"); + return 2; + } + if (sigsetjmp(jb, 1) =3D=3D 0) { + fn(); + printf("FAIL: phase 2 executed page B after mprotect(PROT_NONE)\n"= ); + rc =3D 1; + } else if (!caught) { + printf("FAIL: phase 2 longjmp without entering the handler\n"); + rc =3D 1; + } else { + printf("phase 2 ok (faulted)\n"); + } + + /* Phase 3: map back, overwrite, expect the new code to run. */ + if (mprotect(pb, ps, PROT_READ | PROT_WRITE | PROT_EXEC) !=3D 0) { + perror("mprotect back"); + return 2; + } + n =3D emit_set_ret(pb, 2); + emit_ret(pb + n); + __builtin___clear_cache((char *)pb, (char *)pb + ps); + + long r =3D fn(); + if (r !=3D 2) { + printf("FAIL: phase 3 returned %ld, expected 2 (stale chain)\n", r= ); + rc =3D 1; + } else { + printf("phase 3 ok (new code ran)\n"); + } + return rc; +#endif +} diff --git a/tests/tcg/multiarch/gdbstub/xpage-bp.py b/tests/tcg/multiarch/= gdbstub/xpage-bp.py new file mode 100644 index 00000000000..f40024f16de --- /dev/null +++ b/tests/tcg/multiarch/gdbstub/xpage-bp.py @@ -0,0 +1,37 @@ +"""Test that a breakpoint set after a cross-page chain is established is h= it. + +translator_use_goto_tb() lets a direct branch chain to another page in +user-only builds, which is only safe because a run with no gdbstub can nev= er +acquire a breakpoint. This runs with one, so the chaining must be off and +the breakpoint must still be reached. + +This runs as a sourced script (via -x, via run-test.py). + +SPDX-License-Identifier: GPL-2.0-or-later +""" +from test_gdbstub import main, report + + +def run_test(): + """Run through the tests one by one""" + gdb.Breakpoint("break_here") + gdb.execute("continue") + + # The chain exists by now; put a breakpoint on the far side of it. + target =3D int(gdb.parse_and_eval("(unsigned long)page_b_entry")) + if target =3D=3D 0: + report(True, "no code emitters for this architecture, skipped") + return + gdb.execute("break *{}".format(target)) + gdb.execute("continue") + + pc =3D int(gdb.parse_and_eval("(unsigned long)$pc")) + report(pc =3D=3D target, "stopped at {:#x}, expected {:#x}".format(pc,= target)) + + gdb.execute("delete") + gdb.execute("continue") + exitcode =3D int(gdb.parse_and_eval("$_exitcode")) + report(exitcode =3D=3D 0, "{} =3D=3D 0".format(exitcode)) + + +main(run_test) diff --git a/tests/tcg/multiarch/meson.build b/tests/tcg/multiarch/meson.bu= ild index 508fdb585b7..c3816d3a218 100644 --- a/tests/tcg/multiarch/meson.build +++ b/tests/tcg/multiarch/meson.build @@ -48,6 +48,7 @@ tests +=3D { multiarch/'sigreturn-sigmask.c': {'cflags': ['-lpthread']}, multiarch/'tb-link.c': {'cflags': ['-lpthread']}, multiarch/'test-mmap.c': {}, + multiarch/'test-xpage-chain.c': {'cflags': ['-lpthread']}, multiarch/'testthread.c': {'cflags': ['-lpthread']}, multiarch/'threadcount.c': {'cflags': ['-lpthread']}, } @@ -118,6 +119,12 @@ tests +=3D { 'gdb_test': ['--test', files('gdbstub/follow-fork-mode-parent.py')], }, } +tests +=3D { + multiarch/'test-xpage-chain.c': { + 'test_name': 'xpage-chain', + 'gdb_test': ['--test', files('gdbstub/xpage-bp.py'), '--pargs=3D-b'], + }, +} =20 # Specific plugin tests # Test plugin memory access instrumentation --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195834; cv=none; d=zohomail.com; s=zohoarc; b=cVXzoWTTHhlJZZ8x1AiCnbhy9Su4og7baNtI+LP2fjddQUfOVYAZ6pmzqjIflusWuWfHtwvNvDhd6mT2NM8Csi7fyMfZPkGKwZEAQ0vFJSMcWI2ET61TnyHmmBk8drXPRTmDF2bu3ZCcIIkXbkSnOwy1wNYF583t009JfihfCCw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195834; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j6QG31ddBAoXf5XbCARtw7hjYTU4SqCkiNBwOj5mBjs=; b=fMOYyKmiOneD6XwefMMlAwQo45jJjB4H5q5ilgvNHCircO8QUiRQwXp9rmsd4vBln3pd19hAQxI0mrLG0E0j/SMVRzBRW+yyAWB/cCrneRHtyoxPN7wGZiKfBys+heJHwjaBaRnQaNvNF8QIYSXYa0R2YUayW/3Hordcbz+vru4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790195834346150.6306241363351; Wed, 23 Sep 2026 13:37:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Tgn-0008JK-3J; Wed, 23 Sep 2026 16:35:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9Tg4-00089d-Up for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:55 -0400 Received: from mail-pz2-x0d.google.com ([2607:f8b0:4864:3b::d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg2-0004zq-5N for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:52 -0400 Received: by mail-pz2-x0d.google.com with SMTP id d2e1a72fcca58-85469e25400so740458b3a.0 for ; Wed, 23 Sep 2026 13:34:49 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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We might as well do this via fold_shift, which will also mark rh as having all copies of the sign bit. For the movi paths of multiply vs 0 or mulu2, we're better off tail calling to tcg_opt_gen_movi rather than explicitly returning true. Cc: qemu-stable@nongnu.org Fixes: c9349965ce4 ("tcg: Optimize INDEX_op_mul[us]2 for 0 and 1") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4448 Reviewed-by: Jim MacArthur Signed-off-by: Richard Henderson --- tcg/optimize.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index d291c844ca8..bd91220650b 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2213,6 +2213,7 @@ static bool fold_mul_highpart(OptContext *ctx, TCGOp = *op) return finish_folding(ctx, op); } =20 +static bool fold_shift(OptContext *ctx, TCGOp *op); static bool fold_multiply2(OptContext *ctx, TCGOp *op) { swap_commutative(op->args[0], &op->args[2], &op->args[3]); @@ -2253,15 +2254,13 @@ static bool fold_multiply2(OptContext *ctx, TCGOp *= op) /* The proper opcode is supplied by tcg_opt_gen_mov. */ op2 =3D opt_insert_before(ctx, op, 0, 2); tcg_opt_gen_movi(ctx, op, rl, l); - tcg_opt_gen_movi(ctx, op2, rh, h); - return true; + return tcg_opt_gen_movi(ctx, op2, rh, h); } =20 if (b =3D=3D 0) { op2 =3D opt_insert_before(ctx, op, 0, 2); tcg_opt_gen_movi(ctx, op2, rl, 0); - tcg_opt_gen_movi(ctx, op, rh, 0); - return true; + return tcg_opt_gen_movi(ctx, op, rh, 0); } if (b =3D=3D 1) { op2 =3D opt_insert_before(ctx, op, 0, 2); @@ -2269,20 +2268,18 @@ static bool fold_multiply2(OptContext *ctx, TCGOp *= op) =20 switch (op->opc) { case INDEX_op_mulu2: - tcg_opt_gen_movi(ctx, op, rh, 0); - break; + return tcg_opt_gen_movi(ctx, op, rh, 0); case INDEX_op_muls2: op->opc =3D INDEX_op_sar; op->args[0] =3D rh; op->args[1] =3D rl; op->args[2] =3D arg_new_constant(ctx, tcg_type_size(ctx->type) * 8 - 1= ); - break; + return fold_shift(ctx, op); default: - g_assert_not_reached(); + break; } - - return true; + g_assert_not_reached(); } } return finish_folding(ctx, op); --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195866; cv=none; d=zohomail.com; s=zohoarc; b=TYP9Q6P3IHKQ1nqh1gjyDWsxidC6HHYZDOhTPYqySt8KE/5POhWcY2unRw8PcbUe/YcsvQs9RNn4Rzl4RrydZ0kdC1aV0BctZD9d496JggcMAfTOcvPbg5pvZIKEYm0+jpf3RaHP2jRxgFjRXFuS7DufrF5UF+IogwknxKSBX+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195866; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MnLKuFltvc/Rg1zMvwUFOIX89Pj2+SfPG/1M0nyAyh0=; b=RZKa4vtYkZ6/+ye4g8ClR67rCdjqaKOdYR8RQOKrbFP9wCMrKmz+ZJfg3tIOfsXRK/3HERPAIPpcXUJ2DKKRt5q4koM0DHYU5EUl+pQ6ysEMWiPGZmmE/jlfIFok5qO/bMSjbPBGxd1e1uuvALRY9rH8YremyLibiRd6dgCm0KU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790195865848382.4499989845033; Wed, 23 Sep 2026 13:37:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Tgm-0008Hy-2Q; Wed, 23 Sep 2026 16:35:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9Tg4-00089e-Uz for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:55 -0400 Received: from mail-pz2-x10.google.com ([2607:f8b0:4864:3b::10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg3-000501-1H for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:52 -0400 Received: by mail-pz2-x10.google.com with SMTP id d2e1a72fcca58-85469a34908so963822b3a.0 for ; Wed, 23 Sep 2026 13:34:50 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Wed, 23 Sep 2026 13:34:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Jim MacArthur Subject: [PULL 07/16] tests/tcg/arm: Add regression test for #4448 Date: Wed, 23 Sep 2026 13:34:32 -0700 Message-ID: <20260923203441.31276-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923203441.31276-1-richard.henderson@linaro.org> References: <20260923203441.31276-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:3b::10; envelope-from=richard.henderson@linaro.org; helo=mail-pz2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1790195867134158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Jim MacArthur Signed-off-by: Richard Henderson --- tests/tcg/arm/issue4448.c | 51 +++++++++++++++++++++++++++++++++++++++ tests/tcg/arm/meson.build | 1 + 2 files changed, 52 insertions(+) create mode 100644 tests/tcg/arm/issue4448.c diff --git a/tests/tcg/arm/issue4448.c b/tests/tcg/arm/issue4448.c new file mode 100644 index 00000000000..0a498373a89 --- /dev/null +++ b/tests/tcg/arm/issue4448.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Signed 64-bit product, constant operand first then second. */ +#define SMULL_CONST_LHS(k, x, lo, hi) \ + __asm__("mov r0, #" #k "\n\tsmull %0, %1, r0, %2" \ + : "=3D&r"(lo), "=3D&r"(hi) : "r"(x) : "r0", "cc") + +#define SMULL_CONST_RHS(k, x, lo, hi) \ + __asm__("mov r0, #" #k "\n\tsmull %0, %1, %2, r0" \ + : "=3D&r"(lo), "=3D&r"(hi) : "r"(x) : "r0", "cc") + +/* Unsigned 64-bit product, for contrast: this one is folded correctly. */ +#define UMULL_CONST_LHS(k, x, lo, hi) \ + __asm__("mov r0, #" #k "\n\tumull %0, %1, r0, %2" \ + : "=3D&r"(lo), "=3D&r"(hi) : "r"(x) : "r0", "cc") + +static int64_t s64(int32_t hi, int32_t lo) +{ + return ((int64_t)hi << 32) | (uint32_t)lo; +} + +static uint64_t u64(int32_t hi, int32_t lo) +{ + return ((uint64_t)(uint32_t)hi << 32) | (uint32_t)lo; +} + +int main(void) +{ + static const int32_t values[] =3D { 1961612, -1479053948, -7, 0 }; + + for (unsigned i =3D 0; i < sizeof(values) / sizeof(values[0]); i++) { + int32_t x =3D values[i]; + int32_t lo, hi; + + SMULL_CONST_LHS(1, x, lo, hi); + assert(x =3D=3D s64(hi, lo)); + + SMULL_CONST_RHS(1, x, lo, hi); + assert(x =3D=3D s64(hi, lo)); + + UMULL_CONST_LHS(1, x, lo, hi); + assert((uint32_t)x =3D=3D u64(hi, lo)); + + SMULL_CONST_LHS(0, x, lo, hi); + assert(0 =3D=3D u64(hi, lo)); + } + return 0; +} diff --git a/tests/tcg/arm/meson.build b/tests/tcg/arm/meson.build index 1b491cea026..5c2af2189c5 100644 --- a/tests/tcg/arm/meson.build +++ b/tests/tcg/arm/meson.build @@ -39,6 +39,7 @@ tests +=3D { 'expected_output': 'fcvt.ref', }, 'pcalign-a32.c': {'cflags': ['-marm']}, + 'issue4448.c': {}, } =20 # Vector SHA1 --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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If we let the rest of the code expand as-is, when can we get to the end we'll see the constant, note that it's the same as the current value, remove what we think is "the opcode" that computes this same value. But in this case we've been expanding deposit to multiple opcodes and the removal of only the last opcode breaks the expansion. Fix this by noting the constant result early, before expanding, allowing the entire operation to be removed. Cc: qemu-stable@nongnu.org Fixes: 5f747705a4 ("tcg/optimize: Lower unsupported deposit during optimize= ") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4449 Reviewed-by: Jim MacArthur Signed-off-by: Richard Henderson --- tcg/optimize.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index bd91220650b..1e4d2a0a425 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1708,6 +1708,23 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) type_mask =3D MAKE_64BIT_MASK(0, width); len_mask =3D MAKE_64BIT_MASK(0, len); =20 + /* + * Compute result masks before calling other fold_* subroutines + * which could modify the masks of our inputs. + */ + z_mask =3D deposit64(t1->z_mask, ofs, len, t2->z_mask); + o_mask =3D deposit64(t1->o_mask, ofs, len, t2->o_mask); + if (ofs + len < width) { + s_mask =3D t1->s_mask & ~MAKE_64BIT_MASK(0, ofs + len); + } else { + s_mask =3D t2->s_mask << ofs; + } + + /* Sometimes we prove a constant from non-constants. */ + if (z_mask =3D=3D o_mask) { + return tcg_opt_gen_movi(ctx, op, op->args[0], z_mask); + } + /* Inserting all-zero into a value. */ if ((t2->z_mask & len_mask) =3D=3D 0) { op->opc =3D INDEX_op_and; @@ -1740,18 +1757,6 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op) return fold_or(ctx, op); } =20 - /* - * Compute result masks before calling other fold_* subroutines - * which could modify the masks of our inputs. - */ - z_mask =3D deposit64(t1->z_mask, ofs, len, t2->z_mask); - o_mask =3D deposit64(t1->o_mask, ofs, len, t2->o_mask); - if (ofs + len < width) { - s_mask =3D t1->s_mask & ~MAKE_64BIT_MASK(0, ofs + len); - } else { - s_mask =3D t2->s_mask << ofs; - } - /* Inserting a value into zero. */ if (ti_is_const_val(t1, 0)) { uint64_t need_mask; --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195784; cv=none; d=zohomail.com; s=zohoarc; b=GThJL6HHpw+x5YwN1ee2NyUf3oytsoAHZwcnyEPyDBALdWIkHCcpeLjXy1dXRHgnBVg9gLU3cUtwu6juBJouxgiyV+qGJVm1x0DcLv7OzoWQA1TsuVhqhokgXbs0YQ/U1X5HTbF2g4b4TsLqMMUFtEESj56GFxBZSAp6+1ROcP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195784; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=38rPl2WErEqztjtaSaH7D3tBNYi/tw8oBqoCI67UoZw=; b=gPcMudXKIorSRMmCCYBSy8T1bN8/N13mQVIc75Fimy7q0B7THmmq1vHECtYpF3Q0mN5/Zkr7IbBiuf/XRXdcas49DFbNxmoLKek0nfJQGxmO0EHH+kf5XffJTjK1dqxtMGjiN9rkJCJnm5zYSIFOR9DrdITtX2ghGAHqRY1b2GE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17901957845641003.4501820579862; Wed, 23 Sep 2026 13:36:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Tgk-0008Gp-Ij; Wed, 23 Sep 2026 16:35:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9Tg7-00089v-EK for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:57 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg5-00050i-UU for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:55 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-853e2610bb4so97684b3a.0 for ; Wed, 23 Sep 2026 13:34:53 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Wed, 23 Sep 2026 13:34:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/16] tests/tcg/s390x: Add regression test for #4449 Date: Wed, 23 Sep 2026 13:34:34 -0700 Message-ID: <20260923203441.31276-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923203441.31276-1-richard.henderson@linaro.org> References: <20260923203441.31276-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1790195786590158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tests/tcg/s390x/issue4449.c | 31 +++++++++++++++++++++++++++++++ tests/tcg/s390x/meson.build | 1 + 2 files changed, 32 insertions(+) create mode 100644 tests/tcg/s390x/issue4449.c diff --git a/tests/tcg/s390x/issue4449.c b/tests/tcg/s390x/issue4449.c new file mode 100644 index 00000000000..0c9c80e8cac --- /dev/null +++ b/tests/tcg/s390x/issue4449.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +#define CASE(name, old, cst, sh) \ + static void __attribute__((noinline)) case_##name(void) { \ + unsigned long t1, got; \ + __asm__("lhi %0," #cst "\n\t" /* low 32 known, high not */ \ + "lghi %1," #old "\n\t" /* whole register constant */ \ + "sllk %1,%0," #sh "\n\t" /* 32-bit write =3D deposit */ \ + "brc 15,1f\n\t" /* ends the translation block */ \ + "nop\n" \ + "1:" \ + : "=3Dr"(t1), "=3Dr"(got) : : ); = \ + unsigned long want =3D (unsigned)(cst) << (sh); \ + assert(got =3D=3D want); = \ + } + +CASE(a, 256, 128, 1); +CASE(b, 128, 128, 0); +CASE(c, 512, 128, 2); +CASE(d, 2, 1, 1); + +int main() +{ + case_a(); + case_b(); + case_c(); + case_d(); + return 0; +} diff --git a/tests/tcg/s390x/meson.build b/tests/tcg/s390x/meson.build index 57ea6c5ca55..39a480033de 100644 --- a/tests/tcg/s390x/meson.build +++ b/tests/tcg/s390x/meson.build @@ -84,6 +84,7 @@ tests +=3D { 'cpacf-pcc.c': {}, 'cpacf-pckmo.c': {}, 'cpacf-prno.c': {}, + 'issue4449.c': {}, } =20 foreach src: tests_s390x_pgm --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195866; cv=none; d=zohomail.com; s=zohoarc; b=ZrXprcEzWzxWDFZ+J/dS+Td0EntNsfjw6BGjpdBqLSjWDZ8owOsf5SQxC9DY/QWAcXuHIZa5egn+o8qgL7GPHdsW9JPLWK4pcmMr+QwzQHFlrhkzL0L6K9NIDM1EN1rOQq60KGGkrNPAlT6JvHEXvOK7yJb5qp51P8WqBA+AXQ4= ARC-Message-Signature: i=1; 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As long as the target translator wraps pc properly, this allows address space wraparound to function correctly. This avoids an assert on a valid i386 system-mode test case. Reported-by: Tao Cui Reviewed-by: Jim MacArthur Signed-off-by: Richard Henderson --- include/exec/translator.h | 3 +++ accel/tcg/translator.c | 45 ++++++++++++++++++++++++--------------- 2 files changed, 31 insertions(+), 17 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 978dee25add..104e6d4f361 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -55,6 +55,8 @@ typedef enum DisasJumpType { * @pc_first: Address of first guest instruction in this TB. * @pc_next: Address of next guest instruction in this TB (current during * disassembly). + * @pc_second_page: Address of the beginning of the second page of this TB, + * or -1 if the TB does not yet extend to a second page. * @is_jmp: What instruction to disassemble next. * @num_insns: Number of translated instructions (including current). * @max_insns: Maximum number of instructions to be translated in this TB. @@ -69,6 +71,7 @@ struct DisasContextBase { TranslationBlock *tb; vaddr pc_first; vaddr pc_next; + vaddr pc_second_page; DisasJumpType is_jmp; int num_insns; int max_insns; diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 3f08c1c15c7..2083f4285a2 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -169,6 +169,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, db->tb =3D tb; db->pc_first =3D pc; db->pc_next =3D pc; + db->pc_second_page =3D -1; db->is_jmp =3D DISAS_NEXT; db->num_insns =3D 0; db->max_insns =3D *max_insns; @@ -328,16 +329,18 @@ static bool translator_ld(CPUArchState *env, DisasCon= textBase *db, /* * The read must conclude on the second page and not extend to a third. * - * TODO: We could allow the two pages to be virtually discontiguous, - * since we already allow the two pages to be physically discontiguous. - * The only reasonable use case would be executing an insn at the end - * of the address space wrapping around to the beginning. For that, - * we would need to know the current width of the address space. - * In the meantime, assert. + * TODO: This doesn't handle address space wraparound properly for + * multi-byte reads, as we don't know the size of the address space he= re. + * But if the target translator wraps pc to 0 itself, and issues align= ed + * reads, then this can work. */ - base =3D (base & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - assert(((base ^ pc) & TARGET_PAGE_MASK) =3D=3D 0); - assert(((base ^ last) & TARGET_PAGE_MASK) =3D=3D 0); + if (db->pc_second_page =3D=3D -1) { + db->pc_second_page =3D pc & TARGET_PAGE_MASK; + } else { + assert((pc & TARGET_PAGE_MASK) =3D=3D db->pc_second_page); + } + assert((last & TARGET_PAGE_MASK) =3D=3D db->pc_second_page); + base =3D db->pc_second_page; host =3D db->host_addr[1]; =20 if (host =3D=3D NULL) { @@ -415,16 +418,24 @@ static void record_save(DisasContextBase *db, vaddr p= c, { int offset; =20 - /* Do not record probes before the start of TB. */ - if (pc < db->pc_first) { - return; - } - /* - * In translator_access, we verified that pc is within 2 pages - * of pc_first, thus this will never overflow. + * In translator_ld, we verified that we touched no more than 2 pages, + * but we did not verify that they were virtually contiguous. + * Here, reimagine the two pages as virtually contiguous. */ - offset =3D pc - db->pc_first; + if (likely(((db->pc_first ^ pc) & TARGET_PAGE_MASK) =3D=3D 0)) { + /* first page */ + /* Do not record probes before the start of TB. */ + if (pc < db->pc_first) { + return; + } + offset =3D pc - db->pc_first; + } else { + int first_page_end_offset =3D -(db->pc_first | TARGET_PAGE_MASK); + assert(db->pc_second_page !=3D -1); + assert((pc & TARGET_PAGE_MASK) =3D=3D db->pc_second_page); + offset =3D pc - db->pc_second_page + first_page_end_offset; + } =20 /* * Either the first or second page may be I/O. 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The top page (0xfffff000) is SeaBIOS ROM, so the cross-boundary byte is the ROM's own 0x00 (add r/m8, r8) at 0xffffffff, whose modrm is fetched from [0x0]. A short exit stub is placed there. The case runs on qemu-system-i386 since the bug is 32-bit only. Signed-off-by: Tao Cui Message-ID: <20260709020529.126652-3-cui.tao@linux.dev> [rth: Simplify and convert to meson test harness] Reviewed-by: Jim MacArthur Signed-off-by: Richard Henderson --- tests/tcg/i386/system/meson.build | 4 ++++ tests/tcg/i386/system/wraparound.S | 35 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 tests/tcg/i386/system/wraparound.S diff --git a/tests/tcg/i386/system/meson.build b/tests/tcg/i386/system/meso= n.build index d3f73997c7f..c08563d0ab5 100644 --- a/tests/tcg/i386/system/meson.build +++ b/tests/tcg/i386/system/meson.build @@ -34,6 +34,10 @@ foreach t: tcg_tests['multiarch-softmmu']['tests'] endforeach endforeach =20 +tests +=3D { + 'wraparound.S': { 'cflags': cflags, 'qemu_args': ['-m', '4G'] + qemu_def= _args } +} + if 'qemu-system-i386' in emulators tcg_tests +=3D { 'i386-softmmu': { diff --git a/tests/tcg/i386/system/wraparound.S b/tests/tcg/i386/system/wra= paround.S new file mode 100644 index 00000000000..9c77b3a8468 --- /dev/null +++ b/tests/tcg/i386/system/wraparound.S @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Regression test for the translator_ld crash when an instruction + * straddles the end of the 32-bit address space (i386). + */ + + .code32 + .section .text + +main: + /* + * The top page (0xfffff000) is SeaBIOS ROM and cannot be written. + * Its byte at 0xffffffff (0x00 =3D "add r/m8, r8") already crosse= s the + * page boundary into page1 at 0x0, which is exactly the case + * translator_ld must handle without aborting. Reaching 0xfffffffe + * runs the ROM's cld, then that add; the add's modrm is fetched f= rom + * [0x0], which is RAM, so build a short exit stub there: + * + * [0x0] c0 modrm -> "add al, al" (reg; EIP -> 1) + * [0x1] c3 ret + * + * Note: this relies on the SeaBIOS byte at 0xffffffff being 0x00 + * (add r/m8, r8); if that ever changes, the stub below must move. + * + * Note that eax =3D 0 before and after the stub, so this becomes + * the exit code of the test. + */ + xor %eax, %eax + movw $0xc3c0, (%eax) + movl $0xfffffffe, %ecx + jmp *%ecx + + .globl main + .type main, @function + .size main, . - main --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195850; cv=none; d=zohomail.com; s=zohoarc; b=U91zLwj7c72fEfOi8WmoKlt0v6UT7uxq63IC5iGftQgfX8JstxSpEO6Od0PPhfNMHcGfQs0D7GCqBeL/LRKBTejp/OWHBJZMURlBCxfwpJYarc31Iw4LyGT8vq9721j9MJis779rUL48y+ihtrZHB4hgyzFrVgu5fLoj4970pqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195850; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iw6NmWPUmuvdUzCnsYRZeVRMe166tP0/X361NQb/yjU=; b=Y/UGMpTF+5lCyBD9QHCjbLELUX9Eip5aG6ehfeo9q5nKU6eyuIfjojBzpBXoJsvNjuPNBPSp+JoETnHyQmQL9Pkt6ia06Z2T9HuBC7G3gbTHik1PCGbOR5BacSRBrJs4admB9zGBENNWZPAVt2v1o4BJ8DeSYXl9blkJvCRZulY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790195850114605.4324842226381; Wed, 23 Sep 2026 13:37:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9TiG-0001Ur-Jr; Wed, 23 Sep 2026 16:37:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9TgA-0008B1-PK for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:35:00 -0400 Received: from mail-pz2-x0f.google.com ([2607:f8b0:4864:3b::f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg9-00051D-03 for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:58 -0400 Received: by mail-pz2-x0f.google.com with SMTP id d2e1a72fcca58-85a4329731cso811609b3a.3 for ; Wed, 23 Sep 2026 13:34:55 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 489df0e7386..ecc1f54c1bf 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1158,32 +1158,39 @@ static const TCGOutOpLoad outop_ld =3D { /* Register allocation descriptions for every TCGOpcode. */ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add), + /* addc1o is implemented with set_carry + addcio */ + OUTOP(INDEX_op_addc1o, TCGOutOpBinary, outop_addcio), OUTOP(INDEX_op_addci, TCGOutOpAddSubCarry, outop_addci), OUTOP(INDEX_op_addcio, TCGOutOpBinary, outop_addcio), OUTOP(INDEX_op_addco, TCGOutOpBinary, outop_addco), - /* addc1o is implemented with set_carry + addcio */ - OUTOP(INDEX_op_addc1o, TCGOutOpBinary, outop_addcio), OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond), OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16), OUTOP(INDEX_op_bswap32, TCGOutOpBswap, outop_bswap32), + OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz), OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop), OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz), OUTOP(INDEX_op_deposit, TCGOutOpDeposit, outop_deposit), OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), - OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), + OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2), OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv), OUTOP(INDEX_op_extract, TCGOutOpExtract, outop_extract), OUTOP(INDEX_op_extract2, TCGOutOpExtract2, outop_extract2), - OUTOP(INDEX_op_ld8u, TCGOutOpLoad, outop_ld8u), - OUTOP(INDEX_op_ld8s, TCGOutOpLoad, outop_ld8s), - OUTOP(INDEX_op_ld16u, TCGOutOpLoad, outop_ld16u), - OUTOP(INDEX_op_ld16s, TCGOutOpLoad, outop_ld16s), + OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), + OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), + OUTOP(INDEX_op_extrl_i64_i32, TCGOutOpUnary, outop_extrl_i64_i32), + OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), OUTOP(INDEX_op_ld, TCGOutOpLoad, outop_ld), + OUTOP(INDEX_op_ld8s, TCGOutOpLoad, outop_ld8s), + OUTOP(INDEX_op_ld8u, TCGOutOpLoad, outop_ld8u), + OUTOP(INDEX_op_ld16s, TCGOutOpLoad, outop_ld16s), + OUTOP(INDEX_op_ld16u, TCGOutOpLoad, outop_ld16u), + OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), + OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond), OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2), @@ -1203,7 +1210,9 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2), OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems), OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu), + OUTOP(INDEX_op_revbit8, TCGOutOpUnary, outop_revbit8), OUTOP(INDEX_op_revbit32, TCGOutOpBswap, outop_revbit32), + OUTOP(INDEX_op_revbit64, TCGOutOpUnary, outop_revbit64), OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl), OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr), OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar), @@ -1216,28 +1225,18 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D= { OUTOP(INDEX_op_st, TCGOutOpStore, outop_st), OUTOP(INDEX_op_st8, TCGOutOpStore, outop_st8), OUTOP(INDEX_op_st16, TCGOutOpStore, outop_st16), + OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st), OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub), + /* subb1o is implemented with set_borrow + subbio */ + OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio), OUTOP(INDEX_op_subbi, TCGOutOpAddSubCarry, outop_subbi), OUTOP(INDEX_op_subbio, TCGOutOpAddSubCarry, outop_subbio), OUTOP(INDEX_op_subbo, TCGOutOpAddSubCarry, outop_subbo), - /* subb1o is implemented with set_borrow + subbio */ - OUTOP(INDEX_op_subb1o, TCGOutOpAddSubCarry, outop_subbio), OUTOP(INDEX_op_umax, TCGOutOpBinary, outop_umax), OUTOP(INDEX_op_umin, TCGOutOpBinary, outop_umin), OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), =20 [INDEX_op_goto_ptr] =3D &outop_goto_ptr, - - OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), - OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), - OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), - OUTOP(INDEX_op_extrl_i64_i32, TCGOutOpUnary, outop_extrl_i64_i32), - OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), - OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u), - OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s), - OUTOP(INDEX_op_revbit8, TCGOutOpUnary, outop_revbit8), - OUTOP(INDEX_op_revbit64, TCGOutOpUnary, outop_revbit64), - OUTOP(INDEX_op_st32, TCGOutOpStore, outop_st), }; =20 #undef OUTOP --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195883; cv=none; d=zohomail.com; s=zohoarc; b=VCJqOSnJ70kompZq7yk+bj0T0Og95Uy11uA+4iKVhYIho33HhosC/VbWdjmHyg5BxKg5/hj6RLKufSsHQ8XRs23uY5vyTOtnkZ6T4i9fZxeojeFjwaYQojMrRR1BaCxITo/yGWo+pJxAZYJWf1vW+ZxObhwOw/1cPxQ9k7wfOr4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195883; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=PsKFn4pRALYWaoNgjaJtEuJl3huqiCPhAS0dlA5jb+M=; b=VIdXBivRqjh+7+IHe7IaHY93OkhrJk/x/UM6uGiKzCECNcjglyjy4mfxNjNRD2Zjzh43w6ZGcNrGda/2Mu5oCMbSmbXPUu7LI4QvcWX2HzLwC8a5X2aGhfF1C2I4j4DcrD6RPJFkjQk95IBUFAkgS1eSKcqlK3+ScfLUUT0tuQA= ARC-Authentication-Results: i=1; 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This replaces the highly constrained mul insn from the base x86 isa. Signed-off-by: Richard Henderson --- tcg/x86_64/tcg-target-con-set.h | 2 ++ tcg/x86_64/tcg-target.c.inc | 36 ++++++++++++++++++++++++++++++--- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/tcg/x86_64/tcg-target-con-set.h b/tcg/x86_64/tcg-target-con-se= t.h index 458d69c3c07..7df9bf49177 100644 --- a/tcg/x86_64/tcg-target-con-set.h +++ b/tcg/x86_64/tcg-target-con-set.h @@ -42,6 +42,7 @@ C_O1_I2(r, 0, reZ) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) C_O1_I2(r, L, L) +C_O1_I2(r, r, d) C_O1_I2(r, r, r) C_O1_I2(r, r, re) C_O1_I2(r, r, ri) @@ -56,5 +57,6 @@ C_O1_I4(r, r, reT, r, 0) C_O1_I4(r, r, r, ri, ri) C_O2_I1(r, r, L) C_O2_I2(a, d, a, r) +C_O2_I2(r, r, r, d) C_O2_I2(r, r, L, L) C_O2_I3(a, d, 0, 1, r) diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 2c8f1f3e580..590c9c24020 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -274,6 +274,7 @@ static bool tcg_target_const_match(int64_t val, int ct, #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_MULX (0xf6 | P_SIMDF2 | P_EXT38) #define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) #define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) #define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) @@ -2732,19 +2733,48 @@ static const TCGOutOpBinary outop_mulsh =3D { .base.static_constraint =3D C_NotImplemented, }; =20 +static void tgen_muluh(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, TCGReg a2) +{ + /* + * Note from the architecture manual: + * If the first and second operand are identical, + * it will contain the high half of the multiplication result. + */ + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; + tcg_out_vex_modrm(s, OPC_MULX + rexw, a0, a0, a1); +} + +static TCGConstraintSetIndex cset_muluh(TCGType type, unsigned flags) +{ + return have_bmi2 ? C_O1_I2(r, r, d) : C_NotImplemented; +} + static const TCGOutOpBinary outop_muluh =3D { - .base.static_constraint =3D C_NotImplemented, + .base.static_constraint =3D C_Dynamic, + .base.dynamic_constraint =3D cset_muluh, + .out_rrr =3D tgen_muluh, }; =20 static void tgen_mulu2(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) { int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; - tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, a3); + if (have_bmi2) { + tcg_out_vex_modrm(s, OPC_MULX + rexw, a1, a0, a2); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, a3); + } +} + +static TCGConstraintSetIndex cset_mulu2(TCGType type, unsigned flags) +{ + return have_bmi2 ? C_O2_I2(r, r, r, d) : C_O2_I2(a, d, a, r); } =20 static const TCGOutOpMul2 outop_mulu2 =3D { - .base.static_constraint =3D C_O2_I2(a, d, a, r), + .base.static_constraint =3D C_Dynamic, + .base.dynamic_constraint =3D cset_mulu2, .out_rrrr =3D tgen_mulu2, }; =20 --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195838; cv=none; d=zohomail.com; s=zohoarc; b=PEEpO//fpWsYBLhFowrBWhCE4vjD6pySOs5NihzZUa0htBsWGjRECraOWzNwoZj4bxUXQUcbpHrTX6E9HTzF/xEEunAitx+k5QYrmj9STwB5+oKwvV2EiCou26AtGUfXDdO8rsA79vI6ScvdcLTbXSP7EFlZ9VbslUXH/Of0dDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195838; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iu9gCM+s0VdQe0NL+JCl/IZq6aTzQsY0y78oZAVciM8=; b=EJ63zs2l0bQwQfNOi9qPgCaiI1rjD9+PedV3AA8vx7PrqZ08DP6iuokS45u/bUpXsFnsNYbPquDk9iSXpRYs/1KH3mHPuu2LecI3zwDvuGiKYViV+dMzanu73SOwqAn46gam9jSfiAZ+XTQ2lIIvt5oEgWyDzpLrOikOXR0KObA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790195838439253.7446943939707; Wed, 23 Sep 2026 13:37:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Tgn-0008JP-FY; Wed, 23 Sep 2026 16:35:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9TgB-0008BZ-Tl for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:35:04 -0400 Received: from mail-pz2-x0f.google.com ([2607:f8b0:4864:3b::f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9Tg9-00051U-81 for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:59 -0400 Received: by mail-pz2-x0f.google.com with SMTP id d2e1a72fcca58-85469f20513so815991b3a.0 for ; Wed, 23 Sep 2026 13:34:56 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Also, assert vtype initialized for whole-register stores and moves. Fixes: f63e7089b4 ("tcg/riscv: Add basic support for vector") Reported-by: Max Chou Reviewed-by: Palmer Dabbelt Signed-off-by: Richard Henderson --- tcg/riscv64/tcg-target.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 2ce9d47a633..de9a3570b23 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -775,6 +775,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: + tcg_debug_assert(s->riscv_cur_type !=3D TCG_TYPE_COUNT); { int lmul =3D type - riscv_lg2_vlenb; int nf =3D 1 << MAX(lmul, 0); @@ -1014,6 +1015,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg arg, unsigned idx =3D type - riscv_lg2_vlenb; =20 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld)); + /* We must initialize vtype to something to avoid VILL. */ + if (s->riscv_cur_type =3D=3D TCG_TYPE_COUNT) { + set_vtype(s, type, MO_8); + } insn =3D whole_reg_ld[idx]; } else { static const RISCVInsn unit_stride_ld[] =3D { @@ -1046,6 +1051,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: + tcg_debug_assert(s->riscv_cur_type !=3D TCG_TYPE_COUNT); if (type >=3D riscv_lg2_vlenb) { static const RISCVInsn whole_reg_st[] =3D { OPC_VS1R_V, OPC_VS2R_V, OPC_VS4R_V, OPC_VS8R_V --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195887; cv=none; d=zohomail.com; s=zohoarc; b=DVi1iOBA3D1LflBEiS1FtntV9DpdjBnko1Zc1A/+IFOQVyq6YTOEEeiF9HIB5HDZiwVNJgCli78Ane8CDekMYHNby8qqPSYIVwe5uuUHmrdqaWygrz2EDk9OeFRPG+GliPUtV+7iCQRviSoePZQuEPGmPnhTbhPdCs8yE6AG100= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195887; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=z0hFSulIzG2frxbzSf/EGXrp3EDo/qS7TjkfOkfAqlY=; b=oCv0NlqxbErCK//+o/0v44pICm6aeyryoZXwuXE9EFA/5GwZwMh5hw0VcF3+a83/SWOPXUwrw3OtR/uyokpnNpXv7pt2faYfr7U2qhax+eDF2cSK9zmAIGm2qa3MBv1pQXOLlzrje2Z00Gv7P1P9R4gCV1GREKmyJUXjnRmpmsM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179019588735978.44314287621216; Wed, 23 Sep 2026 13:38:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Tgm-0008IP-Cl; Wed, 23 Sep 2026 16:35:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9TgD-0008Br-4g for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:35:04 -0400 Received: from mail-pz2-x0f.google.com ([2607:f8b0:4864:3b::f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9TgA-00051p-Bv for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:34:59 -0400 Received: by mail-pz2-x0f.google.com with SMTP id d2e1a72fcca58-8692a856865so648775b3a.2 for ; Wed, 23 Sep 2026 13:34:57 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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Reviewed-by: Matt Turner Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/accel/accel-cpu-ops.h | 2 +- include/system/hvf_int.h | 2 +- accel/hvf/hvf-accel-ops.c | 3 +-- accel/kvm/kvm-accel-ops.c | 4 ++-- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/accel/accel-cpu-ops.h b/include/accel/accel-cpu-ops.h index f0c7ee7542c..af71fd9ab34 100644 --- a/include/accel/accel-cpu-ops.h +++ b/include/accel/accel-cpu-ops.h @@ -85,7 +85,7 @@ struct AccelOpsClass { int64_t (*get_elapsed_ticks)(void); =20 /* gdbstub hooks */ - int (*update_guest_debug)(CPUState *cpu); + void (*update_guest_debug)(CPUState *cpu); int (*insert_gdbstub_breakpoint)(CPUState *cpu, GdbBreakpointType type, vaddr addr, vaddr len); int (*remove_gdbstub_breakpoint)(CPUState *cpu, GdbBreakpointType type, diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h index a01691ce172..1b419b5428a 100644 --- a/include/system/hvf_int.h +++ b/include/system/hvf_int.h @@ -105,7 +105,7 @@ void hvf_arch_remove_all_gdbstub_hw_breakpoints(void); * Update guest to enable or disable debugging. Per-arch specifics will be * handled by calling down to hvf_arch_update_guest_debug. */ -int hvf_update_guest_debug(CPUState *cpu); +void hvf_update_guest_debug(CPUState *cpu); =20 bool hvf_arch_cpu_realize(CPUState *cpu, Error **errp); uint32_t hvf_arch_get_default_ipa_bit_size(void); diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index d2276d8513e..6491a109ba4 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -227,10 +227,9 @@ static void do_hvf_update_guest_debug(CPUState *cpu, r= un_on_cpu_data arg) hvf_arch_update_guest_debug(cpu); } =20 -int hvf_update_guest_debug(CPUState *cpu) +void hvf_update_guest_debug(CPUState *cpu) { run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL); - return 0; } =20 static int hvf_insert_gdbstub_breakpoint(CPUState *cpu, GdbBreakpointType = type, diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index c8e7aa38709..47244d33f7d 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -86,9 +86,9 @@ static bool kvm_cpus_are_resettable(void) } =20 #ifdef TARGET_KVM_HAVE_GUEST_DEBUG -static int kvm_update_guest_debug_ops(CPUState *cpu) +static void kvm_update_guest_debug_ops(CPUState *cpu) { - return kvm_update_guest_debug(cpu, 0); + kvm_update_guest_debug(cpu, 0); } #endif =20 --=20 2.53.0 From nobody Sat Sep 26 19:16:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1790195785; cv=none; d=zohomail.com; s=zohoarc; b=B04XYkE3QE0C2lFJygWB+y5bG7PdbqPQeDAOR1lyT+w4ECyMK7qklfzTgrjVTtulTUPsuJXcuGOqITgjzQlXygd6NIjDWwlpYF/SAUpLAMU/1os8prjQOzKtIiLQfNLJLdcxCvGc4E4KXHxgyU6rjbz2/8NpPRRskyOQZ6gRU3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790195785; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jLp6ahCU93BTd2BLkEfZzfIJIRR9NWTXSUP87yd1ubw=; b=C2oDbT2UXEYxHlEvzmFh1AOwfk1VSUHp3ELWiP6jOGFsmv0KD/drce5XazCI2z118Ru1lc7hCMrCgunNHkVdaTQ2aJnP23EcaM1B0YsIvY1n3+KWlhkj+rU5x1vOhnGIApQbDWALPyFZEwq7a5Xfv4Igdy2IPZemJfvA0nQgyG8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17901957855051020.507957050153; Wed, 23 Sep 2026 13:36:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9Th3-0008WA-2f; Wed, 23 Sep 2026 16:35:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9TgD-0008Bw-I5 for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:35:06 -0400 Received: from mail-pz2-x0e.google.com ([2607:f8b0:4864:3b::e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x9TgA-00051y-Tj for qemu-devel@nongnu.org; Wed, 23 Sep 2026 16:35:01 -0400 Received: by mail-pz2-x0e.google.com with SMTP id 41be03b00d2f7-cc50bcf87b2so713638a12.1 for ; Wed, 23 Sep 2026 13:34:58 -0700 (PDT) Received: from stoup (174-21-68-150.tukw.qwest.net. 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It recomputes the same value every time: uint32_t cflags =3D cpu->tcg_cflags; if (unlikely(cpu_single_stepping(cpu))) { ... } else if (qatomic_read(&one_insn_per_tb)) { ... } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { ... } That is three loads and three branches on the hottest path in the interpreter, for state that changes only when gdb enables single-step, when one-insn-per-tb is toggled, or when the log mask changes. None of the three has to be sampled at dispatch time. Fold each into CPUState::tcg_cflags where it changes and curr_cflags() becomes a single load of a field that TB lookup has to read anyway. The derived bits -- CF_COUNT_MASK, CF_NO_GOTO_TB, CF_NO_GOTO_PTR and CF_SINGLE_STEP -- are never set by tcg_cflags_set(), so tcg_update_cflags() can recompute them in place without disturbing the rest, and conversely tcg_cflags_set() ORs in its bits without disturbing them. There are three places to call it: - tcg_exec_realizefn(), so that a CPU created after the command line has been parsed starts out with the right value. This covers user-only, where tcg_cpu_init_cflags() is not reached. linux-user's cpu_copy() copies tcg_cflags wholesale, so a cloned thread inherits it. - cpu_single_step(), which changes one CPU. gdb is the only caller that matters; in system mode it runs with the vCPUs stopped, and in user mode gdb_continue_partial() can reach a thread that is still running, because gdb_handlesig() stops only the thread that trapped. That is exactly the plain cross-thread store to another CPU's CPUState that cpu->singlestep_flags already was, read back by that CPU through cpu_single_stepping() in curr_cflags(). This patch changes which field carries it, not who writes it or how. - hmp_one_insn_per_tb() and hmp_log(), which change every CPU while the vCPUs are running, so the update is queued with async_run_on_cpu() and each CPU writes its own cflags from its own thread. The command line spellings of those two settings need nothing: they are parsed before any CPU is realized, so tcg_exec_realizefn() picks them up. Measured with qemu-alpha running an emulated alpha gcc 16.2.0 compiling the SQLite 3.45.1 amalgamation (255k lines, -O2) on an x86-64 host, in a build configured with --enable-lto: before: 1,646,994,254,249 instructions after: 1,562,204,796,597 instructions -5.15% That workload issues 8.4 billion dispatches, so the per-call saving is small but the aggregate is not. The emulated compiler produces byte-identical output before and after. Wall clock does not move: 133.19s to 132.58s, a 0.46% difference against a run-to-run spread larger than that. The removed work is a few predictable loads and branches that the host executes largely in parallel with the surrounding dispatch, so this patch is worth taking for the instruction count and for what it enables, not for a time saving that can be measured on its own. v4: Update the cflags from the HMP handlers for 'log' and 'one-insn-per-tb' rather than from qemu_set_log_internal() and the accelerator property setter. Those are the paths that reach a running vCPU, and the monitor is the only thing that does. Suggested by Richard Henderson. v4: Queue the per-CPU update with async_run_on_cpu() rather than async_safe_run_on_cpu(). Halting the other vCPUs buys nothing: the queued work already runs on the owning CPU's own thread. Suggested by Alex Bennee, who also asked whether there are cross-vCPU updates of tcg_cflags at all. With this change the monitor path has none: the only remaining writer from another thread is cpu_single_step(), above, which is neither new nor made worse here. v4: Move the stub to accel/stubs/, which is where the other accelerator stubs live. Signed-off-by: Matt Turner Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20260901034808.3524945-2-mattst88@gmail.com> --- accel/tcg/internal-common.h | 11 +++++++++-- include/system/tcg.h | 12 ++++++++++++ accel/tcg/cpu-exec-common.c | 37 ++++++++++++++++++++++++++++++++++--- accel/tcg/cpu-exec.c | 3 +++ accel/tcg/tcg-accel-ops.c | 1 + cpu-target.c | 5 ++++- monitor/hmp-cmds.c | 7 +++++++ system/runstate-hmp-cmds.c | 18 ++++++++++++------ 8 files changed, 82 insertions(+), 12 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 9e7be2d78df..853d1b51eeb 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -69,8 +69,15 @@ void tlb_destroy(CPUState *cpu); bool tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); =20 -/* current cflags for hashing/comparison */ -uint32_t curr_cflags(CPUState *cpu); +/* + * Current cflags for hashing/comparison. Everything that feeds into the + * value is folded into CPUState::tcg_cflags when it changes, by + * tcg_update_cflags(), so that TB dispatch only has to load it. + */ +static inline uint32_t curr_cflags(CPUState *cpu) +{ + return cpu->tcg_cflags; +} =20 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); =20 diff --git a/include/system/tcg.h b/include/system/tcg.h index 7622dcea302..2c2dbc753b3 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,6 +17,18 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif =20 +/* + * Recompute the parts of CPUState::tcg_cflags that TB dispatch consumes b= ut + * tcg_cflags_set() does not provide: gdb single-step, one-insn-per-tb and + * the CPU_LOG_TB_NOCHAIN log flag. Call whenever one of those changes. + * + * tcg_update_cflags() updates one CPU and must be called from that CPU's + * thread, or with it stopped. tcg_update_all_cflags() updates every CPU + * and is safe to call from the monitor while the vCPUs run. + */ +void tcg_update_cflags(CPUState *cpu); +void tcg_update_all_cflags(void); + /** * qemu_tcg_mttcg_enabled: * Check whether we are running MultiThread TCG or not. diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 44e84344f3b..68077c8fd9d 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -21,11 +21,19 @@ #include "exec/log.h" #include "system/tcg.h" #include "qemu/plugin.h" +#include "qemu/main-loop.h" #include "accel/tcg/cpu-loop.h" #include "internal-common.h" =20 bool tcg_allowed; =20 +/* + * The bits of CPUState::tcg_cflags that tcg_cflags_set() never sets, beca= use + * they are derived from gdb single-step, one-insn-per-tb and -d nochain. + */ +#define CF_DERIVED (CF_COUNT_MASK | CF_NO_GOTO_TB | CF_NO_GOTO_PTR | \ + CF_SINGLE_STEP) + bool tcg_cflags_has(CPUState *cpu, uint32_t flags) { return cpu->tcg_cflags & flags; @@ -33,12 +41,13 @@ bool tcg_cflags_has(CPUState *cpu, uint32_t flags) =20 void tcg_cflags_set(CPUState *cpu, uint32_t flags) { + assert((flags & CF_DERIVED) =3D=3D 0); cpu->tcg_cflags |=3D flags; } =20 -uint32_t curr_cflags(CPUState *cpu) +void tcg_update_cflags(CPUState *cpu) { - uint32_t cflags =3D cpu->tcg_cflags; + uint32_t cflags =3D cpu->tcg_cflags & ~CF_DERIVED; =20 /* * Record gdb single-step. We should be exiting the TB by raising @@ -55,7 +64,29 @@ uint32_t curr_cflags(CPUState *cpu) cflags |=3D CF_NO_GOTO_TB; } =20 - return cflags; + cpu->tcg_cflags =3D cflags; +} + +static void tcg_update_cflags_work(CPUState *cpu, run_on_cpu_data data) +{ + tcg_update_cflags(cpu); +} + +void tcg_update_all_cflags(void) +{ + CPUState *cpu; + + g_assert(bql_locked()); + + /* + * one-insn-per-tb and -d nochain can both be changed from the monitor + * while the vCPUs are running. Queue the update onto each CPU rather + * than writing tcg_cflags from here, so that the field is only ever + * written by the CPU that owns it. + */ + CPU_FOREACH(cpu) { + async_run_on_cpu(cpu, tcg_update_cflags_work, RUN_ON_CPU_NULL); + } } =20 /* exit the current TB, but without causing any exception to be raised */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 46b723cb734..5226cfb7650 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1071,6 +1071,9 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) tcg_target_initialized =3D true; } =20 + /* Pick up one-insn-per-tb and -d nochain from the command line. */ + tcg_update_cflags(cpu); + cpu->tb_jmp_cache =3D g_new0(CPUJumpCache, 1); tlb_init(cpu); #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 9c3d2214162..61e0051b53b 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -222,6 +222,7 @@ static void tcg_accel_ops_init(AccelClass *ac) ops->insert_gdbstub_breakpoint =3D tcg_insert_gdbstub_breakpoint; ops->remove_gdbstub_breakpoint =3D tcg_remove_gdbstub_breakpoint; ops->remove_all_gdbstub_breakpoints =3D tcg_remove_all_gdbstub_breakpo= ints; + ops->update_guest_debug =3D tcg_update_cflags; } =20 static void tcg_accel_ops_class_init(ObjectClass *oc, const void *data) diff --git a/cpu-target.c b/cpu-target.c index 4783845c9bf..9bd1605e831 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -24,6 +24,7 @@ #include "exec/replay-core.h" #include "exec/log.h" #include "hw/core/cpu.h" +#include "system/tcg.h" #include "trace/trace-root.h" =20 /* enable or disable single step mode. EXCP_DEBUG is returned by the @@ -35,7 +36,9 @@ void cpu_single_step(CPUState *cpu, unsigned flags) cpu->singlestep_flags, flags); cpu->singlestep_flags =3D flags; =20 -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + tcg_update_cflags(cpu); +#else const AccelOpsClass *ops =3D cpus_get_accel(); if (ops->update_guest_debug) { ops->update_guest_debug(cpu); diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index 91701ddf331..9b1b94f8ea9 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -40,6 +40,7 @@ #include "system/hw_accel.h" #include "system/memory.h" #include "system/system.h" +#include "system/tcg.h" #include "disas/disas.h" =20 /* Please update hmp-commands.hx when adding or changing commands */ @@ -340,6 +341,12 @@ void hmp_log(MonitorHMP *hmp, const QDict *qdict) =20 if (!qemu_set_log(mask, &err)) { error_report_err(err); + return; + } + + /* CPU_LOG_TB_NOCHAIN feeds into the per-CPU cflags. */ + if (tcg_enabled()) { + tcg_update_all_cflags(); } } =20 diff --git a/system/runstate-hmp-cmds.c b/system/runstate-hmp-cmds.c index ad70b53f8ab..eb34d14d062 100644 --- a/system/runstate-hmp-cmds.c +++ b/system/runstate-hmp-cmds.c @@ -22,6 +22,7 @@ #include "qapi/qapi-commands-run-state.h" #include "qobject/qdict.h" #include "qemu/accel.h" +#include "system/tcg.h" =20 void hmp_info_status(MonitorHMP *hmp, const QDict *qdict) { @@ -43,16 +44,17 @@ void hmp_info_status(MonitorHMP *hmp, const QDict *qdic= t) =20 void hmp_one_insn_per_tb(MonitorHMP *hmp, const QDict *qdict) { - const char *option =3D qdict_get_try_str(qdict, "option"); - AccelState *accel =3D current_accel(); + const char *option; + AccelState *accel; bool newval; =20 - if (!object_property_find(OBJECT(accel), "one-insn-per-tb")) { - monitor_hmp_printf(hmp, - "This accelerator does not support setting one-= insn-per-tb\n"); + if (!tcg_enabled()) { + monitor_hmp_printf(hmp, "This accelerator does not support " + "setting one-insn-per-tb\n"); return; } =20 + option =3D qdict_get_try_str(qdict, "option"); if (!option || !strcmp(option, "on")) { newval =3D true; } else if (!strcmp(option, "off")) { @@ -61,9 +63,13 @@ void hmp_one_insn_per_tb(MonitorHMP *hmp, const QDict *q= dict) monitor_hmp_printf(hmp, "unexpected option %s\n", option); return; } - /* If the property exists then setting it can never fail */ + + accel =3D current_accel(); object_property_set_bool(OBJECT(accel), "one-insn-per-tb", newval, &error_abort); + + /* one-insn-per-tb feeds into the per-CPU cflags. */ + tcg_update_all_cflags(); } =20 void hmp_watchdog_action(MonitorHMP *hmp, const QDict *qdict) --=20 2.53.0