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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::445; envelope-from=36uazagoKCuMXYFSQJdOMZLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--stanleyjhu.bounces.google.com; helo=mail-pf1-x445.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1790175005192158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Existing callers of ufs_clear_req() only invoke it after requests are no longer in flight. In preparation for Task Management Request (TMR) task abort and MCQ queue cleanup support, where individual in-flight requests are aborted without purging the entire SCSI device, track the active SCSIRequest in UfsRequest and cancel any pending request via scsi_req_cancel() in ufs_clear_req(). Signed-off-by: Stanley Jhu --- hw/ufs/lu.c | 8 ++++++++ hw/ufs/ufs.c | 6 ++++++ hw/ufs/ufs.h | 1 + 3 files changed, 15 insertions(+) diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c index bdb1650..5905c49 100644 --- a/hw/ufs/lu.c +++ b/hw/ufs/lu.c @@ -173,6 +173,9 @@ static void ufs_scsi_command_complete(SCSIRequest *scsi= _req, size_t resid) int16_t status =3D scsi_req->status; uint32_t transfered_len =3D scsi_req->cmd.xfer - resid; =20 + assert(req !=3D NULL); + req->sreq =3D NULL; + /* WB / HID accounting should only happen for successful commands */ if (status =3D=3D GOOD) { ufs_wb_process_write_req(req, transfered_len); @@ -190,6 +193,10 @@ static void ufs_scsi_command_complete(SCSIRequest *scs= i_req, size_t resid) =20 static void ufs_scsi_command_cancelled(SCSIRequest *scsi_req) { + UfsRequest *req =3D scsi_req->hba_private; + + assert(req !=3D NULL); + req->sreq =3D NULL; scsi_req->hba_private =3D NULL; scsi_req_unref(scsi_req); } @@ -389,6 +396,7 @@ static UfsReqResult ufs_process_scsi_cmd(UfsLu *lu, Ufs= Request *req) SCSIRequest *scsi_req =3D scsi_req_new(lu->scsi_dev, task_tag, lu->lun, req->req_upiu.sc.cdb, UFS_CDB_SIZE, req); + req->sreq =3D scsi_req; =20 uint32_t len =3D scsi_req_enqueue(scsi_req); if (len) { diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 3c4d742..adae663 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -2221,6 +2221,12 @@ void ufs_complete_req(UfsRequest *req, UfsReqResult = req_result) =20 static void ufs_clear_req(UfsRequest *req) { + if (req->sreq !=3D NULL) { + SCSIRequest *sreq =3D req->sreq; + req->sreq =3D NULL; + scsi_req_cancel(sreq); + } + if (req->sg !=3D NULL) { qemu_sglist_destroy(req->sg); g_free(req->sg); diff --git a/hw/ufs/ufs.h b/hw/ufs/ufs.h index 6f2693b..265a43f 100644 --- a/hw/ufs/ufs.h +++ b/hw/ufs/ufs.h @@ -60,6 +60,7 @@ typedef struct UfsRequest { UtpUpiuRsp rsp_upiu; =20 /* for scsi command */ + SCSIRequest *sreq; QEMUSGList *sg; uint32_t data_len; =20 --=20 2.56.0.rc1.310.g51773c2048-goog From nobody Sat Sep 26 20:01:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Implement Multi-Circular Queue (MCQ) runtime operational registers (SQnRTC, SQnRTS, SQnCTI, SQnIS/IE, CQnIS/IE, CQnIACR) per JEDEC UFSHCI: - Support SQ start, stop, and cleanup (SQnRTC.ICU) using Submission Queue Cleanup Task Information (SQnCTI) to abort the target request and post a CQE with OCS =3D UFS_OCS_ABORTED. - Implement write-1-to-clear per-queue interrupt status (SQnIS, CQnIS) and synchronize the global IS.CQES bit. - Reset MCQ runtime operational registers across HCE resets. Signed-off-by: Stanley Jhu --- hw/ufs/trace-events | 1 + hw/ufs/ufs.c | 111 +++++++++++++++++++++++++++++++++++++++++++- include/block/ufs.h | 15 ++++++ 3 files changed, 125 insertions(+), 2 deletions(-) diff --git a/hw/ufs/trace-events b/hw/ufs/trace-events index 9222933..d8173b1 100644 --- a/hw/ufs/trace-events +++ b/hw/ufs/trace-events @@ -14,6 +14,7 @@ ufs_process_uiccmd(uint32_t uiccmd, uint32_t ucmdarg1, ui= nt32_t ucmdarg2, uint32 ufs_mcq_complete_req(uint8_t qid) "sqid %"PRIu8"" ufs_mcq_create_sq(uint8_t sqid, uint8_t cqid, uint64_t addr, uint16_t size= ) "mcq create sq sqid %"PRIu8", cqid %"PRIu8", addr 0x%"PRIx64", size %"PRI= u16"" ufs_mcq_create_cq(uint8_t cqid, uint64_t addr, uint16_t size) "mcq create = cq cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16"" +ufs_write_mcq_op_reg(uint8_t qid, uint32_t offset, uint32_t data) "qid %"P= RIu8", offset 0x%"PRIx32", data 0x%"PRIx32"" ufs_hce_reset(void) "HCE 1 -> 0 reset: cancelling BHs, resetting MCQ and r= equest lists" =20 # error condition diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index adae663..4d8c641 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -446,13 +446,14 @@ static void ufs_mcq_process_sq(void *opaque) { UfsSq *sq =3D opaque; UfsHc *u =3D sq->u; + UfsMcqOpReg *opr =3D &u->mcq_op_reg[sq->sqid]; UfsSqEntry sqe; UfsRequest *req; hwaddr addr; uint16_t head =3D ufs_mcq_sq_head(u, sq->sqid); int err; =20 - if (u->resetting) { + if (u->resetting || FIELD_EX32(opr->sq.rts, SQRTS, STS)) { return; } =20 @@ -536,6 +537,7 @@ static void ufs_mcq_process_cq(void *opaque) } =20 ufs_clear_req(req); + req->state =3D UFS_REQUEST_IDLE; QTAILQ_INSERT_TAIL(&req->sq->req_list, req, entry); } =20 @@ -770,7 +772,17 @@ static void ufs_hce_reset(UfsHc *u) u->reg.utmrldbr =3D 0; u->reg.utrlcnr =3D 0; u->reg.utrlrsr =3D 0; + u->reg.utriacr =3D 0; + u->reg.utrlclr =3D 0; + if (u->params.mcq) { + u->reg.mcqconfig =3D FIELD_DP32(0, MCQCONFIG, MAC, 0x1f); + } else { + u->reg.mcqconfig =3D 0; + } + u->reg.ie =3D 0; u->reg.is =3D 0; + u->reg.utrlba =3D 0; + u->reg.utrlbau =3D 0; =20 /* 4. Free MCQ Queues and reset MCQ dynamic registers */ if (u->params.mcq) { @@ -970,6 +982,45 @@ static void ufs_mcq_process_db(UfsHc *u, uint8_t qid, = uint32_t db) qemu_bh_schedule(sq->bh); } =20 +static void ufs_mcq_sq_cleanup(UfsHc *u, uint8_t qid) +{ + UfsMcqOpReg *opr =3D &u->mcq_op_reg[qid]; + UfsSq *sq =3D u->sq[qid]; + uint8_t task_tag =3D FIELD_EX32(opr->sq.cti, SQCTI, TASK_TAG); + uint8_t lun =3D FIELD_EX32(opr->sq.cti, SQCTI, LUN); + UfsRequest *req =3D NULL; + + if (sq) { + for (int i =3D 0; i < sq->size; i++) { + UfsRequest *candidate =3D &sq->req[i]; + if ((candidate->state =3D=3D UFS_REQUEST_RUNNING || + candidate->state =3D=3D UFS_REQUEST_ERROR) && + candidate->req_upiu.header.task_tag =3D=3D task_tag && + candidate->req_upiu.header.lun =3D=3D lun) { + req =3D candidate; + break; + } + } + } + + if (req) { + if (req->sreq !=3D NULL) { + SCSIRequest *sreq =3D req->sreq; + req->sreq =3D NULL; + scsi_req_cancel(sreq); + } + req->utrd.header.dword_2 =3D cpu_to_le32( + (le32_to_cpu(req->utrd.header.dword_2) & ~UFS_MASK_OCS) | + UFS_OCS_ABORTED); + req->state =3D UFS_REQUEST_COMPLETE; + QTAILQ_INSERT_TAIL(&sq->cq->req_list, req, entry); + ufs_mcq_process_cq(sq->cq); + } + + opr->sq.rts =3D FIELD_DP32(opr->sq.rts, SQRTS, CUS, 1); + opr->sq.rts =3D FIELD_DP32(opr->sq.rts, SQRTS, RTC, 0); +} + static void ufs_write_mcq_op_reg(UfsHc *u, hwaddr offset, uint32_t data, unsigned size) { @@ -983,6 +1034,9 @@ static void ufs_write_mcq_op_reg(UfsHc *u, hwaddr offs= et, uint32_t data, =20 opr =3D &u->mcq_op_reg[qid]; =20 + trace_ufs_write_mcq_op_reg(qid, (uint32_t)(offset % sizeof(UfsMcqOpReg= )), + data); + switch (offset % sizeof(UfsMcqOpReg)) { case offsetof(UfsMcqOpReg, sq.tp): if (opr->sq.tp !=3D data) { @@ -990,6 +1044,40 @@ static void ufs_write_mcq_op_reg(UfsHc *u, hwaddr off= set, uint32_t data, } opr->sq.tp =3D data; break; + case offsetof(UfsMcqOpReg, sq.rtc): + if (FIELD_EX32(data, SQRTC, STOP)) { + /* SQ_STOP: Stop queue */ + opr->sq.rts =3D FIELD_DP32(opr->sq.rts, SQRTS, STS, 1); + if (u->sq[qid] && u->sq[qid]->bh) { + qemu_bh_cancel(u->sq[qid]->bh); + } + } else { + /* SQ_START: Start queue */ + opr->sq.rts =3D FIELD_DP32(opr->sq.rts, SQRTS, STS, 0); + opr->sq.rts =3D FIELD_DP32(opr->sq.rts, SQRTS, CUS, 0); + if (u->sq[qid] && u->sq[qid]->bh) { + qemu_bh_schedule(u->sq[qid]->bh); + } + } + if (FIELD_EX32(data, SQRTC, ICU)) { + if (FIELD_EX32(opr->sq.rts, SQRTS, STS)) { + /* SQ_ICU: Initiate Cleanup while queue is stopped */ + ufs_mcq_sq_cleanup(u, qid); + } + data =3D FIELD_DP32(data, SQRTC, ICU, 0); + } + opr->sq.rtc =3D data; + break; + case offsetof(UfsMcqOpReg, sq.cti): + opr->sq.cti =3D data; + break; + case offsetof(UfsMcqOpReg, sq_int.is): + opr->sq_int.is &=3D ~data; + ufs_irq_check(u); + break; + case offsetof(UfsMcqOpReg, sq_int.ie): + opr->sq_int.ie =3D data; + break; case offsetof(UfsMcqOpReg, cq.hp): { UfsCq *cq =3D u->cq[qid]; =20 @@ -1006,8 +1094,27 @@ static void ufs_write_mcq_op_reg(UfsHc *u, hwaddr of= fset, uint32_t data, ufs_mcq_update_cq_head(u, qid, data); break; } - case offsetof(UfsMcqOpReg, cq_int.is): + case offsetof(UfsMcqOpReg, cq_int.is): { + bool pending =3D false; + opr->cq_int.is &=3D ~data; + for (int i =3D 0; i < ARRAY_SIZE(u->mcq_op_reg); i++) { + if (u->mcq_op_reg[i].cq_int.is) { + pending =3D true; + break; + } + } + if (!pending) { + u->reg.is =3D FIELD_DP32(u->reg.is, IS, CQES, 0); + } + ufs_irq_check(u); + break; + } + case offsetof(UfsMcqOpReg, cq_int.ie): + opr->cq_int.ie =3D data; + break; + case offsetof(UfsMcqOpReg, cq_int.iacr): + opr->cq_int.iacr =3D data; break; default: trace_ufs_err_invalid_register_offset(offset); diff --git a/include/block/ufs.h b/include/block/ufs.h index d19b3c6..b72403c 100644 --- a/include/block/ufs.h +++ b/include/block/ufs.h @@ -224,6 +224,21 @@ typedef struct QEMU_PACKED UfsMcqSqReg { uint32_t rts; } UfsMcqSqReg; =20 +REG32(SQRTC, offsetof(UfsMcqSqReg, rtc)) + FIELD(SQRTC, STOP, 0, 1) + FIELD(SQRTC, ICU, 1, 1) + +REG32(SQCTI, offsetof(UfsMcqSqReg, cti)) + FIELD(SQCTI, TASK_TAG, 0, 8) + FIELD(SQCTI, LUN, 8, 8) + FIELD(SQCTI, IID, 16, 4) + FIELD(SQCTI, EXT_IID, 20, 4) + +REG32(SQRTS, offsetof(UfsMcqSqReg, rts)) + FIELD(SQRTS, STS, 0, 1) + FIELD(SQRTS, CUS, 1, 1) + FIELD(SQRTS, RTC, 4, 4) + typedef struct QEMU_PACKED UfsMcqCqReg { uint32_t hp; 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charset="utf-8" Implement UTP Task Management Request List (UTMRL) doorbell and TMR processing per JEDEC UFSHCI: - Support UTMRLDBR, UTMRLCLR (clear-on-zero), and UTMRLRSR registers. - Handle UFS_QUERY_TASK and UFS_ABORT_TASK across legacy UTRL and MCQ queues. For MCQ, UFS_ABORT_TASK cancels the active SCSIRequest and defers CQE posting (OCS =3D UFS_OCS_ABORTED) and slot recycling to subsequent SQRTC.ICU cleanup. - Reset UTMRL operational registers on HCE reset. Signed-off-by: Stanley Jhu --- hw/ufs/trace-events | 1 + hw/ufs/ufs.c | 129 +++++++++++++++++++++++++++++++++++++++++++- include/block/ufs.h | 1 + 3 files changed, 130 insertions(+), 1 deletion(-) diff --git a/hw/ufs/trace-events b/hw/ufs/trace-events index d8173b1..5e5a54a 100644 --- a/hw/ufs/trace-events +++ b/hw/ufs/trace-events @@ -15,6 +15,7 @@ ufs_mcq_complete_req(uint8_t qid) "sqid %"PRIu8"" ufs_mcq_create_sq(uint8_t sqid, uint8_t cqid, uint64_t addr, uint16_t size= ) "mcq create sq sqid %"PRIu8", cqid %"PRIu8", addr 0x%"PRIx64", size %"PRI= u16"" ufs_mcq_create_cq(uint8_t cqid, uint64_t addr, uint16_t size) "mcq create = cq cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16"" ufs_write_mcq_op_reg(uint8_t qid, uint32_t offset, uint32_t data) "qid %"P= RIu8", offset 0x%"PRIx32", data 0x%"PRIx32"" +ufs_process_tmr(uint8_t func, uint32_t tag, uint8_t resp) "query_func 0x%"= PRIx8", task_tag %"PRIu32", tm_resp 0x%"PRIx8"" ufs_hce_reset(void) "HCE 1 -> 0 reset: cancelling BHs, resetting MCQ and r= equest lists" =20 # error condition diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 4d8c641..336bdb8 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -772,8 +772,10 @@ static void ufs_hce_reset(UfsHc *u) u->reg.utmrldbr =3D 0; u->reg.utrlcnr =3D 0; u->reg.utrlrsr =3D 0; + u->reg.utmrlrsr =3D 0; u->reg.utriacr =3D 0; u->reg.utrlclr =3D 0; + u->reg.utmrlclr =3D 0; if (u->params.mcq) { u->reg.mcqconfig =3D FIELD_DP32(0, MCQCONFIG, MAC, 0x1f); } else { @@ -783,6 +785,8 @@ static void ufs_hce_reset(UfsHc *u) u->reg.is =3D 0; u->reg.utrlba =3D 0; u->reg.utrlbau =3D 0; + u->reg.utmrlba =3D 0; + u->reg.utmrlbau =3D 0; =20 /* 4. Free MCQ Queues and reset MCQ dynamic registers */ if (u->params.mcq) { @@ -819,6 +823,119 @@ static void ufs_hce_reset(UfsHc *u) ufs_irq_check(u); } =20 +static UfsRequest *ufs_find_req_by_tag(UfsHc *u, uint8_t lun, uint32_t tas= k_tag) +{ + if (task_tag < u->params.nutrs) { + UfsRequest *req =3D &u->req_list[task_tag]; + if ((req->state =3D=3D UFS_REQUEST_RUNNING || + req->state =3D=3D UFS_REQUEST_READY) && + req->req_upiu.header.lun =3D=3D lun && + req->req_upiu.header.task_tag =3D=3D task_tag) { + return req; + } + } + + if (u->params.mcq) { + for (int q =3D 0; q < ARRAY_SIZE(u->sq); q++) { + UfsSq *sq =3D u->sq[q]; + if (!sq) { + continue; + } + for (int i =3D 0; i < sq->size; i++) { + UfsRequest *req =3D &sq->req[i]; + if (req->state =3D=3D UFS_REQUEST_RUNNING && + req->req_upiu.header.lun =3D=3D lun && + req->req_upiu.header.task_tag =3D=3D task_tag) { + return req; + } + } + } + } + + return NULL; +} + +static void ufs_process_tmr(UfsHc *u, uint32_t val) +{ + hwaddr base_addr =3D (((hwaddr)u->reg.utmrlbau) << 32) + u->reg.utmrlb= a; + uint32_t completed_mask =3D 0; + + u->reg.utmrldbr |=3D val; + + for (int i =3D 0; i < u->params.nutmrs; i++) { + if (val & (1 << i)) { + uint64_t desc_addr =3D base_addr + i * sizeof(UtpTaskReqDesc); + UtpTaskReqDesc desc; + uint8_t tm_func, tm_resp, lun; + uint32_t task_tag; + + if (ufs_addr_read(u, desc_addr, &desc, sizeof(desc))) { + continue; + } + + tm_func =3D desc.upiu_req.req_header.query_func; + lun =3D desc.upiu_req.req_header.lun; + task_tag =3D be32_to_cpu(desc.upiu_req.input_param2); + + if (tm_func =3D=3D UFS_QUERY_TASK) { + UfsRequest *req =3D ufs_find_req_by_tag(u, lun, task_tag); + + if (req) { + tm_resp =3D UFS_UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED; + } else { + tm_resp =3D UFS_UPIU_TASK_MANAGEMENT_FUNC_COMPL; + } + } else if (tm_func =3D=3D UFS_ABORT_TASK) { + UfsRequest *req =3D ufs_find_req_by_tag(u, lun, task_tag); + + if (req) { + if (ufs_mcq_req(req)) { + if (req->sreq !=3D NULL) { + SCSIRequest *sreq =3D req->sreq; + req->sreq =3D NULL; + scsi_req_cancel(sreq); + } + req->state =3D UFS_REQUEST_ERROR; + } else { + ufs_clear_req(req); + req->state =3D UFS_REQUEST_IDLE; + u->reg.utrldbr &=3D ~(1 << req->slot); + } + } + tm_resp =3D UFS_UPIU_TASK_MANAGEMENT_FUNC_COMPL; + } else { + tm_resp =3D UFS_UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED; + } + + memset(&desc.upiu_rsp, 0, sizeof(desc.upiu_rsp)); + desc.header.dword_2 =3D cpu_to_le32( + (le32_to_cpu(desc.header.dword_2) & ~UFS_MASK_OCS) | + UFS_OCS_SUCCESS); + desc.upiu_rsp.rsp_header.trans_type =3D + UFS_UPIU_TRANSACTION_TASK_RSP; + desc.upiu_rsp.rsp_header.flags =3D 0; + desc.upiu_rsp.rsp_header.lun =3D desc.upiu_req.req_header.lun; + desc.upiu_rsp.rsp_header.task_tag =3D + desc.upiu_req.req_header.task_tag; + desc.upiu_rsp.rsp_header.response =3D tm_resp; + desc.upiu_rsp.output_param1 =3D cpu_to_be32(tm_resp); + + if (ufs_addr_write(u, desc_addr, &desc, sizeof(desc))) { + continue; + } + + trace_ufs_process_tmr(tm_func, task_tag, tm_resp); + u->reg.utmrldbr &=3D ~(1 << i); + completed_mask |=3D (1 << i); + } + } + + if (completed_mask) { + u->reg.is =3D FIELD_DP32(u->reg.is, IS, UTMRCS, 1); + ufs_irq_check(u); + } +} + static void ufs_write_reg(UfsHc *u, hwaddr offset, uint32_t data, unsigned= size) { switch (offset) { @@ -881,10 +998,20 @@ static void ufs_write_reg(UfsHc *u, hwaddr offset, ui= nt32_t data, unsigned size) case A_MCQCONFIG: u->reg.mcqconfig =3D data; break; - case A_UTRLCLR: case A_UTMRLDBR: + if (!FIELD_EX32(u->reg.hce, HCE, HCE) || + !FIELD_EX32(u->reg.utmrlrsr, UTMRLRSR, UTMRLRSR)) { + break; + } + ufs_process_tmr(u, data); + break; case A_UTMRLCLR: + u->reg.utmrldbr &=3D data; + break; case A_UTMRLRSR: + u->reg.utmrlrsr =3D data; + break; + case A_UTRLCLR: trace_ufs_err_unsupport_register_offset(offset); break; default: diff --git a/include/block/ufs.h b/include/block/ufs.h index b72403c..b051532 100644 --- a/include/block/ufs.h +++ b/include/block/ufs.h @@ -141,6 +141,7 @@ REG32(UTMRLBAU, offsetof(UfsReg, utmrlbau)) REG32(UTMRLDBR, offsetof(UfsReg, utmrldbr)) REG32(UTMRLCLR, offsetof(UfsReg, utmrlclr)) REG32(UTMRLRSR, offsetof(UfsReg, utmrlrsr)) + FIELD(UTMRLRSR, UTMRLRSR, 0, 1) REG32(UICCMD, offsetof(UfsReg, uiccmd)) REG32(UCMDARG1, offsetof(UfsReg, ucmdarg1)) REG32(UCMDARG2, offsetof(UfsReg, ucmdarg2)) --=20 2.56.0.rc1.310.g51773c2048-goog