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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1790113904110158500 Content-Type: text/plain; charset="utf-8" When a PASID-capable device is added behind the PCIe downstream port, for example, an Nvidia GPU, the PCIe downstream ports must expose ACS capability otherwise PASID won't get enabled. In addition, the other use case is GPUDirect RDMA using Data Direct that must require special ACS controls at the PCIe downstream ports for P2P communication. Gate it behind a new x-pcie-acs property (default on), following the x-pcie-* compat-bit convention (x-pcie-ext-tag/x-pcie-err-unc-mask/ x-pcie-ari-nextfn-1), so older machine types can disable it via hw_compat to preserve migration compatibility. Signed-off-by: Tushar Dave --- hw/core/machine.c | 1 + hw/pci-bridge/xio3130_downstream.c | 7 +++++++ hw/pci/pci.c | 2 ++ include/hw/pci/pci.h | 3 +++ 4 files changed, 13 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index 92f7be52a1..4fd48f594f 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -43,6 +43,7 @@ GlobalProperty hw_compat_11_1[] =3D { { "sysbus-ehci-usb", "x-migrate-fetch-addr-64bit", "off" }, { "pci-ehci-usb", "x-migrate-fetch-addr-64bit", "off" }, + { TYPE_PCI_DEVICE, "x-pcie-acs", "off" }, /* Added in 11.2 */ }; const size_t hw_compat_11_1_len =3D G_N_ELEMENTS(hw_compat_11_1); =20 diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 0c3fed3053..87ba30eb36 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -40,6 +40,8 @@ #define XIO3130_SSVID_SSID 0 #define XIO3130_EXP_OFFSET 0x90 #define XIO3130_AER_OFFSET 0x100 +#define XIO3130_ACS_OFFSET \ + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF) =20 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) @@ -60,6 +62,7 @@ static void xio3130_downstream_reset(DeviceState *qdev) pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); pcie_cap_arifwd_reset(d); + pcie_acs_reset(d); pci_bridge_reset(qdev); } =20 @@ -111,6 +114,10 @@ static void xio3130_downstream_realize(PCIDevice *d, E= rror **errp) goto err; } =20 + if (d->cap_present & QEMU_PCIE_CAP_ACS) { + pcie_acs_init(d, XIO3130_ACS_OFFSET); + } + return; =20 err: diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 0efb4eb4bb..807729ca75 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -105,6 +105,8 @@ static const Property pci_props[] =3D { DEFINE_PROP_STRING("sriov-pf", PCIDevice, sriov_pf), DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present, QEMU_PCIE_EXT_TAG_BITNR, true), + DEFINE_PROP_BIT("x-pcie-acs", PCIDevice, cap_present, + QEMU_PCIE_ACS_BITNR, true), { .name =3D "busnr", .info =3D &prop_pci_busnr }, }; =20 diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index f2448e941a..dd52b9639e 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -231,6 +231,9 @@ enum { QEMU_PCI_CAP_PM =3D (1 << QEMU_PCI_CAP_PM_BITNR), #define QEMU_PCI_SKIP_RESET_ON_CPR_BITNR 15 QEMU_PCI_SKIP_RESET_ON_CPR =3D (1 << QEMU_PCI_SKIP_RESET_ON_CPR_BITNR), + /* PCIe ACS (Access Control Services) extended capability present */ +#define QEMU_PCIE_ACS_BITNR 16 + QEMU_PCIE_CAP_ACS =3D (1 << QEMU_PCIE_ACS_BITNR), }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1790113904078158500 Content-Type: text/plain; charset="utf-8" From: Yishai Hadas To support P2P on Guest we must expose to the guest OS the actual PCIe topology and configuration as set by the HYP. Otherwise, the behavior is considered as un-defined. It might fail by SW or HW. Extend both root port and downstream port to get acs ctrl bits that should match the HYP and use them in the guest. Signed-off-by: Yishai Hadas Signed-off-by: Tushar Dave --- hw/pci-bridge/pcie_root_port.c | 10 ++++++++-- hw/pci-bridge/xio3130_downstream.c | 10 ++++++++-- hw/pci/pcie.c | 18 +++++++++++++++--- include/hw/pci/pcie.h | 6 +++--- include/hw/pci/pcie_port.h | 1 + 5 files changed, 35 insertions(+), 10 deletions(-) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 7c3e78010b..3ae0b75146 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -46,6 +46,7 @@ static void rp_write_config(PCIDevice *d, uint32_t addres= s, static void rp_reset_hold(Object *obj, ResetType type) { PCIDevice *d =3D PCI_DEVICE(obj); + PCIEPort *p =3D PCIE_PORT(d); DeviceState *qdev =3D DEVICE(obj); =20 rp_aer_vector_update(d); @@ -53,7 +54,7 @@ static void rp_reset_hold(Object *obj, ResetType type) pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); pcie_cap_arifwd_reset(d); - pcie_acs_reset(d); + pcie_acs_reset(d, p->acs_ctrl); pcie_aer_root_reset(d); pci_bridge_reset(qdev); pci_bridge_disable_base_limit(d); @@ -118,11 +119,15 @@ static void rp_realize(PCIDevice *d, Error **errp) rp_aer_vector_update(d); =20 if (rpc->acs_offset) { - pcie_acs_init(d, rpc->acs_offset); + rc =3D pcie_acs_init(d, rpc->acs_offset, p->acs_ctrl, errp); + if (rc < 0) { + goto err; + } } return; =20 err: + pcie_aer_exit(d); pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); @@ -151,6 +156,7 @@ static void rp_exit(PCIDevice *d) static const Property rp_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_UINT16("acs-ctrl", PCIEPort, acs_ctrl, 0), }; =20 static void rp_instance_post_init(Object *obj) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 87ba30eb36..9829832c39 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -58,11 +58,12 @@ static void xio3130_downstream_write_config(PCIDevice *= d, uint32_t address, static void xio3130_downstream_reset(DeviceState *qdev) { PCIDevice *d =3D PCI_DEVICE(qdev); + PCIEPort *p =3D PCIE_PORT(d); =20 pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); pcie_cap_arifwd_reset(d); - pcie_acs_reset(d); + pcie_acs_reset(d, p->acs_ctrl); pci_bridge_reset(qdev); } =20 @@ -115,12 +116,16 @@ static void xio3130_downstream_realize(PCIDevice *d, = Error **errp) } =20 if (d->cap_present & QEMU_PCIE_CAP_ACS) { - pcie_acs_init(d, XIO3130_ACS_OFFSET); + rc =3D pcie_acs_init(d, XIO3130_ACS_OFFSET, p->acs_ctrl, errp); + if (rc < 0) { + goto err; + } } =20 return; =20 err: + pcie_aer_exit(d); pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); @@ -144,6 +149,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d) static const Property xio3130_downstream_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_UINT16("acs-ctrl", PCIEPort, acs_ctrl, 0), }; =20 static const VMStateDescription vmstate_xio3130_downstream =3D { diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 42bcb9206d..c36f8c58c6 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1260,7 +1260,8 @@ void pcie_ats_init(PCIDevice *dev, uint16_t offset, b= ool aligned) } =20 /* ACS (Access Control Services) */ -void pcie_acs_init(PCIDevice *dev, uint16_t offset) +int pcie_acs_init(PCIDevice *dev, uint16_t offset, uint16_t ctrl_bits, + Error **errp) { bool is_downstream =3D pci_is_express_downstream_port(dev); uint16_t cap_bits =3D 0; @@ -1284,16 +1285,27 @@ void pcie_acs_init(PCIDevice *dev, uint16_t offset) */ cap_bits =3D PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; + + if (ctrl_bits & ~cap_bits) { + error_setg(errp, + "Unsupported ACS capabilities 0x%hx were supplied. " + "Supported capabilities are 0x%hx", + ctrl_bits & ~cap_bits, cap_bits); + return -EINVAL; + } } =20 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); + pci_set_word(dev->config + offset + PCI_ACS_CTRL, ctrl_bits); + + return 0; } =20 -void pcie_acs_reset(PCIDevice *dev) +void pcie_acs_reset(PCIDevice *dev, uint16_t val) { if (dev->exp.acs_cap) { - pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); + pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, val); } } =20 diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index ec25e7a7de..1ab7b3eee5 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -137,9 +137,9 @@ bool pcie_insert_capability(PCIDevice *dev, uint16_t ca= p_id, uint8_t cap_ver, uint16_t offset, uint16_t size); void pcie_sync_bridge_lnk(PCIDevice *dev); =20 -void pcie_acs_init(PCIDevice *dev, uint16_t offset); -void pcie_acs_reset(PCIDevice *dev); - +int pcie_acs_init(PCIDevice *dev, uint16_t offset, uint16_t ctrl_bits, + Error **errp); +void pcie_acs_reset(PCIDevice *dev, uint16_t val); void pcie_ari_init(PCIDevice *dev, uint16_t offset); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_n= um); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index b28af067a6..2ad9a563d9 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -36,6 +36,7 @@ struct PCIEPort { =20 /* pci express switch port */ uint8_t port; + uint16_t acs_ctrl; }; =20 void pcie_port_init_reg(PCIDevice *d); --=20 2.34.1 From nobody Sat Sep 26 20:00:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1790113919; 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From: Tushar Dave To: qemu-devel@nongnu.org Cc: mst@redhat.com, philmd@oss.qualcomm.com, zhao1.liu@intel.com, yishaih@nvidia.com, alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com Subject: [PATCH 3/3] hw/pci: Make ACS Control read-only to guests Date: Tue, 22 Sep 2026 16:50:08 -0500 Message-Id: <20260922215008.2554402-4-tdave@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260922215008.2554402-1-tdave@nvidia.com> References: <20260922215008.2554402-1-tdave@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PH0P220CA0022.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:d3::21) To IA3PR12MB923065.namprd12.prod.outlook.com (2603:10b6:208:627::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA3PR12MB923065:EE_|PH0PR12MB8126:EE_ X-MS-Office365-Filtering-Correlation-Id: cf7ff600-dbd6-4202-0291-08df18f3807c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|366016|23010399003|376014|1800799024|10067099003|56012099006|6133799003|18002099003|22082099003|11063799006; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1790113919748158500 Content-Type: text/plain; charset="utf-8" GPUDirect RDMA using data-direct requires a specific ACS configuration on PCIe Root Ports and Downstream Ports. While ACS can be configured via QEMU's 'acs-ctrl' property, the guest kernel may overwrite ACS during standard programming. This change blocks all guest writes to the PCIe ACS Control register and preserves QEMU-provided ACS settings across device resets on PCIe Root Ports and Downstream Ports. Signed-off-by: Tushar Dave --- hw/pci-bridge/pcie_root_port.c | 3 +- hw/pci-bridge/xio3130_downstream.c | 3 +- hw/pci/pcie.c | 45 ++++++++++++++++++++++++++++-- include/hw/pci/pcie.h | 3 ++ include/hw/pci/pcie_port.h | 1 + 5 files changed, 51 insertions(+), 4 deletions(-) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 3ae0b75146..784697b1ca 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -156,7 +156,8 @@ static void rp_exit(PCIDevice *d) static const Property rp_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), - DEFINE_PROP_UINT16("acs-ctrl", PCIEPort, acs_ctrl, 0), + DEFINE_PROP_UNSIGNED_NODEFAULT("acs-ctrl", PCIEPort, acs_ctrl, + qdev_prop_acs_ctrl, uint16_t), }; =20 static void rp_instance_post_init(Object *obj) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 9829832c39..e8717be73a 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -149,7 +149,8 @@ static void xio3130_downstream_exitfn(PCIDevice *d) static const Property xio3130_downstream_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), - DEFINE_PROP_UINT16("acs-ctrl", PCIEPort, acs_ctrl, 0), + DEFINE_PROP_UNSIGNED_NODEFAULT("acs-ctrl", PCIEPort, acs_ctrl, + qdev_prop_acs_ctrl, uint16_t), }; =20 static const VMStateDescription vmstate_xio3130_downstream =3D { diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index c36f8c58c6..08e21022e5 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1265,6 +1265,8 @@ int pcie_acs_init(PCIDevice *dev, uint16_t offset, ui= nt16_t ctrl_bits, { bool is_downstream =3D pci_is_express_downstream_port(dev); uint16_t cap_bits =3D 0; + PCIEPort *p =3D PCIE_PORT(dev); + bool configured =3D p->acs_ctrl_configured; =20 /* For endpoints, only multifunction devs may have an ACS capability: = */ assert(is_downstream || @@ -1286,7 +1288,7 @@ int pcie_acs_init(PCIDevice *dev, uint16_t offset, ui= nt16_t ctrl_bits, cap_bits =3D PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; =20 - if (ctrl_bits & ~cap_bits) { + if (configured && (ctrl_bits & ~cap_bits)) { error_setg(errp, "Unsupported ACS capabilities 0x%hx were supplied. " "Supported capabilities are 0x%hx", @@ -1296,7 +1298,17 @@ int pcie_acs_init(PCIDevice *dev, uint16_t offset, u= int16_t ctrl_bits, } =20 pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); - pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); + + if (is_downstream && configured) { + /* + * Block guest writes to ACS Control entirely to preserve QEMU + * ACS settings + */ + pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, 0); + } else { + pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); + } + pci_set_word(dev->config + offset + PCI_ACS_CTRL, ctrl_bits); =20 return 0; @@ -1309,6 +1321,35 @@ void pcie_acs_reset(PCIDevice *dev, uint16_t val) } } =20 +static void set_acs_ctrl(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCIEPort *p =3D PCIE_PORT(obj); + const Property *prop =3D opaque; + uint16_t *ptr =3D object_field_prop_ptr(obj, prop); + + if (!visit_type_uint16(v, name, ptr, errp)) { + return; + } + p->acs_ctrl_configured =3D true; +} + +static void get_acs_ctrl(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const Property *prop =3D opaque; + uint16_t *ptr =3D object_field_prop_ptr(obj, prop); + + visit_type_uint16(v, name, ptr, errp); +} + +const PropertyInfo qdev_prop_acs_ctrl =3D { + .type =3D "uint16", + .description =3D "PCIe ACS ctrl configuration (unset =3D not configure= d)", + .get =3D get_acs_ctrl, + .set =3D set_acs_ctrl, +}; + void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, bool exec_perm, bool priv= _mod) { diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 1ab7b3eee5..b1d5e8ae20 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -26,6 +26,7 @@ #include "hw/pci/pcie_aer.h" #include "hw/pci/pcie_sriov.h" #include "hw/core/hotplug.h" +#include "hw/core/qdev-properties.h" =20 typedef struct PCIEPort PCIEPort; typedef struct PCIESlot PCIESlot; @@ -86,6 +87,8 @@ struct PCIExpressDevice { =20 #define COMPAT_PROP_PCP "power_controller_present" =20 +extern const PropertyInfo qdev_prop_acs_ctrl; + /* PCI express capability helper functions */ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port, Error **errp); diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 2ad9a563d9..ef2c2ec2cd 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -37,6 +37,7 @@ struct PCIEPort { /* pci express switch port */ uint8_t port; uint16_t acs_ctrl; + bool acs_ctrl_configured; }; =20 void pcie_port_init_reg(PCIDevice *d); --=20 2.34.1