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Mon, 21 Sep 2026 07:29:19 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [RFC PATCH] target/arm: fix user-mode emulation of ID_AA64MMFR0_EL1 Date: Mon, 21 Sep 2026 15:29:10 +0100 Message-ID: <20260921142910.1462880-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=alex.bennee@linaro.org; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1790001072621158500 Since kernel commit b130a8f70cbbf9 (KVM: arm64: Check advertised Stage-2 page size capability) the relevant Stage 2 have been pegged at 1 f(4KB granule not supported at stage 2) by the kernel. As a result the behaviour of the test differs when run on real HW compared to under emulation: id_aa64mmfr0_el1 : 0x00000111ff000000 !!extra bits!! : 0x0000011100000000 Update the test with a new helper to explicitly test for fixed bits and update v8_user_idregs to match real systems. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4566 Signed-off-by: Alex Benn=C3=A9e --- target/arm/helper.c | 7 +++++-- tests/tcg/aarch64/sysregs.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 33 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c3f607e6d6b..7e65f072a4a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6902,8 +6902,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) R_ID_AA64FPFR0_F8CVT_MASK }, { .name =3D "ID_AA64MMFR0_EL1", .exported_bits =3D R_ID_AA64MMFR0_ECV_MASK, - .fixed_bits =3D (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) | - (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, + .fixed_bits =3D (0xfULL << R_ID_AA64MMFR0_TGRAN64_SHIFT) | + (0xfULL << R_ID_AA64MMFR0_TGRAN4_SHIFT) | + (0x1ULL << R_ID_AA64MMFR0_TGRAN4_2_SHIFT) | + (0x1ULL << R_ID_AA64MMFR0_TGRAN64_2_SHIFT) | + (0x1ULL << R_ID_AA64MMFR0_TGRAN16_2_SHIFT) }, { .name =3D "ID_AA64MMFR1_EL1", .exported_bits =3D R_ID_AA64MMFR1_AFP_MASK }, { .name =3D "ID_AA64MMFR2_EL1", diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c index 301e61d0dd4..8f7c5303f77 100644 --- a/tests/tcg/aarch64/sysregs.c +++ b/tests/tcg/aarch64/sysregs.c @@ -54,6 +54,23 @@ int failed_bit_count; } \ }) =20 +/* As above but also check that required fixed bits have expected values */ +#define get_cpu_reg_check_fixed(id, allowed_mask, fixed_mask, expected_val= ) ({ \ + unsigned long __cval =3D get_cpu_reg(id); \ + unsigned long __extra =3D __cval & ~(allowed_mask); \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); = \ + failed_bit_count++; \ + } \ + if ((__cval & (fixed_mask)) !=3D (expected_val)) { \ + printf("%-20s: 0x%016llx (expected fixed 0x%016llx)\n", \ + " !!fixed mismatch!!", \ + (unsigned long long)(__cval & (fixed_mask)), \ + (unsigned long long)(expected_val)); \ + failed_bit_count++; \ + } \ +}) + /* As above but check RAZ */ #define get_cpu_reg_check_zero(id) ({ \ unsigned long __val =3D 0xdeadbeef; \ @@ -127,8 +144,16 @@ int main(void) get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0)); get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff)); get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(00ff,0000,00ff,ffff)); - /* TGran4 & TGran64 as pegged to -1 */ - get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000)); + /* + * TGran4 & TGran64 are pegged to -1 (0xf). + * Stage 2 translation granule support (TGran4_2, TGran64_2, TGran16_2) + * are pegged to safe value 1 as exposed by Linux kernel since + * b130a8f70cbbf9 (KVM: arm64: Check advertised Stage-2 page size capa= bility). + */ + get_cpu_reg_check_fixed(id_aa64mmfr0_el1, + _m(f000, 0111, ff00, 0000), + _m(0000, 0111, ff00, 0000), + _m(0000, 0111, ff00, 0000)); get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000)); get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000)); /* EL1/EL0 reported as AA64 only */ @@ -179,7 +204,7 @@ int main(void) } =20 if (failed_bit_count > 0) { - printf("Extra information leaked to user-space!\n"); + printf("Bit check failure or extra info leaked to user-space!\n"); return 1; } =20 --=20 2.47.3