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Sun, 20 Sep 2026 22:10:06 -0700 (PDT) From: Jacob Whitaker Abrams X-Google-Original-From: Jacob Whitaker Abrams To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Jacob Whitaker Abrams , Samuel Tardieu , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Fabiano Rosas , Laurent Vivier , qemu-arm@nongnu.org (open list:STM32L4x5 SoC Family) Subject: [PATCH v2] hw/char/stm32l4x5_usart.c: Support 16-bit writes Date: Sun, 20 Sep 2026 22:09:59 -0700 Message-ID: <20260921050959.1876719-1-satur9nine@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:3b::14; envelope-from=jwhitakera@gmail.com; helo=mail-pz2-x14.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789967462663158500 Content-Type: text/plain; charset="utf-8" Official STM32CubeL4 drivers use and require support for 16-bit writes to UART registers for proper function despite datasheet claims. Signed-off-by: Jacob Whitaker Abrams --- v2: - Remove all changes other than supporting 16-bit writes UART regs hw/char/stm32l4x5_usart.c | 4 ++-- tests/qtest/stm32l4x5_usart-test.c | 22 +++++++++++++++++++++- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index dd1b099195..3b9883bb23 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -521,12 +521,12 @@ static const MemoryRegionOps stm32l4x5_usart_base_ops= =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .max_access_size =3D 4, - .min_access_size =3D 4, + .min_access_size =3D 2, .unaligned =3D false }, .impl =3D { .max_access_size =3D 4, - .min_access_size =3D 4, + .min_access_size =3D 2, .unaligned =3D false }, }; diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usa= rt-test.c index a72c5a685d..3c6437e75d 100644 --- a/tests/qtest/stm32l4x5_usart-test.c +++ b/tests/qtest/stm32l4x5_usart-test.c @@ -332,6 +332,26 @@ static void test_ack(void) qtest_quit(qts); } =20 +static void test_16bit_access(void) +{ + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + + /* GTPR is declared uint16_t in the official STM driver. */ + qtest_writew(qts, USART1_BASE_ADDR + A_GTPR, 0xABCD); + uint16_t gtpr16 =3D qtest_readw(qts, USART1_BASE_ADDR + A_GTPR); + g_assert_cmpuint(gtpr16, =3D=3D, 0xABCD); + + /* TDR is uint16_t and r/w, register is 9-bits */ + qtest_writew(qts, USART1_BASE_ADDR + A_TDR, 0x01CD); + uint16_t tdr16 =3D qtest_readw(qts, USART1_BASE_ADDR + A_TDR); + g_assert_cmpuint(tdr16, =3D=3D, 0x01CD); + + /* RDR is uint16_t and read only, register is 9-bits */ + qtest_writew(qts, USART1_BASE_ADDR + A_RDR, 0x01FA); + + qtest_quit(qts); +} + static void check_clock(QTestState *qts, const char *path, uint32_t rcc_re= g, uint32_t reg_offset) { @@ -370,6 +390,6 @@ int main(int argc, char **argv) qtest_add_func("stm32l4x5/usart/send_str", test_send_str); qtest_add_func("stm32l4x5/usart/ack", test_ack); qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable); + qtest_add_func("stm32l4x5/usart/16bit_access", test_16bit_access); return g_test_run(); } - --=20 2.43.0