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Fri, 18 Sep 2026 13:10:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Max Chou Subject: [PATCH] tcg/riscv64: Set vtype before whole-register vector loads Date: Fri, 18 Sep 2026 10:10:07 -1000 Message-ID: <20260918201007.153384-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:39::11; envelope-from=richard.henderson@linaro.org; helo=mail-pj2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1789762250306158500 Content-Type: text/plain; charset="utf-8" With vtype uninitialized, VILL might be set, leading to SIGILL. Also, assert vtype initialized for whole-register stores and moves. Cc: Palmer Dabbelt Reported-by: Max Chou Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- tcg/riscv64/tcg-target.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/riscv64/tcg-target.c.inc b/tcg/riscv64/tcg-target.c.inc index 2ce9d47a633..de9a3570b23 100644 --- a/tcg/riscv64/tcg-target.c.inc +++ b/tcg/riscv64/tcg-target.c.inc @@ -775,6 +775,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: + tcg_debug_assert(s->riscv_cur_type !=3D TCG_TYPE_COUNT); { int lmul =3D type - riscv_lg2_vlenb; int nf =3D 1 << MAX(lmul, 0); @@ -1014,6 +1015,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, = TCGReg arg, unsigned idx =3D type - riscv_lg2_vlenb; =20 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld)); + /* We must initialize vtype to something to avoid VILL. */ + if (s->riscv_cur_type =3D=3D TCG_TYPE_COUNT) { + set_vtype(s, type, MO_8); + } insn =3D whole_reg_ld[idx]; } else { static const RISCVInsn unit_stride_ld[] =3D { @@ -1046,6 +1051,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, case TCG_TYPE_V64: case TCG_TYPE_V128: case TCG_TYPE_V256: + tcg_debug_assert(s->riscv_cur_type !=3D TCG_TYPE_COUNT); if (type >=3D riscv_lg2_vlenb) { static const RISCVInsn whole_reg_st[] =3D { OPC_VS1R_V, OPC_VS2R_V, OPC_VS4R_V, OPC_VS8R_V --=20 2.53.0