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Fri, 18 Sep 2026 03:12:00 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf Subject: [PATCH v8 1/7] hw/misc: Add Beckhoff CCAT device Date: Fri, 18 Sep 2026 12:11:52 +0200 Message-ID: <20260918101158.42101-2-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789726420867158500 Content-Type: text/plain; charset="utf-8" From: YannickV This adds the Beckhoff Communication Controller (CCAT). The information block, EEPROM interface and DMA controller are currently implemented. The EEPROM provides production information for Beckhoff Devices. An EEPORM binary must therefor be handed over. It should be aligned to a power of two. If no EEPROM binary is handed over an empty EEPROM of size 4096 is initialized. This device is needed for the Beckhoff CX7200 board emulation. Signed-off-by: YannickV --- hw/misc/Kconfig | 2 + hw/misc/beckhoff_ccat.c | 347 ++++++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 350 insertions(+) create mode 100644 hw/misc/beckhoff_ccat.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 46e3c03cc8df..605833829b0a 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -261,6 +261,8 @@ config AXIADO_CLK bool =20 config K230_DECOMP_GZIP + +config BECKHOFF_CCAT bool =20 source macio/Kconfig diff --git a/hw/misc/beckhoff_ccat.c b/hw/misc/beckhoff_ccat.c new file mode 100644 index 000000000000..58c38f3b1df1 --- /dev/null +++ b/hw/misc/beckhoff_ccat.c @@ -0,0 +1,347 @@ +/* + * Beckhoff Communication Controller Emulation + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/sysbus.h" +#include "qemu/units.h" +#include "hw/core/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "system/block-backend.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "system/dma.h" +#include "qemu/error-report.h" +#include "block/block.h" +#include "block/block_int.h" +#include "block/qdict.h" +#include "hw/block/block.h" +#include "migration/vmstate.h" +#include "qemu/bswap.h" + +#ifndef CCAT_ERR_DEBUG +#define CCAT_ERR_DEBUG 0 +#endif + +#define TYPE_BECKHOFF_CCAT "beckhoff-ccat" +OBJECT_DECLARE_SIMPLE_TYPE(BeckhoffCcat, BECKHOFF_CCAT) + +#define MAX_NUM_SLOTS 32 +#define CCAT_FUNCTION_BLOCK_SIZE 16 + +#define CCAT_EEPROM_OFFSET 0x100 +#define CCAT_DMA_OFFSET 0x8000 + +#define CCAT_MEM_SIZE (64 * KiB) +#define CCAT_DMA_SIZE 0x800 +#define CCAT_EEPROM_SIZE 0x20 + +#define EEPROM_MEMORY_SIZE 0x1000 + +#define EEPROM_CMD_OFFSET (CCAT_EEPROM_OFFSET + 0x00) + #define EEPROM_CMD_WRITE_MASK 0x2 + #define EEPROM_CMD_READ_MASK 0x1 +#define EEPROM_ADR_OFFSET (CCAT_EEPROM_OFFSET + 0x04) +#define EEPROM_DATA_OFFSET (CCAT_EEPROM_OFFSET + 0x08) + +#define DMA_BUFFER_OFFSET (CCAT_DMA_OFFSET + 0x00) +#define DMA_DIRECTION_OFFSET (CCAT_DMA_OFFSET + 0x7c0) + #define DMA_DIRECTION_MASK 1 +#define DMA_TRANSFER_OFFSET (CCAT_DMA_OFFSET + 0x7c4) +#define DMA_HOST_ADR_OFFSET (CCAT_DMA_OFFSET + 0x7c8) +#define DMA_TRANSFER_LENGTH_OFFSET (CCAT_DMA_OFFSET + 0x7cc) + +/* + * The information block is always located at address 0x0. + * Address and size are therefore replaced by two identifiers. + * The Parameter give information about the maximal number of + * function slots and the creation date (in this case 01.01.2001) + */ +#define CCAT_ID_1 0x88a4 +#define CCAT_ID_2 0x54414343 +#define CCAT_INFO_BLOCK_PARAMS ((MAX_NUM_SLOTS << 0) | (0x1 << 8) | \ + (0x1 << 16) | (0x1 << 24)) + +#define CCAT_FUN_TYPE_ENTRY 0x0001 +#define CCAT_FUN_TYPE_EEPROM 0x0012 +#define CCAT_FUN_TYPE_DMA 0x0013 + +typedef struct BeckhoffCcat { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint8_t mem[CCAT_MEM_SIZE]; + + BlockBackend *eeprom_blk; + uint8_t *eeprom_storage; + uint32_t eeprom_size; +} BeckhoffCcat; + +static void sync_eeprom(BeckhoffCcat *s) +{ + if (!s->eeprom_blk) { + return; + } + blk_pwrite(s->eeprom_blk, 0, s->eeprom_size, s->eeprom_storage, 0); +} + +static uint64_t beckhoff_ccat_eeprom_read(void *opaque, hwaddr addr, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_eeprom_write(void *opaque, hwaddr addr, uint64_t= val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + uint64_t eeprom_adr; + uint64_t buf; + uint32_t bytes_to_read; + + switch (addr) { + case EEPROM_CMD_OFFSET: + eeprom_adr =3D ldl_le_p(&s->mem[EEPROM_ADR_OFFSET]); + eeprom_adr =3D (eeprom_adr * 2) % s->eeprom_size; + if (val & EEPROM_CMD_READ_MASK) { + buf =3D 0; + bytes_to_read =3D 8; + if (eeprom_adr > s->eeprom_size - 8) { + bytes_to_read =3D s->eeprom_size - eeprom_adr; + } + buf =3D ldn_le_p(s->eeprom_storage + eeprom_adr, bytes_to_read= ); + stq_le_p(&s->mem[EEPROM_DATA_OFFSET], buf); + } else if (val & EEPROM_CMD_WRITE_MASK) { + buf =3D ldl_le_p(&s->mem[EEPROM_DATA_OFFSET]); + stw_le_p((s->eeprom_storage + eeprom_adr), buf); + sync_eeprom(s); + } + break; + default: + stn_le_p(&s->mem[addr], size, val); + } +} + +static uint64_t beckhoff_ccat_dma_read(void *opaque, hwaddr addr, unsigned= size) +{ + BeckhoffCcat *s =3D opaque; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + /* + * Real hardware keeps the 0x1 bit set while the DMA transfer is + * running. Complete the emulated transfer only after software has + * observed that intermediate state, since Beckhoff drivers expect= the DMA + * transfer not to finish immediately. + */ + if (s->mem[DMA_TRANSFER_OFFSET] & 0x1) { + s->mem[DMA_TRANSFER_OFFSET] =3D 0; + } + break; + } + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_dma_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + dma_addr_t dma_addr; + uint8_t len; + uint8_t *mem_buf; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + len =3D s->mem[DMA_TRANSFER_LENGTH_OFFSET]; + mem_buf =3D &s->mem[DMA_BUFFER_OFFSET]; + dma_addr =3D ldl_le_p(&s->mem[DMA_HOST_ADR_OFFSET]); + if (s->mem[DMA_DIRECTION_OFFSET] & DMA_DIRECTION_MASK) { + dma_memory_read(&address_space_memory, dma_addr, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } else { + /* + * The write transfer uses Host DMA Address + 8 as the target + * offset, as described in the CCAT manual Version 0.0.41 + * section 20.2. + */ + dma_memory_write(&address_space_memory, dma_addr + 8, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } + break; + } + stn_le_p(&s->mem[addr], size, val); +} + +static uint64_t beckhoff_ccat_read(void *opaque, hwaddr addr, unsigned siz= e) +{ + BeckhoffCcat *s =3D opaque; + uint64_t val =3D 0; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + return beckhoff_ccat_eeprom_read(opaque, addr, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + return beckhoff_ccat_dma_read(opaque, addr, size); + } else { + val =3D ldn_le_p(&s->mem[addr], size); + } + + return val; +} + +static void beckhoff_ccat_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + beckhoff_ccat_eeprom_write(opaque, addr, val, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + beckhoff_ccat_dma_write(opaque, addr, val, size); + } else { + stn_le_p(&s->mem[addr], size, val); + } +} + +static const MemoryRegionOps beckhoff_ccat_ops =3D { + .read =3D beckhoff_ccat_read, + .write =3D beckhoff_ccat_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static void beckhoff_ccat_reset_hold(Object *obj, ResetType type) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(obj); + + memset(&s->mem[0], 0, MAX_NUM_SLOTS * CCAT_FUNCTION_BLOCK_SIZE); + + size_t offset =3D 0 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_ENTRY); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], CCAT_INFO_BLOCK_PARAMS); + stl_le_p(&s->mem[offset + 8], CCAT_ID_1); + stl_le_p(&s->mem[offset + 12], CCAT_ID_2); + + offset =3D 11 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_EEPROM); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_EEPROM_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_EEPROM_SIZE); + + offset =3D 15 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_DMA); + stw_le_p(&s->mem[offset + 2], 0x0000); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_DMA_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_DMA_SIZE); +} + +static void beckhoff_ccat_realize(DeviceState *dev, Error **errp) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + BlockBackend *blk; + + blk =3D s->eeprom_blk; + + if (blk) { + uint64_t blk_size =3D blk_getlength(blk); + if (!is_power_of_2(blk_size)) { + error_setg(errp, "Blockend size is not a power of two."); + return; + } + + if (blk_size < 512) { + error_setg(errp, "Blockend size is too small."); + return; + } else { + blk_set_perm(blk, BLK_PERM_WRITE, BLK_PERM_ALL, errp); + + s->eeprom_size =3D blk_size; + s->eeprom_blk =3D blk; + s->eeprom_storage =3D blk_blockalign(s->eeprom_blk, s->eeprom_= size); + + if (!blk_check_size_and_read_all(s->eeprom_blk, DEVICE(s), + s->eeprom_storage, s->eeprom_= size, + errp)) { + return; + } + } + } else { + s->eeprom_size =3D EEPROM_MEMORY_SIZE; + s->eeprom_storage =3D blk_blockalign(NULL, s->eeprom_size); + memset(s->eeprom_storage, 0x00, s->eeprom_size); + } +} + +static void beckhoff_ccat_init(Object *obj) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &beckhoff_ccat_ops, s, + TYPE_BECKHOFF_CCAT, CCAT_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_beckhoff_ccat =3D { + .name =3D "beckhoff-ccat", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8_ARRAY(mem, BeckhoffCcat, CCAT_MEM_SIZE), + VMSTATE_UINT32(eeprom_size, BeckhoffCcat), + VMSTATE_VBUFFER_UINT32(eeprom_storage, BeckhoffCcat, 1, NULL, + eeprom_size), + VMSTATE_END_OF_LIST() + } +}; + +static const Property beckhoff_ccat_properties[] =3D { + DEFINE_PROP_DRIVE("eeprom", BeckhoffCcat, eeprom_blk), +}; + +static void beckhoff_ccat_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D beckhoff_ccat_realize; + rc->phases.hold =3D beckhoff_ccat_reset_hold; + dc->vmsd =3D &vmstate_beckhoff_ccat; + device_class_set_props(dc, beckhoff_ccat_properties); +} + +static const TypeInfo beckhoff_ccat_info =3D { + .name =3D TYPE_BECKHOFF_CCAT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BeckhoffCcat), + .instance_init =3D beckhoff_ccat_init, + .class_init =3D beckhoff_ccat_class_init, +}; + +static void beckhoff_ccat_register_types(void) +{ + type_register_static(&beckhoff_ccat_info); +} + +type_init(beckhoff_ccat_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 9790afa1044f..7b808d56860e 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -16,6 +16,7 @@ system_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l= 2x0.c')) system_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integra= tor_debug.c')) system_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) system_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) +system_ss.add(when: 'CONFIG_BECKHOFF_CCAT', if_true: files('beckhoff_ccat.= c')) =20 system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) =20 --=20 2.47.3 From nobody Sat Sep 26 22:15:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 18 Sep 2026 03:12:02 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf Subject: [PATCH v8 2/7] hw/arm/xilinx_zynq: Add flash type as machine class property Date: Fri, 18 Sep 2026 12:11:53 +0200 Message-ID: <20260918101158.42101-3-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789726456861158500 Content-Type: text/plain; charset="utf-8" From: YannickV Introduce ZynqMachineClass with qspi_flash_type field to allow different Zynq-based machines to specify their flash device type. The base Zynq machine defaults to n25q128. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 19 ++++++++++++++----- include/hw/arm/xilinx_zynq.h | 8 +++++++- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index c1897ab1cf33..31d5b5e5caa5 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -117,7 +117,8 @@ static void gem_init(uint32_t base, qemu_irq irq) } =20 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi, int unit0) + bool is_qspi, int unit0, + const char *flash_type) { int unit =3D unit0; DeviceState *dev; @@ -149,7 +150,8 @@ static inline int zynq_init_spi_flashes(uint32_t base_a= ddr, qemu_irq irq, =20 for (j =3D 0; j < num_ss; ++j) { DriveInfo *dinfo =3D drive_get(IF_MTD, 0, unit++); - flash_dev =3D qdev_new("n25q128"); + + flash_dev =3D qdev_new(flash_type); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -201,6 +203,7 @@ static void ddr_ctrl_init(uint32_t base) static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); + ZynqMachineClass *zmc =3D ZYNQ_MACHINE_GET_CLASS(machine); MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); DeviceState *dev, *slcr; @@ -280,9 +283,12 @@ static void zynq_init(MachineState *machine) pic[n] =3D qdev_get_gpio_in(dev, n); } =20 - n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0); - n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n); - n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n); + n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0, + zmc->qspi_flash_type); + n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n, + zmc->qspi_flash_type); + n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n, + zmc->qspi_flash_type); =20 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]= ); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]= ); @@ -458,6 +464,7 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); + ZynqMachineClass *zmc =3D ZYNQ_MACHINE_CLASS(oc); ObjectProperty *prop; mc->desc =3D "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; @@ -471,11 +478,13 @@ static void zynq_machine_class_init(ObjectClass *oc, = const void *data) "Supported boot modes:" " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); + zmc->qspi_flash_type =3D "n25q128"; } =20 static const TypeInfo zynq_machine_type =3D { .name =3D TYPE_ZYNQ_MACHINE, .parent =3D TYPE_MACHINE, + .class_size =3D sizeof(ZynqMachineClass), .class_init =3D zynq_machine_class_init, .instance_size =3D sizeof(ZynqMachineState), }; diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index 669c516ad150..33a68cdcd15e 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -12,12 +12,13 @@ #ifndef QEMU_ARM_ZYNQ_H #define QEMU_ARM_ZYNQ_H =20 +#include "hw/core/boards.h" #include "target/arm/cpu-qom.h" #include "hw/core/qdev-clock.h" #include "hw/arm/boot.h" =20 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") -OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) +OBJECT_DECLARE_TYPE(ZynqMachineState, ZynqMachineClass, ZYNQ_MACHINE) =20 #define ZYNQ_MAX_CPUS 2 =20 @@ -29,4 +30,9 @@ struct ZynqMachineState { struct arm_boot_info bootinfo; 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Fri, 18 Sep 2026 03:12:03 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf Subject: [PATCH v8 3/7] hw/misc/zynq_slcr: Add CPU clock outputs and ratios Date: Fri, 18 Sep 2026 12:11:54 +0200 Message-ID: <20260918101158.42101-4-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789726476920158501 Content-Type: text/plain; charset="utf-8" From: YannickV Add CPU clock outputs and derive the related domains from the base CPU clock ratio. This makes the CPU clock domains visible and keeps their ratios consistent with the hardware clock tree. Signed-off-by: YannickV --- hw/misc/zynq_slcr.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d0f899c3be4d..86f8685d2b2e 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -61,6 +61,13 @@ REG32(DDR_PLL_CFG, 0x114) REG32(IO_PLL_CFG, 0x118) =20 REG32(ARM_CLK_CTRL, 0x120) + FIELD(ARM_CLK_CTRL, CPU_PERI_CLKACT, 28, 1); + FIELD(ARM_CLK_CTRL, CPU_1XCLKACT, 27, 1); + FIELD(ARM_CLK_CTRL, CPU_2XCLKACT, 26, 1); + FIELD(ARM_CLK_CTRL, CPU_3OR2XCLKACT, 25, 1); + FIELD(ARM_CLK_CTRL, CPU_6OR4XCLKACT, 24, 1); + FIELD(ARM_CLK_CTRL, DIVISOR, 8, 6); + FIELD(ARM_CLK_CTRL, SRCSEL, 4, 2); REG32(DDR_CLK_CTRL, 0x124) REG32(DCI_CLK_CTRL, 0x128) REG32(APER_CLK_CTRL, 0x12c) @@ -98,6 +105,7 @@ FPGA_CTRL_REGS(3, 0x1a0) REG32(BANDGAP_TRIP, 0x1b8) REG32(PLL_PREDIVISOR, 0x1c0) REG32(CLK_621_TRUE, 0x1c4) + FIELD(CLK_621_TRUE, CLK_621_TRUE, 0, 1) =20 REG32(PSS_RST_CTRL, 0x200) FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1) @@ -206,6 +214,10 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + Clock *cpu_1x; + Clock *cpu_2x; + Clock *cpu_3x2x; + Clock *cpu_6x4x; uint8_t boot_mode; }; =20 @@ -286,14 +298,31 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLC= RState *s, uint64_t ps_clk) uint64_t io_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTR= L]); uint64_t arm_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_C= TRL]); uint64_t ddr_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_C= TRL]); + uint64_t cpu_base; =20 uint64_t uart_mux[4] =3D {io_pll, io_pll, arm_pll, ddr_pll}; + uint64_t cpu_mux[4] =3D {arm_pll, arm_pll, ddr_pll, io_pll}; + + bool use_621 =3D FIELD_EX32(s->regs[R_CLK_621_TRUE], CLK_621_TRUE, + CLK_621_TRUE); + /* Select 6:2:1 (true) or 4:2:1 (false) CPU clock ratios. */ + uint32_t ratio_6x4x =3D use_621 ? 6 : 4; + uint32_t ratio_3x2x =3D use_621 ? 3 : 2; + =20 /* compute uartX reference clocks */ clock_set(s->uart0_ref_clk, ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); clock_set(s->uart1_ref_clk, ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); + + /* Base is CPU clock (6x/4x domain). Derive other CPU domains via rati= os. */ + cpu_base =3D ZYNQ_COMPUTE_CLK(s, cpu_mux, R_ARM_CLK_CTRL, CPU_6OR4XCLK= ACT); + + clock_set(s->cpu_6x4x, cpu_base); + clock_set(s->cpu_3x2x, cpu_base * ratio_6x4x / ratio_3x2x); + clock_set(s->cpu_2x, cpu_base * ratio_6x4x / 2); + clock_set(s->cpu_1x, cpu_base * ratio_6x4x); } =20 /** @@ -322,6 +351,10 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *= s) { clock_propagate(s->uart0_ref_clk); clock_propagate(s->uart1_ref_clk); + clock_propagate(s->cpu_1x); + clock_propagate(s->cpu_2x); + clock_propagate(s->cpu_3x2x); + clock_propagate(s->cpu_6x4x); } =20 static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) @@ -619,6 +652,10 @@ static const ClockPortInitArray zynq_slcr_clocks =3D { QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, ClockU= pdate), QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_1x), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_2x), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_3x2x), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_6x4x), QDEV_CLOCK_END }; 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Fri, 18 Sep 2026 03:12:04 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf Subject: [PATCH v8 4/7] hw/timer, cpu: Add Clock API support to A9MPCore timers Date: Fri, 18 Sep 2026 12:11:55 +0200 Message-ID: <20260918101158.42101-5-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1789726465013158500 Content-Type: text/plain; charset="utf-8" From: YannickV Add a clock input to a9gtimer, arm_mptimer and a9mpcore. a9mpcore distributes the clock to the other timers. If no clock is connected, falls back to 100 MHz for backward compatibility with existing machine types. Frequency calculation now uses the input clock and prescaler values according to ARM Cortex-A9 MPCore Technical Reference Manual. More information about the A9MPCore timers can be found here: https://developer.arm.com/documentation/ddi0407/c/timers-and-watchdog-regis= ters?lang=3Den Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 1 + hw/cpu/a9mpcore.c | 12 ++++++++++ hw/timer/a9gtimer.c | 42 +++++++++++++++++++++++++++++----- hw/timer/arm_mptimer.c | 19 +++++++++++---- include/hw/cpu/a9mpcore.h | 1 + include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 7 files changed, 67 insertions(+), 11 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 31d5b5e5caa5..f7190118f7ff 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -265,6 +265,7 @@ static void zynq_init(MachineState *machine) dev =3D qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); + qdev_connect_clock_in(dev, "clk", qdev_get_clock_out(slcr, "cpu_3x2x")= ); busdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 2127f9557892..5ffdc9277b4a 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -14,6 +14,8 @@ #include "hw/cpu/a9mpcore.h" #include "hw/core/irq.h" #include "hw/core/qdev-properties.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/clock.h" #include "hw/core/cpu.h" #include "target/arm/cpu-qom.h" =20 @@ -42,6 +44,13 @@ static void a9mp_priv_initfn(Object *obj) object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); =20 object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); + + /* + * Register a clock input. If no clock is connected the + * frequency falls back to 100 MHz for backward compatibility. + */ + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL, 0); + clock_set_ns(s->clk, 10); } =20 static void a9mp_priv_realize(DeviceState *dev, Error **errp) @@ -103,6 +112,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error *= *errp) =20 gtimerdev =3D DEVICE(&s->gtimer); qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); + qdev_connect_clock_in(gtimerdev, "clk", s->clk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) { return; } @@ -110,6 +120,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error *= *errp) =20 mptimerdev =3D DEVICE(&s->mptimer); qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + qdev_connect_clock_in(mptimerdev, "clk", s->clk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { return; } @@ -117,6 +128,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error *= *errp) =20 wdtdev =3D DEVICE(&s->wdt); qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); + qdev_connect_clock_in(wdtdev, "clk", s->clk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) { return; } diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 3a086915c817..6c6b7afb398c 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -24,6 +24,9 @@ #include "hw/core/hw-error.h" #include "hw/core/irq.h" #include "hw/core/qdev-properties.h" +#include "hw/core/qdev-properties-system.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/clock.h" #include "hw/timer/a9gtimer.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -60,12 +63,30 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerSta= te *s) return current_cpu->cpu_index; } =20 -static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) +static inline uint32_t a9_gtimer_get_prescale(A9GTimerState *s) { - uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, - R_CONTROL_PRESCALER_LEN); + return extract32(s->control, R_CONTROL_PRESCALER_SHIFT, + R_CONTROL_PRESCALER_LEN) + 1; +} =20 - return (prescale + 1) * 10; +static inline uint64_t a9_gtimer_ns_to_ticks(A9GTimerState *s, uint64_t ns) +{ + assert(!(s->control & R_CONTROL_TIMER_ENABLE) || clock_get(s->clk) != =3D 0); + + return clock_ns_to_ticks(s->clk, ns) / + a9_gtimer_get_prescale(s); +} + +static inline uint64_t a9_gtimer_ticks_to_ns(A9GTimerState *s, uint64_t ti= cks) +{ + uint32_t prescale =3D a9_gtimer_get_prescale(s); + + assert(!(s->control & R_CONTROL_TIMER_ENABLE) || clock_get(s->clk) != =3D 0); + if (ticks > UINT64_MAX / prescale) { + return INT64_MAX; + } + + return clock_ticks_to_ns(s->clk, ticks * prescale); } =20 static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s) @@ -74,7 +95,7 @@ static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState = *s) =20 ret.now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); ret.new =3D s->ref_counter + - (ret.now - s->cpu_ref_time) / a9_gtimer_get_conv(s); + a9_gtimer_ns_to_ticks(s, ret.now - s->cpu_ref_time); return ret; } =20 @@ -117,7 +138,8 @@ static void a9_gtimer_update(A9GTimerState *s, bool syn= c) if (next_cdiff) { DB_PRINT("scheduling qemu_timer to fire again in %" PRIx64 " cycles\n", next_cdiff); - timer_mod(s->timer, update.now + next_cdiff * a9_gtimer_get_conv(s= )); + timer_mod(s->timer, update.now + + a9_gtimer_ticks_to_ns(s, next_cdiff)); } =20 if (s->control & R_CONTROL_TIMER_ENABLE) { @@ -295,6 +317,13 @@ static void a9_gtimer_reset(DeviceState *dev) a9_gtimer_update(s, false); } =20 +static void a9_gtimer_init(Object *obj) +{ + A9GTimerState *s =3D A9_GTIMER(obj); + + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL, 0); +} + static void a9_gtimer_realize(DeviceState *dev, Error **errp) { A9GTimerState *s =3D A9_GTIMER(dev); @@ -391,6 +420,7 @@ static const TypeInfo a9_gtimer_info =3D { .name =3D TYPE_A9_GTIMER, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(A9GTimerState), + .instance_init =3D a9_gtimer_init, .class_init =3D a9_gtimer_class_init, }; =20 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 88158144b23f..6802ca29c927 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -24,9 +24,13 @@ #include "hw/core/irq.h" #include "hw/core/ptimer.h" #include "hw/core/qdev-properties.h" +#include "hw/core/qdev-properties-system.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/clock.h" #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -58,10 +62,12 @@ static inline void timerblock_update_irq(TimerBlock *tb) qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); } =20 -/* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ -static inline uint32_t timerblock_scale(uint32_t control) +static inline void timerblock_set_period(TimerBlock *tb, uint32_t control) { - return (((control >> 8) & 0xff) + 1) * 10; + uint32_t prescale =3D (((control >> 8) & 0xff) + 1); + + assert((control & 1) =3D=3D 0 || clock_get(tb->clk) !=3D 0); + ptimer_set_period_from_clock(tb->timer, tb->clk, prescale); } =20 /* Must be called within a ptimer transaction block */ @@ -155,7 +161,7 @@ static void timerblock_write(void *opaque, hwaddr addr, ptimer_stop(tb->timer); } if ((control & 0xff00) !=3D (value & 0xff00)) { - ptimer_set_period(tb->timer, timerblock_scale(value)); + timerblock_set_period(tb, value); } if (value & 1) { uint64_t count =3D ptimer_get_count(tb->timer); @@ -222,7 +228,7 @@ static void timerblock_reset(TimerBlock *tb) ptimer_transaction_begin(tb->timer); ptimer_stop(tb->timer); ptimer_set_limit(tb->timer, 0, 1); - ptimer_set_period(tb->timer, timerblock_scale(0)); + timerblock_set_period(tb, 0); ptimer_transaction_commit(tb->timer); } } @@ -244,6 +250,8 @@ static void arm_mptimer_init(Object *obj) memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s, "arm_mptimer_timer", 0x20); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL, 0); } =20 static void arm_mptimer_realize(DeviceState *dev, Error **errp) @@ -269,6 +277,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) */ for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; + tb->clk =3D s->clk; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h index 60765990247b..11b4b7cfe952 100644 --- a/include/hw/cpu/a9mpcore.h +++ b/include/hw/cpu/a9mpcore.h @@ -34,6 +34,7 @@ struct A9MPPrivState { A9GTimerState gtimer; ARMMPTimerState mptimer; ARMMPTimerState wdt; + Clock *clk; }; =20 #endif diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 5c9b048b9545..ef198a969e75 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -87,6 +87,7 @@ struct A9GTimerState { uint32_t control; /* only non per cpu banked bits valid */ =20 A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS]; + Clock *clk; }; =20 typedef struct A9GTimerUpdate { diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index 4c6f5696319c..723f9b931997 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -33,6 +33,7 @@ typedef struct { struct ptimer_state *timer; qemu_irq irq; MemoryRegion iomem; + Clock *clk; } TimerBlock; =20 #define TYPE_ARM_MPTIMER "arm_mptimer" @@ -44,6 +45,7 @@ struct ARMMPTimerState { /*< public >*/ =20 uint32_t num_cpu; + Clock *clk; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; }; --=20 2.47.3 From nobody Sat Sep 26 22:15:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 18 Sep 2026 03:12:05 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf Subject: [PATCH v8 5/7] hw/arm/xilinx_zynq: Make PS frequency configurable Date: Fri, 18 Sep 2026 12:11:56 +0200 Message-ID: <20260918101158.42101-6-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::11; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789726476888158500 Content-Type: text/plain; charset="utf-8" From: YannickV Add ps_clk_freq to ZynqMachineClass so derived machine types can set their own PS clock frequency instead of using the hardcoded default. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 3 ++- include/hw/arm/xilinx_zynq.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index f7190118f7ff..1e09182b1cbe 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -253,7 +253,7 @@ static void zynq_init(MachineState *machine) object_property_add_child(OBJECT(zynq_machine), "ps_clk", OBJECT(zynq_machine->ps_clk)); object_unref(OBJECT(zynq_machine->ps_clk)); - clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); + clock_set_hz(zynq_machine->ps_clk, zmc->ps_clk_freq); =20 /* Create slcr, keep a pointer to connect clocks */ slcr =3D qdev_new("xilinx-zynq_slcr"); @@ -480,6 +480,7 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); zmc->qspi_flash_type =3D "n25q128"; + zmc->ps_clk_freq =3D PS_CLK_FREQUENCY; } =20 static const TypeInfo zynq_machine_type =3D { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index 33a68cdcd15e..a52caca18eb9 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -33,6 +33,7 @@ struct ZynqMachineState { struct ZynqMachineClass { MachineClass parent_class; const char *qspi_flash_type; + uint64_t ps_clk_freq; }; =20 #endif /* QEMU_ARM_ZYNQ_H */ --=20 2.47.3 From nobody Sat Sep 26 22:15:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1789726454; cv=none; d=zohomail.com; s=zohoarc; b=GgbZMyEtrgPxa/rf4q0EtYtC0Cb4kou3mtYHId2qA6SodvrdtNKcAdLa0cykef8H2UIWhTcfIsE/hnYyzvnixaV6QNYSOgln6ciQfZ9Pw+M0Qy6SFFNlPlzekPCyvH9XQ1IUaaYJgRwq1xoh2cLkcWO/cdzAYH6w09nmSA5Ysxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789726454; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=G06ebrzhC++l4jiv/i/SbggAjFbZj6iqgJHSmd7Z4QQ=; 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Fri, 18 Sep 2026 03:12:06 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf Subject: [PATCH v8 6/7] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Date: Fri, 18 Sep 2026 12:11:57 +0200 Message-ID: <20260918101158.42101-7-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::11; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x11.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789726454826158500 Content-Type: text/plain; charset="utf-8" From: YannickV Introduce a new machine type 'beckhoff-cx7200' that inherits from the xilinx-zynq-a9 machine. The CX7200 is an industrial PC based on the Xilinx Zynq-7000 SoC. The machine preserves all standard Zynq features (boot-mode selection, SPI, UART, Ethernet, etc.) while adding CX7200-specific hardware components. Signed-off-by: YannickV Reviewed-by: Peter Maydell --- MAINTAINERS | 9 +++++ hw/arm/Kconfig | 7 ++++ hw/arm/beckhoff_CX7200.c | 79 ++++++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 4 files changed, 96 insertions(+) create mode 100644 hw/arm/beckhoff_CX7200.c diff --git a/MAINTAINERS b/MAINTAINERS index 9012bf476da9..49c40c2dd587 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1153,6 +1153,15 @@ F: include/hw/adc/zynq-xadc.h X: hw/ssi/xilinx_* F: docs/system/arm/xlnx-zynq.rst =20 +Beckhoff CX7200 +M: Yannick Vossen +M: Corvin Koehne +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/beckhoff_CX7200.c +F: hw/misc/beckhoff_ccat.c +F: include/hw/misc/beckhoff_ccat.h + Xilinx ZynqMP and Versal M: Alistair Francis M: Edgar E. Iglesias diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index eae06369b02f..c5ef7e68f8b8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -277,6 +277,13 @@ config ZYNQ select XLNX_ZYNQ_DDRC select ZYNQ_DEVCFG =20 +config BECKHOFF_CX7200 + bool + default y + depends on TCG && ARM + select ZYNQ + select BECKHOFF_CCAT + config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c new file mode 100644 index 000000000000..606d62d78110 --- /dev/null +++ b/hw/arm/beckhoff_CX7200.c @@ -0,0 +1,79 @@ +/* + * Modified Xilinx Zynq Baseboard System emulation for Beckhoff CX7200. + * + * Copyright (c) 2026 Beckhoff Automation GmbH & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/core/boards.h" +#include "hw/block/block.h" +#include "hw/core/loader.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/clock.h" +#include "qemu/error-report.h" +#include "hw/arm/xilinx_zynq.h" /* For ZynqMachineState */ +#include "hw/cpu/a9mpcore.h" +#include "hw/timer/a9gtimer.h" +#include "qom/object.h" + +#define TYPE_CX7200_MACHINE MACHINE_TYPE_NAME("beckhoff-cx7200") + +#define CX7200_PS_CLK_FREQUENCY (40 * 1000 * 1000) + +static void ccat_init(uint32_t base, BlockBackend *eeprom_blk) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("beckhoff-ccat"); + if (eeprom_blk) { + qdev_prop_set_drive_err(dev, "eeprom", eeprom_blk, &error_fatal); + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + +static void beckhoff_cx7200_init(MachineState *machine) +{ + DriveInfo *di; + BlockBackend *blk; + MachineClass *parent_mc; + + parent_mc =3D MACHINE_CLASS(object_class_get_parent( + object_get_class(OBJECT(machine)))); + parent_mc->init(machine); + + di =3D drive_get(IF_NONE, 0, 0); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + ccat_init(0x40000000, blk); +} + +static void beckhoff_cx7200_machine_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + ZynqMachineClass *zmc =3D ZYNQ_MACHINE_CLASS(oc); + + mc->desc =3D "Beckhoff CX7200 Industrial PC (Zynq-based)"; + mc->init =3D beckhoff_cx7200_init; + zmc->qspi_flash_type =3D "is25lp016d"; + zmc->ps_clk_freq =3D CX7200_PS_CLK_FREQUENCY; +} + +static const TypeInfo beckhoff_cx7200_machine_type =3D { + .name =3D TYPE_CX7200_MACHINE, + .parent =3D TYPE_ZYNQ_MACHINE, + .class_init =3D beckhoff_cx7200_machine_class_init, + .instance_size =3D sizeof(ZynqMachineState), +}; + +static void beckhoff_cx7200_machine_register_types(void) +{ + type_register_static(&beckhoff_cx7200_machine_type); +} + +type_init(beckhoff_cx7200_machine_register_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index bcc068de0403..6c7b4870bf6a 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -1,6 +1,7 @@ arm_common_ss =3D ss.source_set() arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) +arm_common_ss.add(when: 'CONFIG_BECKHOFF_CX7200', if_true: files('beckhoff= _CX7200.c')) arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) arm_common_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.= c')) --=20 2.47.3 From nobody Sat Sep 26 22:15:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 18 Sep 2026 03:12:07 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Corvin Koehne , qemu-block@nongnu.org, Peter Maydell , Hanna Reitz , Pierrick Bouvier , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , "Edgar E. Iglesias" , Yannick Vossen , qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v8 7/7] docs/system/arm: Add support for Beckhoff CX7200 Date: Fri, 18 Sep 2026 12:11:58 +0200 Message-ID: <20260918101158.42101-8-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260918101158.42101-1-corvin.koehne@gmail.com> References: <20260918101158.42101-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::10; envelope-from=corvin.koehne@gmail.com; helo=mail-wm2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1789726446729158501 From: YannickV This commit offers some documentation on the Beckhoff CX7200 qemu emulation. Signed-off-by: YannickV Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- docs/system/arm/beckhoff-cx7200.rst | 68 +++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 69 insertions(+) create mode 100644 docs/system/arm/beckhoff-cx7200.rst diff --git a/docs/system/arm/beckhoff-cx7200.rst b/docs/system/arm/beckhoff= -cx7200.rst new file mode 100644 index 000000000000..a46fded324b3 --- /dev/null +++ b/docs/system/arm/beckhoff-cx7200.rst @@ -0,0 +1,68 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Beckhoff CX7200 (``beckhoff-cx7200``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Beckhoff CX7200 is based on the same architecture as the Xilinx Zynq A= 9. +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. +The Beckhoff Communication Controller (CCAT) can be found in the PL of Zyn= q. + +You can find more detail about this board on +`the manufacturer's product page `__. +The SoC is documented in the +`Zynq 7000 Technical Reference manual `__. + +The CX7200 supports the following: + +- Arm Cortex-A9 MPCore CPU + + - Cortex-A9 CPUs + - GIC v1 interrupt controller + - Generic timer + - Watchdog timer + +- OCM 256KB +- SMC SRAM 64MB +- Zynq SLCR +- SPI x2 +- QSPI +- UART +- TTC x2 +- Gigabit Ethernet Controller x2 +- SD Controller x2 +- XADC +- Arm PrimeCell DMA Controller +- DDR Memory +- USB 2.0 x2 +- DDR Controller +- Beckhoff Communication Controller (CCAT) + + - EEPROM Interface + - DMA Controller + +The following is not supported: + +- I2C + +Running +""""""" +Directly loading an ELF file to the CPU of the CX7200 to run TC/RTOS +(based on FreeRTOS): + +.. code-block:: bash + + $ qemu-system-arm -M beckhoff-cx7200 \ + -device loader,file=3DCX7200_Zynq_Fsbl.elf \ + -display none + + +For setting the EEPROM content of the CCAT provide the following on the +command line: + +.. code-block:: bash + + -drive file=3Deeprom.bin,format=3Draw,id=3Dccat-eeprom + +The size of eeprom.bin must be aligned to a power of 2 and bigger than +256 bytes. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 260cd7e4d6b5..66d7dc43b538 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -82,6 +82,7 @@ Board-specific documentation arm/aspeed arm/bananapi_m2u.rst arm/b-l475e-iot01a.rst + arm/beckhoff-cx7200 arm/sabrelite arm/digic arm/cubieboard --=20 2.47.3